* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2012-01-25 15:27 Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 1/5] target-arm: Fix implementation of TLB invalidate operations Peter Maydell
` (5 more replies)
0 siblings, 6 replies; 24+ messages in thread
From: Peter Maydell @ 2012-01-25 15:27 UTC (permalink / raw)
To: Aurelien Jarno, Blue Swirl; +Cc: qemu-devel
Here's the latest target-arm pullreq. It includes Mark's fix for
config_base_register, which is in turn a dependency of the arm-devs
pullreq I'm about to send out, and which I'd like to get in before
Anthony's QOM patchset lands and invalidates it :-)
Please pull.
-- PMM
The following changes since commit 5b4448d27d7c6ff6e18a1edc8245cb1db783e37c:
Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2012-01-23 11:00:26 -0600)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
Mark Langsdorf (1):
arm: store the config_base_register during cpu_reset
Peter Maydell (4):
target-arm: Fix implementation of TLB invalidate operations
target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
Add dummy implementation of generic timer cp15 registers
Add Cortex-A15 CPU definition
target-arm/cpu.h | 2 +
target-arm/helper.c | 86 ++++++++++++++++++++++++++++++++++++++++++---------
2 files changed, 73 insertions(+), 15 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PATCH 1/5] target-arm: Fix implementation of TLB invalidate operations
2012-01-25 15:27 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
@ 2012-01-25 15:27 ` Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only Peter Maydell
` (4 subsequent siblings)
5 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2012-01-25 15:27 UTC (permalink / raw)
To: Aurelien Jarno, Blue Swirl; +Cc: qemu-devel
Fix some bugs in the implementation of the TLB invalidate
operations on ARM:
* the 'invalidate all' op was not passing flush_global=1
to tlb_flush(); this doesn't have a practical effect since
tlb_flush() currently ignores that argument, but is
semantically incorrect
* 'invalidate by address for all ASIDs' was implemented as
flushing the whole TLB, which invalidates much more than
strictly necessary. Use tlb_flush_page() instead.
We also annotate the ops with the ARM ARM official acronyms.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 13 ++++++-------
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 00458fc..f11279e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1610,18 +1610,17 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
break;
case 8: /* MMU TLB control. */
switch (op2) {
- case 0: /* Invalidate all. */
- tlb_flush(env, 0);
+ case 0: /* Invalidate all (TLBIALL) */
+ tlb_flush(env, 1);
break;
- case 1: /* Invalidate single TLB entry. */
+ case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
tlb_flush_page(env, val & TARGET_PAGE_MASK);
break;
- case 2: /* Invalidate on ASID. */
+ case 2: /* Invalidate by ASID (TLBIASID) */
tlb_flush(env, val == 0);
break;
- case 3: /* Invalidate single entry on MVA. */
- /* ??? This is like case 1, but ignores ASID. */
- tlb_flush(env, 1);
+ case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
+ tlb_flush_page(env, val & TARGET_PAGE_MASK);
break;
default:
goto bad_reg;
--
1.7.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
2012-01-25 15:27 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 1/5] target-arm: Fix implementation of TLB invalidate operations Peter Maydell
@ 2012-01-25 15:27 ` Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 3/5] arm: store the config_base_register during cpu_reset Peter Maydell
` (3 subsequent siblings)
5 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2012-01-25 15:27 UTC (permalink / raw)
To: Aurelien Jarno, Blue Swirl; +Cc: qemu-devel
In the helper routines for VCVT float-to-int conversions, add
an explicit cast rather than relying on the softfloat int32
type being exactly 32 bits wide (which it is not guaranteed to be).
Without this, if the softfloat type was 64 bits wide we would
get zero-extension of the 32 bit value from the ARM register
rather than sign-extension, since TCG i32 values are passed as
uint32_t.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f11279e..f6e998b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2785,7 +2785,7 @@ DO_VFP_cmp(d, float64)
float##fsz HELPER(name)(uint32_t x, void *fpstp) \
{ \
float_status *fpst = fpstp; \
- return sign##int32_to_##float##fsz(x, fpst); \
+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
}
#define CONV_FTOI(name, fsz, sign, round) \
--
1.7.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PATCH 3/5] arm: store the config_base_register during cpu_reset
2012-01-25 15:27 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 1/5] target-arm: Fix implementation of TLB invalidate operations Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only Peter Maydell
@ 2012-01-25 15:27 ` Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15 registers Peter Maydell
` (2 subsequent siblings)
5 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2012-01-25 15:27 UTC (permalink / raw)
To: Aurelien Jarno, Blue Swirl; +Cc: qemu-devel
From: Mark Langsdorf <mark.langsdorf@calxeda.com>
Long term, the config_base_register will be a QDM parameter. In the
meantime, models that use it need to be able to preserve it across
cpu_reset() calls.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f6e998b..22e40fc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -255,6 +255,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
void cpu_reset(CPUARMState *env)
{
uint32_t id;
+ uint32_t tmp = 0;
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -262,9 +263,11 @@ void cpu_reset(CPUARMState *env)
}
id = env->cp15.c0_cpuid;
+ tmp = env->cp15.c15_config_base_address;
memset(env, 0, offsetof(CPUARMState, breakpoints));
if (id)
cpu_reset_model_id(env, id);
+ env->cp15.c15_config_base_address = tmp;
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
--
1.7.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15 registers
2012-01-25 15:27 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2012-01-25 15:27 ` [Qemu-devel] [PATCH 3/5] arm: store the config_base_register during cpu_reset Peter Maydell
@ 2012-01-25 15:27 ` Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition Peter Maydell
2012-01-28 13:12 ` [Qemu-devel] [PULL 0/5] target-arm queue Blue Swirl
5 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2012-01-25 15:27 UTC (permalink / raw)
To: Aurelien Jarno, Blue Swirl; +Cc: qemu-devel
Add a dummy implementation of the cp15 registers for the generic
timer (found in the Cortex-A15), just sufficient for Linux to
decide that it can't use it. This requires at least CNTP_CTL and
CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14.
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 12 ++++++++++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 42c53a7..7442c99 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -382,6 +382,7 @@ enum arm_features {
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
+ ARM_FEATURE_GENERIC_TIMER,
};
static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 22e40fc..5e7205a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1764,7 +1764,11 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
goto bad_reg;
}
break;
- case 14: /* Reserved. */
+ case 14: /* Generic timer */
+ if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
+ /* Dummy implementation: RAZ/WI for all */
+ break;
+ }
goto bad_reg;
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
@@ -2134,7 +2138,11 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
default:
goto bad_reg;
}
- case 14: /* Reserved. */
+ case 14: /* Generic timer */
+ if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
+ /* Dummy implementation: RAZ/WI for all */
+ return 0;
+ }
goto bad_reg;
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
--
1.7.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition
2012-01-25 15:27 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2012-01-25 15:27 ` [Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15 registers Peter Maydell
@ 2012-01-25 15:27 ` Peter Maydell
2012-02-10 1:23 ` Paul Brook
2012-01-28 13:12 ` [Qemu-devel] [PULL 0/5] target-arm queue Blue Swirl
5 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2012-01-25 15:27 UTC (permalink / raw)
To: Aurelien Jarno, Blue Swirl; +Cc: qemu-devel
Add a definition of a Cortex-A15 CPU. Note that for the moment we do
not implement any of:
* Large Physical Address Extensions (LPAE)
* Virtualization Extensions
* Generic Timer
* TrustZone (this is also true of our existing Cortex-A9 model, etc)
This CPU model is sufficient to boot a Linux kernel which has been
compiled for an A15 without LPAE enabled.
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++----
2 files changed, 52 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7442c99..0d9b39c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -433,6 +433,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8 0x410fc080
#define ARM_CPUID_CORTEXA9 0x410fc090
+#define ARM_CPUID_CORTEXA15 0x412fc0f1
#define ARM_CPUID_CORTEXM3 0x410fc231
#define ARM_CPUID_ANY 0xffffffff
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5e7205a..ea4f35f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -10,6 +10,16 @@
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
#endif
+#include "sysemu.h"
+
+static uint32_t cortexa15_cp15_c0_c1[8] = {
+ 0x00001131, 0x00011011, 0x02010555, 0x00000000,
+ 0x10201105, 0x20000000, 0x01240000, 0x02102211
+};
+
+static uint32_t cortexa15_cp15_c0_c2[8] = {
+ 0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0
+};
static uint32_t cortexa9_cp15_c0_c1[8] =
{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
@@ -158,6 +168,27 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
env->cp15.c1_sys = 0x00c50078;
break;
+ case ARM_CPUID_CORTEXA15:
+ set_feature(env, ARM_FEATURE_V7);
+ set_feature(env, ARM_FEATURE_VFP4);
+ set_feature(env, ARM_FEATURE_VFP_FP16);
+ set_feature(env, ARM_FEATURE_NEON);
+ set_feature(env, ARM_FEATURE_THUMB2EE);
+ set_feature(env, ARM_FEATURE_ARM_DIV);
+ set_feature(env, ARM_FEATURE_V7MP);
+ set_feature(env, ARM_FEATURE_GENERIC_TIMER);
+ env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
+ env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
+ env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
+ memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
+ memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
+ env->cp15.c0_cachetype = 0x8444c004;
+ env->cp15.c0_clid = 0x0a200023;
+ env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
+ env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
+ env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
+ env->cp15.c1_sys = 0x00c50078;
+ break;
case ARM_CPUID_CORTEXM3:
set_feature(env, ARM_FEATURE_V7);
set_feature(env, ARM_FEATURE_M);
@@ -416,6 +447,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
{ ARM_CPUID_CORTEXM3, "cortex-m3"},
{ ARM_CPUID_CORTEXA8, "cortex-a8"},
{ ARM_CPUID_CORTEXA9, "cortex-a9"},
+ { ARM_CPUID_CORTEXA15, "cortex-a15" },
{ ARM_CPUID_TI925T, "ti925t" },
{ ARM_CPUID_PXA250, "pxa250" },
{ ARM_CPUID_SA1100, "sa1100" },
@@ -670,8 +702,6 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
#else
-extern int semihosting_enabled;
-
/* Map CPU modes onto saved register banks. */
static inline int bank_number(CPUState *env, int mode)
{
@@ -1945,6 +1975,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
case ARM_CPUID_CORTEXA8:
return 2;
case ARM_CPUID_CORTEXA9:
+ case ARM_CPUID_CORTEXA15:
return 0;
default:
goto bad_reg;
@@ -2065,11 +2096,26 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
goto bad_reg;
}
case 1: /* L2 cache */
- if (crm != 0) {
+ /* L2 Lockdown and Auxiliary control. */
+ switch (op2) {
+ case 0:
+ /* L2 cache lockdown (A8 only) */
+ return 0;
+ case 2:
+ /* L2 cache auxiliary control (A8) or control (A15) */
+ if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) {
+ /* Linux wants the number of processors from here.
+ * Might as well set the interrupt-controller bit too.
+ */
+ return ((smp_cpus - 1) << 24) | (1 << 23);
+ }
+ return 0;
+ case 3:
+ /* L2 cache extended control (A15) */
+ return 0;
+ default:
goto bad_reg;
}
- /* L2 Lockdown and Auxiliary control. */
- return 0;
default:
goto bad_reg;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition
2012-01-25 15:27 ` [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition Peter Maydell
@ 2012-02-10 1:23 ` Paul Brook
2012-02-10 1:35 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Paul Brook @ 2012-02-10 1:23 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, Peter Maydell, Aurelien Jarno
> Add a definition of a Cortex-A15 CPU. Note that for the moment we do
> not implement any of:
> * Large Physical Address Extensions (LPAE)
> * Virtualization Extensions
> * Generic Timer
Are there feature bits that the guest can check before blindly using them? I
assume for at least LPAE and the timer there's a way for the OS to test for
these features without just poking at them and seing if they explode.
If so it's worth adding coments describing where these diverge from a real
A15.
Paul
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition
2012-02-10 1:23 ` Paul Brook
@ 2012-02-10 1:35 ` Peter Maydell
2012-02-10 2:09 ` Paul Brook
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2012-02-10 1:35 UTC (permalink / raw)
To: Paul Brook; +Cc: Blue Swirl, qemu-devel, Aurelien Jarno
On 10 February 2012 01:23, Paul Brook <paul@codesourcery.com> wrote:
>> Add a definition of a Cortex-A15 CPU. Note that for the moment we do
>> not implement any of:
>> * Large Physical Address Extensions (LPAE)
>> * Virtualization Extensions
>> * Generic Timer
>
> Are there feature bits that the guest can check before blindly using them? I
> assume for at least LPAE and the timer there's a way for the OS to test for
> these features without just poking at them and seing if they explode.
>
> If so it's worth adding coments describing where these diverge from a real
> A15.
There are feature bits, yes, but I've followed the general current
qemu practice of following the feature bits of the real hardware
rather than clearing feature bits for things we don't support
(eg for A9 we are currently claiming TrustZone and ThumbEE when
neither are actually true for QEMU).
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition
2012-02-10 1:35 ` Peter Maydell
@ 2012-02-10 2:09 ` Paul Brook
0 siblings, 0 replies; 24+ messages in thread
From: Paul Brook @ 2012-02-10 2:09 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, Peter Maydell, Aurelien Jarno
> >> Add a definition of a Cortex-A15 CPU. Note that for the moment we do
> >> not implement any of:
> >> * Large Physical Address Extensions (LPAE)
> >> * Virtualization Extensions
> >> * Generic Timer
> >
> > Are there feature bits that the guest can check before blindly using
> > them? I assume for at least LPAE and the timer there's a way for the OS
> > to test for these features without just poking at them and seing if they
> > explode.
> >
> > If so it's worth adding coments describing where these diverge from a
> > real A15.
>
> There are feature bits, yes, but I've followed the general current
> qemu practice of following the feature bits of the real hardware
> rather than clearing feature bits for things we don't support
> (eg for A9 we are currently claiming TrustZone and ThumbEE when
> neither are actually true for QEMU).
These are bugs.
Paul
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2012-01-25 15:27 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2012-01-25 15:27 ` [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition Peter Maydell
@ 2012-01-28 13:12 ` Blue Swirl
5 siblings, 0 replies; 24+ messages in thread
From: Blue Swirl @ 2012-01-28 13:12 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Aurelien Jarno
On Wed, Jan 25, 2012 at 15:27, Peter Maydell <peter.maydell@linaro.org> wrote:
> Here's the latest target-arm pullreq. It includes Mark's fix for
> config_base_register, which is in turn a dependency of the arm-devs
> pullreq I'm about to send out, and which I'd like to get in before
> Anthony's QOM patchset lands and invalidates it :-)
>
> Please pull.
Thanks, pulled.
> -- PMM
>
>
> The following changes since commit 5b4448d27d7c6ff6e18a1edc8245cb1db783e37c:
>
> Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2012-01-23 11:00:26 -0600)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> Mark Langsdorf (1):
> arm: store the config_base_register during cpu_reset
>
> Peter Maydell (4):
> target-arm: Fix implementation of TLB invalidate operations
> target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
> Add dummy implementation of generic timer cp15 registers
> Add Cortex-A15 CPU definition
>
> target-arm/cpu.h | 2 +
> target-arm/helper.c | 86 ++++++++++++++++++++++++++++++++++++++++++---------
> 2 files changed, 73 insertions(+), 15 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2016-01-11 14:34 Peter Maydell
2016-01-11 16:11 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2016-01-11 14:34 UTC (permalink / raw)
To: qemu-devel
Not very many patches here, but no point holding on to them.
I'm not going to email out the libvixl upgrade patch because
it's so big it'd get blocked by the list server anyway.
thanks
-- PMM
The following changes since commit 692a5519ab1510ff48bdde9701017b9425643058:
Merge remote-tracking branch 'remotes/mjt/tags/pull-trivial-patches-2016-01-11' into staging (2016-01-11 12:56:58 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160111
for you to fetch changes up to fe84fe5e2a59d5e83f043226114153bd3ccb1c51:
hw/arm/virt: Support legacy -nic command line syntax (2016-01-11 14:23:03 +0000)
----------------------------------------------------------------
target-arm queue:
* i.MX: move i.MX31 CCM object to register array
* xilinx_axidma: remove dead code
* xlnx-zynqmp: Add support for high DDR memory regions
* disas/libvixl: Update to upstream VIXL 1.12
* virt: Support legacy -nic command line syntax
----------------------------------------------------------------
Alistair Francis (1):
xlnx-zynqmp: Add support for high DDR memory regions
Andrew Jones (1):
hw/dma/xilinx_axidma: remove dead code
Ashok Kumar (1):
hw/arm/virt: Support legacy -nic command line syntax
Jean-Christophe DUBOIS (1):
i.MX: move i.MX31 CCM object to register array
Peter Maydell (1):
disas/libvixl: Update to upstream VIXL 1.12
disas/arm-a64.cc | 2 +-
disas/libvixl/Makefile.objs | 9 +-
disas/libvixl/README | 3 +-
disas/libvixl/a64/assembler-a64.h | 2353 ----------
disas/libvixl/a64/disasm-a64.cc | 1954 ---------
disas/libvixl/a64/instructions-a64.cc | 314 --
disas/libvixl/a64/instructions-a64.h | 384 --
disas/libvixl/vixl/a64/assembler-a64.h | 4624 ++++++++++++++++++++
disas/libvixl/{ => vixl}/a64/constants-a64.h | 967 +++-
disas/libvixl/{ => vixl}/a64/cpu-a64.h | 6 +-
disas/libvixl/{ => vixl}/a64/decoder-a64.cc | 210 +-
disas/libvixl/{ => vixl}/a64/decoder-a64.h | 58 +-
disas/libvixl/vixl/a64/disasm-a64.cc | 3487 +++++++++++++++
disas/libvixl/{ => vixl}/a64/disasm-a64.h | 17 +-
disas/libvixl/vixl/a64/instructions-a64.cc | 622 +++
disas/libvixl/vixl/a64/instructions-a64.h | 757 ++++
disas/libvixl/{ => vixl}/code-buffer.h | 2 +-
.../{utils.cc => vixl/compiler-intrinsics.cc} | 137 +-
disas/libvixl/vixl/compiler-intrinsics.h | 155 +
disas/libvixl/{ => vixl}/globals.h | 82 +-
disas/libvixl/vixl/invalset.h | 775 ++++
disas/libvixl/{ => vixl}/platform.h | 2 +-
disas/libvixl/vixl/utils.cc | 142 +
disas/libvixl/{ => vixl}/utils.h | 115 +-
hw/arm/virt.c | 14 +
hw/arm/xlnx-ep108.c | 35 +-
hw/arm/xlnx-zynqmp.c | 37 +
hw/dma/xilinx_axidma.c | 10 -
hw/misc/imx31_ccm.c | 188 +-
include/hw/arm/xlnx-zynqmp.h | 12 +
include/hw/misc/imx31_ccm.h | 38 +-
31 files changed, 12185 insertions(+), 5326 deletions(-)
delete mode 100644 disas/libvixl/a64/assembler-a64.h
delete mode 100644 disas/libvixl/a64/disasm-a64.cc
delete mode 100644 disas/libvixl/a64/instructions-a64.cc
delete mode 100644 disas/libvixl/a64/instructions-a64.h
create mode 100644 disas/libvixl/vixl/a64/assembler-a64.h
rename disas/libvixl/{ => vixl}/a64/constants-a64.h (51%)
rename disas/libvixl/{ => vixl}/a64/cpu-a64.h (96%)
rename disas/libvixl/{ => vixl}/a64/decoder-a64.cc (81%)
rename disas/libvixl/{ => vixl}/a64/decoder-a64.h (82%)
create mode 100644 disas/libvixl/vixl/a64/disasm-a64.cc
rename disas/libvixl/{ => vixl}/a64/disasm-a64.h (94%)
create mode 100644 disas/libvixl/vixl/a64/instructions-a64.cc
create mode 100644 disas/libvixl/vixl/a64/instructions-a64.h
rename disas/libvixl/{ => vixl}/code-buffer.h (99%)
rename disas/libvixl/{utils.cc => vixl/compiler-intrinsics.cc} (60%)
create mode 100644 disas/libvixl/vixl/compiler-intrinsics.h
rename disas/libvixl/{ => vixl}/globals.h (52%)
create mode 100644 disas/libvixl/vixl/invalset.h
rename disas/libvixl/{ => vixl}/platform.h (98%)
create mode 100644 disas/libvixl/vixl/utils.cc
rename disas/libvixl/{ => vixl}/utils.h (68%)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2016-01-11 14:34 Peter Maydell
@ 2016-01-11 16:11 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2016-01-11 16:11 UTC (permalink / raw)
To: QEMU Developers
On 11 January 2016 at 14:34, Peter Maydell <peter.maydell@linaro.org> wrote:
> Not very many patches here, but no point holding on to them.
> I'm not going to email out the libvixl upgrade patch because
> it's so big it'd get blocked by the list server anyway.
>
> thanks
> -- PMM
>
>
> The following changes since commit 692a5519ab1510ff48bdde9701017b9425643058:
>
> Merge remote-tracking branch 'remotes/mjt/tags/pull-trivial-patches-2016-01-11' into staging (2016-01-11 12:56:58 +0000)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160111
>
> for you to fetch changes up to fe84fe5e2a59d5e83f043226114153bd3ccb1c51:
>
> hw/arm/virt: Support legacy -nic command line syntax (2016-01-11 14:23:03 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * i.MX: move i.MX31 CCM object to register array
> * xilinx_axidma: remove dead code
> * xlnx-zynqmp: Add support for high DDR memory regions
> * disas/libvixl: Update to upstream VIXL 1.12
> * virt: Support legacy -nic command line syntax
>
There was a compile issue with the "xlnx-zynqmp: Add support for high DDR
memory regions" patch; I have dropped it and will redo the pull.
thanks
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2016-04-04 16:43 Peter Maydell
2016-04-05 8:32 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2016-04-04 16:43 UTC (permalink / raw)
To: qemu-devel
ARM changes for rc1: a small set of bugfixes which didn't quite
make rc0, mostly.
thanks
-- PMM
The following changes since commit c40e13e106243a6798b7b02b4d7de5ff6c9be128:
bsd-user: add necessary includes to fix warnings (2016-04-04 16:17:18 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160404
for you to fetch changes up to bf06c1123a427fefc2cf9cf8019578eafc19eb6f:
target-arm: Make the 64-bit version of VTCR do the migration (2016-04-04 17:33:52 +0100)
----------------------------------------------------------------
target-arm queue:
* bcm2836: wire up CPU timer interrupts correctly
* linux-user: ignore EXCP_YIELD in ARM cpu_loop()
* target-arm: correctly reset SCTLR_EL3
* target-arm: remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
* target-arm: make the 64-bit version of VTCR do the migration
----------------------------------------------------------------
Peter Maydell (5):
hw/arm/bcm2836: Wire up CPU timer interrupts correctly
linux-user: arm: Handle (ignore) EXCP_YIELD in ARM cpu_loop()
target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs
target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
target-arm: Make the 64-bit version of VTCR do the migration
hw/arm/bcm2836.c | 6 +++++-
linux-user/main.c | 6 ++++++
target-arm/helper.c | 31 ++++++++++++++++++-------------
3 files changed, 29 insertions(+), 14 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2016-04-04 16:43 Peter Maydell
@ 2016-04-05 8:32 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2016-04-05 8:32 UTC (permalink / raw)
To: QEMU Developers
On 4 April 2016 at 17:43, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM changes for rc1: a small set of bugfixes which didn't quite
> make rc0, mostly.
>
> thanks
> -- PMM
>
>
> The following changes since commit c40e13e106243a6798b7b02b4d7de5ff6c9be128:
>
> bsd-user: add necessary includes to fix warnings (2016-04-04 16:17:18 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160404
>
> for you to fetch changes up to bf06c1123a427fefc2cf9cf8019578eafc19eb6f:
>
> target-arm: Make the 64-bit version of VTCR do the migration (2016-04-04 17:33:52 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * bcm2836: wire up CPU timer interrupts correctly
> * linux-user: ignore EXCP_YIELD in ARM cpu_loop()
> * target-arm: correctly reset SCTLR_EL3
> * target-arm: remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
> * target-arm: make the 64-bit version of VTCR do the migration
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2017-10-31 13:11 Peter Maydell
2017-10-31 15:33 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2017-10-31 13:11 UTC (permalink / raw)
To: qemu-devel
Just small stuff. I expect/hope to get the "report attributes
in PAR register" fix from Andrew in, but will either send another
pull or just apply it as a single patch once it's been reviewed.
(I think we can call it a bugfix anyway, since it fixes booting
of Windows on ARM.)
thanks
-- PMM
The following changes since commit abf6e752e55b2f5afb48303429dea2db7c3a62de:
Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20171030' into staging (2017-10-30 13:02:45 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171031
for you to fetch changes up to 168df2dea701bbf3118bdfea7794369dfa694d3d:
hw/pci-host/gpex: Improve INTX to gsi routing error checking (2017-10-31 11:50:52 +0000)
----------------------------------------------------------------
target-arm queue:
* fix instruction-length bit in syndrome for WFI/WFE traps
* xlnx-zcu102: Specify the max number of CPUs
* msf2: Remove dead code reported by Coverity
* msf2: Wire up SYSRESETREQ in SoC for system reset
* hw/pci-host/gpex: Improve INTX to gsi routing error checking
----------------------------------------------------------------
Alistair Francis (1):
xlnx-zcu102: Specify the max number of CPUs
Eric Auger (1):
hw/pci-host/gpex: Improve INTX to gsi routing error checking
Stefano Stabellini (1):
fix WFI/WFE length in syndrome register
Subbaraya Sundeep (2):
msf2: Remove dead code reported by Coverity
msf2: Wire up SYSRESETREQ in SoC for system reset
target/arm/helper.h | 2 +-
target/arm/internals.h | 3 ++-
hw/arm/msf2-soc.c | 11 +++++++++++
hw/arm/xlnx-zcu102.c | 1 +
hw/pci-host/gpex.c | 10 ++++++++--
hw/ssi/mss-spi.c | 18 ++++++++++++++----
target/arm/op_helper.c | 7 ++++---
target/arm/psci.c | 2 +-
target/arm/translate-a64.c | 7 ++++++-
target/arm/translate.c | 10 +++++++++-
10 files changed, 57 insertions(+), 14 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2017-10-31 13:11 Peter Maydell
@ 2017-10-31 15:33 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2017-10-31 15:33 UTC (permalink / raw)
To: QEMU Developers
On 31 October 2017 at 13:11, Peter Maydell <peter.maydell@linaro.org> wrote:
> Just small stuff. I expect/hope to get the "report attributes
> in PAR register" fix from Andrew in, but will either send another
> pull or just apply it as a single patch once it's been reviewed.
> (I think we can call it a bugfix anyway, since it fixes booting
> of Windows on ARM.)
>
> thanks
> -- PMM
>
>
> The following changes since commit abf6e752e55b2f5afb48303429dea2db7c3a62de:
>
> Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20171030' into staging (2017-10-30 13:02:45 +0000)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171031
>
> for you to fetch changes up to 168df2dea701bbf3118bdfea7794369dfa694d3d:
>
> hw/pci-host/gpex: Improve INTX to gsi routing error checking (2017-10-31 11:50:52 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * fix instruction-length bit in syndrome for WFI/WFE traps
> * xlnx-zcu102: Specify the max number of CPUs
> * msf2: Remove dead code reported by Coverity
> * msf2: Wire up SYSRESETREQ in SoC for system reset
> * hw/pci-host/gpex: Improve INTX to gsi routing error checking
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2018-07-23 14:41 Peter Maydell
2018-07-23 16:08 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2018-07-23 14:41 UTC (permalink / raw)
To: qemu-devel
target-arm queue for 3.0:
Thomas' fixes for instrospection issues with a handful of
devices (including one microblaze one that I include in this
pullreq for convenience's sake), plus my bugfix for a
corner case of small MPU region support.
thanks
-- PMM
The following changes since commit 55b1f14cefcb19ce6d5e28c4c83404230888aa7e:
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-07-23 14:03:14 +0100)
are available in the Git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180723
for you to fetch changes up to 1ddc9b98c3cb89fe23a55ba924000fd645253e87:
hw/intc/exynos4210_gic: Turn instance_init into realize function (2018-07-23 15:21:27 +0100)
----------------------------------------------------------------
target-arm queue:
* spitz, exynos: fix bugs when introspecting some devices
* hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
* target/arm: Correctly handle overlapping small MPU regions
* hw/sd/bcm2835_sdhost: Fix PIO mode writes
----------------------------------------------------------------
Guenter Roeck (1):
hw/sd/bcm2835_sdhost: Fix PIO mode writes
Peter Maydell (1):
target/arm: Correctly handle overlapping small MPU regions
Thomas Huth (3):
hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
hw/arm/spitz: Move problematic nand_init() code to realize function
hw/intc/exynos4210_gic: Turn instance_init into realize function
hw/arm/spitz.c | 15 ++++++++++----
hw/intc/exynos4210_gic.c | 6 +++---
hw/microblaze/xlnx-zynqmp-pmu.c | 10 ++++-----
hw/sd/bcm2835_sdhost.c | 20 ++++++++++++++----
target/arm/helper.c | 46 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 80 insertions(+), 17 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2018-07-23 14:41 Peter Maydell
@ 2018-07-23 16:08 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2018-07-23 16:08 UTC (permalink / raw)
To: QEMU Developers
On 23 July 2018 at 15:41, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm queue for 3.0:
>
> Thomas' fixes for instrospection issues with a handful of
> devices (including one microblaze one that I include in this
> pullreq for convenience's sake), plus my bugfix for a
> corner case of small MPU region support.
>
> thanks
> -- PMM
>
> The following changes since commit 55b1f14cefcb19ce6d5e28c4c83404230888aa7e:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-07-23 14:03:14 +0100)
>
> are available in the Git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180723
>
> for you to fetch changes up to 1ddc9b98c3cb89fe23a55ba924000fd645253e87:
>
> hw/intc/exynos4210_gic: Turn instance_init into realize function (2018-07-23 15:21:27 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * spitz, exynos: fix bugs when introspecting some devices
> * hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
> * target/arm: Correctly handle overlapping small MPU regions
> * hw/sd/bcm2835_sdhost: Fix PIO mode writes
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2018-11-06 11:38 Peter Maydell
2018-11-06 13:12 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2018-11-06 11:38 UTC (permalink / raw)
To: qemu-devel
Handful of bugfix patches for arm for rc0; also
one milkymist patch, thrown in since I was putting
the pullreq together anyway.
thanks
-- PMM
The following changes since commit 03c1ca1c51783603d42eb0f91d35961f0f4b4947:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181105' into staging (2018-11-06 09:10:46 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181106
for you to fetch changes up to 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512:
target/arm: Fix ATS1Hx instructions (2018-11-06 11:32:14 +0000)
----------------------------------------------------------------
target-arm queue:
* Remove can't-happen if() from handle_vec_simd_shli()
* hw/arm/exynos4210: Zero memory allocated for Exynos4210State
* Set S and PTW in 64-bit PAR format
* Fix ATS1Hx instructions
* milkymist: Check for failure trying to load BIOS image
----------------------------------------------------------------
Peter Maydell (5):
target/arm: Remove can't-happen if() from handle_vec_simd_shli()
milkymist: Check for failure trying to load BIOS image
hw/arm/exynos4210: Zero memory allocated for Exynos4210State
target/arm: Set S and PTW in 64-bit PAR format
target/arm: Fix ATS1Hx instructions
hw/arm/exynos4210.c | 2 +-
hw/lm32/milkymist.c | 5 ++++-
target/arm/helper.c | 14 ++++++++------
target/arm/translate-a64.c | 8 +++-----
4 files changed, 16 insertions(+), 13 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2018-11-06 11:38 Peter Maydell
@ 2018-11-06 13:12 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2018-11-06 13:12 UTC (permalink / raw)
To: QEMU Developers
On 6 November 2018 at 11:38, Peter Maydell <peter.maydell@linaro.org> wrote:
> Handful of bugfix patches for arm for rc0; also
> one milkymist patch, thrown in since I was putting
> the pullreq together anyway.
>
> thanks
> -- PMM
>
> The following changes since commit 03c1ca1c51783603d42eb0f91d35961f0f4b4947:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181105' into staging (2018-11-06 09:10:46 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181106
>
> for you to fetch changes up to 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512:
>
> target/arm: Fix ATS1Hx instructions (2018-11-06 11:32:14 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Remove can't-happen if() from handle_vec_simd_shli()
> * hw/arm/exynos4210: Zero memory allocated for Exynos4210State
> * Set S and PTW in 64-bit PAR format
> * Fix ATS1Hx instructions
> * milkymist: Check for failure trying to load BIOS image
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2019-07-22 13:14 Peter Maydell
2019-07-22 14:50 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2019-07-22 13:14 UTC (permalink / raw)
To: qemu-devel
target-arm queue for rc2. This has 3 Arm related bug fixes,
and a couple of non-arm patches which don't have an obviously
better route into the tree.
thanks
-- PMM
The following changes since commit b9e02bb3f98174209dbd5c96858e65a31723221b:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-07-19' into staging (2019-07-22 10:11:28 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190722
for you to fetch changes up to ddb45afbfbc639365d6c934e4e29f6de5e5e2a0e:
contrib/elf2dmp: Build download.o with CURL_CFLAGS (2019-07-22 14:07:39 +0100)
----------------------------------------------------------------
target-arm queue:
* target/arm: Add missing break statement for Hypervisor Trap Exception
(fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC)
* hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
* target/arm: Limit ID register assertions to TCG
* configure: Clarify URL to source downloads
* contrib/elf2dmp: Build download.o with CURL_CFLAGS
----------------------------------------------------------------
Peter Maydell (4):
hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
target/arm: Limit ID register assertions to TCG
configure: Clarify URL to source downloads
contrib/elf2dmp: Build download.o with CURL_CFLAGS
Philippe Mathieu-Daudé (1):
target/arm: Add missing break statement for Hypervisor Trap Exception
configure | 2 +-
Makefile | 1 -
contrib/elf2dmp/Makefile.objs | 3 +++
include/hw/arm/fsl-imx6ul.h | 2 +-
hw/arm/fsl-imx6ul.c | 62 +++++++++++++------------------------------
hw/arm/mcimx6ul-evk.c | 2 +-
target/arm/cpu.c | 7 +++--
target/arm/helper.c | 1 +
8 files changed, 30 insertions(+), 50 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2019-07-22 13:14 Peter Maydell
@ 2019-07-22 14:50 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2019-07-22 14:50 UTC (permalink / raw)
To: QEMU Developers
On Mon, 22 Jul 2019 at 14:14, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> target-arm queue for rc2. This has 3 Arm related bug fixes,
> and a couple of non-arm patches which don't have an obviously
> better route into the tree.
>
> thanks
> -- PMM
>
> The following changes since commit b9e02bb3f98174209dbd5c96858e65a31723221b:
>
> Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-07-19' into staging (2019-07-22 10:11:28 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190722
>
> for you to fetch changes up to ddb45afbfbc639365d6c934e4e29f6de5e5e2a0e:
>
> contrib/elf2dmp: Build download.o with CURL_CFLAGS (2019-07-22 14:07:39 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * target/arm: Add missing break statement for Hypervisor Trap Exception
> (fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC)
> * hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
> * target/arm: Limit ID register assertions to TCG
> * configure: Clarify URL to source downloads
> * contrib/elf2dmp: Build download.o with CURL_CFLAGS
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2019-07-26 15:19 Peter Maydell
2019-07-26 16:09 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2019-07-26 15:19 UTC (permalink / raw)
To: qemu-devel
Handful of bug fixes to sneak in before rc3.
thanks
-- PMM
The following changes since commit c985266ea5b50e46e07b3568c1346e10064205c9:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190726' into staging (2019-07-26 13:52:06 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190726
for you to fetch changes up to 67505c114e6acc26f3a1a2b74833c61b6a34ff95:
hw/arm/boot: Further improve initrd positioning code (2019-07-26 16:17:56 +0100)
----------------------------------------------------------------
target-arm queue:
* Fix broken migration on pl330 device
* Fix broken migration on stellaris-input device
* Add type checks to vmstate varry macros to avoid this class of bugs
* hw/arm/boot: Fix some remaining cases where we would put the
initrd on top of the kernel image
----------------------------------------------------------------
Damien Hedde (1):
pl330: fix vmstate description
Peter Maydell (4):
stellaris_input: Fix vmstate description of buttons field
vmstate.h: Type check VMSTATE_STRUCT_VARRAY macros
hw/arm/boot: Rename elf_{low, high}_addr to image_{low, high}_addr
hw/arm/boot: Further improve initrd positioning code
include/migration/vmstate.h | 30 ++++++++++++++++++++++++------
hw/arm/boot.c | 37 +++++++++++++++++++++++++++----------
hw/dma/pl330.c | 17 +++++++++--------
hw/input/stellaris_input.c | 10 ++++++----
4 files changed, 66 insertions(+), 28 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2019-07-26 15:19 Peter Maydell
@ 2019-07-26 16:09 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2019-07-26 16:09 UTC (permalink / raw)
To: QEMU Developers
On Fri, 26 Jul 2019 at 16:19, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Handful of bug fixes to sneak in before rc3.
>
> thanks
> -- PMM
>
> The following changes since commit c985266ea5b50e46e07b3568c1346e10064205c9:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190726' into staging (2019-07-26 13:52:06 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190726
>
> for you to fetch changes up to 67505c114e6acc26f3a1a2b74833c61b6a34ff95:
>
> hw/arm/boot: Further improve initrd positioning code (2019-07-26 16:17:56 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Fix broken migration on pl330 device
> * Fix broken migration on stellaris-input device
> * Add type checks to vmstate varry macros to avoid this class of bugs
> * hw/arm/boot: Fix some remaining cases where we would put the
> initrd on top of the kernel image
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2019-07-26 16:09 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-01-25 15:27 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 1/5] target-arm: Fix implementation of TLB invalidate operations Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 3/5] arm: store the config_base_register during cpu_reset Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15 registers Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition Peter Maydell
2012-02-10 1:23 ` Paul Brook
2012-02-10 1:35 ` Peter Maydell
2012-02-10 2:09 ` Paul Brook
2012-01-28 13:12 ` [Qemu-devel] [PULL 0/5] target-arm queue Blue Swirl
2016-01-11 14:34 Peter Maydell
2016-01-11 16:11 ` Peter Maydell
2016-04-04 16:43 Peter Maydell
2016-04-05 8:32 ` Peter Maydell
2017-10-31 13:11 Peter Maydell
2017-10-31 15:33 ` Peter Maydell
2018-07-23 14:41 Peter Maydell
2018-07-23 16:08 ` Peter Maydell
2018-11-06 11:38 Peter Maydell
2018-11-06 13:12 ` Peter Maydell
2019-07-22 13:14 Peter Maydell
2019-07-22 14:50 ` Peter Maydell
2019-07-26 15:19 Peter Maydell
2019-07-26 16:09 ` Peter Maydell
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