* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2017-10-31 13:11 Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register Peter Maydell
` (5 more replies)
0 siblings, 6 replies; 21+ messages in thread
From: Peter Maydell @ 2017-10-31 13:11 UTC (permalink / raw)
To: qemu-devel
Just small stuff. I expect/hope to get the "report attributes
in PAR register" fix from Andrew in, but will either send another
pull or just apply it as a single patch once it's been reviewed.
(I think we can call it a bugfix anyway, since it fixes booting
of Windows on ARM.)
thanks
-- PMM
The following changes since commit abf6e752e55b2f5afb48303429dea2db7c3a62de:
Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20171030' into staging (2017-10-30 13:02:45 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171031
for you to fetch changes up to 168df2dea701bbf3118bdfea7794369dfa694d3d:
hw/pci-host/gpex: Improve INTX to gsi routing error checking (2017-10-31 11:50:52 +0000)
----------------------------------------------------------------
target-arm queue:
* fix instruction-length bit in syndrome for WFI/WFE traps
* xlnx-zcu102: Specify the max number of CPUs
* msf2: Remove dead code reported by Coverity
* msf2: Wire up SYSRESETREQ in SoC for system reset
* hw/pci-host/gpex: Improve INTX to gsi routing error checking
----------------------------------------------------------------
Alistair Francis (1):
xlnx-zcu102: Specify the max number of CPUs
Eric Auger (1):
hw/pci-host/gpex: Improve INTX to gsi routing error checking
Stefano Stabellini (1):
fix WFI/WFE length in syndrome register
Subbaraya Sundeep (2):
msf2: Remove dead code reported by Coverity
msf2: Wire up SYSRESETREQ in SoC for system reset
target/arm/helper.h | 2 +-
target/arm/internals.h | 3 ++-
hw/arm/msf2-soc.c | 11 +++++++++++
hw/arm/xlnx-zcu102.c | 1 +
hw/pci-host/gpex.c | 10 ++++++++--
hw/ssi/mss-spi.c | 18 ++++++++++++++----
target/arm/op_helper.c | 7 ++++---
target/arm/psci.c | 2 +-
target/arm/translate-a64.c | 7 ++++++-
target/arm/translate.c | 10 +++++++++-
10 files changed, 57 insertions(+), 14 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register
2017-10-31 13:11 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
@ 2017-10-31 13:11 ` Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs Peter Maydell
` (4 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2017-10-31 13:11 UTC (permalink / raw)
To: qemu-devel
From: Stefano Stabellini <sstabellini@kernel.org>
WFI/E are often, but not always, 4 bytes long. When they are, we need to
set ARM_EL_IL_SHIFT in the syndrome register.
Pass the instruction length to HELPER(wfi), use it to decrement pc
appropriately and to pass an is_16bit flag to syn_wfx, which sets
ARM_EL_IL_SHIFT if needed.
Set dc->insn in both arm_tr_translate_insn and thumb_tr_translate_insn.
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
Message-id: alpine.DEB.2.10.1710241055160.574@sstabellini-ThinkPad-X260
[PMM: move setting of dc->insn for Thumb so it is correct for 32 bit insns]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 2 +-
target/arm/internals.h | 3 ++-
target/arm/op_helper.c | 7 ++++---
target/arm/psci.c | 2 +-
target/arm/translate-a64.c | 7 ++++++-
target/arm/translate.c | 10 +++++++++-
6 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 2cf6f74..439d228 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -48,7 +48,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
DEF_HELPER_2(exception_internal, void, env, i32)
DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
DEF_HELPER_1(setend, void, env)
-DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_2(wfi, void, env, i32)
DEF_HELPER_1(wfe, void, env)
DEF_HELPER_1(yield, void, env)
DEF_HELPER_1(pre_hvc, void, env)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 43106a2..d9cc75e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -428,9 +428,10 @@ static inline uint32_t syn_breakpoint(int same_el)
| ARM_EL_IL | 0x22;
}
-static inline uint32_t syn_wfx(int cv, int cond, int ti)
+static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
{
return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
+ (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) |
(cv << 24) | (cond << 20) | ti;
}
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 138d0df..a40a84a 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -463,7 +463,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
return 0;
}
-void HELPER(wfi)(CPUARMState *env)
+void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
int target_el = check_wfx_trap(env, false);
@@ -476,8 +476,9 @@ void HELPER(wfi)(CPUARMState *env)
}
if (target_el) {
- env->pc -= 4;
- raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0), target_el);
+ env->pc -= insn_len;
+ raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2),
+ target_el);
}
cs->exception_index = EXCP_HLT;
diff --git a/target/arm/psci.c b/target/arm/psci.c
index fc34b26..eb7b88e 100644
--- a/target/arm/psci.c
+++ b/target/arm/psci.c
@@ -189,7 +189,7 @@ void arm_handle_psci_call(ARMCPU *cpu)
} else {
env->regs[0] = 0;
}
- helper_wfi(env);
+ helper_wfi(env, 4);
break;
case QEMU_PSCI_0_1_FN_MIGRATE:
case QEMU_PSCI_0_2_FN_MIGRATE:
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e98fbcf..caca05a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11400,17 +11400,22 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
gen_helper_yield(cpu_env);
break;
case DISAS_WFI:
+ {
/* This is a special case because we don't want to just halt the CPU
* if trying to debug across a WFI.
*/
+ TCGv_i32 tmp = tcg_const_i32(4);
+
gen_a64_set_pc_im(dc->pc);
- gen_helper_wfi(cpu_env);
+ gen_helper_wfi(cpu_env, tmp);
+ tcg_temp_free_i32(tmp);
/* The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway.
*/
tcg_gen_exit_tb(0);
break;
}
+ }
}
/* Functions above can change dc->pc, so re-align db->pc_next */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6ba4ae9..df57dbb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -12125,6 +12125,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
}
insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
+ dc->insn = insn;
dc->pc += 4;
disas_arm_insn(dc, insn);
@@ -12200,6 +12201,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
insn = insn << 16 | insn2;
dc->pc += 2;
}
+ dc->insn = insn;
if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
uint32_t cond = dc->condexec_cond;
@@ -12326,12 +12328,18 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
/* nothing more to generate */
break;
case DISAS_WFI:
- gen_helper_wfi(cpu_env);
+ {
+ TCGv_i32 tmp = tcg_const_i32((dc->thumb &&
+ !(dc->insn & (1U << 31))) ? 2 : 4);
+
+ gen_helper_wfi(cpu_env, tmp);
+ tcg_temp_free_i32(tmp);
/* The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway.
*/
tcg_gen_exit_tb(0);
break;
+ }
case DISAS_WFE:
gen_helper_wfe(cpu_env);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs
2017-10-31 13:11 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register Peter Maydell
@ 2017-10-31 13:11 ` Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity Peter Maydell
` (3 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2017-10-31 13:11 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair.francis@xilinx.com>
Specify the number of CPUs that can run on ZynqMP.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xlnx-zcu102.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 519a16e..e2d15a1 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -240,6 +240,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_IDE;
mc->units_per_default_bus = 1;
mc->ignore_memory_transaction_failures = true;
+ mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
}
static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity
2017-10-31 13:11 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs Peter Maydell
@ 2017-10-31 13:11 ` Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset Peter Maydell
` (2 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2017-10-31 13:11 UTC (permalink / raw)
To: qemu-devel
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Fixed incorrect frame size mask, validated maximum frame
size in spi_write and removed dead code.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1508898544-10307-1-git-send-email-sundeep.lkml@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/ssi/mss-spi.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
index 5a8e308..d60daba 100644
--- a/hw/ssi/mss-spi.c
+++ b/hw/ssi/mss-spi.c
@@ -76,9 +76,10 @@
#define C_BIGFIFO (1 << 29)
#define C_RESET (1 << 31)
-#define FRAMESZ_MASK 0x1F
+#define FRAMESZ_MASK 0x3F
#define FMCOUNT_MASK 0x00FFFF00
#define FMCOUNT_SHIFT 8
+#define FRAMESZ_MAX 32
static void txfifo_reset(MSSSpiState *s)
{
@@ -104,10 +105,8 @@ static void set_fifodepth(MSSSpiState *s)
s->fifo_depth = 32;
} else if (size <= 16) {
s->fifo_depth = 16;
- } else if (size <= 32) {
- s->fifo_depth = 8;
} else {
- s->fifo_depth = 4;
+ s->fifo_depth = 8;
}
}
@@ -301,6 +300,17 @@ static void spi_write(void *opaque, hwaddr addr,
if (s->enabled) {
break;
}
+ /*
+ * [31:6] bits are reserved bits and for future use.
+ * [5:0] are for frame size. Only [5:0] bits are validated
+ * during write, [31:6] bits are untouched.
+ */
+ if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided."
+ "Maximum frame size is %u\n",
+ __func__, value & FRAMESZ_MASK, FRAMESZ_MAX);
+ break;
+ }
s->regs[R_SPI_DFSIZE] = value;
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset
2017-10-31 13:11 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2017-10-31 13:11 ` [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity Peter Maydell
@ 2017-10-31 13:11 ` Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking Peter Maydell
2017-10-31 15:33 ` [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
5 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2017-10-31 13:11 UTC (permalink / raw)
To: qemu-devel
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Implemented system reset by creating SYSRESETREQ gpio
out from nvic.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Message-id: 1509253165-7434-1-git-send-email-sundeep.lkml@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/msf2-soc.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index 6f97fa9..a8ec2cd 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -57,6 +57,13 @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
+static void do_sys_reset(void *opaque, int n, int level)
+{
+ if (level) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ }
+}
+
static void m2sxxx_soc_initfn(Object *obj)
{
MSF2State *s = MSF2_SOC(obj);
@@ -125,6 +132,10 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
error_append_hint(errp, "m3clk can not be zero\n");
return;
}
+
+ qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
+ qemu_allocate_irq(&do_sys_reset, NULL, 0));
+
system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
for (i = 0; i < MSF2_NUM_UARTS; i++) {
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking
2017-10-31 13:11 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2017-10-31 13:11 ` [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset Peter Maydell
@ 2017-10-31 13:11 ` Peter Maydell
2017-10-31 15:33 ` [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
5 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2017-10-31 13:11 UTC (permalink / raw)
To: qemu-devel
From: Eric Auger <eric.auger@redhat.com>
We exposed gpex_set_irq_num() for machines to set the INTx to
GSI routing. However if the machine forgets to call that
function we currently do not check the association was properly
done. Let's initialize gsi values to -1 and if this value is
found in gpex_route_intx_pin_to_irq, set the routing mode as
disabled.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1508776211-22175-1-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/pci-host/gpex.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index 4090793..edf305b 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -57,9 +57,14 @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
{
PCIINTxRoute route;
GPEXHost *s = opaque;
+ int gsi = s->irq_num[pin];
- route.mode = PCI_INTX_ENABLED;
- route.irq = s->irq_num[pin];
+ route.irq = gsi;
+ if (gsi < 0) {
+ route.mode = PCI_INTX_DISABLED;
+ } else {
+ route.mode = PCI_INTX_ENABLED;
+ }
return route;
}
@@ -81,6 +86,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->io_ioport);
for (i = 0; i < GPEX_NUM_IRQS; i++) {
sysbus_init_irq(sbd, &s->irq[i]);
+ s->irq_num[i] = -1;
}
pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2017-10-31 13:11 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2017-10-31 13:11 ` [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking Peter Maydell
@ 2017-10-31 15:33 ` Peter Maydell
5 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2017-10-31 15:33 UTC (permalink / raw)
To: QEMU Developers
On 31 October 2017 at 13:11, Peter Maydell <peter.maydell@linaro.org> wrote:
> Just small stuff. I expect/hope to get the "report attributes
> in PAR register" fix from Andrew in, but will either send another
> pull or just apply it as a single patch once it's been reviewed.
> (I think we can call it a bugfix anyway, since it fixes booting
> of Windows on ARM.)
>
> thanks
> -- PMM
>
>
> The following changes since commit abf6e752e55b2f5afb48303429dea2db7c3a62de:
>
> Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20171030' into staging (2017-10-30 13:02:45 +0000)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20171031
>
> for you to fetch changes up to 168df2dea701bbf3118bdfea7794369dfa694d3d:
>
> hw/pci-host/gpex: Improve INTX to gsi routing error checking (2017-10-31 11:50:52 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * fix instruction-length bit in syndrome for WFI/WFE traps
> * xlnx-zcu102: Specify the max number of CPUs
> * msf2: Remove dead code reported by Coverity
> * msf2: Wire up SYSRESETREQ in SoC for system reset
> * hw/pci-host/gpex: Improve INTX to gsi routing error checking
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2019-07-26 15:19 Peter Maydell
2019-07-26 16:09 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Peter Maydell @ 2019-07-26 15:19 UTC (permalink / raw)
To: qemu-devel
Handful of bug fixes to sneak in before rc3.
thanks
-- PMM
The following changes since commit c985266ea5b50e46e07b3568c1346e10064205c9:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190726' into staging (2019-07-26 13:52:06 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190726
for you to fetch changes up to 67505c114e6acc26f3a1a2b74833c61b6a34ff95:
hw/arm/boot: Further improve initrd positioning code (2019-07-26 16:17:56 +0100)
----------------------------------------------------------------
target-arm queue:
* Fix broken migration on pl330 device
* Fix broken migration on stellaris-input device
* Add type checks to vmstate varry macros to avoid this class of bugs
* hw/arm/boot: Fix some remaining cases where we would put the
initrd on top of the kernel image
----------------------------------------------------------------
Damien Hedde (1):
pl330: fix vmstate description
Peter Maydell (4):
stellaris_input: Fix vmstate description of buttons field
vmstate.h: Type check VMSTATE_STRUCT_VARRAY macros
hw/arm/boot: Rename elf_{low, high}_addr to image_{low, high}_addr
hw/arm/boot: Further improve initrd positioning code
include/migration/vmstate.h | 30 ++++++++++++++++++++++++------
hw/arm/boot.c | 37 +++++++++++++++++++++++++++----------
hw/dma/pl330.c | 17 +++++++++--------
hw/input/stellaris_input.c | 10 ++++++----
4 files changed, 66 insertions(+), 28 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2019-07-26 15:19 Peter Maydell
@ 2019-07-26 16:09 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2019-07-26 16:09 UTC (permalink / raw)
To: QEMU Developers
On Fri, 26 Jul 2019 at 16:19, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Handful of bug fixes to sneak in before rc3.
>
> thanks
> -- PMM
>
> The following changes since commit c985266ea5b50e46e07b3568c1346e10064205c9:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190726' into staging (2019-07-26 13:52:06 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190726
>
> for you to fetch changes up to 67505c114e6acc26f3a1a2b74833c61b6a34ff95:
>
> hw/arm/boot: Further improve initrd positioning code (2019-07-26 16:17:56 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Fix broken migration on pl330 device
> * Fix broken migration on stellaris-input device
> * Add type checks to vmstate varry macros to avoid this class of bugs
> * hw/arm/boot: Fix some remaining cases where we would put the
> initrd on top of the kernel image
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2019-07-22 13:14 Peter Maydell
2019-07-22 14:50 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Peter Maydell @ 2019-07-22 13:14 UTC (permalink / raw)
To: qemu-devel
target-arm queue for rc2. This has 3 Arm related bug fixes,
and a couple of non-arm patches which don't have an obviously
better route into the tree.
thanks
-- PMM
The following changes since commit b9e02bb3f98174209dbd5c96858e65a31723221b:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-07-19' into staging (2019-07-22 10:11:28 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190722
for you to fetch changes up to ddb45afbfbc639365d6c934e4e29f6de5e5e2a0e:
contrib/elf2dmp: Build download.o with CURL_CFLAGS (2019-07-22 14:07:39 +0100)
----------------------------------------------------------------
target-arm queue:
* target/arm: Add missing break statement for Hypervisor Trap Exception
(fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC)
* hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
* target/arm: Limit ID register assertions to TCG
* configure: Clarify URL to source downloads
* contrib/elf2dmp: Build download.o with CURL_CFLAGS
----------------------------------------------------------------
Peter Maydell (4):
hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
target/arm: Limit ID register assertions to TCG
configure: Clarify URL to source downloads
contrib/elf2dmp: Build download.o with CURL_CFLAGS
Philippe Mathieu-Daudé (1):
target/arm: Add missing break statement for Hypervisor Trap Exception
configure | 2 +-
Makefile | 1 -
contrib/elf2dmp/Makefile.objs | 3 +++
include/hw/arm/fsl-imx6ul.h | 2 +-
hw/arm/fsl-imx6ul.c | 62 +++++++++++++------------------------------
hw/arm/mcimx6ul-evk.c | 2 +-
target/arm/cpu.c | 7 +++--
target/arm/helper.c | 1 +
8 files changed, 30 insertions(+), 50 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2019-07-22 13:14 Peter Maydell
@ 2019-07-22 14:50 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2019-07-22 14:50 UTC (permalink / raw)
To: QEMU Developers
On Mon, 22 Jul 2019 at 14:14, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> target-arm queue for rc2. This has 3 Arm related bug fixes,
> and a couple of non-arm patches which don't have an obviously
> better route into the tree.
>
> thanks
> -- PMM
>
> The following changes since commit b9e02bb3f98174209dbd5c96858e65a31723221b:
>
> Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-07-19' into staging (2019-07-22 10:11:28 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190722
>
> for you to fetch changes up to ddb45afbfbc639365d6c934e4e29f6de5e5e2a0e:
>
> contrib/elf2dmp: Build download.o with CURL_CFLAGS (2019-07-22 14:07:39 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * target/arm: Add missing break statement for Hypervisor Trap Exception
> (fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC)
> * hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
> * target/arm: Limit ID register assertions to TCG
> * configure: Clarify URL to source downloads
> * contrib/elf2dmp: Build download.o with CURL_CFLAGS
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2018-11-06 11:38 Peter Maydell
2018-11-06 13:12 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Peter Maydell @ 2018-11-06 11:38 UTC (permalink / raw)
To: qemu-devel
Handful of bugfix patches for arm for rc0; also
one milkymist patch, thrown in since I was putting
the pullreq together anyway.
thanks
-- PMM
The following changes since commit 03c1ca1c51783603d42eb0f91d35961f0f4b4947:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181105' into staging (2018-11-06 09:10:46 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181106
for you to fetch changes up to 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512:
target/arm: Fix ATS1Hx instructions (2018-11-06 11:32:14 +0000)
----------------------------------------------------------------
target-arm queue:
* Remove can't-happen if() from handle_vec_simd_shli()
* hw/arm/exynos4210: Zero memory allocated for Exynos4210State
* Set S and PTW in 64-bit PAR format
* Fix ATS1Hx instructions
* milkymist: Check for failure trying to load BIOS image
----------------------------------------------------------------
Peter Maydell (5):
target/arm: Remove can't-happen if() from handle_vec_simd_shli()
milkymist: Check for failure trying to load BIOS image
hw/arm/exynos4210: Zero memory allocated for Exynos4210State
target/arm: Set S and PTW in 64-bit PAR format
target/arm: Fix ATS1Hx instructions
hw/arm/exynos4210.c | 2 +-
hw/lm32/milkymist.c | 5 ++++-
target/arm/helper.c | 14 ++++++++------
target/arm/translate-a64.c | 8 +++-----
4 files changed, 16 insertions(+), 13 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2018-11-06 11:38 Peter Maydell
@ 2018-11-06 13:12 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2018-11-06 13:12 UTC (permalink / raw)
To: QEMU Developers
On 6 November 2018 at 11:38, Peter Maydell <peter.maydell@linaro.org> wrote:
> Handful of bugfix patches for arm for rc0; also
> one milkymist patch, thrown in since I was putting
> the pullreq together anyway.
>
> thanks
> -- PMM
>
> The following changes since commit 03c1ca1c51783603d42eb0f91d35961f0f4b4947:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181105' into staging (2018-11-06 09:10:46 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181106
>
> for you to fetch changes up to 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512:
>
> target/arm: Fix ATS1Hx instructions (2018-11-06 11:32:14 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Remove can't-happen if() from handle_vec_simd_shli()
> * hw/arm/exynos4210: Zero memory allocated for Exynos4210State
> * Set S and PTW in 64-bit PAR format
> * Fix ATS1Hx instructions
> * milkymist: Check for failure trying to load BIOS image
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2018-07-23 14:41 Peter Maydell
2018-07-23 16:08 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Peter Maydell @ 2018-07-23 14:41 UTC (permalink / raw)
To: qemu-devel
target-arm queue for 3.0:
Thomas' fixes for instrospection issues with a handful of
devices (including one microblaze one that I include in this
pullreq for convenience's sake), plus my bugfix for a
corner case of small MPU region support.
thanks
-- PMM
The following changes since commit 55b1f14cefcb19ce6d5e28c4c83404230888aa7e:
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-07-23 14:03:14 +0100)
are available in the Git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180723
for you to fetch changes up to 1ddc9b98c3cb89fe23a55ba924000fd645253e87:
hw/intc/exynos4210_gic: Turn instance_init into realize function (2018-07-23 15:21:27 +0100)
----------------------------------------------------------------
target-arm queue:
* spitz, exynos: fix bugs when introspecting some devices
* hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
* target/arm: Correctly handle overlapping small MPU regions
* hw/sd/bcm2835_sdhost: Fix PIO mode writes
----------------------------------------------------------------
Guenter Roeck (1):
hw/sd/bcm2835_sdhost: Fix PIO mode writes
Peter Maydell (1):
target/arm: Correctly handle overlapping small MPU regions
Thomas Huth (3):
hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
hw/arm/spitz: Move problematic nand_init() code to realize function
hw/intc/exynos4210_gic: Turn instance_init into realize function
hw/arm/spitz.c | 15 ++++++++++----
hw/intc/exynos4210_gic.c | 6 +++---
hw/microblaze/xlnx-zynqmp-pmu.c | 10 ++++-----
hw/sd/bcm2835_sdhost.c | 20 ++++++++++++++----
target/arm/helper.c | 46 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 80 insertions(+), 17 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2018-07-23 14:41 Peter Maydell
@ 2018-07-23 16:08 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2018-07-23 16:08 UTC (permalink / raw)
To: QEMU Developers
On 23 July 2018 at 15:41, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm queue for 3.0:
>
> Thomas' fixes for instrospection issues with a handful of
> devices (including one microblaze one that I include in this
> pullreq for convenience's sake), plus my bugfix for a
> corner case of small MPU region support.
>
> thanks
> -- PMM
>
> The following changes since commit 55b1f14cefcb19ce6d5e28c4c83404230888aa7e:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-07-23 14:03:14 +0100)
>
> are available in the Git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180723
>
> for you to fetch changes up to 1ddc9b98c3cb89fe23a55ba924000fd645253e87:
>
> hw/intc/exynos4210_gic: Turn instance_init into realize function (2018-07-23 15:21:27 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * spitz, exynos: fix bugs when introspecting some devices
> * hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
> * target/arm: Correctly handle overlapping small MPU regions
> * hw/sd/bcm2835_sdhost: Fix PIO mode writes
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2016-04-04 16:43 Peter Maydell
2016-04-05 8:32 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Peter Maydell @ 2016-04-04 16:43 UTC (permalink / raw)
To: qemu-devel
ARM changes for rc1: a small set of bugfixes which didn't quite
make rc0, mostly.
thanks
-- PMM
The following changes since commit c40e13e106243a6798b7b02b4d7de5ff6c9be128:
bsd-user: add necessary includes to fix warnings (2016-04-04 16:17:18 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160404
for you to fetch changes up to bf06c1123a427fefc2cf9cf8019578eafc19eb6f:
target-arm: Make the 64-bit version of VTCR do the migration (2016-04-04 17:33:52 +0100)
----------------------------------------------------------------
target-arm queue:
* bcm2836: wire up CPU timer interrupts correctly
* linux-user: ignore EXCP_YIELD in ARM cpu_loop()
* target-arm: correctly reset SCTLR_EL3
* target-arm: remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
* target-arm: make the 64-bit version of VTCR do the migration
----------------------------------------------------------------
Peter Maydell (5):
hw/arm/bcm2836: Wire up CPU timer interrupts correctly
linux-user: arm: Handle (ignore) EXCP_YIELD in ARM cpu_loop()
target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs
target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
target-arm: Make the 64-bit version of VTCR do the migration
hw/arm/bcm2836.c | 6 +++++-
linux-user/main.c | 6 ++++++
target-arm/helper.c | 31 ++++++++++++++++++-------------
3 files changed, 29 insertions(+), 14 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2016-04-04 16:43 Peter Maydell
@ 2016-04-05 8:32 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2016-04-05 8:32 UTC (permalink / raw)
To: QEMU Developers
On 4 April 2016 at 17:43, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM changes for rc1: a small set of bugfixes which didn't quite
> make rc0, mostly.
>
> thanks
> -- PMM
>
>
> The following changes since commit c40e13e106243a6798b7b02b4d7de5ff6c9be128:
>
> bsd-user: add necessary includes to fix warnings (2016-04-04 16:17:18 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160404
>
> for you to fetch changes up to bf06c1123a427fefc2cf9cf8019578eafc19eb6f:
>
> target-arm: Make the 64-bit version of VTCR do the migration (2016-04-04 17:33:52 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * bcm2836: wire up CPU timer interrupts correctly
> * linux-user: ignore EXCP_YIELD in ARM cpu_loop()
> * target-arm: correctly reset SCTLR_EL3
> * target-arm: remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
> * target-arm: make the 64-bit version of VTCR do the migration
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2016-01-11 14:34 Peter Maydell
2016-01-11 16:11 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Peter Maydell @ 2016-01-11 14:34 UTC (permalink / raw)
To: qemu-devel
Not very many patches here, but no point holding on to them.
I'm not going to email out the libvixl upgrade patch because
it's so big it'd get blocked by the list server anyway.
thanks
-- PMM
The following changes since commit 692a5519ab1510ff48bdde9701017b9425643058:
Merge remote-tracking branch 'remotes/mjt/tags/pull-trivial-patches-2016-01-11' into staging (2016-01-11 12:56:58 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160111
for you to fetch changes up to fe84fe5e2a59d5e83f043226114153bd3ccb1c51:
hw/arm/virt: Support legacy -nic command line syntax (2016-01-11 14:23:03 +0000)
----------------------------------------------------------------
target-arm queue:
* i.MX: move i.MX31 CCM object to register array
* xilinx_axidma: remove dead code
* xlnx-zynqmp: Add support for high DDR memory regions
* disas/libvixl: Update to upstream VIXL 1.12
* virt: Support legacy -nic command line syntax
----------------------------------------------------------------
Alistair Francis (1):
xlnx-zynqmp: Add support for high DDR memory regions
Andrew Jones (1):
hw/dma/xilinx_axidma: remove dead code
Ashok Kumar (1):
hw/arm/virt: Support legacy -nic command line syntax
Jean-Christophe DUBOIS (1):
i.MX: move i.MX31 CCM object to register array
Peter Maydell (1):
disas/libvixl: Update to upstream VIXL 1.12
disas/arm-a64.cc | 2 +-
disas/libvixl/Makefile.objs | 9 +-
disas/libvixl/README | 3 +-
disas/libvixl/a64/assembler-a64.h | 2353 ----------
disas/libvixl/a64/disasm-a64.cc | 1954 ---------
disas/libvixl/a64/instructions-a64.cc | 314 --
disas/libvixl/a64/instructions-a64.h | 384 --
disas/libvixl/vixl/a64/assembler-a64.h | 4624 ++++++++++++++++++++
disas/libvixl/{ => vixl}/a64/constants-a64.h | 967 +++-
disas/libvixl/{ => vixl}/a64/cpu-a64.h | 6 +-
disas/libvixl/{ => vixl}/a64/decoder-a64.cc | 210 +-
disas/libvixl/{ => vixl}/a64/decoder-a64.h | 58 +-
disas/libvixl/vixl/a64/disasm-a64.cc | 3487 +++++++++++++++
disas/libvixl/{ => vixl}/a64/disasm-a64.h | 17 +-
disas/libvixl/vixl/a64/instructions-a64.cc | 622 +++
disas/libvixl/vixl/a64/instructions-a64.h | 757 ++++
disas/libvixl/{ => vixl}/code-buffer.h | 2 +-
.../{utils.cc => vixl/compiler-intrinsics.cc} | 137 +-
disas/libvixl/vixl/compiler-intrinsics.h | 155 +
disas/libvixl/{ => vixl}/globals.h | 82 +-
disas/libvixl/vixl/invalset.h | 775 ++++
disas/libvixl/{ => vixl}/platform.h | 2 +-
disas/libvixl/vixl/utils.cc | 142 +
disas/libvixl/{ => vixl}/utils.h | 115 +-
hw/arm/virt.c | 14 +
hw/arm/xlnx-ep108.c | 35 +-
hw/arm/xlnx-zynqmp.c | 37 +
hw/dma/xilinx_axidma.c | 10 -
hw/misc/imx31_ccm.c | 188 +-
include/hw/arm/xlnx-zynqmp.h | 12 +
include/hw/misc/imx31_ccm.h | 38 +-
31 files changed, 12185 insertions(+), 5326 deletions(-)
delete mode 100644 disas/libvixl/a64/assembler-a64.h
delete mode 100644 disas/libvixl/a64/disasm-a64.cc
delete mode 100644 disas/libvixl/a64/instructions-a64.cc
delete mode 100644 disas/libvixl/a64/instructions-a64.h
create mode 100644 disas/libvixl/vixl/a64/assembler-a64.h
rename disas/libvixl/{ => vixl}/a64/constants-a64.h (51%)
rename disas/libvixl/{ => vixl}/a64/cpu-a64.h (96%)
rename disas/libvixl/{ => vixl}/a64/decoder-a64.cc (81%)
rename disas/libvixl/{ => vixl}/a64/decoder-a64.h (82%)
create mode 100644 disas/libvixl/vixl/a64/disasm-a64.cc
rename disas/libvixl/{ => vixl}/a64/disasm-a64.h (94%)
create mode 100644 disas/libvixl/vixl/a64/instructions-a64.cc
create mode 100644 disas/libvixl/vixl/a64/instructions-a64.h
rename disas/libvixl/{ => vixl}/code-buffer.h (99%)
rename disas/libvixl/{utils.cc => vixl/compiler-intrinsics.cc} (60%)
create mode 100644 disas/libvixl/vixl/compiler-intrinsics.h
rename disas/libvixl/{ => vixl}/globals.h (52%)
create mode 100644 disas/libvixl/vixl/invalset.h
rename disas/libvixl/{ => vixl}/platform.h (98%)
create mode 100644 disas/libvixl/vixl/utils.cc
rename disas/libvixl/{ => vixl}/utils.h (68%)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2016-01-11 14:34 Peter Maydell
@ 2016-01-11 16:11 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2016-01-11 16:11 UTC (permalink / raw)
To: QEMU Developers
On 11 January 2016 at 14:34, Peter Maydell <peter.maydell@linaro.org> wrote:
> Not very many patches here, but no point holding on to them.
> I'm not going to email out the libvixl upgrade patch because
> it's so big it'd get blocked by the list server anyway.
>
> thanks
> -- PMM
>
>
> The following changes since commit 692a5519ab1510ff48bdde9701017b9425643058:
>
> Merge remote-tracking branch 'remotes/mjt/tags/pull-trivial-patches-2016-01-11' into staging (2016-01-11 12:56:58 +0000)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160111
>
> for you to fetch changes up to fe84fe5e2a59d5e83f043226114153bd3ccb1c51:
>
> hw/arm/virt: Support legacy -nic command line syntax (2016-01-11 14:23:03 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * i.MX: move i.MX31 CCM object to register array
> * xilinx_axidma: remove dead code
> * xlnx-zynqmp: Add support for high DDR memory regions
> * disas/libvixl: Update to upstream VIXL 1.12
> * virt: Support legacy -nic command line syntax
>
There was a compile issue with the "xlnx-zynqmp: Add support for high DDR
memory regions" patch; I have dropped it and will redo the pull.
thanks
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PULL 0/5] target-arm queue
@ 2012-01-25 15:27 Peter Maydell
2012-01-28 13:12 ` Blue Swirl
0 siblings, 1 reply; 21+ messages in thread
From: Peter Maydell @ 2012-01-25 15:27 UTC (permalink / raw)
To: Aurelien Jarno, Blue Swirl; +Cc: qemu-devel
Here's the latest target-arm pullreq. It includes Mark's fix for
config_base_register, which is in turn a dependency of the arm-devs
pullreq I'm about to send out, and which I'd like to get in before
Anthony's QOM patchset lands and invalidates it :-)
Please pull.
-- PMM
The following changes since commit 5b4448d27d7c6ff6e18a1edc8245cb1db783e37c:
Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2012-01-23 11:00:26 -0600)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
Mark Langsdorf (1):
arm: store the config_base_register during cpu_reset
Peter Maydell (4):
target-arm: Fix implementation of TLB invalidate operations
target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
Add dummy implementation of generic timer cp15 registers
Add Cortex-A15 CPU definition
target-arm/cpu.h | 2 +
target-arm/helper.c | 86 ++++++++++++++++++++++++++++++++++++++++++---------
2 files changed, 73 insertions(+), 15 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PULL 0/5] target-arm queue
2012-01-25 15:27 Peter Maydell
@ 2012-01-28 13:12 ` Blue Swirl
0 siblings, 0 replies; 21+ messages in thread
From: Blue Swirl @ 2012-01-28 13:12 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Aurelien Jarno
On Wed, Jan 25, 2012 at 15:27, Peter Maydell <peter.maydell@linaro.org> wrote:
> Here's the latest target-arm pullreq. It includes Mark's fix for
> config_base_register, which is in turn a dependency of the arm-devs
> pullreq I'm about to send out, and which I'd like to get in before
> Anthony's QOM patchset lands and invalidates it :-)
>
> Please pull.
Thanks, pulled.
> -- PMM
>
>
> The following changes since commit 5b4448d27d7c6ff6e18a1edc8245cb1db783e37c:
>
> Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2012-01-23 11:00:26 -0600)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> Mark Langsdorf (1):
> arm: store the config_base_register during cpu_reset
>
> Peter Maydell (4):
> target-arm: Fix implementation of TLB invalidate operations
> target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
> Add dummy implementation of generic timer cp15 registers
> Add Cortex-A15 CPU definition
>
> target-arm/cpu.h | 2 +
> target-arm/helper.c | 86 ++++++++++++++++++++++++++++++++++++++++++---------
> 2 files changed, 73 insertions(+), 15 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2019-07-26 16:09 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-31 13:11 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking Peter Maydell
2017-10-31 15:33 ` [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2019-07-26 15:19 Peter Maydell
2019-07-26 16:09 ` Peter Maydell
2019-07-22 13:14 Peter Maydell
2019-07-22 14:50 ` Peter Maydell
2018-11-06 11:38 Peter Maydell
2018-11-06 13:12 ` Peter Maydell
2018-07-23 14:41 Peter Maydell
2018-07-23 16:08 ` Peter Maydell
2016-04-04 16:43 Peter Maydell
2016-04-05 8:32 ` Peter Maydell
2016-01-11 14:34 Peter Maydell
2016-01-11 16:11 ` Peter Maydell
2012-01-25 15:27 Peter Maydell
2012-01-28 13:12 ` Blue Swirl
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