* [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board
@ 2011-09-15 5:59 Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 1/8] arm, davinci: add SYSCFG1 base and register struct Heiko Schocher
` (7 more replies)
0 siblings, 8 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
Cores: ARM 456 MHz
DDR: 300 MHz
I2C: ready
DRAM: 64 MiB
WARNING: Caches not enabled
Flash: 2 MiB
NAND: 128 MiB
In: serial
Out: serial
Err: serial
Net: DaVinci-EMAC
The enbw_cmc board boots from NOR flash with the NOR
direct boot method.
Heiko Schocher (8):
arm, davinci: add SYSCFG1 base and register struct
arm, davinci: add some missing defines in hardware.h
arm, davinci, am1808, gpio: add missing defines for bank 8
arm, davinci: add ddr2 definition
arm, davinci: add NOR Boot Configuration Word
arm, davinci, am1808: add lowlevel functions for booting from NOR
arm, davinci, da8xx: add cpuinfo
arm, davinci: add support for am1808 based enbw_cmc board
arch/arm/cpu/arm926ejs/davinci/Makefile | 1 +
arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c | 428 +++++++++++++++
arch/arm/cpu/arm926ejs/davinci/cpu.c | 16 +-
arch/arm/cpu/arm926ejs/start.S | 9 +
.../arm/include/asm/arch-davinci/am1808_lowlevel.h | 44 ++
arch/arm/include/asm/arch-davinci/ddr2_defs.h | 96 ++++
arch/arm/include/asm/arch-davinci/gpio.h | 2 +
arch/arm/include/asm/arch-davinci/hardware.h | 27 +
board/enbw/enbw_cmc/Makefile | 51 ++
board/enbw/enbw_cmc/enbw_cmc.c | 574 ++++++++++++++++++++
boards.cfg | 1 +
doc/README.davinci | 9 +
include/configs/enbw_cmc.h | 440 +++++++++++++++
13 files changed, 1696 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
create mode 100644 arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
create mode 100644 arch/arm/include/asm/arch-davinci/ddr2_defs.h
create mode 100644 board/enbw/enbw_cmc/Makefile
create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
create mode 100644 include/configs/enbw_cmc.h
The following patches are also needed for this board support:
[U-Boot] : davinci: Replace CONFIG_PRELOADER with CONFIG_SPL_BUILD in board/davinci/common/misc.c
http://patchwork.ozlabs.org/patch/114482/
[U-Boot] arm, fdt: update ethernet mac address before booting Linux
http://patchwork.ozlabs.org/patch/114736/
[U-Boot] CFI: trigger watchdog in write_buf()
http://patchwork.ozlabs.org/patch/114737/
[U-Boot] net, davinci_emac: make less verbose - turn printf() into debug()
http://patchwork.ozlabs.org/patch/114738/
[U-Boot] i2c, davinci: add i2c set speed
http://patchwork.ozlabs.org/patch/114739/
[U-Boot] arm, logbuffer: make it compileclean
http://patchwork.ozlabs.org/patch/114740/
[U-Boot] post, arm: make post support for arm compile clean
http://patchwork.ozlabs.org/patch/114741/
[U-Boot] cosmetic, post: Codingstyle cleanup
http://patchwork.ozlabs.org/patch/114742/
[U-Boot] arm, post: add missing post_time_ms for arm
http://patchwork.ozlabs.org/patch/114743/
[U-Boot] net, davinci_emac: add KSZ8864 switch
http://patchwork.ozlabs.org/patch/114744/
[U-Boot] net, davinci_emac: let the EMAC detect the PHYs
http://patchwork.ozlabs.org/patch/114745/
[U-Boot,1/3] arm, davinci: move davinci_timer in header file
http://patchwork.ozlabs.org/patch/114747/
[U-Boot,2/3] arm, davinci: add missing timer baseaddresses for !DA8xx cpu
http://patchwork.ozlabs.org/patch/114746/
[U-Boot,3/3] arm, davinci: add internal WDT support for AM1808 cpus
http://patchwork.ozlabs.org/patch/114748/
[U-Boot,1/2] arm, davinci: add RTC base addr
http://patchwork.ozlabs.org/patch/114749/
[U-Boot,2/2] rtc, davinci: add support for davinci internal RTC
http://patchwork.ozlabs.org/patch/114750/
--
1.7.6
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 1/8] arm, davinci: add SYSCFG1 base and register struct
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
@ 2011-09-15 5:59 ` Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 2/8] arm, davinci: add some missing defines in hardware.h Heiko Schocher
` (6 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/include/asm/arch-davinci/hardware.h | 16 ++++++++++++++++
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 19ab680..dcc71d6 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -142,6 +142,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
+#define DAVINCI_SYSCFG1_BASE 0x01e2c000
#define DAVINCI_MMC_SD0_BASE 0x01c40000
#define DAVINCI_MMC_SD1_BASE 0x01e1b000
#define DAVINCI_TIMER2_BASE 0x01f0c000
@@ -448,6 +449,21 @@ struct davinci_syscfg_regs {
#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
+struct davinci_syscfg1_regs {
+ dv_reg vtpio_ctl;
+ dv_reg ddr_slew;
+ dv_reg deepsleep;
+ dv_reg pupd_ena;
+ dv_reg pupd_sel;
+ dv_reg rxactive;
+ dv_reg pwrdwn;
+};
+
+#define davinci_syscfg1_regs \
+ ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
+
+#define DDR_SLEW_CMOSEN_BIT 4
+
/* Interrupt controller */
struct davinci_aintc_regs {
dv_reg revid;
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 2/8] arm, davinci: add some missing defines in hardware.h
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 1/8] arm, davinci: add SYSCFG1 base and register struct Heiko Schocher
@ 2011-09-15 5:59 ` Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 3/8] arm, davinci, am1808, gpio: add missing defines for bank 8 Heiko Schocher
` (5 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/include/asm/arch-davinci/hardware.h | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index dcc71d6..b6a3209 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -322,6 +322,11 @@ void davinci_errata_workarounds(void);
#else /* CONFIG_SOC_DA8XX */
+#define PSC_ENABLE 0x3
+#define PSC_DISABLE 0x2
+#define PSC_SYNCRESET 0x1
+#define PSC_SWRSTDISABLE 0x0
+
#define PSC_PSC0_MODULE_ID_CNT 16
#define PSC_PSC1_MODULE_ID_CNT 32
@@ -464,6 +469,12 @@ struct davinci_syscfg1_regs {
#define DDR_SLEW_CMOSEN_BIT 4
+#define VTP_POWERDWN (1 << 6)
+#define VTP_LOCK (1 << 7)
+#define VTP_CLKRZ (1 << 13)
+#define VTP_READY (1 << 15)
+#define VTP_IOPWRDWN (1 << 14)
+
/* Interrupt controller */
struct davinci_aintc_regs {
dv_reg revid;
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 3/8] arm, davinci, am1808, gpio: add missing defines for bank 8
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 1/8] arm, davinci: add SYSCFG1 base and register struct Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 2/8] arm, davinci: add some missing defines in hardware.h Heiko Schocher
@ 2011-09-15 5:59 ` Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 4/8] arm, davinci: add ddr2 definition Heiko Schocher
` (4 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/include/asm/arch-davinci/gpio.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/include/asm/arch-davinci/gpio.h
index 29dcccf..ef65ffb 100644
--- a/arch/arm/include/asm/arch-davinci/gpio.h
+++ b/arch/arm/include/asm/arch-davinci/gpio.h
@@ -35,6 +35,7 @@
#define DAVINCI_GPIO_BANK23 0x01E26038
#define DAVINCI_GPIO_BANK45 0x01E26060
#define DAVINCI_GPIO_BANK67 0x01E26088
+#define DAVINCI_GPIO_BANK8 0x01E260B0
#endif /* CONFIG_SOC_DA8XX */
struct davinci_gpio {
@@ -62,6 +63,7 @@ struct davinci_gpio_bank {
#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
+#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
#define gpio_status() gpio_info()
#define GPIO_NAME_SIZE 20
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 4/8] arm, davinci: add ddr2 definition
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
` (2 preceding siblings ...)
2011-09-15 5:59 ` [U-Boot] [PATCH 3/8] arm, davinci, am1808, gpio: add missing defines for bank 8 Heiko Schocher
@ 2011-09-15 5:59 ` Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 5/8] arm, davinci: add NOR Boot Configuration Word Heiko Schocher
` (3 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/include/asm/arch-davinci/ddr2_defs.h | 96 +++++++++++++++++++++++++
1 files changed, 96 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-davinci/ddr2_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
new file mode 100644
index 0000000..1b9430c
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_DDR2_DEFS_H_
+#define _DV_DDR2_DEFS_H_
+
+/*
+ * DDR2 Memory Ctrl Register structure
+ * See sprueh7d.pdf for more details.
+ */
+struct dv_ddr2_regs_ctrl {
+ unsigned char rsvd0[4]; /* 0x00 */
+ unsigned int sdrstat; /* 0x04 */
+ unsigned int sdbcr; /* 0x08 */
+ unsigned int sdrcr; /* 0x0C */
+ unsigned int sdtimr; /* 0x10 */
+ unsigned int sdtimr2; /* 0x14 */
+ unsigned char rsvd1[4]; /* 0x18 */
+ unsigned int sdbcr2; /* 0x1C */
+ unsigned int pbbpr; /* 0x20 */
+ unsigned char rsvd2[156]; /* 0x24 */
+ unsigned int irr; /* 0xC0 */
+ unsigned int imr; /* 0xC4 */
+ unsigned int imsr; /* 0xC8 */
+ unsigned int imcr; /* 0xCC */
+ unsigned char rsvd3[20]; /* 0xD0 */
+ unsigned int ddrphycr; /* 0xE4 */
+ unsigned int ddrphycr2; /* 0xE8 */
+ unsigned char rsvd4[4]; /* 0xEC */
+};
+
+#define DV_DDR_PHY_PWRDNEN 0x40
+#define DV_DDR_PHY_EXT_STRBEN 0x80
+#define DV_DDR_PHY_RD_LATENCY_SHIFT 0
+
+#define DV_DDR_SDTMR1_RFC_SHIFT 25
+#define DV_DDR_SDTMR1_RP_SHIFT 22
+#define DV_DDR_SDTMR1_RCD_SHIFT 19
+#define DV_DDR_SDTMR1_WR_SHIFT 16
+#define DV_DDR_SDTMR1_RAS_SHIFT 11
+#define DV_DDR_SDTMR1_RC_SHIFT 6
+#define DV_DDR_SDTMR1_RRD_SHIFT 3
+#define DV_DDR_SDTMR1_WTR_SHIFT 0
+
+#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
+#define DV_DDR_SDTMR2_XP_SHIFT 25
+#define DV_DDR_SDTMR2_XSNR_SHIFT 16
+#define DV_DDR_SDTMR2_XSRD_SHIFT 8
+#define DV_DDR_SDTMR2_RTP_SHIFT 5
+#define DV_DDR_SDTMR2_CKE_SHIFT 0
+
+#define DV_DDR_SDCR_DDR2TERM1_SHIFT 27
+#define DV_DDR_SDCR_IBANK_POS_SHIFT 26
+#define DV_DDR_SDCR_MSDRAMEN_SHIFT 25
+#define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24
+#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23
+#define DV_DDR_SDCR_DDR_DDQS_SHIFT 22
+#define DV_DDR_SDCR_DDR2EN_SHIFT 20
+#define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18
+#define DV_DDR_SDCR_DDREN_SHIFT 17
+#define DV_DDR_SDCR_SDRAMEN_SHIFT 16
+#define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15
+#define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14
+#define DV_DDR_SDCR_CL_SHIFT 9
+#define DV_DDR_SDCR_IBANK_SHIFT 4
+#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
+
+#define DV_DDR_SRCR_LPMODEN_SHIFT 31
+#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30
+
+#define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
+#define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
+
+#define dv_ddr2_regs_ctrl \
+ ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
+
+#endif /* _DV_DDR2_DEFS_H_ */
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 5/8] arm, davinci: add NOR Boot Configuration Word
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
` (3 preceding siblings ...)
2011-09-15 5:59 ` [U-Boot] [PATCH 4/8] arm, davinci: add ddr2 definition Heiko Schocher
@ 2011-09-15 5:59 ` Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR Heiko Schocher
` (2 subsequent siblings)
7 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
to add the "NOR Boot Configuration Word" on AM18xx based boards,
define CONFIG_SYS_DV_NOR_BOOT_CFG.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/cpu/arm926ejs/start.S | 9 +++++++++
doc/README.davinci | 9 +++++++++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 16e35c2..9d0e3d7 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -51,9 +51,18 @@
*/
+#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.globl _start
_start:
+.globl _NOR_BOOT_CFG
+_NOR_BOOT_CFG:
+ .word CONFIG_SYS_DV_NOR_BOOT_CFG
b reset
+#else
+.globl _start
+_start:
+ b reset
+#endif
#ifdef CONFIG_SPL_BUILD
/* No exception handlers in preloader */
ldr pc, _hang
diff --git a/doc/README.davinci b/doc/README.davinci
index 0204372..5f1bdc8 100644
--- a/doc/README.davinci
+++ b/doc/README.davinci
@@ -139,3 +139,12 @@ http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214
7) TI DA850 EVM
http://focus.ti.com/docs/prod/folders/print/omap-l138.html
http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
+
+Davinci special defines
+=======================
+
+CONFIG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode
+ need a "NOR Boot Configuration Word" stored
+ in the NOR Flash. This define adds this.
+ More Info about this, see:
+ spraba5a.pdf chapter 3.1
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
` (4 preceding siblings ...)
2011-09-15 5:59 ` [U-Boot] [PATCH 5/8] arm, davinci: add NOR Boot Configuration Word Heiko Schocher
@ 2011-09-15 5:59 ` Heiko Schocher
2011-09-26 8:02 ` Christian Riesch
2011-09-30 6:57 ` Christian Riesch
2011-09-15 5:59 ` [U-Boot] [PATCH 7/8] arm, davinci, da8xx: add cpuinfo Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 8/8] arm, davinci: add support for am1808 based enbw_cmc board Heiko Schocher
7 siblings, 2 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/cpu/arm926ejs/davinci/Makefile | 1 +
arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c | 428 ++++++++++++++++++++
.../arm/include/asm/arch-davinci/am1808_lowlevel.h | 44 ++
3 files changed, 473 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
create mode 100644 arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index b38623a..0310957 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-y += cpu.o timer.o psc.o
+COBJS-$(CONFIG_AM18018_LOWLEVEL) += am1808_lowlevel.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
new file mode 100644
index 0000000..1ea4a9f
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
@@ -0,0 +1,428 @@
+/*
+ * SoC-specific lowlevel code for AM1808 and similar chips
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/am1808_lowlevel.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+
+void am1808_waitloop(unsigned long loopcnt)
+{
+ unsigned long i;
+
+ for (i = 0; i < loopcnt; i++)
+ asm(" NOP");
+}
+
+int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
+{
+ if (reg == davinci_pllc0_regs)
+ /* Unlock PLL registers. */
+ clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010);
+
+ /*
+ * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
+ * through MMR
+ */
+ clrbits_le32(®->pllctl, 0x00000020);
+ /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
+ clrbits_le32(®->pllctl, 0x00000200);
+
+ /* Set PLLEN=0 => PLL BYPASS MODE */
+ clrbits_le32(®->pllctl, 0x00000001);
+
+ am1808_waitloop(150);
+
+ if (reg == davinci_pllc0_regs) {
+ /*
+ * Select the Clock Mode bit 8 as External Clock or On Chip
+ * Oscilator
+ */
+ dv_maskbits(®->pllctl, 0xFFFFFEFF);
+ setbits_le32(®->pllctl, (CONFIG_SYS_DV_CLKMODE << 8));
+ }
+
+ /* Clear PLLRST bit to reset the PLL */
+ clrbits_le32(®->pllctl, 0x00000008);
+
+ /* Disable the PLL output */
+ setbits_le32(®->pllctl, 0x00000010);
+
+ /* PLL initialization sequence */
+ /*
+ * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
+ * power down bit
+ */
+ clrbits_le32(®->pllctl, 0x00000002);
+
+ /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
+ clrbits_le32(®->pllctl, 0x00000010);
+
+ /* Program the required multiplier value in PLLM */
+ writel(pllmult, ®->pllm);
+
+ /* program the postdiv */
+ if (reg == davinci_pllc0_regs)
+ writel((0x8000 | CONFIG_SYS_AM1808_PLL0_POSTDIV),
+ ®->postdiv);
+ else
+ writel((0x8000 | CONFIG_SYS_AM1808_PLL1_POSTDIV),
+ ®->postdiv);
+
+ /*
+ * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
+ * no GO operation is currently in progress
+ */
+ while ((readl(®->pllstat) & 0x1) == 1)
+ ;
+
+ if (reg == davinci_pllc0_regs) {
+ writel(CONFIG_SYS_AM1808_PLL0_PLLDIV1, ®->plldiv1);
+ writel(CONFIG_SYS_AM1808_PLL0_PLLDIV2, ®->plldiv2);
+ writel(CONFIG_SYS_AM1808_PLL0_PLLDIV3, ®->plldiv3);
+ writel(CONFIG_SYS_AM1808_PLL0_PLLDIV4, ®->plldiv4);
+ writel(CONFIG_SYS_AM1808_PLL0_PLLDIV5, ®->plldiv5);
+ writel(CONFIG_SYS_AM1808_PLL0_PLLDIV6, ®->plldiv6);
+ writel(CONFIG_SYS_AM1808_PLL0_PLLDIV7, ®->plldiv7);
+ } else {
+ writel(CONFIG_SYS_AM1808_PLL1_PLLDIV1, ®->plldiv1);
+ writel(CONFIG_SYS_AM1808_PLL1_PLLDIV2, ®->plldiv2);
+ writel(CONFIG_SYS_AM1808_PLL1_PLLDIV3, ®->plldiv3);
+ }
+
+ /*
+ * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
+ * transition.
+ */
+ setbits_le32(®->pllcmd, 0x01);
+
+ /*
+ * Wait for the GOSTAT bit in PLLSTAT to clear to 0
+ * (completion of phase alignment).
+ */
+ while ((readl(®->pllstat) & 0x1) == 1)
+ ;
+
+ /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
+ am1808_waitloop(200);
+
+ /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
+ setbits_le32(®->pllctl, 0x00000008);
+
+ /* Wait for PLL to lock. See PLL spec for PLL lock time */
+ am1808_waitloop(2400);
+
+ /*
+ * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
+ * mode
+ */
+ setbits_le32(®->pllctl, 0x00000001);
+
+
+ /*
+ * clear EMIFA and EMIFB clock source settings, let them
+ * run off SYSCLK
+ */
+ if (reg == davinci_pllc0_regs)
+ dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8);
+
+ return 0;
+}
+
+void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
+ unsigned char domain, unsigned char state)
+{
+ struct davinci_psc_regs *reg;
+ dv_reg_p mdstat, mdctl;
+
+ if (pscnum == 0) {
+ reg = davinci_psc0_regs;
+ mdstat = ®->psc0.mdstat[module];
+ mdctl = ®->psc0.mdctl[module];
+ } else {
+ reg = davinci_psc1_regs;
+ mdstat = ®->psc1.mdstat[module];
+ mdctl = ®->psc1.mdctl[module];
+ }
+
+ /* Wait for any outstanding transition to complete */
+ while ((readl(®->ptstat) & (0x00000001 << domain)))
+ ;
+
+ /* If we are already in that state, just return */
+ if ((readl(mdstat) & 0x1F) == state)
+ return;
+
+ /* Perform transition */
+ writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
+ setbits_le32(®->ptcmd, (0x00000001 << domain));
+
+ /* Wait for transition to complete */
+ while (readl(®->ptstat) & (0x00000001 << domain))
+ ;
+
+ /* Wait and verify the state */
+ while ((readl(mdstat) & 0x1F) != state)
+ ;
+}
+
+int am1808_ddr_setup(unsigned int freq)
+{
+ unsigned long tmp;
+
+ /* Enable the Clock to DDR2/mDDR */
+ am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
+
+ tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+ if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
+ /* Begin VTP Calibration */
+ clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+ clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+ clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+
+ /* Polling READY bit to see when VTP calibration is done */
+ tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+ while ((tmp & VTP_READY) != VTP_READY)
+ tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
+ }
+
+ writel(CONFIG_SYS_AM1808_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+ clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+ (1 << DDR_SLEW_CMOSEN_BIT));
+
+ setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
+
+ writel((CONFIG_SYS_AM1808_DDR2_SDBCR & ~0xf0000000) |
+ (readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/
+ &dv_ddr2_regs_ctrl->sdbcr);
+ writel(CONFIG_SYS_AM1808_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+
+ writel(CONFIG_SYS_AM1808_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+ writel(CONFIG_SYS_AM1808_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+ clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr,
+ (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT));
+
+ /*
+ * LPMODEN and MCLKSTOPEN must be set!
+ * Without this bits set, PSC don;t switch states !!
+ */
+ writel(CONFIG_SYS_AM1808_DDR2_SDRCR |
+ (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
+ (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
+ &dv_ddr2_regs_ctrl->sdrcr);
+
+ /* SyncReset the Clock to EMIF3A SDRAM */
+ am1808_lpc_transition(1, 6, 0, PSC_SYNCRESET);
+ /* Enable the Clock to EMIF3A SDRAM */
+ am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
+
+ /* disable self refresh */
+ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
+ writel(0x30, &dv_ddr2_regs_ctrl->pbbpr);
+
+ return 0;
+}
+
+static void am1808_set_mdctl(dv_reg_p mdctl)
+{
+ if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
+ writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
+}
+
+void am1808_psc_init(void)
+{
+ struct davinci_psc_regs *reg;
+ int i;
+
+ /* PSC 0 domain 0 init */
+ reg = davinci_psc0_regs;
+ while ((readl(®->ptstat) & 0x00000001))
+ ;
+
+ for (i = 3; i <= 4 ; i++)
+ am1808_set_mdctl(®->psc0.mdctl[i]);
+
+ for (i = 7; i <= 12 ; i++)
+ am1808_set_mdctl(®->psc0.mdctl[i]);
+
+ /* Do Always-On Power Domain Transitions */
+ setbits_le32(®->ptcmd, 0x00000001);
+ while (readl(®->ptstat) & 0x00000001)
+ ;
+
+ /* PSC1, domain 1 init */
+ reg = davinci_psc1_regs;
+ while ((readl(®->ptstat) & 0x00000001))
+ ;
+
+ am1808_set_mdctl(®->psc1.mdctl[3]);
+ am1808_set_mdctl(®->psc1.mdctl[6]);
+
+ /* UART1 + UART2 */
+ for (i = 12 ; i <= 13 ; i++)
+ am1808_set_mdctl(®->psc1.mdctl[i]);
+
+ am1808_set_mdctl(®->psc1.mdctl[26]);
+ am1808_set_mdctl(®->psc1.mdctl[31]);
+
+ /* Do Always-On Power Domain Transitions */
+ setbits_le32(®->ptcmd, 0x00000001);
+ while (readl(®->ptstat) & 0x00000001)
+ ;
+}
+
+void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value)
+{
+ clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
+ setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+ return;
+}
+
+#if defined(CONFIG_NAND_SPL)
+void nand_boot(void)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ /* copy image from NOR to RAM */
+ memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST,
+ (void *)CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE);
+
+ /* and jump to it ... */
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ (*uboot)();
+}
+#endif
+
+#if defined(CONFIG_NAND_SPL)
+void board_init_f(ulong bootflag)
+#else
+int arch_cpu_init(void)
+#endif
+{
+ /*
+ * copied from arch/arm/cpu/arm926ejs/start.S
+ *
+ * flush v4 I/D caches
+ */
+ asm("mov r0, #0");
+ asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
+ asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ asm("mrc p15, 0, r0, c1, c0, 0");
+ /* clear bits 13, 9:8 (--V- --RS) */
+ asm("bic r0, r0, #0x00002300");
+ /* clear bits 7, 2:0 (B--- -CAM) */
+ asm("bic r0, r0, #0x00000087");
+ /* set bit 2 (A) Align */
+ asm("orr r0, r0, #0x00000002");
+ /* set bit 12 (I) I-Cache */
+ asm("orr r0, r0, #0x00001000");
+ asm("mcr p15, 0, r0, c1, c0, 0");
+
+ /* Unlock kick registers */
+ writel(0x83e70b13, &davinci_syscfg_regs->kick0);
+ writel(0x95a4f1e0, &davinci_syscfg_regs->kick1);
+
+ dv_maskbits(&davinci_syscfg_regs->suspsrc,
+ ((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16)));
+
+ /* System PSC setup - enable all */
+ am1808_psc_init();
+
+ /* Setup Pinmux */
+ am1808_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX0);
+ am1808_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX1);
+ am1808_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX2);
+ am1808_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX3);
+ am1808_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX4);
+ am1808_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX5);
+ am1808_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX6);
+ am1808_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX7);
+ am1808_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX8);
+ am1808_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX9);
+ am1808_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX10);
+ am1808_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX11);
+ am1808_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX12);
+ am1808_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX13);
+ am1808_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX14);
+ am1808_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX15);
+ am1808_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX16);
+ am1808_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX17);
+ am1808_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX18);
+ am1808_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX19);
+
+ /* PLL setup */
+ am1808_pll_init(davinci_pllc0_regs, CONFIG_SYS_AM1808_PLL0_PLLM);
+ am1808_pll_init(davinci_pllc1_regs, CONFIG_SYS_AM1808_PLL1_PLLM);
+
+ /* GPIO setup */
+ board_gpio_init();
+
+ /* setup CSn config */
+ writel(CONFIG_SYS_AM1808_CS2CFG, &davinci_emif_regs->ab1cr);
+ writel(CONFIG_SYS_AM1808_CS3CFG, &davinci_emif_regs->ab2cr);
+
+ am1808_lpc_transition(1, 13, 0, PSC_ENABLE);
+ NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+ /*
+ * Fix Power and Emulation Management Register
+ * see sprufw3a.pdf page 37 Table 24
+ */
+ writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001,
+ (CONFIG_SYS_NS16550_COM1 + 0x30));
+#if defined(CONFIG_NAND_SPL)
+ puts("ddr init\n");
+ am1808_ddr_setup(132);
+
+ puts("boot u-boot ...\n");
+
+ nand_boot();
+#else
+ am1808_ddr_setup(132);
+ return 0;
+#endif
+}
diff --git a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h b/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
new file mode 100644
index 0000000..0bc7f76
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
@@ -0,0 +1,44 @@
+/*
+ * SoC-specific lowlevel code for AM1808 and similar chips
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __AM1808_LOWLEVEL_H
+#define __AM1808_LOWLEVEL_H
+
+/* NOR Boot Configuration Word Field Descriptions */
+#define AM1808_NORBOOT_COPY_XK(X) ((X - 1) << 8)
+#define AM1808_NORBOOT_METHOD_DIRECT (1 << 4)
+#define AM1808_NORBOOT_16BIT (1 << 0)
+
+#define dv_maskbits(addr, val) \
+ writel((readl(addr) & val), addr)
+
+void am1808_waitloop(unsigned long loopcnt);
+int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
+void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
+ unsigned char domain, unsigned char state);
+int am1808_ddr_setup(unsigned int freq);
+void am1808_psc_init(void);
+void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value);
+
+#endif /* #ifndef __AM1808_LOWLEVEL_H */
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 7/8] arm, davinci, da8xx: add cpuinfo
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
` (5 preceding siblings ...)
2011-09-15 5:59 ` [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR Heiko Schocher
@ 2011-09-15 5:59 ` Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 8/8] arm, davinci: add support for am1808 based enbw_cmc board Heiko Schocher
7 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/cpu/arm926ejs/davinci/cpu.c | 16 ++++++++++++++--
1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index b705dfd..02819f6 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -115,7 +115,18 @@ int clk_get(enum davinci_clk_ids id)
out:
return pll_out;
}
-#endif /* CONFIG_SOC_DA8XX */
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ printf("Cores: ARM %d MHz",
+ clk_get(DAVINCI_ARM_CLKID) / 1000000);
+ printf("\nDDR: %d MHz\n",
+ /* DDR PHY uses an x2 input clock */
+ clk_get(0x10001) / 1000000);
+ return 0;
+}
+#endif
+#else /* CONFIG_SOC_DA8XX */
#ifdef CONFIG_DISPLAY_CPUINFO
@@ -194,7 +205,8 @@ unsigned int davinci_arm_clk_get()
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
}
#endif
-#endif
+#endif /* CONFIG_DISPLAY_CPUINFO */
+#endif /* !CONFIG_SOC_DA8XX */
/*
* Initializes on-chip ethernet controllers.
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
` (6 preceding siblings ...)
2011-09-15 5:59 ` [U-Boot] [PATCH 7/8] arm, davinci, da8xx: add cpuinfo Heiko Schocher
@ 2011-09-15 5:59 ` Heiko Schocher
2011-09-15 7:39 ` Igor Grinberg
2011-09-19 5:50 ` [U-Boot] [PATCH v2 " Heiko Schocher
7 siblings, 2 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 5:59 UTC (permalink / raw)
To: u-boot
- booting from NOR Flash with direct boot method
- POST support
- LOGBUF support
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
board/enbw/enbw_cmc/Makefile | 51 ++++
board/enbw/enbw_cmc/enbw_cmc.c | 574 ++++++++++++++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/enbw_cmc.h | 440 ++++++++++++++++++++++++++++++
4 files changed, 1066 insertions(+), 0 deletions(-)
create mode 100644 board/enbw/enbw_cmc/Makefile
create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
create mode 100644 include/configs/enbw_cmc.h
diff --git a/board/enbw/enbw_cmc/Makefile b/board/enbw/enbw_cmc/Makefile
new file mode 100644
index 0000000..bdba069
--- /dev/null
+++ b/board/enbw/enbw_cmc/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
new file mode 100644
index 0000000..1b9ee67
--- /dev/null
+++ b/board/enbw/enbw_cmc/enbw_cmc.c
@@ -0,0 +1,574 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/timer_defs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+/* missing functions from board/davinci/common/misc.c */
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
+{
+ /*
+ * Mask all IRQs by clearing the global enable and setting
+ * the enable clear for all the 90 interrupts.
+ */
+
+ writel(0, &davinci_aintc_regs->ger);
+
+ writel(0, &davinci_aintc_regs->hier);
+
+ writel(0xffffffff, &davinci_aintc_regs->ecr1);
+ writel(0xffffffff, &davinci_aintc_regs->ecr2);
+ writel(0xffffffff, &davinci_aintc_regs->ecr3);
+}
+#endif
+
+void davinci_emac_mii_mode_sel(int mode_sel)
+{
+ int val;
+
+ val = readl(&davinci_syscfg_regs->cfgchip3);
+ if (mode_sel == 0)
+ val &= ~(1 << 8);
+ else
+ val |= (1 << 8);
+ writel(val, &davinci_syscfg_regs->cfgchip3);
+}
+
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+ const int n_items)
+{
+ int i;
+
+ for (i = 0; i < n_items; i++)
+ lpsc_on(item[i].lpsc_no);
+
+ return 0;
+}
+
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ const int n_items)
+{
+ return 0;
+}
+
+static void enbw_cmc_switch(int port, int on)
+{
+ const char *devname;
+ unsigned char phyaddr = 3;
+ unsigned char reg = 0;
+ unsigned short data;
+
+ if (port == 1)
+ phyaddr = 2;
+
+ devname = miiphy_get_current_dev();
+ if (!devname) {
+ printf("Error: no mii device\n");
+ return;
+ }
+ if (miiphy_read(devname, phyaddr, reg, &data) != 0) {
+ printf("Error reading from the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+ if (on)
+ data &= ~0x0800;
+ else
+ data |= 0x0800;
+
+ if (miiphy_write(devname, phyaddr, reg, data) != 0) {
+ printf("Error writing to the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+}
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+
+ /* arch number of the board */
+ gd->bd->bi_arch_number = 3585;
+
+ /* address of boot parameters, not used as booting with DTT */
+ gd->bd->bi_boot_params = 0;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ clrbits_le32(&davinci_syscfg_regs->suspsrc,
+ (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2));
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ davinci_emac_mii_mode_sel(0);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ if (hwconfig_subarg_cmp("switch", "lan", "on"))
+ /* Switch port lan on */
+ enbw_cmc_switch(1, 1);
+ else
+ enbw_cmc_switch(1, 0);
+
+ if (hwconfig_subarg_cmp("switch", "pwl", "on"))
+ /* Switch port pwl on */
+ enbw_cmc_switch(2, 1);
+ else
+ enbw_cmc_switch(2, 0);
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size(
+ (long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_PREBOOT
+static uchar kbd_magic_prefix[] = "key_magic_";
+static uchar kbd_command_prefix[] = "key_cmd_";
+
+struct kbd_data_t {
+ char s1;
+};
+
+struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank01;
+ unsigned long reg;
+
+ /* read SW1 + SW2 */
+ reg = readl(&gpio->in_data);
+ kbd_data->s1 = ((reg & 0x00003000) >> 12);
+ return kbd_data;
+}
+
+static int compare_magic(const struct kbd_data_t *kbd_data, char *str)
+{
+ char s1 = str[0];
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s1)
+ return -1;
+
+ return 0;
+}
+
+static char *key_match(const struct kbd_data_t *kbd_data)
+{
+ char magic[sizeof(kbd_magic_prefix) + 1];
+ char *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ kbd_magic_keys = getenv("magic_keys");
+ if (kbd_magic_keys == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+
+ if (compare_magic(kbd_data, getenv(magic)) == 0) {
+ char cmd_name[sizeof(kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv(cmd_name);
+
+ return cmd;
+ }
+ }
+
+ return NULL;
+}
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_PREBOOT
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ char *str = strdup(key_match(get_keys(&kbd_data)));
+ /* Set or delete definition */
+ setenv("preboot", str);
+ free(str);
+#endif /* CONFIG_PREBOOT */
+
+#ifdef CONFIG_HW_WATCHDOG
+ davinci_hw_watchdog_enable();
+#endif
+
+ return 0;
+}
+
+struct cmc_led {
+ char name[20];
+ struct davinci_gpio *gpio;
+ unsigned long mask;
+};
+
+struct cmc_led led_table[] = {
+ {"led1", davinci_gpio_bank01, 0x80000000},
+ {"led2", davinci_gpio_bank01, 0x00000002},
+ {"led3", davinci_gpio_bank01, 0x00000004},
+ {"led4", davinci_gpio_bank01, 0x00000008},
+ {"led5", davinci_gpio_bank01, 0x00000010},
+ {"led6", davinci_gpio_bank01, 0x00000020},
+ {"led7", davinci_gpio_bank01, 0x00000040},
+ {"led8", davinci_gpio_bank01, 0x00004000},
+};
+
+static int cmc_get_led_state(struct cmc_led *led)
+{
+ struct davinci_gpio *gpio = led->gpio;
+ unsigned long reg;
+
+ /* read SW1 + SW2 */
+ reg = readl(&gpio->in_data);
+ if ((reg & led->mask) == led->mask)
+ return 1;
+
+ return 0;
+}
+
+static int cmc_set_led_state(struct cmc_led *led, int state)
+{
+ struct davinci_gpio *gpio = led->gpio;
+ unsigned long reg;
+
+ reg = readl(&gpio->out_data);
+ if (state)
+ reg |= led->mask;
+ else
+ reg &= ~led->mask;
+
+ writel(reg, &gpio->out_data);
+ return 0;
+}
+
+static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct cmc_led *led;
+ int found = 0;
+ int i = 0;
+ int only_print = 0;
+ int len = ARRAY_SIZE(led_table);
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if (argc < 3)
+ only_print = 1;
+
+ led = led_table;
+ while ((!found) && (i < len)) {
+ if (strcmp(argv[1], led->name) == 0) {
+ found = 1;
+ } else {
+ led++;
+ i++;
+ }
+ }
+ if (!found)
+ return cmd_usage(cmdtp);
+
+ if (only_print) {
+ if (cmc_get_led_state(led))
+ printf("on\n");
+ else
+ printf("off\n");
+
+ return 0;
+ }
+ if (strcmp(argv[2], "on") == 0)
+ cmc_set_led_state(led, 1);
+ else
+ cmc_set_led_state(led, 0);
+
+ return 0;
+}
+
+U_BOOT_CMD(led, 3, 1, do_led,
+ "switch on/off board led",
+ "[name] [on/off]"
+);
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ davinci_hw_watchdog_reset();
+}
+#endif
+
+#if defined(CONFIG_POST)
+void arch_memory_failure_handle(void)
+{
+ int state = 1;
+
+ printf("%s: blinking with LEDs\n", __func__);
+ while (1) {
+ cmc_set_led_state(&led_table[0], state);
+ cmc_set_led_state(&led_table[1], state);
+ cmc_set_led_state(&led_table[2], state);
+ if (state)
+ state = 0;
+ else
+ state = 1;
+ udelay(500);
+ }
+}
+#endif
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void bootcount_store(ulong a)
+{
+ void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ /*
+ * write RTC kick register to enable write
+ * for RTC Scratch registers. Cratch0 and 1 are
+ * used for bootcount values.
+ */
+ out_be32(reg + 0x0c, 0x130be783);
+ out_be32(reg + 0x10, 0xe0f1a495);
+ out_be32(reg, a);
+ out_be32(reg + 4, BOOTCOUNT_MAGIC);
+}
+
+ulong bootcount_load(void)
+{
+ void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ if (in_be32(reg + 4) != BOOTCOUNT_MAGIC)
+ return 0;
+ else
+ return in_be32(reg);
+}
+#endif
+
+void board_gpio_init(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank8;
+
+ /*
+ * Counter IF: RS485 enable, low enable
+ * GP8[11] = Out[9] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000800);
+ clrbits_le32(&gpio->out_data, 0x00000800);
+ /*
+ * Counter IF: Isolation RS485
+ * GP8[10] = Out[10] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000400);
+ clrbits_le32(&gpio->out_data, 0x00000400);
+ /*
+ * W2HUT: RS485 Rx enable:
+ * GP8[9] = Out[11] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000200);
+ clrbits_le32(&gpio->out_data, 0x00000200);
+ /*
+ * W2HUT: Isolation RS485:
+ * GP8[8] = Out[12] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000100);
+ clrbits_le32(&gpio->out_data, 0x00000100);
+
+ gpio = davinci_gpio_bank67;
+ /*
+ * SW Reset 4 port LAN switch
+ * GP7[15] = Out[4] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x80000000);
+ setbits_le32(&gpio->out_data, 0x80000000);
+ /*
+ * Enable 11V PLC Vaa, high active
+ * GP7[14] = Out[3] set to output state 0
+ */
+ clrbits_le32(&gpio->dir, 0x40000000);
+ clrbits_le32(&gpio->out_data, 0x40000000);
+ /*
+ * Enable 1.5V PLC Core, high active
+ * GP7[13] = Out[2] set to output state 0
+ */
+ clrbits_le32(&gpio->dir, 0x20000000);
+ clrbits_le32(&gpio->out_data, 0x20000000);
+ /*
+ * Disable USB0 VBUS, low active
+ * GP7[12] = Out[2] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x10000000);
+ setbits_le32(&gpio->out_data, 0x10000000);
+ /*
+ * SW_reset for PLC modul, low active
+ * GP6[13] = Out[5] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x00002000);
+ setbits_le32(&gpio->out_data, 0x00002000);
+ /*
+ * LCM Bus Signal RS; R/W and E
+ * GP6[12..11] = Out[6..7]
+ */
+ clrbits_le32(&gpio->dir, 0x00001800);
+ clrbits_le32(&gpio->out_data, 0x00001800);
+ /*
+ * Pairing-button for PLC Modul = Out[18]
+ */
+ clrbits_le32(&gpio->dir, 0x00000400);
+ clrbits_le32(&gpio->out_data, 0x00000400);
+ /*
+ * PLC MDIO CLK
+ * GP6[9] = Out[14]
+ */
+ clrbits_le32(&gpio->dir, 0x00000200);
+ clrbits_le32(&gpio->out_data, 0x00000200);
+ /*
+ * HK218, active high
+ * GP6[8] = Out[15], set to 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000100);
+ clrbits_le32(&gpio->out_data, 0x00000100);
+ /*
+ * SW reset TPM ctrl., active low
+ * GP6[0] = Out[13], set to 1
+ */
+ clrbits_le32(&gpio->dir, 0x00000001);
+ setbits_le32(&gpio->out_data, 0x00000001);
+
+ gpio = davinci_gpio_bank23;
+ /*
+ * LCM: Signal E
+ * GP2[2] = Out[8]
+ */
+ clrbits_le32(&gpio->dir, 0x00000004);
+ setbits_le32(&gpio->out_data, 0x00000004);
+
+ gpio = davinci_gpio_bank01;
+ /*
+ * PV-IF RS485 RxD Enable\
+ */
+ clrbits_le32(&gpio->dir, 0x00008000);
+ clrbits_le32(&gpio->out_data, 0x00008000);
+ /*
+ * set LED pins to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x8000407e);
+ clrbits_le32(&gpio->out_data, 0x8000407e);
+
+ /*
+ * Set the LED 1 - 4 to on
+ */
+ cmc_set_led_state(&led_table[1], 1);
+ cmc_set_led_state(&led_table[2], 1);
+ cmc_set_led_state(&led_table[3], 1);
+ cmc_set_led_state(&led_table[4], 1);
+ return;
+}
diff --git a/boards.cfg b/boards.cfg
index 8a5bfc1..7db43fa 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -128,6 +128,7 @@ davinci_dvevm arm arm926ejs dvevm davinci
davinci_schmoogie arm arm926ejs schmoogie davinci davinci
davinci_sffsdr arm arm926ejs sffsdr davinci davinci
davinci_sonata arm arm926ejs sonata davinci davinci
+enbw_cmc arm arm926ejs enbw_cmc enbw davinci
km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI
km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood
mgcoge3un arm arm926ejs km_arm keymile kirkwood
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
new file mode 100644
index 0000000..5de752f
--- /dev/null
+++ b/include/configs/enbw_cmc.h
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_NAND
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_AM18018_LOWLEVEL
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_HOSTNAME enbw_cmc
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+#define CONFIG_CMD_I2C
+
+#define CONFIG_CMD_DTT
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=" \
+ "physmap-flash.0:" \
+ "512k(U-Boot)," \
+ "64k(env1)," \
+ "64k(env2)," \
+ "-(rest);" \
+ "davinci_nand.1:" \
+ "128k(dtb)," \
+ "2m(kernel)," \
+ "4m(rootfs)," \
+ "-(userfs)"
+
+
+#define CONFIG_CMD_MTDPARTS
+
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 2
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_BASE 0x60000000
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_FLASH_SHOW_PROGRESS 99
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
+ CONFIG_ENV_SECT_SIZE)
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u-boot_addr_r=c0000000\0" \
+ "uboot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${u-boot_addr_r} ${uboot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
+ "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE) \
+ " ${filesize};" \
+ "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk-arm/arm\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "kernel_addr_r=c0700000\0" \
+ "fdt_addr_r=c0600000\0" \
+ "ramdisk_addr_r=c0a00000\0" \
+ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
+ xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 220000 400000;\0" \
+ "nand_ld_kernel=nand read ${kernel_addr_r} 20000 200000;\0" \
+ "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000;\0" \
+ "load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
+ "load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
+ "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyS2," \
+ "${baudrate}n8\0" \
+ "net_nfs=run load_fdt load_kernel; " \
+ "run nfsargs addip addcon addmtd;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "flash_self=run load_nand ramargs addip addcon;bootm " \
+ "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+ "bootcmd=run net_nfs\0" \
+ "machid=e01\0" \
+ "key_cmd0=echo hallo0\0" \
+ "key_cmd1=echo hallo1\0" \
+ "key_cmd2=echo hallo2\0" \
+ "key_cmd3=echo hallo3\0" \
+ "key_magic_0=0\0" \
+ "key_magic_1=1\0" \
+ "key_magic_2=2\0" \
+ "key_magic_3=3\0" \
+ "magic_keys=0123\0" \
+ "hwconfig=switch:lan=on,pwl=off\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "\0"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_HWCONFIG
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+#define CONFIG_MISC_INIT_R 1
+
+#define CONFIG_CMC_RESET_PIN 0x04000000
+#define CONFIG_CMC_RESET_TIMEOUT 3
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
+#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
+#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
+
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_DAVINCI
+
+/* FDT support */
+#define CONFIG_OF_LIBFDT 1
+
+/* LowLevel Init */
+/* PLL */
+#define CONFIG_SYS_DV_CLKMODE 0
+#define CONFIG_SYS_AM1808_PLL0_POSTDIV 1
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV1 0x8000
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV2 0x8001
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV3 0x8002 /* 100MHz */
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV4 0x8003
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV5 0x8002
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV6 CONFIG_SYS_AM1808_PLL0_PLLDIV1
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV7 0x8005
+
+#define CONFIG_SYS_AM1808_PLL1_POSTDIV 1
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV1 0x8000
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV2 0x8001
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV3 0x8002
+
+#define CONFIG_SYS_AM1808_PLL0_PLLM 37 /* PLL0 -> 456 MHz */
+#define CONFIG_SYS_AM1808_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
+
+/* DDR RAM */
+#define CONFIG_SYS_AM1808_DDR2_DDRPHYCR (0 | \
+ (0x1 << 7) | \
+ (0x1 << 6) | \
+ (0x4 << 0))
+
+#define CONFIG_SYS_AM1808_DDR2_SDBCR (0 | \
+ (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
+ (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
+ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
+ (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
+ (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
+ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+#define CONFIG_SYS_AM1808_DDR2_SDBCR2 4 /* 13 row address bits */
+
+/*
+ * freq = 132MHz -> t = 8ns
+ */
+#define CONFIG_SYS_AM1808_DDR2_SDTIMR (0 | \
+ (0x0c << 25) | /* tRFC = 105 105/8 = 13 - 1 = 0xc */ \
+ (1 << 22) | /* tRP 15/8 = 2 - 1 = 1 */ \
+ (1 << 19) | /* tRCD 15/8 = 2 - 1 = 1 */ \
+ (1 << 16) | /* tWR 15/8 = 2 - 1 = 1 */ \
+ (5 << 11) | /* tRAS 45/8 = 6 - 1 = 5 */ \
+ (7 << 6) | /* tRC 60/8 = 8 - 1 = 7 */ \
+ (1 << 3) | /* tRRD 12/8 = 2 -1 = 1 */ \
+ (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
+ ((2 - 1) << 0)) /* tWTR 7.5 ns min 2 clocks */
+
+/*
+ * freq = 132MHz -> t=8ns
+ */
+#define CONFIG_SYS_AM1808_DDR2_SDTIMR2 (0 | \
+ (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
+ (8 << 27) | /* tRASMAX [(70us/7800ns)-1] */ \
+ (2 << 25) | /* tXP = 2, tCKe = 3 -> 3 - 1 = 2 */ \
+ (0 << 23) | /* tODT (Not supported) */ \
+ (13 << 16) | /* tXSNR = tRFC + 10 = 115 115/8 = 14 - 1 = 13 */ \
+ (24 << 8) | /* tXSRD = 200 200/8 = 25 - 1 = 24 */ \
+ (0 << 5) | /* tRTP = 7.5 7.5/8 = 1 - 1 = 0 */ \
+ (2 << 0)) /* tCKE = 3 -> 3 - 1 = 2 */
+
+#define CONFIG_SYS_AM1808_DDR2_SDRCR 0x00000407
+
+/*
+ * with Pin Setup Utility from TI
+ * missing GPIO pin setup
+ */
+#define CONFIG_SYS_AM1808_PINMUX0 0x44448888
+#define CONFIG_SYS_AM1808_PINMUX1 0x48888884
+#define CONFIG_SYS_AM1808_PINMUX2 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX3 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX4 0x22222288
+#define CONFIG_SYS_AM1808_PINMUX5 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX6 0x11818811
+#define CONFIG_SYS_AM1808_PINMUX7 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX8 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX9 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX10 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX11 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX12 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX13 0x88888800
+#define CONFIG_SYS_AM1808_PINMUX14 0x00000088
+#define CONFIG_SYS_AM1808_PINMUX15 0x00000000
+#define CONFIG_SYS_AM1808_PINMUX16 0x88888880
+#define CONFIG_SYS_AM1808_PINMUX17 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX18 0x88022288
+#define CONFIG_SYS_AM1808_PINMUX19 0x08022288
+
+#define CONFIG_SYS_AM1808_CS2CFG 0x08624311
+#define CONFIG_SYS_AM1808_CS3CFG 0x04222310
+
+/*
+ * NOR Bootconfiguration word:
+ * Method: Direc boot
+ * EMIFA access mode: 16 Bit
+ */
+#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
+
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
+#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x01c23060
+
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_DCACHE_OFF
+#endif /* __CONFIG_H */
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-15 5:59 ` [U-Boot] [PATCH 8/8] arm, davinci: add support for am1808 based enbw_cmc board Heiko Schocher
@ 2011-09-15 7:39 ` Igor Grinberg
2011-09-15 7:56 ` Heiko Schocher
2011-09-19 5:50 ` [U-Boot] [PATCH v2 " Heiko Schocher
1 sibling, 1 reply; 31+ messages in thread
From: Igor Grinberg @ 2011-09-15 7:39 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 09/15/11 08:59, Heiko Schocher wrote:
> - booting from NOR Flash with direct boot method
> - POST support
> - LOGBUF support
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
> Cc: Paulraj Sandeep <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
[...]
> diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
> new file mode 100644
> index 0000000..1b9ee67
> --- /dev/null
> +++ b/board/enbw/enbw_cmc/enbw_cmc.c
[...]
> +
> +int board_init(void)
> +{
> +#ifndef CONFIG_USE_IRQ
> + irq_init();
> +#endif
> +
> + /* arch number of the board */
> + gd->bd->bi_arch_number = 3585;
There is a new standard option for assigning the machid.
Now, this should be done in the board config file and the above two lines removed.
Please, see the CONFIG_MACH_TYPE in the U-Boot documentation (README file).
[...]
> diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
> new file mode 100644
> index 0000000..5de752f
> --- /dev/null
> +++ b/include/configs/enbw_cmc.h
[...]
> +/*
> + * Board
> + */
> +#define CONFIG_DRIVER_TI_EMAC
> +#define CONFIG_USE_NAND
Consider adding here:
#define MACH_TYPE_ENBW_CMC 3585
#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
[...]
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-15 7:39 ` Igor Grinberg
@ 2011-09-15 7:56 ` Heiko Schocher
0 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-15 7:56 UTC (permalink / raw)
To: u-boot
Hello Igor,
Igor Grinberg wrote:
> Hi Heiko,
>
> On 09/15/11 08:59, Heiko Schocher wrote:
>> - booting from NOR Flash with direct boot method
>> - POST support
>> - LOGBUF support
>>
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>> Cc: Paulraj Sandeep <s-paulraj@ti.com>
>> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
>> ---
>
> [...]
>
>> diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
>> new file mode 100644
>> index 0000000..1b9ee67
>> --- /dev/null
>> +++ b/board/enbw/enbw_cmc/enbw_cmc.c
>
> [...]
>
>> +
>> +int board_init(void)
>> +{
>> +#ifndef CONFIG_USE_IRQ
>> + irq_init();
>> +#endif
>> +
>> + /* arch number of the board */
>> + gd->bd->bi_arch_number = 3585;
>
> There is a new standard option for assigning the machid.
> Now, this should be done in the board config file and the above two lines removed.
> Please, see the CONFIG_MACH_TYPE in the U-Boot documentation (README file).
Ah, thanks!
> [...]
>
>> diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
>> new file mode 100644
>> index 0000000..5de752f
>> --- /dev/null
>> +++ b/include/configs/enbw_cmc.h
>
> [...]
>
>> +/*
>> + * Board
>> + */
>> +#define CONFIG_DRIVER_TI_EMAC
>> +#define CONFIG_USE_NAND
>
> Consider adding here:
> #define MACH_TYPE_ENBW_CMC 3585
> #define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
Yep! Change this for v2, thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-15 5:59 ` [U-Boot] [PATCH 8/8] arm, davinci: add support for am1808 based enbw_cmc board Heiko Schocher
2011-09-15 7:39 ` Igor Grinberg
@ 2011-09-19 5:50 ` Heiko Schocher
2011-09-23 20:47 ` Paulraj, Sandeep
2011-09-30 7:55 ` Christian Riesch
1 sibling, 2 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-19 5:50 UTC (permalink / raw)
To: u-boot
- booting from NOR Flash with direct boot method
- POST support
- LOGBUF support
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
- changes for v2
- use CONFIG_MACH_TYPE instead setting the MACH_TYPE in
board specific code, as Igor Grinberg suggested.
- add logversion=2 to default Environment
board/enbw/enbw_cmc/Makefile | 51 ++++
board/enbw/enbw_cmc/enbw_cmc.c | 570 ++++++++++++++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/enbw_cmc.h | 443 +++++++++++++++++++++++++++++++
4 files changed, 1065 insertions(+), 0 deletions(-)
create mode 100644 board/enbw/enbw_cmc/Makefile
create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
create mode 100644 include/configs/enbw_cmc.h
diff --git a/board/enbw/enbw_cmc/Makefile b/board/enbw/enbw_cmc/Makefile
new file mode 100644
index 0000000..bdba069
--- /dev/null
+++ b/board/enbw/enbw_cmc/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
new file mode 100644
index 0000000..8947a2a
--- /dev/null
+++ b/board/enbw/enbw_cmc/enbw_cmc.c
@@ -0,0 +1,570 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/timer_defs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+/* missing functions from board/davinci/common/misc.c */
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
+{
+ /*
+ * Mask all IRQs by clearing the global enable and setting
+ * the enable clear for all the 90 interrupts.
+ */
+
+ writel(0, &davinci_aintc_regs->ger);
+
+ writel(0, &davinci_aintc_regs->hier);
+
+ writel(0xffffffff, &davinci_aintc_regs->ecr1);
+ writel(0xffffffff, &davinci_aintc_regs->ecr2);
+ writel(0xffffffff, &davinci_aintc_regs->ecr3);
+}
+#endif
+
+void davinci_emac_mii_mode_sel(int mode_sel)
+{
+ int val;
+
+ val = readl(&davinci_syscfg_regs->cfgchip3);
+ if (mode_sel == 0)
+ val &= ~(1 << 8);
+ else
+ val |= (1 << 8);
+ writel(val, &davinci_syscfg_regs->cfgchip3);
+}
+
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+ const int n_items)
+{
+ int i;
+
+ for (i = 0; i < n_items; i++)
+ lpsc_on(item[i].lpsc_no);
+
+ return 0;
+}
+
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ const int n_items)
+{
+ return 0;
+}
+
+static void enbw_cmc_switch(int port, int on)
+{
+ const char *devname;
+ unsigned char phyaddr = 3;
+ unsigned char reg = 0;
+ unsigned short data;
+
+ if (port == 1)
+ phyaddr = 2;
+
+ devname = miiphy_get_current_dev();
+ if (!devname) {
+ printf("Error: no mii device\n");
+ return;
+ }
+ if (miiphy_read(devname, phyaddr, reg, &data) != 0) {
+ printf("Error reading from the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+ if (on)
+ data &= ~0x0800;
+ else
+ data |= 0x0800;
+
+ if (miiphy_write(devname, phyaddr, reg, data) != 0) {
+ printf("Error writing to the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+}
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+ /* address of boot parameters, not used as booting with DTT */
+ gd->bd->bi_boot_params = 0;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ clrbits_le32(&davinci_syscfg_regs->suspsrc,
+ (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2));
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ davinci_emac_mii_mode_sel(0);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ if (hwconfig_subarg_cmp("switch", "lan", "on"))
+ /* Switch port lan on */
+ enbw_cmc_switch(1, 1);
+ else
+ enbw_cmc_switch(1, 0);
+
+ if (hwconfig_subarg_cmp("switch", "pwl", "on"))
+ /* Switch port pwl on */
+ enbw_cmc_switch(2, 1);
+ else
+ enbw_cmc_switch(2, 0);
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size(
+ (long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_PREBOOT
+static uchar kbd_magic_prefix[] = "key_magic_";
+static uchar kbd_command_prefix[] = "key_cmd_";
+
+struct kbd_data_t {
+ char s1;
+};
+
+struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank01;
+ unsigned long reg;
+
+ /* read SW1 + SW2 */
+ reg = readl(&gpio->in_data);
+ kbd_data->s1 = ((reg & 0x00003000) >> 12);
+ return kbd_data;
+}
+
+static int compare_magic(const struct kbd_data_t *kbd_data, char *str)
+{
+ char s1 = str[0];
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s1)
+ return -1;
+
+ return 0;
+}
+
+static char *key_match(const struct kbd_data_t *kbd_data)
+{
+ char magic[sizeof(kbd_magic_prefix) + 1];
+ char *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ kbd_magic_keys = getenv("magic_keys");
+ if (kbd_magic_keys == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+
+ if (compare_magic(kbd_data, getenv(magic)) == 0) {
+ char cmd_name[sizeof(kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv(cmd_name);
+
+ return cmd;
+ }
+ }
+
+ return NULL;
+}
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_PREBOOT
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ char *str = strdup(key_match(get_keys(&kbd_data)));
+ /* Set or delete definition */
+ setenv("preboot", str);
+ free(str);
+#endif /* CONFIG_PREBOOT */
+
+#ifdef CONFIG_HW_WATCHDOG
+ davinci_hw_watchdog_enable();
+#endif
+
+ return 0;
+}
+
+struct cmc_led {
+ char name[20];
+ struct davinci_gpio *gpio;
+ unsigned long mask;
+};
+
+struct cmc_led led_table[] = {
+ {"led1", davinci_gpio_bank01, 0x80000000},
+ {"led2", davinci_gpio_bank01, 0x00000002},
+ {"led3", davinci_gpio_bank01, 0x00000004},
+ {"led4", davinci_gpio_bank01, 0x00000008},
+ {"led5", davinci_gpio_bank01, 0x00000010},
+ {"led6", davinci_gpio_bank01, 0x00000020},
+ {"led7", davinci_gpio_bank01, 0x00000040},
+ {"led8", davinci_gpio_bank01, 0x00004000},
+};
+
+static int cmc_get_led_state(struct cmc_led *led)
+{
+ struct davinci_gpio *gpio = led->gpio;
+ unsigned long reg;
+
+ /* read SW1 + SW2 */
+ reg = readl(&gpio->in_data);
+ if ((reg & led->mask) == led->mask)
+ return 1;
+
+ return 0;
+}
+
+static int cmc_set_led_state(struct cmc_led *led, int state)
+{
+ struct davinci_gpio *gpio = led->gpio;
+ unsigned long reg;
+
+ reg = readl(&gpio->out_data);
+ if (state)
+ reg |= led->mask;
+ else
+ reg &= ~led->mask;
+
+ writel(reg, &gpio->out_data);
+ return 0;
+}
+
+static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct cmc_led *led;
+ int found = 0;
+ int i = 0;
+ int only_print = 0;
+ int len = ARRAY_SIZE(led_table);
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if (argc < 3)
+ only_print = 1;
+
+ led = led_table;
+ while ((!found) && (i < len)) {
+ if (strcmp(argv[1], led->name) == 0) {
+ found = 1;
+ } else {
+ led++;
+ i++;
+ }
+ }
+ if (!found)
+ return cmd_usage(cmdtp);
+
+ if (only_print) {
+ if (cmc_get_led_state(led))
+ printf("on\n");
+ else
+ printf("off\n");
+
+ return 0;
+ }
+ if (strcmp(argv[2], "on") == 0)
+ cmc_set_led_state(led, 1);
+ else
+ cmc_set_led_state(led, 0);
+
+ return 0;
+}
+
+U_BOOT_CMD(led, 3, 1, do_led,
+ "switch on/off board led",
+ "[name] [on/off]"
+);
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ davinci_hw_watchdog_reset();
+}
+#endif
+
+#if defined(CONFIG_POST)
+void arch_memory_failure_handle(void)
+{
+ int state = 1;
+
+ printf("%s: blinking with LEDs\n", __func__);
+ while (1) {
+ cmc_set_led_state(&led_table[0], state);
+ cmc_set_led_state(&led_table[1], state);
+ cmc_set_led_state(&led_table[2], state);
+ if (state)
+ state = 0;
+ else
+ state = 1;
+ udelay(500);
+ }
+}
+#endif
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void bootcount_store(ulong a)
+{
+ void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ /*
+ * write RTC kick register to enable write
+ * for RTC Scratch registers. Cratch0 and 1 are
+ * used for bootcount values.
+ */
+ out_be32(reg + 0x0c, 0x130be783);
+ out_be32(reg + 0x10, 0xe0f1a495);
+ out_be32(reg, a);
+ out_be32(reg + 4, BOOTCOUNT_MAGIC);
+}
+
+ulong bootcount_load(void)
+{
+ void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ if (in_be32(reg + 4) != BOOTCOUNT_MAGIC)
+ return 0;
+ else
+ return in_be32(reg);
+}
+#endif
+
+void board_gpio_init(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank8;
+
+ /*
+ * Counter IF: RS485 enable, low enable
+ * GP8[11] = Out[9] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000800);
+ clrbits_le32(&gpio->out_data, 0x00000800);
+ /*
+ * Counter IF: Isolation RS485
+ * GP8[10] = Out[10] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000400);
+ clrbits_le32(&gpio->out_data, 0x00000400);
+ /*
+ * W2HUT: RS485 Rx enable:
+ * GP8[9] = Out[11] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000200);
+ clrbits_le32(&gpio->out_data, 0x00000200);
+ /*
+ * W2HUT: Isolation RS485:
+ * GP8[8] = Out[12] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000100);
+ clrbits_le32(&gpio->out_data, 0x00000100);
+
+ gpio = davinci_gpio_bank67;
+ /*
+ * SW Reset 4 port LAN switch
+ * GP7[15] = Out[4] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x80000000);
+ setbits_le32(&gpio->out_data, 0x80000000);
+ /*
+ * Enable 11V PLC Vaa, high active
+ * GP7[14] = Out[3] set to output state 0
+ */
+ clrbits_le32(&gpio->dir, 0x40000000);
+ clrbits_le32(&gpio->out_data, 0x40000000);
+ /*
+ * Enable 1.5V PLC Core, high active
+ * GP7[13] = Out[2] set to output state 0
+ */
+ clrbits_le32(&gpio->dir, 0x20000000);
+ clrbits_le32(&gpio->out_data, 0x20000000);
+ /*
+ * Disable USB0 VBUS, low active
+ * GP7[12] = Out[2] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x10000000);
+ setbits_le32(&gpio->out_data, 0x10000000);
+ /*
+ * SW_reset for PLC modul, low active
+ * GP6[13] = Out[5] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x00002000);
+ setbits_le32(&gpio->out_data, 0x00002000);
+ /*
+ * LCM Bus Signal RS; R/W and E
+ * GP6[12..11] = Out[6..7]
+ */
+ clrbits_le32(&gpio->dir, 0x00001800);
+ clrbits_le32(&gpio->out_data, 0x00001800);
+ /*
+ * Pairing-button for PLC Modul = Out[18]
+ */
+ clrbits_le32(&gpio->dir, 0x00000400);
+ clrbits_le32(&gpio->out_data, 0x00000400);
+ /*
+ * PLC MDIO CLK
+ * GP6[9] = Out[14]
+ */
+ clrbits_le32(&gpio->dir, 0x00000200);
+ clrbits_le32(&gpio->out_data, 0x00000200);
+ /*
+ * HK218, active high
+ * GP6[8] = Out[15], set to 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000100);
+ clrbits_le32(&gpio->out_data, 0x00000100);
+ /*
+ * SW reset TPM ctrl., active low
+ * GP6[0] = Out[13], set to 1
+ */
+ clrbits_le32(&gpio->dir, 0x00000001);
+ setbits_le32(&gpio->out_data, 0x00000001);
+
+ gpio = davinci_gpio_bank23;
+ /*
+ * LCM: Signal E
+ * GP2[2] = Out[8]
+ */
+ clrbits_le32(&gpio->dir, 0x00000004);
+ setbits_le32(&gpio->out_data, 0x00000004);
+
+ gpio = davinci_gpio_bank01;
+ /*
+ * PV-IF RS485 RxD Enable\
+ */
+ clrbits_le32(&gpio->dir, 0x00008000);
+ clrbits_le32(&gpio->out_data, 0x00008000);
+ /*
+ * set LED pins to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x8000407e);
+ clrbits_le32(&gpio->out_data, 0x8000407e);
+
+ /*
+ * Set the LED 1 - 4 to on
+ */
+ cmc_set_led_state(&led_table[1], 1);
+ cmc_set_led_state(&led_table[2], 1);
+ cmc_set_led_state(&led_table[3], 1);
+ cmc_set_led_state(&led_table[4], 1);
+ return;
+}
diff --git a/boards.cfg b/boards.cfg
index 8a5bfc1..7db43fa 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -128,6 +128,7 @@ davinci_dvevm arm arm926ejs dvevm davinci
davinci_schmoogie arm arm926ejs schmoogie davinci davinci
davinci_sffsdr arm arm926ejs sffsdr davinci davinci
davinci_sonata arm arm926ejs sonata davinci davinci
+enbw_cmc arm arm926ejs enbw_cmc enbw davinci
km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI
km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood
mgcoge3un arm arm926ejs km_arm keymile kirkwood
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
new file mode 100644
index 0000000..e203089
--- /dev/null
+++ b/include/configs/enbw_cmc.h
@@ -0,0 +1,443 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_NAND
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_AM18018_LOWLEVEL
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_HOSTNAME enbw_cmc
+#define CONFIG_DISPLAY_CPUINFO
+
+#define MACH_TYPE_ENBW_CMC 3585
+#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+#define CONFIG_CMD_I2C
+
+#define CONFIG_CMD_DTT
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=" \
+ "physmap-flash.0:" \
+ "512k(U-Boot)," \
+ "64k(env1)," \
+ "64k(env2)," \
+ "-(rest);" \
+ "davinci_nand.1:" \
+ "128k(dtb)," \
+ "2m(kernel)," \
+ "4m(rootfs)," \
+ "-(userfs)"
+
+
+#define CONFIG_CMD_MTDPARTS
+
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 2
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_BASE 0x60000000
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_FLASH_SHOW_PROGRESS 99
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
+ CONFIG_ENV_SECT_SIZE)
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u-boot_addr_r=c0000000\0" \
+ "uboot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${u-boot_addr_r} ${uboot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
+ "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE) \
+ " ${filesize};" \
+ "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk-arm/arm\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "kernel_addr_r=c0700000\0" \
+ "fdt_addr_r=c0600000\0" \
+ "ramdisk_addr_r=c0a00000\0" \
+ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
+ xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 220000 400000;\0" \
+ "nand_ld_kernel=nand read ${kernel_addr_r} 20000 200000;\0" \
+ "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000;\0" \
+ "load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
+ "load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
+ "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyS2," \
+ "${baudrate}n8\0" \
+ "net_nfs=run load_fdt load_kernel; " \
+ "run nfsargs addip addcon addmtd;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "flash_self=run load_nand ramargs addip addcon;bootm " \
+ "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+ "bootcmd=run net_nfs\0" \
+ "machid=e01\0" \
+ "key_cmd0=echo hallo0\0" \
+ "key_cmd1=echo hallo1\0" \
+ "key_cmd2=echo hallo2\0" \
+ "key_cmd3=echo hallo3\0" \
+ "key_magic_0=0\0" \
+ "key_magic_1=1\0" \
+ "key_magic_2=2\0" \
+ "key_magic_3=3\0" \
+ "magic_keys=0123\0" \
+ "hwconfig=switch:lan=on,pwl=off\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "logversion=2\0" \
+ "\0"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_HWCONFIG
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+#define CONFIG_MISC_INIT_R 1
+
+#define CONFIG_CMC_RESET_PIN 0x04000000
+#define CONFIG_CMC_RESET_TIMEOUT 3
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
+#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
+#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
+
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_DAVINCI
+
+/* FDT support */
+#define CONFIG_OF_LIBFDT 1
+
+/* LowLevel Init */
+/* PLL */
+#define CONFIG_SYS_DV_CLKMODE 0
+#define CONFIG_SYS_AM1808_PLL0_POSTDIV 1
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV1 0x8000
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV2 0x8001
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV3 0x8002 /* 100MHz */
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV4 0x8003
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV5 0x8002
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV6 CONFIG_SYS_AM1808_PLL0_PLLDIV1
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV7 0x8005
+
+#define CONFIG_SYS_AM1808_PLL1_POSTDIV 1
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV1 0x8000
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV2 0x8001
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV3 0x8002
+
+#define CONFIG_SYS_AM1808_PLL0_PLLM 37 /* PLL0 -> 456 MHz */
+#define CONFIG_SYS_AM1808_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
+
+/* DDR RAM */
+#define CONFIG_SYS_AM1808_DDR2_DDRPHYCR (0 | \
+ (0x1 << 7) | \
+ (0x1 << 6) | \
+ (0x4 << 0))
+
+#define CONFIG_SYS_AM1808_DDR2_SDBCR (0 | \
+ (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
+ (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
+ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
+ (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
+ (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
+ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+#define CONFIG_SYS_AM1808_DDR2_SDBCR2 4 /* 13 row address bits */
+
+/*
+ * freq = 132MHz -> t = 8ns
+ */
+#define CONFIG_SYS_AM1808_DDR2_SDTIMR (0 | \
+ (0x0c << 25) | /* tRFC = 105 105/8 = 13 - 1 = 0xc */ \
+ (1 << 22) | /* tRP 15/8 = 2 - 1 = 1 */ \
+ (1 << 19) | /* tRCD 15/8 = 2 - 1 = 1 */ \
+ (1 << 16) | /* tWR 15/8 = 2 - 1 = 1 */ \
+ (5 << 11) | /* tRAS 45/8 = 6 - 1 = 5 */ \
+ (7 << 6) | /* tRC 60/8 = 8 - 1 = 7 */ \
+ (1 << 3) | /* tRRD 12/8 = 2 -1 = 1 */ \
+ (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
+ ((2 - 1) << 0)) /* tWTR 7.5 ns min 2 clocks */
+
+/*
+ * freq = 132MHz -> t=8ns
+ */
+#define CONFIG_SYS_AM1808_DDR2_SDTIMR2 (0 | \
+ (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
+ (8 << 27) | /* tRASMAX [(70us/7800ns)-1] */ \
+ (2 << 25) | /* tXP = 2, tCKe = 3 -> 3 - 1 = 2 */ \
+ (0 << 23) | /* tODT (Not supported) */ \
+ (13 << 16) | /* tXSNR = tRFC + 10 = 115 115/8 = 14 - 1 = 13 */ \
+ (24 << 8) | /* tXSRD = 200 200/8 = 25 - 1 = 24 */ \
+ (0 << 5) | /* tRTP = 7.5 7.5/8 = 1 - 1 = 0 */ \
+ (2 << 0)) /* tCKE = 3 -> 3 - 1 = 2 */
+
+#define CONFIG_SYS_AM1808_DDR2_SDRCR 0x00000407
+
+/*
+ * with Pin Setup Utility from TI
+ * missing GPIO pin setup
+ */
+#define CONFIG_SYS_AM1808_PINMUX0 0x44448888
+#define CONFIG_SYS_AM1808_PINMUX1 0x48888884
+#define CONFIG_SYS_AM1808_PINMUX2 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX3 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX4 0x22222288
+#define CONFIG_SYS_AM1808_PINMUX5 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX6 0x11818811
+#define CONFIG_SYS_AM1808_PINMUX7 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX8 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX9 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX10 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX11 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX12 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX13 0x88888800
+#define CONFIG_SYS_AM1808_PINMUX14 0x00000088
+#define CONFIG_SYS_AM1808_PINMUX15 0x00000000
+#define CONFIG_SYS_AM1808_PINMUX16 0x88888880
+#define CONFIG_SYS_AM1808_PINMUX17 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX18 0x88022288
+#define CONFIG_SYS_AM1808_PINMUX19 0x08022288
+
+#define CONFIG_SYS_AM1808_CS2CFG 0x08624311
+#define CONFIG_SYS_AM1808_CS3CFG 0x04222310
+
+/*
+ * NOR Bootconfiguration word:
+ * Method: Direc boot
+ * EMIFA access mode: 16 Bit
+ */
+#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
+
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
+#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x01c23060
+
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_DCACHE_OFF
+#endif /* __CONFIG_H */
--
1.7.6
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-19 5:50 ` [U-Boot] [PATCH v2 " Heiko Schocher
@ 2011-09-23 20:47 ` Paulraj, Sandeep
2011-09-26 5:43 ` Heiko Schocher
2011-09-30 7:55 ` Christian Riesch
1 sibling, 1 reply; 31+ messages in thread
From: Paulraj, Sandeep @ 2011-09-23 20:47 UTC (permalink / raw)
To: u-boot
>
> - booting from NOR Flash with direct boot method
> - POST support
> - LOGBUF support
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
> Cc: Paulraj Sandeep <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> ---
> - changes for v2
> - use CONFIG_MACH_TYPE instead setting the MACH_TYPE in
> board specific code, as Igor Grinberg suggested.
> - add logversion=2 to default Environment
>
> board/enbw/enbw_cmc/Makefile | 51 ++++
> board/enbw/enbw_cmc/enbw_cmc.c | 570
> ++++++++++++++++++++++++++++++++++++++++
> boards.cfg | 1 +
> include/configs/enbw_cmc.h | 443 +++++++++++++++++++++++++++++++
> 4 files changed, 1065 insertions(+), 0 deletions(-)
> create mode 100644 board/enbw/enbw_cmc/Makefile
> create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
> create mode 100644 include/configs/enbw_cmc.h
>
Heiko,
I applied all your patches and MAKEALL returned a failure for only the enbw_cmc board.
Can you please take a look?
Because of this I have not applied this to u-boot-ti.
Regards,
Sandeep
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-23 20:47 ` Paulraj, Sandeep
@ 2011-09-26 5:43 ` Heiko Schocher
2011-09-26 6:03 ` Paulraj, Sandeep
0 siblings, 1 reply; 31+ messages in thread
From: Heiko Schocher @ 2011-09-26 5:43 UTC (permalink / raw)
To: u-boot
Hello Paulraj,
Paulraj, Sandeep wrote:
>
>> - booting from NOR Flash with direct boot method
>> - POST support
>> - LOGBUF support
>>
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>> Cc: Paulraj Sandeep <s-paulraj@ti.com>
>> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
>> Cc: Igor Grinberg <grinberg@compulab.co.il>
>> ---
>> - changes for v2
>> - use CONFIG_MACH_TYPE instead setting the MACH_TYPE in
>> board specific code, as Igor Grinberg suggested.
>> - add logversion=2 to default Environment
>>
>> board/enbw/enbw_cmc/Makefile | 51 ++++
>> board/enbw/enbw_cmc/enbw_cmc.c | 570
>> ++++++++++++++++++++++++++++++++++++++++
>> boards.cfg | 1 +
>> include/configs/enbw_cmc.h | 443 +++++++++++++++++++++++++++++++
>> 4 files changed, 1065 insertions(+), 0 deletions(-)
>> create mode 100644 board/enbw/enbw_cmc/Makefile
>> create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
>> create mode 100644 include/configs/enbw_cmc.h
>>
>
> Heiko,
>
> I applied all your patches and MAKEALL returned a failure for only the enbw_cmc board.
>
> Can you please take a look?
>
> Because of this I have not applied this to u-boot-ti.
Hmm.. just did a rebase to TOT and I see with all my patches:
[hs at pollux u-boot]$ ./MAKEALL enbw_cmc
Configuring for enbw_cmc board...
text data bss dec hex filename
407034 8576 257656 673266 a45f2 ./u-boot
--------------------- SUMMARY ----------------------------
Boards compiled: 1
----------------------------------------------------------
[hs at pollux u-boot]$
Did you apllied all patches, as stated here?:
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/108514
How looks your compile error?
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-26 5:43 ` Heiko Schocher
@ 2011-09-26 6:03 ` Paulraj, Sandeep
2011-09-26 6:08 ` Heiko Schocher
2011-09-27 7:05 ` Albert ARIBAUD
0 siblings, 2 replies; 31+ messages in thread
From: Paulraj, Sandeep @ 2011-09-26 6:03 UTC (permalink / raw)
To: u-boot
>Did you apllied all patches, as stated here?:
>
>http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/108514
>
>How looks your compile error?
ah, i did not see the entire list of dependencies.
I did not apply all the patches as some of them should not be applied by me.
i have sent Albert a pull request without this patch for the time being.
Hope by the next pull request, all the dependencies would have made it to mainline.
Regards,
Sandeep
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-26 6:03 ` Paulraj, Sandeep
@ 2011-09-26 6:08 ` Heiko Schocher
2011-09-27 7:05 ` Albert ARIBAUD
1 sibling, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-26 6:08 UTC (permalink / raw)
To: u-boot
Hello Paulraj,
Paulraj, Sandeep wrote:
>> Did you apllied all patches, as stated here?:
>>
>> http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/108514
>>
>> How looks your compile error?
>
> ah, i did not see the entire list of dependencies.
> I did not apply all the patches as some of them should not be applied by me.
Ok!
> i have sent Albert a pull request without this patch for the time being.
>
> Hope by the next pull request, all the dependencies would have made it to mainline.
Hmm.. maybe you can post your compileerror, so I can see which patch
is missing?
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-15 5:59 ` [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR Heiko Schocher
@ 2011-09-26 8:02 ` Christian Riesch
2011-09-26 8:28 ` Heiko Schocher
2011-09-30 6:57 ` Christian Riesch
1 sibling, 1 reply; 31+ messages in thread
From: Christian Riesch @ 2011-09-26 8:02 UTC (permalink / raw)
To: u-boot
Heiko,
I am looking forward to see these patches in mainline u-boot. My
custom board also directly boots from NOR, so I think there is a lot I
can re-use for my board.
I have one question, please see below:
On Thu, Sep 15, 2011 at 7:59 AM, Heiko Schocher <hs@denx.de> wrote:
> Signed-off-by: Heiko Schocher <hs@denx.de>
> Cc: Paulraj Sandeep <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
> ?arch/arm/cpu/arm926ejs/davinci/Makefile ? ? ? ? ? ?| ? ?1 +
> ?arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c ? | ?428 ++++++++++++++++++++
> ?.../arm/include/asm/arch-davinci/am1808_lowlevel.h | ? 44 ++
> ?3 files changed, 473 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
> ?create mode 100644 arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
[...]
> diff --git a/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
> new file mode 100644
> index 0000000..1ea4a9f
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
[...]
> +void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
> + ? ? ? ? ? ? ? unsigned char domain, unsigned char state)
> +{
> + ? ? ? struct davinci_psc_regs *reg;
> + ? ? ? dv_reg_p mdstat, mdctl;
> +
> + ? ? ? if (pscnum == 0) {
> + ? ? ? ? ? ? ? reg = davinci_psc0_regs;
> + ? ? ? ? ? ? ? mdstat = ®->psc0.mdstat[module];
> + ? ? ? ? ? ? ? mdctl = ®->psc0.mdctl[module];
> + ? ? ? } else {
> + ? ? ? ? ? ? ? reg = davinci_psc1_regs;
> + ? ? ? ? ? ? ? mdstat = ®->psc1.mdstat[module];
> + ? ? ? ? ? ? ? mdctl = ®->psc1.mdctl[module];
> + ? ? ? }
> +
> + ? ? ? /* Wait for any outstanding transition to complete */
> + ? ? ? while ((readl(®->ptstat) & (0x00000001 << domain)))
> + ? ? ? ? ? ? ? ;
> +
> + ? ? ? /* If we are already in that state, just return */
> + ? ? ? if ((readl(mdstat) & 0x1F) == state)
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? /* Perform transition */
> + ? ? ? writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
> + ? ? ? setbits_le32(®->ptcmd, (0x00000001 << domain));
> +
> + ? ? ? /* Wait for transition to complete */
> + ? ? ? while (readl(®->ptstat) & (0x00000001 << domain))
> + ? ? ? ? ? ? ? ;
> +
> + ? ? ? /* Wait and verify the state */
> + ? ? ? while ((readl(mdstat) & 0x1F) != state)
> + ? ? ? ? ? ? ? ;
> +}
There is some similar code in arch/arm/cpu/arm926ejs/davinci/psc.c. Is
there any reason why you don't use this code or adapt it for your
needs?
Regards, Christian
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-26 8:02 ` Christian Riesch
@ 2011-09-26 8:28 ` Heiko Schocher
2011-09-27 6:57 ` Christian Riesch
0 siblings, 1 reply; 31+ messages in thread
From: Heiko Schocher @ 2011-09-26 8:28 UTC (permalink / raw)
To: u-boot
Hello Christian,
Christian Riesch wrote:
> Heiko,
> I am looking forward to see these patches in mainline u-boot. My
> custom board also directly boots from NOR, so I think there is a lot I
> can re-use for my board.
Thats the goal ;-)
> I have one question, please see below:
[...]
>> +void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
>> + unsigned char domain, unsigned char state)
>> +{
[...]
>> + /* Wait for transition to complete */
>> + while (readl(®->ptstat) & (0x00000001 << domain))
>> + ;
>> +
>> + /* Wait and verify the state */
>> + while ((readl(mdstat) & 0x1F) != state)
>> + ;
>> +}
>
> There is some similar code in arch/arm/cpu/arm926ejs/davinci/psc.c. Is
> there any reason why you don't use this code or adapt it for your
> needs?
No, there is no reason, just missed it! I try the functions in
arch/arm/cpu/arm926ejs/davinci/psc.c and if they work, I remove the
am1808_lpc_transition function.
Thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-26 8:28 ` Heiko Schocher
@ 2011-09-27 6:57 ` Christian Riesch
2011-09-27 7:27 ` Heiko Schocher
2011-09-27 11:18 ` Heiko Schocher
0 siblings, 2 replies; 31+ messages in thread
From: Christian Riesch @ 2011-09-27 6:57 UTC (permalink / raw)
To: u-boot
Hello Heiko,
Thank you for your reply. I have just noticed that the patches have
already been pulled into arm/next so I guess I am quite late with my
comments. I'd like to apologize for this; apparently I need another
email filter that also filters for messages containing "am1808" and
not only "da850" ;-)
Which brings me to my next point: AFAIK Texas Instruments's AM18xx
SoCs, their OMAP-L138, and their DA850 based devices basically differ
only in the DSP/PRU part of the device. If you are (like in u-boot)
only interested in the ARM part of chip, they are basically the same
device. For some reason the Linux kernel and u-boot support for all
these devices is labelled da850... Although I have no hardware to test
it, I guess that your DDR memory controller initialization code could
be used for the OMAP-L138 and the corresponding Davinci device as
well. So since all code in u-boot for the entire device family is
labelled da850... I guess your DDR initialization functions should get
this prefix as well for consistency. Any comments from the
maintainers/TI employees who know these devices better than I do?
On Mon, Sep 26, 2011 at 10:28 AM, Heiko Schocher <hs@denx.de> wrote:
> Hello Christian,
>
> Christian Riesch wrote:
>> Heiko,
>> I am looking forward to see these patches in mainline u-boot. My
>> custom board also directly boots from NOR, so I think there is a lot I
>> can re-use for my board.
>
> Thats the goal ;-)
>
>> I have one question, please see below:
> [...]
>>> +void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
>>> + ? ? ? ? ? ? ? unsigned char domain, unsigned char state)
>>> +{
> [...]
>>> + ? ? ? /* Wait for transition to complete */
>>> + ? ? ? while (readl(®->ptstat) & (0x00000001 << domain))
>>> + ? ? ? ? ? ? ? ;
>>> +
>>> + ? ? ? /* Wait and verify the state */
>>> + ? ? ? while ((readl(mdstat) & 0x1F) != state)
>>> + ? ? ? ? ? ? ? ;
>>> +}
>>
>> There is some similar code in arch/arm/cpu/arm926ejs/davinci/psc.c. Is
>> there any reason why you don't use this code or adapt it for your
>> needs?
>
> No, there is no reason, just missed it! I try the functions in
> arch/arm/cpu/arm926ejs/davinci/psc.c and if they work, I remove the
> am1808_lpc_transition function.
Ok. Actually you do LPSC transitions twice in your board
configuration, first in the low level initialization in
arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c (using your own
function) and then again in your board initialization in
board/enbw/enbw_cmc/enbw_cmc.c (using the code in
arch/arm/cpu/arm926ejs/davinci/psc.c). I assume you ran into the same
problem as I did with the da850evm board. The UART is used before it
is turned on in the board_init() function. A few weeks ago I submitted
a patch [1][2] for this issue but did not get any comments on it.
Would you mind having a look at it so we could find a common solution
for both your configuration and the da850evm?
Regards, Christian
[1] http://lists.denx.de/pipermail/u-boot/2011-September/100352.html
[2] http://patchwork.ozlabs.org/patch/113335/
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-26 6:03 ` Paulraj, Sandeep
2011-09-26 6:08 ` Heiko Schocher
@ 2011-09-27 7:05 ` Albert ARIBAUD
1 sibling, 0 replies; 31+ messages in thread
From: Albert ARIBAUD @ 2011-09-27 7:05 UTC (permalink / raw)
To: u-boot
Hi all,
On 26/09/2011 08:03, Paulraj, Sandeep wrote:
>
>
>
>
>> Did you apllied all patches, as stated here?:
>>
>> http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/108514
>>
>> How looks your compile error?
>
> ah, i did not see the entire list of dependencies.
> I did not apply all the patches as some of them should not be applied by me.
>
> i have sent Albert a pull request without this patch for the time being.
>
> Hope by the next pull request, all the dependencies would have made it to mainline.
Note that at least some of the dependencies are in /next branches, so
they won't appear in u-boot[-arm]/master until the upcoming merge window
opens.
> Regards,
> Sandeep
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-27 6:57 ` Christian Riesch
@ 2011-09-27 7:27 ` Heiko Schocher
2011-09-27 8:37 ` Christian Riesch
2011-09-27 11:18 ` Heiko Schocher
1 sibling, 1 reply; 31+ messages in thread
From: Heiko Schocher @ 2011-09-27 7:27 UTC (permalink / raw)
To: u-boot
Hello Christian,
Christian Riesch wrote:
> Hello Heiko,
> Thank you for your reply. I have just noticed that the patches have
> already been pulled into arm/next so I guess I am quite late with my
> comments. I'd like to apologize for this; apparently I need another
No problem. Thanks for your reply!
> email filter that also filters for messages containing "am1808" and
> not only "da850" ;-)
;-)
> Which brings me to my next point: AFAIK Texas Instruments's AM18xx
> SoCs, their OMAP-L138, and their DA850 based devices basically differ
> only in the DSP/PRU part of the device. If you are (like in u-boot)
> only interested in the ARM part of chip, they are basically the same
> device. For some reason the Linux kernel and u-boot support for all
> these devices is labelled da850... Although I have no hardware to test
> it, I guess that your DDR memory controller initialization code could
> be used for the OMAP-L138 and the corresponding Davinci device as
> well. So since all code in u-boot for the entire device family is
> labelled da850... I guess your DDR initialization functions should get
> this prefix as well for consistency. Any comments from the
> maintainers/TI employees who know these devices better than I do?
Yes of course, such a rename should be done, if somebody has tested it!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-27 7:27 ` Heiko Schocher
@ 2011-09-27 8:37 ` Christian Riesch
2011-09-27 8:50 ` Heiko Schocher
0 siblings, 1 reply; 31+ messages in thread
From: Christian Riesch @ 2011-09-27 8:37 UTC (permalink / raw)
To: u-boot
Hello Heiko,
>> Which brings me to my next point: AFAIK Texas Instruments's AM18xx
>> SoCs, their OMAP-L138, and their DA850 based devices basically differ
>> only in the DSP/PRU part of the device. If you are (like in u-boot)
>> only interested in the ARM part of chip, they are basically the same
>> device. For some reason the Linux kernel and u-boot support for all
>> these devices is labelled da850... Although I have no hardware to test
>> it, I guess that your DDR memory controller initialization code could
>> be used for the OMAP-L138 and the corresponding Davinci device as
>> well. So since all code in u-boot for the entire device family is
>> labelled da850... I guess your DDR initialization functions should get
>> this prefix as well for consistency. Any comments from the
>> maintainers/TI employees who know these devices better than I do?
>
> Yes of course, such a rename should be done, if somebody has tested it!
I just wonder what is worse, having code in there that is labelled
da850 but not tested on all devices of the family, or having it
renamed every time someone finds out that it also runs on other
devices. TI uses a common PLL initialization code in its User Boot
Loader (UBL) for OMAP-L138, DA850, AM180x, so it should be pretty save
to rename it right now.
Did you also read the rest of my last email, the PSC part?
Regards, Christian
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-27 8:37 ` Christian Riesch
@ 2011-09-27 8:50 ` Heiko Schocher
2011-09-27 10:36 ` Christian Riesch
0 siblings, 1 reply; 31+ messages in thread
From: Heiko Schocher @ 2011-09-27 8:50 UTC (permalink / raw)
To: u-boot
Hello Christian,
Christian Riesch wrote:
> Hello Heiko,
>
>>> Which brings me to my next point: AFAIK Texas Instruments's AM18xx
>>> SoCs, their OMAP-L138, and their DA850 based devices basically differ
>>> only in the DSP/PRU part of the device. If you are (like in u-boot)
>>> only interested in the ARM part of chip, they are basically the same
>>> device. For some reason the Linux kernel and u-boot support for all
>>> these devices is labelled da850... Although I have no hardware to test
>>> it, I guess that your DDR memory controller initialization code could
>>> be used for the OMAP-L138 and the corresponding Davinci device as
>>> well. So since all code in u-boot for the entire device family is
>>> labelled da850... I guess your DDR initialization functions should get
>>> this prefix as well for consistency. Any comments from the
>>> maintainers/TI employees who know these devices better than I do?
>> Yes of course, such a rename should be done, if somebody has tested it!
>
> I just wonder what is worse, having code in there that is labelled
> da850 but not tested on all devices of the family, or having it
> renamed every time someone finds out that it also runs on other
> devices. TI uses a common PLL initialization code in its User Boot
> Loader (UBL) for OMAP-L138, DA850, AM180x, so it should be pretty save
> to rename it right now.
Feel free to sent a patch ;-)
> Did you also read the rest of my last email, the PSC part?
Yep, and I sent a response here:
http://lists.denx.de/pipermail/u-boot/2011-September/102340.html
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-27 8:50 ` Heiko Schocher
@ 2011-09-27 10:36 ` Christian Riesch
0 siblings, 0 replies; 31+ messages in thread
From: Christian Riesch @ 2011-09-27 10:36 UTC (permalink / raw)
To: u-boot
Heiko,
On Tue, Sep 27, 2011 at 10:50 AM, Heiko Schocher <hs@denx.de> wrote:
>> Did you also read the rest of my last email, the PSC part?
>
> Yep, and I sent a response here:
>
> http://lists.denx.de/pipermail/u-boot/2011-September/102340.html
No, I meant the last part of the email I sent this morning,
http://lists.denx.de/pipermail/u-boot/2011-September/102481.html
Regards, Christian
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-27 6:57 ` Christian Riesch
2011-09-27 7:27 ` Heiko Schocher
@ 2011-09-27 11:18 ` Heiko Schocher
1 sibling, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-27 11:18 UTC (permalink / raw)
To: u-boot
Hello Christian,
Sorry didn't realized that there was more at the end of your EMail!
Christian Riesch wrote:
> Hello Heiko,
> Thank you for your reply. I have just noticed that the patches have
> already been pulled into arm/next so I guess I am quite late with my
> comments. I'd like to apologize for this; apparently I need another
> email filter that also filters for messages containing "am1808" and
> not only "da850" ;-)
[...]
> Ok. Actually you do LPSC transitions twice in your board
> configuration, first in the low level initialization in
> arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c (using your own
> function) and then again in your board initialization in
> board/enbw/enbw_cmc/enbw_cmc.c (using the code in
> arch/arm/cpu/arm926ejs/davinci/psc.c). I assume you ran into the same
> problem as I did with the da850evm board. The UART is used before it
> is turned on in the board_init() function. A few weeks ago I submitted
a) you are right, I enable the PSC for the UART twice, what is not
optimal! I remove this in my board code. Thanks for detecting
this!
b) I enable the PSC for the UART in
arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c arch_cpu_init(),
so the UART is enabled on my board before calling board_early_init_f()
as in your patch [1]. So I am save on this site.
c) If using the "Legacy NOR Boot" Method with u-boot spl Framework,
(not tested this with the new Framework, only with the old),
we are also on the save side here, as the SPL code enables the
PSC for the UART in arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
board_init_f(), same as for the "direct NOR boot" method I used
on the enbw_cmc board.
> a patch [1][2] for this issue but did not get any comments on it.
> Would you mind having a look at it so we could find a common solution
> for both your configuration and the da850evm?
> [1] http://lists.denx.de/pipermail/u-boot/2011-September/100352.html
> [2] http://patchwork.ozlabs.org/patch/113335/
I think there are two points:
a) move this init to board_early_init_f() as you did it
b) remove the UART enable, as it is done in UBL or U-Boot code (SPL
or in arch_cpu_init())
But this should be decided from the board maintainer added
Sudhakar Rajashekhara to CC, as it affects the da850 board ...
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-15 5:59 ` [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR Heiko Schocher
2011-09-26 8:02 ` Christian Riesch
@ 2011-09-30 6:57 ` Christian Riesch
2011-09-30 7:11 ` Heiko Schocher
1 sibling, 1 reply; 31+ messages in thread
From: Christian Riesch @ 2011-09-30 6:57 UTC (permalink / raw)
To: u-boot
Heiko,
On Thu, Sep 15, 2011 at 7:59 AM, Heiko Schocher <hs@denx.de> wrote:
> Signed-off-by: Heiko Schocher <hs@denx.de>
> Cc: Paulraj Sandeep <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
> ?arch/arm/cpu/arm926ejs/davinci/Makefile ? ? ? ? ? ?| ? ?1 +
> ?arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c ? | ?428 ++++++++++++++++++++
> ?.../arm/include/asm/arch-davinci/am1808_lowlevel.h | ? 44 ++
> ?3 files changed, 473 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
> ?create mode 100644 arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
>
> diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
> index b38623a..0310957 100644
> --- a/arch/arm/cpu/arm926ejs/davinci/Makefile
> +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
> @@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
> ?LIB ? ?= $(obj)lib$(SOC).o
>
> ?COBJS-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= cpu.o timer.o psc.o
> +COBJS-$(CONFIG_AM18018_LOWLEVEL) ? ? ? += am1808_lowlevel.o
AM18018 - is this intended or just a typo?
Thanks, Christian
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR
2011-09-30 6:57 ` Christian Riesch
@ 2011-09-30 7:11 ` Heiko Schocher
0 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-30 7:11 UTC (permalink / raw)
To: u-boot
Hello Christian,
Christian Riesch wrote:
> Heiko,
>
> On Thu, Sep 15, 2011 at 7:59 AM, Heiko Schocher <hs@denx.de> wrote:
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>> Cc: Paulraj Sandeep <s-paulraj@ti.com>
>> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
>> ---
>> arch/arm/cpu/arm926ejs/davinci/Makefile | 1 +
>> arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c | 428 ++++++++++++++++++++
>> .../arm/include/asm/arch-davinci/am1808_lowlevel.h | 44 ++
>> 3 files changed, 473 insertions(+), 0 deletions(-)
>> create mode 100644 arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
>> create mode 100644 arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
>>
>> diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
>> index b38623a..0310957 100644
>> --- a/arch/arm/cpu/arm926ejs/davinci/Makefile
>> +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
>> @@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
>> LIB = $(obj)lib$(SOC).o
>>
>> COBJS-y += cpu.o timer.o psc.o
>> +COBJS-$(CONFIG_AM18018_LOWLEVEL) += am1808_lowlevel.o
>
> AM18018 - is this intended or just a typo?
Just a typo, thanks for detecting!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-19 5:50 ` [U-Boot] [PATCH v2 " Heiko Schocher
2011-09-23 20:47 ` Paulraj, Sandeep
@ 2011-09-30 7:55 ` Christian Riesch
2011-09-30 8:46 ` Heiko Schocher
1 sibling, 1 reply; 31+ messages in thread
From: Christian Riesch @ 2011-09-30 7:55 UTC (permalink / raw)
To: u-boot
Hello Heiko,
On Mon, Sep 19, 2011 at 7:50 AM, Heiko Schocher <hs@denx.de> wrote:
> - booting from NOR Flash with direct boot method
> - POST support
> - LOGBUF support
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
> Cc: Paulraj Sandeep <s-paulraj@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> ---
> - changes for v2
> ?- use CONFIG_MACH_TYPE instead setting the MACH_TYPE in
> ? ?board specific code, as Igor Grinberg suggested.
> ?- add logversion=2 to default Environment
>
> ?board/enbw/enbw_cmc/Makefile ? | ? 51 ++++
> ?board/enbw/enbw_cmc/enbw_cmc.c | ?570 ++++++++++++++++++++++++++++++++++++++++
> ?boards.cfg ? ? ? ? ? ? ? ? ? ? | ? ?1 +
> ?include/configs/enbw_cmc.h ? ? | ?443 +++++++++++++++++++++++++++++++
> ?4 files changed, 1065 insertions(+), 0 deletions(-)
> ?create mode 100644 board/enbw/enbw_cmc/Makefile
> ?create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
> ?create mode 100644 include/configs/enbw_cmc.h
[...]
> diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
> new file mode 100644
> index 0000000..e203089
> --- /dev/null
> +++ b/include/configs/enbw_cmc.h
[...]
> +#define CONFIG_SYS_AM1808_PLL0_PLLM ? ?37 ? ? ?/* PLL0 -> 456 MHz */
With a 24 MHz input frequency this would result in a PLL0 frequency of
24MHz / PREDIV * (CONFIG_SYS_AM1808_PLL0_PLLM + 1), so I guess you
assume a PREDIV of 2 here (PREDIV register value 0x00008001). However,
the AM1808 datasheet and the reference guide (section 7.3.10) state
that the default PREDIV is 1 (register value 0x00008000) and I don't
see how you set the PREDIV to 2. Am I missing something here?
Regards, Christian
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-30 7:55 ` Christian Riesch
@ 2011-09-30 8:46 ` Heiko Schocher
2011-09-30 9:02 ` Christian Riesch
0 siblings, 1 reply; 31+ messages in thread
From: Heiko Schocher @ 2011-09-30 8:46 UTC (permalink / raw)
To: u-boot
Hello Christian,
Christian Riesch wrote:
> Hello Heiko,
>
> On Mon, Sep 19, 2011 at 7:50 AM, Heiko Schocher <hs@denx.de> wrote:
>> - booting from NOR Flash with direct boot method
>> - POST support
>> - LOGBUF support
>>
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>> Cc: Paulraj Sandeep <s-paulraj@ti.com>
>> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
>> Cc: Igor Grinberg <grinberg@compulab.co.il>
>> ---
>> - changes for v2
>> - use CONFIG_MACH_TYPE instead setting the MACH_TYPE in
>> board specific code, as Igor Grinberg suggested.
>> - add logversion=2 to default Environment
>>
>> board/enbw/enbw_cmc/Makefile | 51 ++++
>> board/enbw/enbw_cmc/enbw_cmc.c | 570 ++++++++++++++++++++++++++++++++++++++++
>> boards.cfg | 1 +
>> include/configs/enbw_cmc.h | 443 +++++++++++++++++++++++++++++++
>> 4 files changed, 1065 insertions(+), 0 deletions(-)
>> create mode 100644 board/enbw/enbw_cmc/Makefile
>> create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
>> create mode 100644 include/configs/enbw_cmc.h
>
> [...]
>
>> diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
>> new file mode 100644
>> index 0000000..e203089
>> --- /dev/null
>> +++ b/include/configs/enbw_cmc.h
>
> [...]
>
>> +#define CONFIG_SYS_AM1808_PLL0_PLLM 37 /* PLL0 -> 456 MHz */
>
> With a 24 MHz input frequency this would result in a PLL0 frequency of
> 24MHz / PREDIV * (CONFIG_SYS_AM1808_PLL0_PLLM + 1), so I guess you
> assume a PREDIV of 2 here (PREDIV register value 0x00008001). However,
No. The comment is wrong! I fix the comment from PLL0 to PLLC0
in the next patch version, thanks!
> the AM1808 datasheet and the reference guide (section 7.3.10) state
> that the default PREDIV is 1 (register value 0x00008000) and I don't
> see how you set the PREDIV to 2. Am I missing something here?
For calculating the resulting frequencies for the used Sysclocks
don;t forget the POSTDIV value
#define CONFIG_SYS_AM1808_PLL0_POSTDIV 1
So the correct calculation is:
(24MHz / PREDIV * (CONFIG_SYS_AM1808_PLL0_PLLM + 1)) / POSTDIV
(And with that, I get 456 MHz ;-)
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-30 8:46 ` Heiko Schocher
@ 2011-09-30 9:02 ` Christian Riesch
2011-09-30 9:32 ` Heiko Schocher
0 siblings, 1 reply; 31+ messages in thread
From: Christian Riesch @ 2011-09-30 9:02 UTC (permalink / raw)
To: u-boot
Hello Heiko,
thanks for your reply.
On Fri, Sep 30, 2011 at 10:46 AM, Heiko Schocher <hs@denx.de> wrote:
> Christian Riesch wrote:
>> On Mon, Sep 19, 2011 at 7:50 AM, Heiko Schocher <hs@denx.de> wrote:
>>> - booting from NOR Flash with direct boot method
>>> - POST support
>>> - LOGBUF support
>>>
>>> Signed-off-by: Heiko Schocher <hs@denx.de>
>>> Cc: Paulraj Sandeep <s-paulraj@ti.com>
>>> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
>>> Cc: Igor Grinberg <grinberg@compulab.co.il>
>>> ---
>>> - changes for v2
>>> ?- use CONFIG_MACH_TYPE instead setting the MACH_TYPE in
>>> ? ?board specific code, as Igor Grinberg suggested.
>>> ?- add logversion=2 to default Environment
>>>
>>> ?board/enbw/enbw_cmc/Makefile ? | ? 51 ++++
>>> ?board/enbw/enbw_cmc/enbw_cmc.c | ?570 ++++++++++++++++++++++++++++++++++++++++
>>> ?boards.cfg ? ? ? ? ? ? ? ? ? ? | ? ?1 +
>>> ?include/configs/enbw_cmc.h ? ? | ?443 +++++++++++++++++++++++++++++++
>>> ?4 files changed, 1065 insertions(+), 0 deletions(-)
>>> ?create mode 100644 board/enbw/enbw_cmc/Makefile
>>> ?create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c
>>> ?create mode 100644 include/configs/enbw_cmc.h
>>
>> [...]
>>
>>> diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
>>> new file mode 100644
>>> index 0000000..e203089
>>> --- /dev/null
>>> +++ b/include/configs/enbw_cmc.h
>>
>> [...]
>>
>>> +#define CONFIG_SYS_AM1808_PLL0_PLLM ? ?37 ? ? ?/* PLL0 -> 456 MHz */
>>
>> With a 24 MHz input frequency this would result in a PLL0 frequency of
>> 24MHz / PREDIV * (CONFIG_SYS_AM1808_PLL0_PLLM + 1), so I guess you
>> assume a PREDIV of 2 here (PREDIV register value 0x00008001). However,
>
> No. The comment is wrong! I fix the comment from PLL0 to PLLC0
> in the next patch version, thanks!
Ok.
>> the AM1808 datasheet and the reference guide (section 7.3.10) state
>> that the default PREDIV is 1 (register value 0x00008000) and I don't
>> see how you set the PREDIV to 2. Am I missing something here?
>
> For calculating the resulting frequencies for the used Sysclocks
> don;t forget the POSTDIV value
>
> #define CONFIG_SYS_AM1808_PLL0_POSTDIV ?1
>
> So the correct calculation is:
>
> (24MHz / PREDIV * (CONFIG_SYS_AM1808_PLL0_PLLM + 1)) / POSTDIV
>
> (And with that, I get 456 MHz ;-)
But then you would be running PLL0 with 24MHz *
(CONFIG_SYS_AM1808_PLL0_PLLM + 1) = 912 MHz !? That would be out of
specs since the PLL output frequency must be between 300 and 600 MHz
according to the datasheet.
However, you can't set the PLLM to 37 anyway, since it's only a 5 bit
field, (37 & 0x1f) results in 5, so you only multiply the frequency by
6 in the PLL, resulting in 144MHz PLL frequency.
Regards, Christian
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH v2 8/8] arm, davinci: add support for am1808 based enbw_cmc board
2011-09-30 9:02 ` Christian Riesch
@ 2011-09-30 9:32 ` Heiko Schocher
0 siblings, 0 replies; 31+ messages in thread
From: Heiko Schocher @ 2011-09-30 9:32 UTC (permalink / raw)
To: u-boot
Hello Christian,
Christian Riesch wrote:
> Hello Heiko,
> thanks for your reply.
>
> On Fri, Sep 30, 2011 at 10:46 AM, Heiko Schocher <hs@denx.de> wrote:
>> Christian Riesch wrote:
>>> On Mon, Sep 19, 2011 at 7:50 AM, Heiko Schocher <hs@denx.de> wrote:
>>>> - booting from NOR Flash with direct boot method
>>>> - POST support
>>>> - LOGBUF support
>>>>
>>>> Signed-off-by: Heiko Schocher <hs@denx.de>
>>>> Cc: Paulraj Sandeep <s-paulraj@ti.com>
>>>> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
>>>> Cc: Igor Grinberg <grinberg@compulab.co.il>
>>>> ---
>>>> - changes for v2
>>>> - use CONFIG_MACH_TYPE instead setting the MACH_TYPE in
>>>> board specific code, as Igor Grinberg suggested.
>>>> - add logversion=2 to default Environment
[...]
>> #define CONFIG_SYS_AM1808_PLL0_POSTDIV 1
>>
>> So the correct calculation is:
>>
>> (24MHz / PREDIV * (CONFIG_SYS_AM1808_PLL0_PLLM + 1)) / POSTDIV
>>
>> (And with that, I get 456 MHz ;-)
>
> But then you would be running PLL0 with 24MHz *
> (CONFIG_SYS_AM1808_PLL0_PLLM + 1) = 912 MHz !? That would be out of
> specs since the PLL output frequency must be between 300 and 600 MHz
> according to the datasheet.
Yep, you are right! Fixed
CONFIG_SYS_AM1808_PLL0_PLLM to 18
CONFIG_SYS_AM1808_PLL0_POSTDIV to 0
Thanks!
> However, you can't set the PLLM to 37 anyway, since it's only a 5 bit
> field, (37 & 0x1f) results in 5, so you only multiply the frequency by
> 6 in the PLL, resulting in 144MHz PLL frequency.
Hmm... you are right here also, but I see:
=> md 1c11100
01c11100: 00000049 00000014 00020000 00000000 I...............
01c11110: 00000025 00008000 00008000 00008001 %...............
^
Pllm
strange ...
Thanks for this review!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2011-09-30 9:32 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-09-15 5:59 [U-Boot] [PATCH 0/8] arm, davinci: add support for the am1808 based enbw_cmc board Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 1/8] arm, davinci: add SYSCFG1 base and register struct Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 2/8] arm, davinci: add some missing defines in hardware.h Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 3/8] arm, davinci, am1808, gpio: add missing defines for bank 8 Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 4/8] arm, davinci: add ddr2 definition Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 5/8] arm, davinci: add NOR Boot Configuration Word Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 6/8] arm, davinci, am1808: add lowlevel functions for booting from NOR Heiko Schocher
2011-09-26 8:02 ` Christian Riesch
2011-09-26 8:28 ` Heiko Schocher
2011-09-27 6:57 ` Christian Riesch
2011-09-27 7:27 ` Heiko Schocher
2011-09-27 8:37 ` Christian Riesch
2011-09-27 8:50 ` Heiko Schocher
2011-09-27 10:36 ` Christian Riesch
2011-09-27 11:18 ` Heiko Schocher
2011-09-30 6:57 ` Christian Riesch
2011-09-30 7:11 ` Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 7/8] arm, davinci, da8xx: add cpuinfo Heiko Schocher
2011-09-15 5:59 ` [U-Boot] [PATCH 8/8] arm, davinci: add support for am1808 based enbw_cmc board Heiko Schocher
2011-09-15 7:39 ` Igor Grinberg
2011-09-15 7:56 ` Heiko Schocher
2011-09-19 5:50 ` [U-Boot] [PATCH v2 " Heiko Schocher
2011-09-23 20:47 ` Paulraj, Sandeep
2011-09-26 5:43 ` Heiko Schocher
2011-09-26 6:03 ` Paulraj, Sandeep
2011-09-26 6:08 ` Heiko Schocher
2011-09-27 7:05 ` Albert ARIBAUD
2011-09-30 7:55 ` Christian Riesch
2011-09-30 8:46 ` Heiko Schocher
2011-09-30 9:02 ` Christian Riesch
2011-09-30 9:32 ` Heiko Schocher
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