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* [PULL 00/32] riscv-to-apply queue
@ 2021-06-08  0:29 Alistair Francis
  2021-06-08  0:29 ` [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Alistair Francis
                   ` (32 more replies)
  0 siblings, 33 replies; 40+ messages in thread
From: Alistair Francis @ 2021-06-08  0:29 UTC (permalink / raw)
  To: qemu-devel, peter.maydell; +Cc: alistair23, Alistair Francis

The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca:

  Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07 15:45:48 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210608-1

for you to fetch changes up to d2c1a177b138be35cb96216baa870c3564b123e4:

  target/riscv: rvb: add b-ext version cpu option (2021-06-08 09:59:46 +1000)

----------------------------------------------------------------
Second RISC-V PR for QEMU 6.1

 - Update the PLIC and CLINT DT bindings
 - Improve documentation for RISC-V machines
 - Support direct kernel boot for microchip_pfsoc
 - Fix WFI exception behaviour
 - Improve CSR printing
 - Initial support for the experimental Bit Manip extension

----------------------------------------------------------------
Alistair Francis (2):
      docs/system: Move the RISC-V -bios information to removed
      target/riscv/pmp: Add assert for ePMP operations

Bin Meng (9):
      hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
      hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
      hw/riscv: Support the official CLINT DT bindings
      hw/riscv: Support the official PLIC DT bindings
      docs/system/riscv: Correct the indentation level of supported devices
      docs/system/riscv: sifive_u: Document '-dtb' usage
      hw/riscv: Use macros for BIOS image names
      hw/riscv: microchip_pfsoc: Support direct kernel boot
      target/riscv: Remove unnecessary riscv_*_names[] declaration

Changbin Du (1):
      target/riscv: Dump CSR mscratch/sscratch/satp

Frank Chang (6):
      target/riscv: rvb: count bits set
      target/riscv: add gen_shifti() and gen_shiftiw() helper functions
      target/riscv: rvb: single-bit instructions
      target/riscv: rvb: generalized reverse
      target/riscv: rvb: generalized or-combine
      target/riscv: rvb: add b-ext version cpu option

Jose Martins (1):
      target/riscv: fix wfi exception behavior

Kito Cheng (11):
      target/riscv: reformat @sh format encoding for B-extension
      target/riscv: rvb: count leading/trailing zeros
      target/riscv: rvb: logic-with-negate
      target/riscv: rvb: pack two words into one register
      target/riscv: rvb: min/max instructions
      target/riscv: rvb: sign-extend instructions
      target/riscv: rvb: shift ones
      target/riscv: rvb: rotate (left/right)
      target/riscv: rvb: address calculation
      target/riscv: rvb: add/shift with prefix zero-extend
      target/riscv: rvb: support and turn on B-extension from command line

LIU Zhiwei (1):
      target/riscv: Pass the same value to oprsz and maxsz.

Philippe Mathieu-Daudé (1):
      target/riscv: Do not include 'pmp.h' in user emulation

 docs/system/deprecated.rst                 |  19 --
 docs/system/removed-features.rst           |   5 +
 docs/system/riscv/microchip-icicle-kit.rst |  50 +++-
 docs/system/riscv/sifive_u.rst             |  77 +++--
 docs/system/target-riscv.rst               |  13 +-
 include/hw/riscv/boot.h                    |   5 +
 target/riscv/cpu.h                         |   9 +-
 target/riscv/cpu_bits.h                    |   1 +
 target/riscv/helper.h                      |   6 +
 target/riscv/insn32.decode                 |  87 +++++-
 hw/riscv/microchip_pfsoc.c                 |  81 +++++-
 hw/riscv/sifive_u.c                        |  24 +-
 hw/riscv/spike.c                           |  12 +-
 hw/riscv/virt.c                            |  25 +-
 target/riscv/bitmanip_helper.c             |  90 ++++++
 target/riscv/cpu.c                         |  38 ++-
 target/riscv/op_helper.c                   |  11 +-
 target/riscv/pmp.c                         |   4 +
 target/riscv/translate.c                   | 306 ++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc    | 438 +++++++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvi.c.inc    |  54 +---
 target/riscv/insn_trans/trans_rvv.c.inc    |  89 +++---
 target/riscv/meson.build                   |   1 +
 23 files changed, 1260 insertions(+), 185 deletions(-)
 create mode 100644 target/riscv/bitmanip_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc


^ permalink raw reply	[flat|nested] 40+ messages in thread
* [PULL 00/32] riscv-to-apply queue
@ 2023-02-07  7:09 Alistair Francis
  2023-02-07 20:12 ` Peter Maydell
  0 siblings, 1 reply; 40+ messages in thread
From: Alistair Francis @ 2023-02-07  7:09 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b:

  Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging (2023-02-05 16:49:09 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230207

for you to fetch changes up to 5474aa4f3e0a3e9c171db7c55b5baf15f2e2778c:

  hw/riscv: virt: Simplify virt_{get,set}_aclint() (2023-02-07 08:21:32 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 8.0

* Update disas for xnor/orn/andn and slli.uw
* Update opentitan IRQs
* Fix rom code when Zicsr is disabled
* Update VS timer whenever htimedelta changes
* A collection of fixes for virtulisation
* Set tval for triggered watchpoints
* Cleanups for board and FDT creation
* Add support for the T-Head vendor extensions
* A fix for virtual instr exception
* Fix ctzw behavior
* Fix SBI getchar handler for KVM

----------------------------------------------------------------
Alistair Francis (1):
      hw/riscv: boot: Don't use CSRs if they are disabled

Anup Patel (4):
      target/riscv: Update VS timer whenever htimedelta changes
      target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
      target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
      target/riscv: Ensure opcode is saved for all relevant instructions

Bin Meng (1):
      hw/riscv: virt: Simplify virt_{get,set}_aclint()

Christoph Müllner (14):
      RISC-V: Adding XTheadCmo ISA extension
      RISC-V: Adding XTheadSync ISA extension
      RISC-V: Adding XTheadBa ISA extension
      RISC-V: Adding XTheadBb ISA extension
      RISC-V: Adding XTheadBs ISA extension
      RISC-V: Adding XTheadCondMov ISA extension
      RISC-V: Adding T-Head multiply-accumulate instructions
      RISC-V: Adding T-Head MemPair extension
      RISC-V: Adding T-Head MemIdx extension
      RISC-V: Adding T-Head FMemIdx extension
      RISC-V: Set minimum priv version for Zfh to 1.11
      RISC-V: Add initial support for T-Head C906
      RISC-V: Adding XTheadFmv ISA extension
      target/riscv: add a MAINTAINERS entry for XThead* extension support

Daniel Henrique Barboza (6):
      hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()
      hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'
      hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'
      hw/riscv/boot.c: calculate fdt size after fdt_pack()
      hw/riscv: split fdt address calculation from fdt load
      hw/riscv: change riscv_compute_fdt_addr() semantics

Deepak Gupta (1):
      target/riscv: fix for virtual instr exception

Philipp Tomsich (1):
      target/riscv: update disas.c for xnor/orn/andn and slli.uw

Sergey Matyukevich (1):
      target/riscv: set tval for triggered watchpoints

Vladimir Isaev (2):
      target/riscv: fix ctzw behavior
      target/riscv: fix SBI getchar handler for KVM

Wilfred Mallawa (1):
      include/hw/riscv/opentitan: update opentitan IRQs

 MAINTAINERS                                 |    8 +
 include/hw/riscv/boot.h                     |    4 +-
 include/hw/riscv/opentitan.h                |   14 +-
 target/riscv/cpu.h                          |   12 +
 target/riscv/cpu_vendorid.h                 |    6 +
 target/riscv/helper.h                       |    1 +
 target/riscv/xthead.decode                  |  185 +++++
 disas/riscv.c                               |    8 +-
 hw/riscv/boot.c                             |   62 +-
 hw/riscv/microchip_pfsoc.c                  |    7 +-
 hw/riscv/opentitan.c                        |   80 +-
 hw/riscv/sifive_u.c                         |    8 +-
 hw/riscv/spike.c                            |   25 +-
 hw/riscv/virt.c                             |  476 ++++++------
 target/riscv/cpu.c                          |   55 +-
 target/riscv/cpu_helper.c                   |    8 +-
 target/riscv/csr.c                          |   16 +
 target/riscv/debug.c                        |    1 -
 target/riscv/kvm.c                          |    5 +-
 target/riscv/op_helper.c                    |    6 +
 target/riscv/time_helper.c                  |   36 +-
 target/riscv/translate.c                    |   32 +
 target/riscv/insn_trans/trans_rva.c.inc     |   10 +-
 target/riscv/insn_trans/trans_rvb.c.inc     |    1 +
 target/riscv/insn_trans/trans_rvd.c.inc     |    2 +
 target/riscv/insn_trans/trans_rvf.c.inc     |    2 +
 target/riscv/insn_trans/trans_rvh.c.inc     |    3 +
 target/riscv/insn_trans/trans_rvi.c.inc     |    2 +
 target/riscv/insn_trans/trans_rvzfh.c.inc   |    2 +
 target/riscv/insn_trans/trans_svinval.c.inc |    3 +
 target/riscv/insn_trans/trans_xthead.c.inc  | 1094 +++++++++++++++++++++++++++
 target/riscv/meson.build                    |    1 +
 32 files changed, 1847 insertions(+), 328 deletions(-)
 create mode 100644 target/riscv/cpu_vendorid.h
 create mode 100644 target/riscv/xthead.decode
 create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc


^ permalink raw reply	[flat|nested] 40+ messages in thread
* [PULL 00/32] riscv-to-apply queue
@ 2020-06-19  6:24 Alistair Francis
  2020-06-19  7:22 ` no-reply
  2020-06-19 12:37 ` Peter Maydell
  0 siblings, 2 replies; 40+ messages in thread
From: Alistair Francis @ 2020-06-19  6:24 UTC (permalink / raw)
  To: peter.maydell, qemu-devel; +Cc: alistair23, Alistair Francis

The following changes since commit eefe34ea4b82c2b47abe28af4cc7247d51553626:

  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200617a' into staging (2020-06-18 15:30:13 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200618-1

for you to fetch changes up to fad6a8463510ff5e0fb31bb451a6c3218a45d179:

  hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-18 23:09:16 -0700)

----------------------------------------------------------------
This is a range of patches for RISC-V.

Some key points are:
 - Generalise the CPU init functions
 - Support the SiFive revB machine
 - Improvements to the Hypervisor implementation and error checking
 - Connect some OpenTitan devices
 - Changes to the sifive_u machine to support U-boot

----------------------------------------------------------------
Alistair Francis (11):
      sifive_e: Support the revB machine
      target/riscv: Set access as data_load when validating stage-2 PTEs
      target/riscv: Report errors validating 2nd-stage PTEs
      target/riscv: Move the hfence instructions to the rvh decode
      target/riscv: Implement checks for hfence
      riscv/opentitan: Fix the ROM size
      hw/char: Initial commit of Ibex UART
      hw/intc: Initial commit of lowRISC Ibex PLIC
      riscv/opentitan: Connect the PLIC device
      riscv/opentitan: Connect the UART device
      target/riscv: Use a smaller guess size for no-MMU PMP

Bin Meng (20):
      riscv: Generalize CPU init routine for the base CPU
      riscv: Generalize CPU init routine for the gcsu CPU
      riscv: Generalize CPU init routine for the imacu CPU
      riscv: Keep the CPU init routine names consistent
      hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
      hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
      hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
      hw/riscv: sifive_u: Generate device tree node for OTP
      hw/riscv: sifive_gpio: Clean up the codes
      hw/riscv: sifive_gpio: Add a new 'ngpio' property
      hw/riscv: sifive_u: Hook a GPIO controller
      hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
      hw/riscv: sifive_u: Add reset functionality
      hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
      hw/riscv: sifive_u: Add a new property msel for MSEL pin state
      target/riscv: Rename IBEX CPU init routine
      hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
      hw/riscv: sifive_u: Support different boot source per MSEL pin state
      hw/riscv: sifive_u: Sort the SoC memmap table entries
      hw/riscv: sifive_u: Add a dummy DDR memory controller device

Ian Jiang (1):
      riscv: Add helper to make NaN-boxing for FP register

 include/hw/char/ibex_uart.h                    | 110 ++++++
 include/hw/intc/ibex_plic.h                    |  63 ++++
 include/hw/riscv/opentitan.h                   |  16 +
 include/hw/riscv/sifive_e.h                    |   1 +
 include/hw/riscv/sifive_gpio.h                 |   8 +-
 include/hw/riscv/sifive_u.h                    |  27 ++
 target/riscv/helper.h                          |   5 +
 target/riscv/insn32.decode                     |   8 +-
 hw/char/ibex_uart.c                            | 492 +++++++++++++++++++++++++
 hw/intc/ibex_plic.c                            | 261 +++++++++++++
 hw/riscv/opentitan.c                           |  71 +++-
 hw/riscv/sifive_e.c                            |  60 ++-
 hw/riscv/sifive_gpio.c                         |  45 ++-
 hw/riscv/sifive_u.c                            | 157 ++++++--
 target/riscv/cpu.c                             |  69 ++--
 target/riscv/cpu_helper.c                      |   9 +-
 target/riscv/insn_trans/trans_privileged.inc.c |  38 --
 target/riscv/insn_trans/trans_rvf.inc.c        |  17 +-
 target/riscv/insn_trans/trans_rvh.inc.c        |  37 ++
 target/riscv/op_helper.c                       |  13 +
 target/riscv/pmp.c                             |  14 +-
 target/riscv/translate.c                       |   1 +
 MAINTAINERS                                    |   4 +
 hw/char/Makefile.objs                          |   1 +
 hw/intc/Makefile.objs                          |   1 +
 hw/riscv/Kconfig                               |   4 +
 26 files changed, 1350 insertions(+), 182 deletions(-)
 create mode 100644 include/hw/char/ibex_uart.h
 create mode 100644 include/hw/intc/ibex_plic.h
 create mode 100644 hw/char/ibex_uart.c
 create mode 100644 hw/intc/ibex_plic.c
 create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c


^ permalink raw reply	[flat|nested] 40+ messages in thread
end of thread, other threads:[~2023-02-07 20:13 UTC | newest]

Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-08  0:29 [PULL 00/32] riscv-to-apply queue Alistair Francis
2021-06-08  0:29 ` [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Alistair Francis
2021-06-08  0:29 ` [PULL 02/32] hw/riscv: virt: " Alistair Francis
2021-06-08  0:29 ` [PULL 03/32] hw/riscv: Support the official CLINT DT bindings Alistair Francis
2021-06-08  0:29 ` [PULL 04/32] hw/riscv: Support the official PLIC " Alistair Francis
2021-06-08  0:29 ` [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices Alistair Francis
2021-06-08  0:29 ` [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage Alistair Francis
2021-06-08  0:29 ` [PULL 07/32] hw/riscv: Use macros for BIOS image names Alistair Francis
2021-06-08  0:29 ` [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot Alistair Francis
2021-06-08  0:29 ` [PULL 09/32] target/riscv: fix wfi exception behavior Alistair Francis
2021-06-08  0:29 ` [PULL 10/32] docs/system: Move the RISC-V -bios information to removed Alistair Francis
2021-06-08  0:29 ` [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation Alistair Francis
2021-06-08  0:29 ` [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration Alistair Francis
2021-06-08  0:29 ` [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp Alistair Francis
2021-06-08  0:29 ` [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations Alistair Francis
2021-06-08  0:29 ` [PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz Alistair Francis
2021-06-08  0:29 ` [PULL 16/32] target/riscv: reformat @sh format encoding for B-extension Alistair Francis
2021-06-08  0:29 ` [PULL 17/32] target/riscv: rvb: count leading/trailing zeros Alistair Francis
2021-06-08  0:29 ` [PULL 18/32] target/riscv: rvb: count bits set Alistair Francis
2021-06-08  0:29 ` [PULL 19/32] target/riscv: rvb: logic-with-negate Alistair Francis
2021-06-08  0:29 ` [PULL 20/32] target/riscv: rvb: pack two words into one register Alistair Francis
2021-06-08  0:29 ` [PULL 21/32] target/riscv: rvb: min/max instructions Alistair Francis
2021-06-08  0:29 ` [PULL 22/32] target/riscv: rvb: sign-extend instructions Alistair Francis
2021-06-08  0:29 ` [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions Alistair Francis
2021-06-08  0:29 ` [PULL 24/32] target/riscv: rvb: single-bit instructions Alistair Francis
2021-06-08  0:29 ` [PULL 25/32] target/riscv: rvb: shift ones Alistair Francis
2021-06-08  0:29 ` [PULL 26/32] target/riscv: rvb: rotate (left/right) Alistair Francis
2021-06-08  0:29 ` [PULL 27/32] target/riscv: rvb: generalized reverse Alistair Francis
2021-06-08  0:29 ` [PULL 28/32] target/riscv: rvb: generalized or-combine Alistair Francis
2021-06-08  0:29 ` [PULL 29/32] target/riscv: rvb: address calculation Alistair Francis
2021-06-08  0:29 ` [PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend Alistair Francis
2021-06-08  0:29 ` [PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line Alistair Francis
2021-06-08  0:29 ` [PULL 32/32] target/riscv: rvb: add b-ext version cpu option Alistair Francis
2021-06-08 16:50 ` [PULL 00/32] riscv-to-apply queue Peter Maydell
  -- strict thread matches above, loose matches on Subject: below --
2023-02-07  7:09 Alistair Francis
2023-02-07 20:12 ` Peter Maydell
2020-06-19  6:24 Alistair Francis
2020-06-19  7:22 ` no-reply
2020-06-19 12:37 ` Peter Maydell
2020-06-19 15:27   ` Alistair Francis

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