* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-05-22 3:25 ` Anson Huang
0 siblings, 0 replies; 24+ messages in thread
From: Anson Huang @ 2018-05-22 3:25 UTC (permalink / raw)
To: linux-arm-kernel
i.MX6UL has GPIO clock gates in CCM CCGR, add
them into clock tree for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
drivers/clk/imx/clk-imx6ul.c | 5 +++++
include/dt-bindings/clock/imx6ul-clock.h | 31 ++++++++++++++++++-------------
2 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index ba563ba..3ea2d97 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -360,6 +360,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
if (clk_on_imx6ull())
clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18);
+ clks[IMX6UL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30);
/* CCGR1 */
clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
@@ -376,6 +377,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
+ clks[IMX6UL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
+ clks[IMX6UL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
/* CCGR2 */
if (clk_on_imx6ull()) {
@@ -389,6 +392,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14);
+ clks[IMX6UL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26);
clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
@@ -405,6 +409,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6);
clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6);
clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
+ clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index 9564597..1291328 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -242,20 +242,25 @@
#define IMX6UL_CLK_CKO2_PODF 229
#define IMX6UL_CLK_CKO2 230
#define IMX6UL_CLK_CKO 231
+#define IMX6UL_CLK_GPIO1 232
+#define IMX6UL_CLK_GPIO2 233
+#define IMX6UL_CLK_GPIO3 234
+#define IMX6UL_CLK_GPIO4 235
+#define IMX6UL_CLK_GPIO5 236
/* For i.MX6ULL */
-#define IMX6ULL_CLK_ESAI_PRED 232
-#define IMX6ULL_CLK_ESAI_PODF 233
-#define IMX6ULL_CLK_ESAI_EXTAL 234
-#define IMX6ULL_CLK_ESAI_MEM 235
-#define IMX6ULL_CLK_ESAI_IPG 236
-#define IMX6ULL_CLK_DCP_CLK 237
-#define IMX6ULL_CLK_EPDC_PRE_SEL 238
-#define IMX6ULL_CLK_EPDC_SEL 239
-#define IMX6ULL_CLK_EPDC_PODF 240
-#define IMX6ULL_CLK_EPDC_ACLK 241
-#define IMX6ULL_CLK_EPDC_PIX 242
-#define IMX6ULL_CLK_ESAI_SEL 243
-#define IMX6UL_CLK_END 244
+#define IMX6ULL_CLK_ESAI_PRED 237
+#define IMX6ULL_CLK_ESAI_PODF 238
+#define IMX6ULL_CLK_ESAI_EXTAL 239
+#define IMX6ULL_CLK_ESAI_MEM 240
+#define IMX6ULL_CLK_ESAI_IPG 241
+#define IMX6ULL_CLK_DCP_CLK 242
+#define IMX6ULL_CLK_EPDC_PRE_SEL 243
+#define IMX6ULL_CLK_EPDC_SEL 244
+#define IMX6ULL_CLK_EPDC_PODF 245
+#define IMX6ULL_CLK_EPDC_ACLK 246
+#define IMX6ULL_CLK_EPDC_PIX 247
+#define IMX6ULL_CLK_ESAI_SEL 248
+#define IMX6UL_CLK_END 249
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 2/2] ARM: dts: imx6ul: add GPIO clocks
2018-05-22 3:25 ` Anson Huang
@ 2018-05-22 3:26 ` Anson Huang
-1 siblings, 0 replies; 24+ messages in thread
From: Anson Huang @ 2018-05-22 3:26 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland,
mturquette, sboyd, michael, matteo.lisi
Cc: Linux-imx, linux-arm-kernel, devicetree, linux-kernel, linux-clk
i.MX6UL has GPIO clock gates in CCM CCGR, add
clock property for GPIO driver to make sure all
GPIO banks work as expected.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 1241972..405e068 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -437,6 +437,7 @@
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -450,6 +451,7 @@
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -462,6 +464,7 @@
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -474,6 +477,7 @@
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -486,6 +490,7 @@
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/2] ARM: dts: imx6ul: add GPIO clocks
@ 2018-05-22 3:26 ` Anson Huang
0 siblings, 0 replies; 24+ messages in thread
From: Anson Huang @ 2018-05-22 3:26 UTC (permalink / raw)
To: linux-arm-kernel
i.MX6UL has GPIO clock gates in CCM CCGR, add
clock property for GPIO driver to make sure all
GPIO banks work as expected.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 1241972..405e068 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -437,6 +437,7 @@
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -450,6 +451,7 @@
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -462,6 +464,7 @@
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -474,6 +477,7 @@
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -486,6 +490,7 @@
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 2/2] ARM: dts: imx6ul: add GPIO clocks
2018-05-22 3:26 ` Anson Huang
@ 2018-05-22 11:26 ` Fabio Estevam
-1 siblings, 0 replies; 24+ messages in thread
From: Fabio Estevam @ 2018-05-22 11:26 UTC (permalink / raw)
To: Anson Huang
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring,
Mark Rutland, Michael Turquette, Stephen Boyd, Michael Trimarchi,
Matteo Lisi, NXP Linux Team,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel, linux-clk
On Tue, May 22, 2018 at 12:26 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> clock property for GPIO driver to make sure all
> GPIO banks work as expected.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 2/2] ARM: dts: imx6ul: add GPIO clocks
@ 2018-05-22 11:26 ` Fabio Estevam
0 siblings, 0 replies; 24+ messages in thread
From: Fabio Estevam @ 2018-05-22 11:26 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 22, 2018 at 12:26 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> clock property for GPIO driver to make sure all
> GPIO banks work as expected.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
2018-05-22 3:25 ` Anson Huang
@ 2018-05-22 11:25 ` Fabio Estevam
-1 siblings, 0 replies; 24+ messages in thread
From: Fabio Estevam @ 2018-05-22 11:25 UTC (permalink / raw)
To: Anson Huang
Cc: Shawn Guo, Sascha Hauer, Fabio Estevam, Rob Herring,
Mark Rutland, Michael Turquette, Stephen Boyd, Michael Trimarchi,
Matteo Lisi, NXP Linux Team,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel, linux-clk
On Tue, May 22, 2018 at 12:25 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> them into clock tree for clock management.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-05-22 11:25 ` Fabio Estevam
0 siblings, 0 replies; 24+ messages in thread
From: Fabio Estevam @ 2018-05-22 11:25 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 22, 2018 at 12:25 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> them into clock tree for clock management.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
2018-05-22 3:25 ` Anson Huang
@ 2018-05-22 12:25 ` Stefan Wahren
-1 siblings, 0 replies; 24+ messages in thread
From: Stefan Wahren @ 2018-05-22 12:25 UTC (permalink / raw)
To: michael, robh+dt, fabio.estevam, mark.rutland, Anson Huang,
matteo.lisi, shawnguo, kernel, mturquette, sboyd
Cc: linux-clk, Linux-imx, devicetree, linux-kernel, linux-arm-kernel
Hi Anson,
> Anson Huang <Anson.Huang@nxp.com> hat am 22. Mai 2018 um 05:25 geschrieben:
>
>
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> them into clock tree for clock management.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> drivers/clk/imx/clk-imx6ul.c | 5 +++++
> include/dt-bindings/clock/imx6ul-clock.h | 31 ++++++++++++++++++-------------
> 2 files changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index ba563ba..3ea2d97 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -360,6 +360,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
> if (clk_on_imx6ull())
> clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18);
> + clks[IMX6UL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30);
>
> /* CCGR1 */
> clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
> @@ -376,6 +377,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
> clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
> clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
> + clks[IMX6UL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
> + clks[IMX6UL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
>
> /* CCGR2 */
> if (clk_on_imx6ull()) {
> @@ -389,6 +392,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
> clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
> clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14);
> + clks[IMX6UL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26);
> clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
> clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
>
> @@ -405,6 +409,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6);
> clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6);
> clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
> + clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
> clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
> clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
> clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
> diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
> index 9564597..1291328 100644
> --- a/include/dt-bindings/clock/imx6ul-clock.h
> +++ b/include/dt-bindings/clock/imx6ul-clock.h
> @@ -242,20 +242,25 @@
> #define IMX6UL_CLK_CKO2_PODF 229
> #define IMX6UL_CLK_CKO2 230
> #define IMX6UL_CLK_CKO 231
> +#define IMX6UL_CLK_GPIO1 232
> +#define IMX6UL_CLK_GPIO2 233
> +#define IMX6UL_CLK_GPIO3 234
> +#define IMX6UL_CLK_GPIO4 235
> +#define IMX6UL_CLK_GPIO5 236
this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.
>
> /* For i.MX6ULL */
> -#define IMX6ULL_CLK_ESAI_PRED 232
> -#define IMX6ULL_CLK_ESAI_PODF 233
> -#define IMX6ULL_CLK_ESAI_EXTAL 234
> -#define IMX6ULL_CLK_ESAI_MEM 235
> -#define IMX6ULL_CLK_ESAI_IPG 236
> -#define IMX6ULL_CLK_DCP_CLK 237
> -#define IMX6ULL_CLK_EPDC_PRE_SEL 238
> -#define IMX6ULL_CLK_EPDC_SEL 239
> -#define IMX6ULL_CLK_EPDC_PODF 240
> -#define IMX6ULL_CLK_EPDC_ACLK 241
> -#define IMX6ULL_CLK_EPDC_PIX 242
> -#define IMX6ULL_CLK_ESAI_SEL 243
> -#define IMX6UL_CLK_END 244
> +#define IMX6ULL_CLK_ESAI_PRED 237
> +#define IMX6ULL_CLK_ESAI_PODF 238
> +#define IMX6ULL_CLK_ESAI_EXTAL 239
> +#define IMX6ULL_CLK_ESAI_MEM 240
> +#define IMX6ULL_CLK_ESAI_IPG 241
> +#define IMX6ULL_CLK_DCP_CLK 242
> +#define IMX6ULL_CLK_EPDC_PRE_SEL 243
> +#define IMX6ULL_CLK_EPDC_SEL 244
> +#define IMX6ULL_CLK_EPDC_PODF 245
> +#define IMX6ULL_CLK_EPDC_ACLK 246
> +#define IMX6ULL_CLK_EPDC_PIX 247
> +#define IMX6ULL_CLK_ESAI_SEL 248
> +#define IMX6UL_CLK_END 249
>
> #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-05-22 12:25 ` Stefan Wahren
0 siblings, 0 replies; 24+ messages in thread
From: Stefan Wahren @ 2018-05-22 12:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi Anson,
> Anson Huang <Anson.Huang@nxp.com> hat am 22. Mai 2018 um 05:25 geschrieben:
>
>
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> them into clock tree for clock management.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> drivers/clk/imx/clk-imx6ul.c | 5 +++++
> include/dt-bindings/clock/imx6ul-clock.h | 31 ++++++++++++++++++-------------
> 2 files changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index ba563ba..3ea2d97 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -360,6 +360,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
> if (clk_on_imx6ull())
> clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18);
> + clks[IMX6UL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30);
>
> /* CCGR1 */
> clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
> @@ -376,6 +377,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
> clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
> clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
> + clks[IMX6UL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
> + clks[IMX6UL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
>
> /* CCGR2 */
> if (clk_on_imx6ull()) {
> @@ -389,6 +392,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
> clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
> clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14);
> + clks[IMX6UL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26);
> clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
> clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
>
> @@ -405,6 +409,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6);
> clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6);
> clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
> + clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
> clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
> clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
> clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
> diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
> index 9564597..1291328 100644
> --- a/include/dt-bindings/clock/imx6ul-clock.h
> +++ b/include/dt-bindings/clock/imx6ul-clock.h
> @@ -242,20 +242,25 @@
> #define IMX6UL_CLK_CKO2_PODF 229
> #define IMX6UL_CLK_CKO2 230
> #define IMX6UL_CLK_CKO 231
> +#define IMX6UL_CLK_GPIO1 232
> +#define IMX6UL_CLK_GPIO2 233
> +#define IMX6UL_CLK_GPIO3 234
> +#define IMX6UL_CLK_GPIO4 235
> +#define IMX6UL_CLK_GPIO5 236
this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.
>
> /* For i.MX6ULL */
> -#define IMX6ULL_CLK_ESAI_PRED 232
> -#define IMX6ULL_CLK_ESAI_PODF 233
> -#define IMX6ULL_CLK_ESAI_EXTAL 234
> -#define IMX6ULL_CLK_ESAI_MEM 235
> -#define IMX6ULL_CLK_ESAI_IPG 236
> -#define IMX6ULL_CLK_DCP_CLK 237
> -#define IMX6ULL_CLK_EPDC_PRE_SEL 238
> -#define IMX6ULL_CLK_EPDC_SEL 239
> -#define IMX6ULL_CLK_EPDC_PODF 240
> -#define IMX6ULL_CLK_EPDC_ACLK 241
> -#define IMX6ULL_CLK_EPDC_PIX 242
> -#define IMX6ULL_CLK_ESAI_SEL 243
> -#define IMX6UL_CLK_END 244
> +#define IMX6ULL_CLK_ESAI_PRED 237
> +#define IMX6ULL_CLK_ESAI_PODF 238
> +#define IMX6ULL_CLK_ESAI_EXTAL 239
> +#define IMX6ULL_CLK_ESAI_MEM 240
> +#define IMX6ULL_CLK_ESAI_IPG 241
> +#define IMX6ULL_CLK_DCP_CLK 242
> +#define IMX6ULL_CLK_EPDC_PRE_SEL 243
> +#define IMX6ULL_CLK_EPDC_SEL 244
> +#define IMX6ULL_CLK_EPDC_PODF 245
> +#define IMX6ULL_CLK_EPDC_ACLK 246
> +#define IMX6ULL_CLK_EPDC_PIX 247
> +#define IMX6ULL_CLK_ESAI_SEL 248
> +#define IMX6UL_CLK_END 249
>
> #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
2018-05-22 12:25 ` Stefan Wahren
(?)
@ 2018-06-02 6:19 ` Stephen Boyd
-1 siblings, 0 replies; 24+ messages in thread
From: Stephen Boyd @ 2018-06-02 6:19 UTC (permalink / raw)
To: Anson Huang, Stefan Wahren, fabio.estevam, kernel, mark.rutland,
matteo.lisi, michael, mturquette, robh+dt, shawnguo
Cc: linux-clk, Linux-imx, devicetree, linux-kernel, linux-arm-kernel
Quoting Stefan Wahren (2018-05-22 05:25:35)
> > +++ b/include/dt-bindings/clock/imx6ul-clock.h
> > @@ -242,20 +242,25 @@
> > #define IMX6UL_CLK_CKO2_PODF 229
> > #define IMX6UL_CLK_CKO2 230
> > #define IMX6UL_CLK_CKO 231
> > +#define IMX6UL_CLK_GPIO1 232
> > +#define IMX6UL_CLK_GPIO2 233
> > +#define IMX6UL_CLK_GPIO3 234
> > +#define IMX6UL_CLK_GPIO4 235
> > +#define IMX6UL_CLK_GPIO5 236
>
> this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.
>
Agreed. Why can't we just tack on more numbers at the end?
> >
> > /* For i.MX6ULL */
> > -#define IMX6ULL_CLK_ESAI_PRED 232
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-06-02 6:19 ` Stephen Boyd
0 siblings, 0 replies; 24+ messages in thread
From: Stephen Boyd @ 2018-06-02 6:19 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Stefan Wahren (2018-05-22 05:25:35)
> > +++ b/include/dt-bindings/clock/imx6ul-clock.h
> > @@ -242,20 +242,25 @@
> > #define IMX6UL_CLK_CKO2_PODF 229
> > #define IMX6UL_CLK_CKO2 230
> > #define IMX6UL_CLK_CKO 231
> > +#define IMX6UL_CLK_GPIO1 232
> > +#define IMX6UL_CLK_GPIO2 233
> > +#define IMX6UL_CLK_GPIO3 234
> > +#define IMX6UL_CLK_GPIO4 235
> > +#define IMX6UL_CLK_GPIO5 236
>
> this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.
>
Agreed. Why can't we just tack on more numbers at the end?
> >
> > /* For i.MX6ULL */
> > -#define IMX6ULL_CLK_ESAI_PRED 232
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-06-02 6:19 ` Stephen Boyd
0 siblings, 0 replies; 24+ messages in thread
From: Stephen Boyd @ 2018-06-02 6:19 UTC (permalink / raw)
To: Anson Huang, Stefan Wahren, fabio.estevam, kernel, mark.rutland,
matteo.lisi, michael, mturquette, robh+dt, shawnguo
Cc: linux-clk, Linux-imx, devicetree, linux-kernel, linux-arm-kernel
Quoting Stefan Wahren (2018-05-22 05:25:35)
> > +++ b/include/dt-bindings/clock/imx6ul-clock.h
> > @@ -242,20 +242,25 @@
> > #define IMX6UL_CLK_CKO2_PODF 229
> > #define IMX6UL_CLK_CKO2 230
> > #define IMX6UL_CLK_CKO 231
> > +#define IMX6UL_CLK_GPIO1 232
> > +#define IMX6UL_CLK_GPIO2 233
> > +#define IMX6UL_CLK_GPIO3 234
> > +#define IMX6UL_CLK_GPIO4 235
> > +#define IMX6UL_CLK_GPIO5 236
> =
> this change looks like a breakage of devicetree ABI. You are changing the=
mean of the existing clock IDs on i.MX6ULL, which probably regress the com=
bination of older DTBs with newer kernel.
> =
Agreed. Why can't we just tack on more numbers at the end?
> > =
> > /* For i.MX6ULL */
> > -#define IMX6ULL_CLK_ESAI_PRED 232
^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
2018-06-02 6:19 ` Stephen Boyd
(?)
@ 2018-06-03 1:36 ` Anson Huang
-1 siblings, 0 replies; 24+ messages in thread
From: Anson Huang @ 2018-06-03 1:36 UTC (permalink / raw)
To: Stephen Boyd, Stefan Wahren, Fabio Estevam, kernel, mark.rutland,
matteo.lisi, michael, mturquette, robh+dt, shawnguo
Cc: linux-clk, dl-linux-imx, devicetree, linux-kernel, linux-arm-kernel
Hi, Stephen
Anson Huang
Best Regards!
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
> Sent: Saturday, June 2, 2018 2:19 PM
> To: Anson Huang <anson.huang@nxp.com>; Stefan Wahren
> <stefan.wahren@i2se.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> kernel@pengutronix.de; mark.rutland@arm.com; matteo.lisi@engicam.com;
> michael@amarulasolutions.com; mturquette@baylibre.com;
> robh+dt@kernel.org; shawnguo@kernel.org
> Cc: linux-clk@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
>
> Quoting Stefan Wahren (2018-05-22 05:25:35)
> > > +++ b/include/dt-bindings/clock/imx6ul-clock.h
> > > @@ -242,20 +242,25 @@
> > > #define IMX6UL_CLK_CKO2_PODF 229
> > > #define IMX6UL_CLK_CKO2 230
> > > #define IMX6UL_CLK_CKO 231
> > > +#define IMX6UL_CLK_GPIO1 232
> > > +#define IMX6UL_CLK_GPIO2 233
> > > +#define IMX6UL_CLK_GPIO3 234
> > > +#define IMX6UL_CLK_GPIO4 235
> > > +#define IMX6UL_CLK_GPIO5 236
> >
> > this change looks like a breakage of devicetree ABI. You are changing the
> mean of the existing clock IDs on i.MX6ULL, which probably regress the
> combination of older DTBs with newer kernel.
> >
>
> Agreed. Why can't we just tack on more numbers at the end?
Ah, yes, I saw 6ULL are at the end of 6UL, so added them in 6UL, but did NOT consider the old dtb support.
Will send out a V2 patch to fix it, and I saw Fabio also sent a patch to fix the clko1/2 definition, I will do the
V2 patch based on his patch.
Anson.
>
> > >
> > > /* For i.MX6ULL */
> > > -#define IMX6ULL_CLK_ESAI_PRED 232
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-06-03 1:36 ` Anson Huang
0 siblings, 0 replies; 24+ messages in thread
From: Anson Huang @ 2018-06-03 1:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi, Stephen
Anson Huang
Best Regards!
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd at kernel.org]
> Sent: Saturday, June 2, 2018 2:19 PM
> To: Anson Huang <anson.huang@nxp.com>; Stefan Wahren
> <stefan.wahren@i2se.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> kernel at pengutronix.de; mark.rutland at arm.com; matteo.lisi at engicam.com;
> michael at amarulasolutions.com; mturquette at baylibre.com;
> robh+dt at kernel.org; shawnguo at kernel.org
> Cc: linux-clk at vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
>
> Quoting Stefan Wahren (2018-05-22 05:25:35)
> > > +++ b/include/dt-bindings/clock/imx6ul-clock.h
> > > @@ -242,20 +242,25 @@
> > > #define IMX6UL_CLK_CKO2_PODF 229
> > > #define IMX6UL_CLK_CKO2 230
> > > #define IMX6UL_CLK_CKO 231
> > > +#define IMX6UL_CLK_GPIO1 232
> > > +#define IMX6UL_CLK_GPIO2 233
> > > +#define IMX6UL_CLK_GPIO3 234
> > > +#define IMX6UL_CLK_GPIO4 235
> > > +#define IMX6UL_CLK_GPIO5 236
> >
> > this change looks like a breakage of devicetree ABI. You are changing the
> mean of the existing clock IDs on i.MX6ULL, which probably regress the
> combination of older DTBs with newer kernel.
> >
>
> Agreed. Why can't we just tack on more numbers at the end?
Ah, yes, I saw 6ULL are at the end of 6UL, so added them in 6UL, but did NOT consider the old dtb support.
Will send out a V2 patch to fix it, and I saw Fabio also sent a patch to fix the clko1/2 definition, I will do the
V2 patch based on his patch.
Anson.
>
> > >
> > > /* For i.MX6ULL */
> > > -#define IMX6ULL_CLK_ESAI_PRED 232
^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-06-03 1:36 ` Anson Huang
0 siblings, 0 replies; 24+ messages in thread
From: Anson Huang @ 2018-06-03 1:36 UTC (permalink / raw)
To: Stephen Boyd, Stefan Wahren, Fabio Estevam, kernel, mark.rutland,
matteo.lisi, michael, mturquette, robh+dt, shawnguo
Cc: linux-clk, dl-linux-imx, devicetree, linux-kernel, linux-arm-kernel
SGksIFN0ZXBoZW4NCg0KQW5zb24gSHVhbmcNCkJlc3QgUmVnYXJkcyENCg0KDQo+IC0tLS0tT3Jp
Z2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IFN0ZXBoZW4gQm95ZCBbbWFpbHRvOnNib3lkQGtl
cm5lbC5vcmddDQo+IFNlbnQ6IFNhdHVyZGF5LCBKdW5lIDIsIDIwMTggMjoxOSBQTQ0KPiBUbzog
QW5zb24gSHVhbmcgPGFuc29uLmh1YW5nQG54cC5jb20+OyBTdGVmYW4gV2FocmVuDQo+IDxzdGVm
YW4ud2FocmVuQGkyc2UuY29tPjsgRmFiaW8gRXN0ZXZhbSA8ZmFiaW8uZXN0ZXZhbUBueHAuY29t
PjsNCj4ga2VybmVsQHBlbmd1dHJvbml4LmRlOyBtYXJrLnJ1dGxhbmRAYXJtLmNvbTsgbWF0dGVv
Lmxpc2lAZW5naWNhbS5jb207DQo+IG1pY2hhZWxAYW1hcnVsYXNvbHV0aW9ucy5jb207IG10dXJx
dWV0dGVAYmF5bGlicmUuY29tOw0KPiByb2JoK2R0QGtlcm5lbC5vcmc7IHNoYXduZ3VvQGtlcm5l
bC5vcmcNCj4gQ2M6IGxpbnV4LWNsa0B2Z2VyLmtlcm5lbC5vcmc7IGRsLWxpbnV4LWlteCA8bGlu
dXgtaW14QG54cC5jb20+Ow0KPiBkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZzsgbGludXgta2Vy
bmVsQHZnZXIua2VybmVsLm9yZzsNCj4gbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQu
b3JnDQo+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggMS8yXSBjbGs6IGlteDZ1bDogYWRkIEdQSU8gY2xv
Y2sgZ2F0ZXMNCj4gDQo+IFF1b3RpbmcgU3RlZmFuIFdhaHJlbiAoMjAxOC0wNS0yMiAwNToyNToz
NSkNCj4gPiA+ICsrKyBiL2luY2x1ZGUvZHQtYmluZGluZ3MvY2xvY2svaW14NnVsLWNsb2NrLmgN
Cj4gPiA+IEBAIC0yNDIsMjAgKzI0MiwyNSBAQA0KPiA+ID4gICNkZWZpbmUgSU1YNlVMX0NMS19D
S08yX1BPREYgICAgICAgICAyMjkNCj4gPiA+ICAjZGVmaW5lIElNWDZVTF9DTEtfQ0tPMiAgICAg
ICAgICAgICAgICAgICAgICAyMzANCj4gPiA+ICAjZGVmaW5lIElNWDZVTF9DTEtfQ0tPICAgICAg
ICAgICAgICAgICAgICAgICAyMzENCj4gPiA+ICsjZGVmaW5lIElNWDZVTF9DTEtfR1BJTzEgICAg
ICAgICAgICAgMjMyDQo+ID4gPiArI2RlZmluZSBJTVg2VUxfQ0xLX0dQSU8yICAgICAgICAgICAg
IDIzMw0KPiA+ID4gKyNkZWZpbmUgSU1YNlVMX0NMS19HUElPMyAgICAgICAgICAgICAyMzQNCj4g
PiA+ICsjZGVmaW5lIElNWDZVTF9DTEtfR1BJTzQgICAgICAgICAgICAgMjM1DQo+ID4gPiArI2Rl
ZmluZSBJTVg2VUxfQ0xLX0dQSU81ICAgICAgICAgICAgIDIzNg0KPiA+DQo+ID4gdGhpcyBjaGFu
Z2UgbG9va3MgbGlrZSBhIGJyZWFrYWdlIG9mIGRldmljZXRyZWUgQUJJLiBZb3UgYXJlIGNoYW5n
aW5nIHRoZQ0KPiBtZWFuIG9mIHRoZSBleGlzdGluZyBjbG9jayBJRHMgb24gaS5NWDZVTEwsIHdo
aWNoIHByb2JhYmx5IHJlZ3Jlc3MgdGhlDQo+IGNvbWJpbmF0aW9uIG9mIG9sZGVyIERUQnMgd2l0
aCBuZXdlciBrZXJuZWwuDQo+ID4NCj4gDQo+IEFncmVlZC4gV2h5IGNhbid0IHdlIGp1c3QgdGFj
ayBvbiBtb3JlIG51bWJlcnMgYXQgdGhlIGVuZD8NCiANCkFoLCB5ZXMsIEkgc2F3IDZVTEwgYXJl
IGF0IHRoZSBlbmQgb2YgNlVMLCBzbyBhZGRlZCB0aGVtIGluIDZVTCwgYnV0IGRpZCBOT1QgY29u
c2lkZXIgdGhlIG9sZCBkdGIgc3VwcG9ydC4NCg0KV2lsbCBzZW5kIG91dCBhIFYyIHBhdGNoIHRv
IGZpeCBpdCwgYW5kIEkgc2F3IEZhYmlvIGFsc28gc2VudCBhIHBhdGNoIHRvIGZpeCB0aGUgY2xr
bzEvMiBkZWZpbml0aW9uLCBJIHdpbGwgZG8gdGhlDQpWMiBwYXRjaCBiYXNlZCBvbiBoaXMgcGF0
Y2guDQoNCkFuc29uLg0KDQo+IA0KPiA+ID4NCj4gPiA+ICAvKiBGb3IgaS5NWDZVTEwgKi8NCj4g
PiA+IC0jZGVmaW5lIElNWDZVTExfQ0xLX0VTQUlfUFJFRCAgICAgICAgICAgICAgICAyMzINCg==
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
2018-05-22 12:25 ` Stefan Wahren
@ 2018-06-02 13:48 ` Fabio Estevam
-1 siblings, 0 replies; 24+ messages in thread
From: Fabio Estevam @ 2018-06-02 13:48 UTC (permalink / raw)
To: Stefan Wahren
Cc: Michael Trimarchi, Rob Herring, Fabio Estevam, Mark Rutland,
Anson Huang, Matteo Lisi, Shawn Guo, Sascha Hauer,
Michael Turquette, Stephen Boyd, linux-clk, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Stefan,
On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren <stefan.wahren@i2se.com> wrote:
>> --- a/include/dt-bindings/clock/imx6ul-clock.h
>> +++ b/include/dt-bindings/clock/imx6ul-clock.h
>> @@ -242,20 +242,25 @@
>> #define IMX6UL_CLK_CKO2_PODF 229
>> #define IMX6UL_CLK_CKO2 230
>> #define IMX6UL_CLK_CKO 231
>> +#define IMX6UL_CLK_GPIO1 232
>> +#define IMX6UL_CLK_GPIO2 233
>> +#define IMX6UL_CLK_GPIO3 234
>> +#define IMX6UL_CLK_GPIO4 235
>> +#define IMX6UL_CLK_GPIO5 236
>
> this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.
Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new
clo01 and clo2 controlled
by CCOSR") which did the same reordering.
Thanks
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-06-02 13:48 ` Fabio Estevam
0 siblings, 0 replies; 24+ messages in thread
From: Fabio Estevam @ 2018-06-02 13:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi Stefan,
On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren <stefan.wahren@i2se.com> wrote:
>> --- a/include/dt-bindings/clock/imx6ul-clock.h
>> +++ b/include/dt-bindings/clock/imx6ul-clock.h
>> @@ -242,20 +242,25 @@
>> #define IMX6UL_CLK_CKO2_PODF 229
>> #define IMX6UL_CLK_CKO2 230
>> #define IMX6UL_CLK_CKO 231
>> +#define IMX6UL_CLK_GPIO1 232
>> +#define IMX6UL_CLK_GPIO2 233
>> +#define IMX6UL_CLK_GPIO3 234
>> +#define IMX6UL_CLK_GPIO4 235
>> +#define IMX6UL_CLK_GPIO5 236
>
> this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.
Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new
clo01 and clo2 controlled
by CCOSR") which did the same reordering.
Thanks
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
2018-06-02 13:48 ` Fabio Estevam
@ 2018-06-02 14:04 ` Michael Nazzareno Trimarchi
-1 siblings, 0 replies; 24+ messages in thread
From: Michael Nazzareno Trimarchi @ 2018-06-02 14:04 UTC (permalink / raw)
To: Fabio Estevam
Cc: Stefan Wahren, Rob Herring, Fabio Estevam, Mark Rutland,
Anson Huang, Matteo Lisi, Shawn Guo, Sascha Hauer,
Michael Turquette, Stephen Boyd, linux-clk, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi
On Sat, Jun 2, 2018 at 3:48 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Stefan,
>
> On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren <stefan.wahren@i2se.com> wrote:
>
>>> --- a/include/dt-bindings/clock/imx6ul-clock.h
>>> +++ b/include/dt-bindings/clock/imx6ul-clock.h
>>> @@ -242,20 +242,25 @@
>>> #define IMX6UL_CLK_CKO2_PODF 229
>>> #define IMX6UL_CLK_CKO2 230
>>> #define IMX6UL_CLK_CKO 231
>>> +#define IMX6UL_CLK_GPIO1 232
>>> +#define IMX6UL_CLK_GPIO2 233
>>> +#define IMX6UL_CLK_GPIO3 234
>>> +#define IMX6UL_CLK_GPIO4 235
>>> +#define IMX6UL_CLK_GPIO5 236
>>
>> this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.
>
> Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new
> clo01 and clo2 controlled
> by CCOSR") which did the same reordering.
>
ull is a preatty new platform so one board was listed. Are you sure
that we need?
Michael
> Thanks
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-06-02 14:04 ` Michael Nazzareno Trimarchi
0 siblings, 0 replies; 24+ messages in thread
From: Michael Nazzareno Trimarchi @ 2018-06-02 14:04 UTC (permalink / raw)
To: linux-arm-kernel
Hi
On Sat, Jun 2, 2018 at 3:48 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Stefan,
>
> On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren <stefan.wahren@i2se.com> wrote:
>
>>> --- a/include/dt-bindings/clock/imx6ul-clock.h
>>> +++ b/include/dt-bindings/clock/imx6ul-clock.h
>>> @@ -242,20 +242,25 @@
>>> #define IMX6UL_CLK_CKO2_PODF 229
>>> #define IMX6UL_CLK_CKO2 230
>>> #define IMX6UL_CLK_CKO 231
>>> +#define IMX6UL_CLK_GPIO1 232
>>> +#define IMX6UL_CLK_GPIO2 233
>>> +#define IMX6UL_CLK_GPIO3 234
>>> +#define IMX6UL_CLK_GPIO4 235
>>> +#define IMX6UL_CLK_GPIO5 236
>>
>> this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel.
>
> Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new
> clo01 and clo2 controlled
> by CCOSR") which did the same reordering.
>
ull is a preatty new platform so one board was listed. Are you sure
that we need?
Michael
> Thanks
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
2018-06-02 14:04 ` Michael Nazzareno Trimarchi
@ 2018-06-02 14:07 ` Fabio Estevam
-1 siblings, 0 replies; 24+ messages in thread
From: Fabio Estevam @ 2018-06-02 14:07 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Stefan Wahren, Rob Herring, Fabio Estevam, Mark Rutland,
Anson Huang, Matteo Lisi, Shawn Guo, Sascha Hauer,
Michael Turquette, Stephen Boyd, linux-clk, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Michael,
On Sat, Jun 2, 2018 at 11:04 AM, Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:
> ull is a preatty new platform so one board was listed. Are you sure
> that we need?
There are several imx6ul based dts in mainline and it is better if we
can avoid dtb breakage when possible.
In this case we can avoid the dtb breakage by adding the new clock
definitions at the end of the file, just like we do for all the other
imx devices.
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-06-02 14:07 ` Fabio Estevam
0 siblings, 0 replies; 24+ messages in thread
From: Fabio Estevam @ 2018-06-02 14:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi Michael,
On Sat, Jun 2, 2018 at 11:04 AM, Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:
> ull is a preatty new platform so one board was listed. Are you sure
> that we need?
There are several imx6ul based dts in mainline and it is better if we
can avoid dtb breakage when possible.
In this case we can avoid the dtb breakage by adding the new clock
definitions at the end of the file, just like we do for all the other
imx devices.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates
2018-06-02 14:07 ` Fabio Estevam
@ 2018-06-02 14:12 ` Michael Nazzareno Trimarchi
-1 siblings, 0 replies; 24+ messages in thread
From: Michael Nazzareno Trimarchi @ 2018-06-02 14:12 UTC (permalink / raw)
To: Fabio Estevam
Cc: Stefan Wahren, Rob Herring, Fabio Estevam, Mark Rutland,
Anson Huang, Matteo Lisi, Shawn Guo, Sascha Hauer,
Michael Turquette, Stephen Boyd, linux-clk, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Fabio
On Sat, Jun 2, 2018 at 4:07 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Michael,
>
> On Sat, Jun 2, 2018 at 11:04 AM, Michael Nazzareno Trimarchi
> <michael@amarulasolutions.com> wrote:
>
>> ull is a preatty new platform so one board was listed. Are you sure
>> that we need?
>
> There are several imx6ul based dts in mainline and it is better if we
> can avoid dtb breakage when possible.
>
> In this case we can avoid the dtb breakage by adding the new clock
> definitions at the end of the file, just like we do for all the other
> imx devices.
Yes, when I add new ul clock I move down ull (that is new), but agree
that this is not possible in general.
Michael
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
@ 2018-06-02 14:12 ` Michael Nazzareno Trimarchi
0 siblings, 0 replies; 24+ messages in thread
From: Michael Nazzareno Trimarchi @ 2018-06-02 14:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Fabio
On Sat, Jun 2, 2018 at 4:07 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Michael,
>
> On Sat, Jun 2, 2018 at 11:04 AM, Michael Nazzareno Trimarchi
> <michael@amarulasolutions.com> wrote:
>
>> ull is a preatty new platform so one board was listed. Are you sure
>> that we need?
>
> There are several imx6ul based dts in mainline and it is better if we
> can avoid dtb breakage when possible.
>
> In this case we can avoid the dtb breakage by adding the new clock
> definitions at the end of the file, just like we do for all the other
> imx devices.
Yes, when I add new ul clock I move down ull (that is new), but agree
that this is not possible in general.
Michael
^ permalink raw reply [flat|nested] 24+ messages in thread