[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

Hi all,

Here are some experimental patches to allow booting ARMv7 SMP
kernel on UP to some extent. Posting these early in case it is
of any help as I know at least Bryan Wu is working on similar
issues.

The patches are very much work in progress, and does not quite
boot to init yet so there's all kinds of things to fix. But at
least these patches allow booting to the point where the fixing
issues might be a bit easier.. Currently it boots to the point
where there are tons of "WARNING: at mm/percpu-vm.c:320 pcpu_alloc"
prints.

I've only tested these on omap3 UP systems so far so YMMV. The
patches are posted on top of v2.6.36-rc1 + omap-fixes branch.
Also available in devel-smp-on-unicore branch in the linux-omap
tree.

Cheers,

Tony

---

Tony Lindgren (4):
      ARM: Add SMP_ON_UP Kconfig option for booting SMP kernel on UP
      ARM: Allow optional UP processor functions for SMP kernels
      ARM: Set separate proc-v7 functions for SMP
      omap: Fix SMP on UP interrupt handling for multi-omap


 arch/arm/Kconfig                               |    7 ++
 arch/arm/include/asm/cacheflush.h              |    6 ++
 arch/arm/include/asm/proc-fns.h                |    8 ++
 arch/arm/include/asm/procinfo.h                |    6 ++
 arch/arm/include/asm/smp_plat.h                |    9 +++
 arch/arm/include/asm/tlbflush.h                |   16 ++++-
 arch/arm/kernel/setup.c                        |   45 ++++++++++++++
 arch/arm/mach-omap2/include/mach/entry-macro.S |   22 +++++++
 arch/arm/mach-omap2/omap-smp.c                 |   16 ++++-
 arch/arm/mach-omap2/timer-gp.c                 |    7 ++
 arch/arm/mm/cache-v7.S                         |   60 +++++++++++++++++++
 arch/arm/mm/mmu.c                              |   20 +++---
 arch/arm/mm/proc-v7.S                          |   77 ++++++++++++++++++++++--
 arch/arm/mm/tlb-v7.S                           |   51 ++++++++++++++++
 14 files changed, 325 insertions(+), 25 deletions(-)

-- 
Signature

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

Hi all,

Here are some experimental patches to allow booting ARMv7 SMP
kernel on UP to some extent. Posting these early in case it is
of any help as I know at least Bryan Wu is working on similar
issues.

The patches are very much work in progress, and does not quite
boot to init yet so there's all kinds of things to fix. But at
least these patches allow booting to the point where the fixing
issues might be a bit easier.. Currently it boots to the point
where there are tons of "WARNING: at mm/percpu-vm.c:320 pcpu_alloc"
prints.

I've only tested these on omap3 UP systems so far so YMMV. The
patches are posted on top of v2.6.36-rc1 + omap-fixes branch.
Also available in devel-smp-on-unicore branch in the linux-omap
tree.

Cheers,

Tony

---

Tony Lindgren (4):
      ARM: Add SMP_ON_UP Kconfig option for booting SMP kernel on UP
      ARM: Allow optional UP processor functions for SMP kernels
      ARM: Set separate proc-v7 functions for SMP
      omap: Fix SMP on UP interrupt handling for multi-omap


 arch/arm/Kconfig                               |    7 ++
 arch/arm/include/asm/cacheflush.h              |    6 ++
 arch/arm/include/asm/proc-fns.h                |    8 ++
 arch/arm/include/asm/procinfo.h                |    6 ++
 arch/arm/include/asm/smp_plat.h                |    9 +++
 arch/arm/include/asm/tlbflush.h                |   16 ++++-
 arch/arm/kernel/setup.c                        |   45 ++++++++++++++
 arch/arm/mach-omap2/include/mach/entry-macro.S |   22 +++++++
 arch/arm/mach-omap2/omap-smp.c                 |   16 ++++-
 arch/arm/mach-omap2/timer-gp.c                 |    7 ++
 arch/arm/mm/cache-v7.S                         |   60 +++++++++++++++++++
 arch/arm/mm/mmu.c                              |   20 +++---
 arch/arm/mm/proc-v7.S                          |   77 ++++++++++++++++++++++--
 arch/arm/mm/tlb-v7.S                           |   51 ++++++++++++++++
 14 files changed, 325 insertions(+), 25 deletions(-)

-- 
Signature

[PATCH 1/4] ARM: Add SMP_ON_UP Kconfig option for booting SMP kernel on UP

[Tony Lindgren]

Add Kconfig option to boot SMP kernel on uniprocessor systems,
and define MULTI_CPU, MULTI_TLB and MULTI_CACHE when SMP_ON_UP
option is set.

This will allow us to dynamically set the uniprocessor functions
during the boot in a way that should also work with ZBOOT_ROM.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/Kconfig                  |    7 +++++++
 arch/arm/include/asm/cacheflush.h |    6 ++++++
 arch/arm/include/asm/proc-fns.h   |    8 ++++++++
 arch/arm/include/asm/tlbflush.h   |    6 ++++++
 4 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9295110..1e9df6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,13 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP
+	default y
+	help
+          Allows booting SMP kernel on uniprocessor systems.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..e0ed5b4 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -26,6 +26,12 @@
 #undef _CACHE
 #undef MULTI_CACHE
 
+/* Force multiple cache support to boot SMP kernel on uniprocessor systems */
+#ifdef CONFIG_SMP_ON_UP
+# undef  MULTI_CACHE
+# define MULTI_CACHE 1
+#endif
+
 #if defined(CONFIG_CPU_CACHE_V3)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 8fdae9b..87a558b 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -20,6 +20,14 @@
 #undef MULTI_CPU
 #undef CPU_NAME
 
+/* Force multiple CPU support to boot SMP kernel on uniprocessor systems */
+#ifdef CONFIG_SMP_ON_UP
+# undef  MULTI_CPU
+# undef  CPU_NAME
+# define MULTI_CPU
+# define CPU_NAME
+#endif
+
 /*
  * CPU_NAME - the prefix for CPU related functions
  */
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..9b310bd 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,12 @@
 #undef _TLB
 #undef MULTI_TLB
 
+/* Force multiple TLB support to boot SMP kernel on uniprocessor systems */
+#ifdef CONFIG_SMP_ON_UP
+# undef  MULTI_TLB
+# define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3

[PATCH 1/4] ARM: Add SMP_ON_UP Kconfig option for booting SMP kernel on UP

[Tony Lindgren]

Add Kconfig option to boot SMP kernel on uniprocessor systems,
and define MULTI_CPU, MULTI_TLB and MULTI_CACHE when SMP_ON_UP
option is set.

This will allow us to dynamically set the uniprocessor functions
during the boot in a way that should also work with ZBOOT_ROM.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/Kconfig                  |    7 +++++++
 arch/arm/include/asm/cacheflush.h |    6 ++++++
 arch/arm/include/asm/proc-fns.h   |    8 ++++++++
 arch/arm/include/asm/tlbflush.h   |    6 ++++++
 4 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9295110..1e9df6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,13 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP
+	default y
+	help
+          Allows booting SMP kernel on uniprocessor systems.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..e0ed5b4 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -26,6 +26,12 @@
 #undef _CACHE
 #undef MULTI_CACHE
 
+/* Force multiple cache support to boot SMP kernel on uniprocessor systems */
+#ifdef CONFIG_SMP_ON_UP
+# undef  MULTI_CACHE
+# define MULTI_CACHE 1
+#endif
+
 #if defined(CONFIG_CPU_CACHE_V3)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 8fdae9b..87a558b 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -20,6 +20,14 @@
 #undef MULTI_CPU
 #undef CPU_NAME
 
+/* Force multiple CPU support to boot SMP kernel on uniprocessor systems */
+#ifdef CONFIG_SMP_ON_UP
+# undef  MULTI_CPU
+# undef  CPU_NAME
+# define MULTI_CPU
+# define CPU_NAME
+#endif
+
 /*
  * CPU_NAME - the prefix for CPU related functions
  */
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..9b310bd 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,12 @@
 #undef _TLB
 #undef MULTI_TLB
 
+/* Force multiple TLB support to boot SMP kernel on uniprocessor systems */
+#ifdef CONFIG_SMP_ON_UP
+# undef  MULTI_TLB
+# define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3

[PATCH 2/4] ARM: Allow optional UP processor functions for SMP kernels

[Tony Lindgren]

Attempt to detect if the hardware is UP hardware, and use the optional
UP specific processors functions in struct proc_info_list if available.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/procinfo.h |    6 +++++
 arch/arm/include/asm/smp_plat.h |    9 ++++++++
 arch/arm/kernel/setup.c         |   45 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mm/mmu.c               |   20 ++++++++++-------
 4 files changed, 71 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/procinfo.h b/arch/arm/include/asm/procinfo.h
index ca52e58..962d01e 100644
--- a/arch/arm/include/asm/procinfo.h
+++ b/arch/arm/include/asm/procinfo.h
@@ -40,6 +40,12 @@ struct proc_info_list {
 	struct cpu_tlb_fns	*tlb;
 	struct cpu_user_fns	*user;
 	struct cpu_cache_fns	*cache;
+
+#ifdef CONFIG_SMP_ON_UP
+	struct processor	*proc_up;
+	struct cpu_tlb_fns	*tlb_up;
+	struct cpu_cache_fns	*cache_up;
+#endif
 };
 
 #else	/* __KERNEL__ */
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..1c2f587 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -18,4 +18,13 @@ static inline int cache_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 
+#ifdef CONFIG_SMP_ON_UP
+extern int smp_on_up(void);
+#else
+static inline int smp_on_up(void)
+{
+	return 0;
+}
+#endif
+
 #endif
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d5231ae..5f3606c 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -289,6 +289,50 @@ static void __init feat_v6_fixup(void)
 		elf_hwcap &= ~HWCAP_TLS;
 }
 
+#ifdef CONFIG_SMP_ON_UP
+
+static int _smp_on_up;
+
+int smp_on_up(void)
+{
+	return _smp_on_up;
+}
+
+static void __init smp_on_up_fixup(struct proc_info_list *list)
+{
+	int id;
+
+	id = read_cpuid_id() & 0xff0f0000;
+	if ((id == 0x41070000) || (id == 0x410f0000)) {
+		int mpidr;
+
+		asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
+		mpidr >>= 30;
+
+		/* SMP hardware? */
+		if (!((mpidr == 0) || (mpidr == 3)))
+			return;
+	}
+
+	_smp_on_up = 1;
+
+	pr_info("CPU: SMP kernel on UP hardware\n");
+
+	if (list->proc_up)
+		processor = *list->proc_up;
+
+	if (list->tlb_up)
+		cpu_tlb = *list->tlb_up;
+
+	if (list->cache_up)
+		cpu_cache = *list->cache_up;
+}
+#else
+static inline void smp_on_up_fixup(struct proc_info_list *list)
+{
+}
+#endif
+
 static void __init setup_processor(void)
 {
 	struct proc_info_list *list;
@@ -331,6 +375,7 @@ static void __init setup_processor(void)
 	elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+	smp_on_up_fixup(list);
 	feat_v6_fixup();
 
 	cacheid_init();
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..f320901 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -430,15 +430,17 @@ static void __init build_mem_type_table(void)
 		/*
 		 * Mark memory with the "shared" attribute for SMP systems
 		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		if (!smp_on_up()) {
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 #endif
 	}
 

[PATCH 2/4] ARM: Allow optional UP processor functions for SMP kernels

[Tony Lindgren]

Attempt to detect if the hardware is UP hardware, and use the optional
UP specific processors functions in struct proc_info_list if available.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/procinfo.h |    6 +++++
 arch/arm/include/asm/smp_plat.h |    9 ++++++++
 arch/arm/kernel/setup.c         |   45 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mm/mmu.c               |   20 ++++++++++-------
 4 files changed, 71 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/procinfo.h b/arch/arm/include/asm/procinfo.h
index ca52e58..962d01e 100644
--- a/arch/arm/include/asm/procinfo.h
+++ b/arch/arm/include/asm/procinfo.h
@@ -40,6 +40,12 @@ struct proc_info_list {
 	struct cpu_tlb_fns	*tlb;
 	struct cpu_user_fns	*user;
 	struct cpu_cache_fns	*cache;
+
+#ifdef CONFIG_SMP_ON_UP
+	struct processor	*proc_up;
+	struct cpu_tlb_fns	*tlb_up;
+	struct cpu_cache_fns	*cache_up;
+#endif
 };
 
 #else	/* __KERNEL__ */
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..1c2f587 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -18,4 +18,13 @@ static inline int cache_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 
+#ifdef CONFIG_SMP_ON_UP
+extern int smp_on_up(void);
+#else
+static inline int smp_on_up(void)
+{
+	return 0;
+}
+#endif
+
 #endif
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d5231ae..5f3606c 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -289,6 +289,50 @@ static void __init feat_v6_fixup(void)
 		elf_hwcap &= ~HWCAP_TLS;
 }
 
+#ifdef CONFIG_SMP_ON_UP
+
+static int _smp_on_up;
+
+int smp_on_up(void)
+{
+	return _smp_on_up;
+}
+
+static void __init smp_on_up_fixup(struct proc_info_list *list)
+{
+	int id;
+
+	id = read_cpuid_id() & 0xff0f0000;
+	if ((id == 0x41070000) || (id == 0x410f0000)) {
+		int mpidr;
+
+		asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
+		mpidr >>= 30;
+
+		/* SMP hardware? */
+		if (!((mpidr == 0) || (mpidr == 3)))
+			return;
+	}
+
+	_smp_on_up = 1;
+
+	pr_info("CPU: SMP kernel on UP hardware\n");
+
+	if (list->proc_up)
+		processor = *list->proc_up;
+
+	if (list->tlb_up)
+		cpu_tlb = *list->tlb_up;
+
+	if (list->cache_up)
+		cpu_cache = *list->cache_up;
+}
+#else
+static inline void smp_on_up_fixup(struct proc_info_list *list)
+{
+}
+#endif
+
 static void __init setup_processor(void)
 {
 	struct proc_info_list *list;
@@ -331,6 +375,7 @@ static void __init setup_processor(void)
 	elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+	smp_on_up_fixup(list);
 	feat_v6_fixup();
 
 	cacheid_init();
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..f320901 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -430,15 +430,17 @@ static void __init build_mem_type_table(void)
 		/*
 		 * Mark memory with the "shared" attribute for SMP systems
 		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		if (!smp_on_up()) {
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 #endif
 	}
 

Re: [PATCH 2/4] ARM: Allow optional UP processor functions for SMP kernels

[Russell King - ARM Linux]

On Tue, Aug 17, 2010 at 01:53:25PM +0300, Tony Lindgren wrote:
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index e621530..1c2f587 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -18,4 +18,13 @@ static inline int cache_ops_need_broadcast(void)
>  	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
>  }
>  
> +#ifdef CONFIG_SMP_ON_UP
> +extern int smp_on_up(void);
> +#else
> +static inline int smp_on_up(void)
> +{
> +	return 0;
> +}
> +#endif
> +
>  #endif
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index d5231ae..5f3606c 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -289,6 +289,50 @@ static void __init feat_v6_fixup(void)
>  		elf_hwcap &= ~HWCAP_TLS;
>  }
>  
> +#ifdef CONFIG_SMP_ON_UP
> +
> +static int _smp_on_up;
> +
> +int smp_on_up(void)
> +{
> +	return _smp_on_up;
> +}

This kind of function to access one bit of data is really silly and
expensive.  If you want to do something like this to hide the data
itself, then instead do this in the header file:

static inline int smp_on_up(void)
{
#ifdef CONFIG_SMP_ON_UP
	extern int _smp_on_up;
	return _smp_on_up;
#else
	return 0;
#endif
}

rather than making the compiler unable to optimize this call by spilling
at least 5 registers each time.

> +	if (list->proc_up)
> +		processor = *list->proc_up;
> +
> +	if (list->tlb_up)
> +		cpu_tlb = *list->tlb_up;
> +
> +	if (list->cache_up)
> +		cpu_cache = *list->cache_up;

I don't think this is a good approach at all - most of the assembly
is identical and I'm sure there's a much better approach to fixing
these things up.

[PATCH 2/4] ARM: Allow optional UP processor functions for SMP kernels

[Russell King - ARM Linux]

On Tue, Aug 17, 2010 at 01:53:25PM +0300, Tony Lindgren wrote:
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index e621530..1c2f587 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -18,4 +18,13 @@ static inline int cache_ops_need_broadcast(void)
>  	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
>  }
>  
> +#ifdef CONFIG_SMP_ON_UP
> +extern int smp_on_up(void);
> +#else
> +static inline int smp_on_up(void)
> +{
> +	return 0;
> +}
> +#endif
> +
>  #endif
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index d5231ae..5f3606c 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -289,6 +289,50 @@ static void __init feat_v6_fixup(void)
>  		elf_hwcap &= ~HWCAP_TLS;
>  }
>  
> +#ifdef CONFIG_SMP_ON_UP
> +
> +static int _smp_on_up;
> +
> +int smp_on_up(void)
> +{
> +	return _smp_on_up;
> +}

This kind of function to access one bit of data is really silly and
expensive.  If you want to do something like this to hide the data
itself, then instead do this in the header file:

static inline int smp_on_up(void)
{
#ifdef CONFIG_SMP_ON_UP
	extern int _smp_on_up;
	return _smp_on_up;
#else
	return 0;
#endif
}

rather than making the compiler unable to optimize this call by spilling
at least 5 registers each time.

> +	if (list->proc_up)
> +		processor = *list->proc_up;
> +
> +	if (list->tlb_up)
> +		cpu_tlb = *list->tlb_up;
> +
> +	if (list->cache_up)
> +		cpu_cache = *list->cache_up;

I don't think this is a good approach at all - most of the assembly
is identical and I'm sure there's a much better approach to fixing
these things up.

Re: [PATCH 2/4] ARM: Allow optional UP processor functions for SMP kernels

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 14:01]:
> On Tue, Aug 17, 2010 at 01:53:25PM +0300, Tony Lindgren wrote:
> 
> > +	if (list->proc_up)
> > +		processor = *list->proc_up;
> > +
> > +	if (list->tlb_up)
> > +		cpu_tlb = *list->tlb_up;
> > +
> > +	if (list->cache_up)
> > +		cpu_cache = *list->cache_up;
> 
> I don't think this is a good approach at all - most of the assembly
> is identical and I'm sure there's a much better approach to fixing
> these things up.

We could simplify it if we tried to detect SMP kernel running
on UP hardware early on and then select the UP vs SMP code as
needed.

Regards,

Tony

[PATCH 2/4] ARM: Allow optional UP processor functions for SMP kernels

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 14:01]:
> On Tue, Aug 17, 2010 at 01:53:25PM +0300, Tony Lindgren wrote:
> 
> > +	if (list->proc_up)
> > +		processor = *list->proc_up;
> > +
> > +	if (list->tlb_up)
> > +		cpu_tlb = *list->tlb_up;
> > +
> > +	if (list->cache_up)
> > +		cpu_cache = *list->cache_up;
> 
> I don't think this is a good approach at all - most of the assembly
> is identical and I'm sure there's a much better approach to fixing
> these things up.

We could simplify it if we tried to detect SMP kernel running
on UP hardware early on and then select the UP vs SMP code as
needed.

Regards,

Tony

[PATCH 3/4] ARM: Set separate proc-v7 functions for SMP

[Tony Lindgren]

Set separate proc-v7 functions for SMP

NOTE: The v7wbi_tlb_flags need to be checked

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/tlbflush.h |   10 +++--
 arch/arm/mm/cache-v7.S          |   60 ++++++++++++++++++++++++++++++
 arch/arm/mm/proc-v7.S           |   77 ++++++++++++++++++++++++++++++++++++---
 arch/arm/mm/tlb-v7.S            |   51 ++++++++++++++++++++++++++
 4 files changed, 188 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 9b310bd..0b2087e 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -191,12 +191,14 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#else
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..acc889c 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -101,6 +101,19 @@ ENTRY(v7_flush_kern_cache_all)
 	mov	pc, lr
 ENDPROC(v7_flush_kern_cache_all)
 
+#ifdef CONFIG_SMP_ON_UP
+ENTRY(v7_flush_kern_cache_all_up)
+ ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
+ THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
+	bl	v7_flush_dcache_all
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
+ ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
+ THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
+	mov	pc, lr
+ENDPROC(v7_flush_kern_cache_all_up)
+#endif
+
 /*
  *	v7_flush_cache_all()
  *
@@ -193,6 +206,37 @@ ENTRY(v7_coherent_user_range)
 ENDPROC(v7_coherent_kern_range)
 ENDPROC(v7_coherent_user_range)
 
+#ifdef CONFIG_SMP_ON_UP
+ENTRY(v7_coherent_kern_range_up)
+ENTRY(v7_coherent_user_range_up)
+ UNWIND(.fnstart		)
+	dcache_line_size r2, r3
+	sub	r3, r2, #1
+	bic	r0, r0, r3
+1:
+ USER(	mcr	p15, 0, r0, c7, c11, 1	)	@ clean D line to the point of unification
+	dsb
+ USER(	mcr	p15, 0, r0, c7, c5, 1	)	@ invalidate I line
+	add	r0, r0, r2
+2:
+	cmp	r0, r1
+	blo	1b
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
+	dsb
+	isb
+	mov	pc, lr
+
+9001:
+	mov	r0, r0, lsr #12
+	mov	r0, r0, lsl #12
+	add	r0, r0, #4096
+	b	2b
+ UNWIND(.fnend		)
+ENDPROC(v7_coherent_kern_range_up)
+ENDPROC(v7_coherent_user_range_up)
+#endif
+
 /*
  *	v7_flush_kern_dcache_area(void *addr, size_t size)
  *
@@ -319,3 +363,19 @@ ENTRY(v7_cache_fns)
 	.long	v7_dma_unmap_area
 	.long	v7_dma_flush_range
 	.size	v7_cache_fns, . - v7_cache_fns
+
+#ifdef CONFIG_SMP_ON_UP
+	.type	v7_cache_fns_up, #object
+ENTRY(v7_cache_fns_up)
+	.long	v7_flush_kern_cache_all_up
+	.long	v7_flush_user_cache_all
+	.long	v7_flush_user_cache_range
+	.long	v7_coherent_kern_range_up
+	.long	v7_coherent_user_range_up
+	.long	v7_flush_kern_dcache_area
+	.long	v7_dma_map_area
+	.long	v7_dma_unmap_area
+	.long	v7_dma_flush_range
+	.size	v7_cache_fns_up, . - v7_cache_fns_up
+#endif
+
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..65981c3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
 #define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
 #define PMD_FLAGS	PMD_SECT_WB
-#else
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,11 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
+#ifdef CONFIG_SMP
+	orr	r0, r0, #TTB_FLAGS_SMP
+#else
 	orr	r0, r0, #TTB_FLAGS
+#endif
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -119,6 +121,31 @@ ENTRY(cpu_v7_switch_mm)
 	mov	pc, lr
 ENDPROC(cpu_v7_switch_mm)
 
+#ifdef CONFIG_SMP_ON_UP
+/*
+ *	cpu_v7_switch_mm_up(pgd_phys, tsk)
+ *
+ *	For booting SMP kerner on uniprocessor system
+ */
+ENTRY(cpu_v7_switch_mm_up)
+#ifdef CONFIG_MMU
+	mov	r2, #0
+	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
+	orr	r0, r0, #TTB_FLAGS
+#ifdef CONFIG_ARM_ERRATA_430973
+	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
+#endif
+	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
+	isb
+1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
+	isb
+	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
+	isb
+#endif
+	mov	pc, lr
+ENDPROC(cpu_v7_switch_mm_up)
+#endif
+
 /*
  *	cpu_v7_set_pte_ext(ptep, pte)
  *
@@ -188,10 +215,17 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
+	mrc	p15, 0, r0, c0, c0, 5		@ read MPIDR
+	mov	r0, r0, lsr #30			@ get processor format and U bit
+	cmp	r0, #0				@ old style MPIDR?
+	beq	1f				@ yes, cortex-A8, uniprocessor
+	cmp	r0, #3				@ new style MPIDR uniprocessor?
+	beq	1f				@ yes, not SMP
 	mrc	p15, 0, r0, c1, c0, 1
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
+1:
 #endif
 	adr	r12, __v7_setup_stack		@ the local stack
 	stmia	r12, {r0-r5, r7, r9, r11, lr}
@@ -235,7 +269,18 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
+#ifdef CONFIG_SMP
+	mrc	p15, 0, r10, c0, c0, 5		@ read MPIDR
+	mov	r10, r10, lsr #30		@ processor format and U bit
+	cmp	r10, #0				@ old style MPIDR?
+	orreq	r4, r4, #TTB_FLAGS		@ yes, cortex-A8, uniprocessor
+	cmpne	r10, #3				@ new style MPIDR uniprocessor?
+	orreq	r4, r4, #TTB_FLAGS		@ yes, uniprocessor mode
+	orrne	r4, r4, #TTB_FLAGS_SMP		@ in SMP mode
+	mov	r10, #0
+#else
 	orr	r4, r4, #TTB_FLAGS
+#endif
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -310,6 +355,21 @@ ENTRY(v7_processor_functions)
 	.word	cpu_v7_set_pte_ext
 	.size	v7_processor_functions, . - v7_processor_functions
 
+#ifdef CONFIG_SMP_ON_UP
+	.type	v7_processor_functions_up, #object
+ENTRY(v7_processor_functions_up)
+	.word	v7_early_abort
+	.word	v7_pabort
+	.word	cpu_v7_proc_init
+	.word	cpu_v7_proc_fin
+	.word	cpu_v7_reset
+	.word	cpu_v7_do_idle
+	.word	cpu_v7_dcache_clean_area
+	.word	cpu_v7_switch_mm_up
+	.word	cpu_v7_set_pte_ext
+	.size	v7_processor_functions_up, . - v7_processor_functions_up
+#endif
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv7"
@@ -333,7 +393,7 @@ __v7_proc_info:
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS		@ UP flags on SMP during initial setup
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -347,4 +407,9 @@ __v7_proc_info:
 	.long	v7wbi_tlb_fns
 	.long	v6_user_fns
 	.long	v7_cache_fns
+#ifdef CONFIG_SMP_ON_UP
+	.long	v7_processor_functions_up
+	.long	v7wbi_tlb_fns_up
+	.long	v7_cache_fns_up
+#endif
 	.size	__v7_proc_info, . - __v7_proc_info
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..9e40b03 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -59,6 +59,28 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
 
+#ifdef CONFIG_SMP_ON_UP
+ENTRY(v7wbi_flush_user_tlb_range_up)
+	vma_vm_mm r3, r2			@ get vma->vm_mm
+	mmid	r3, r3				@ get vm_mm->context.id
+	dsb
+	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
+	mov	r1, r1, lsr #PAGE_SHIFT
+	asid	r3, r3				@ mask ASID
+	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
+	mov	r1, r1, lsl #PAGE_SHIFT
+1:
+	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
+	add	r0, r0, #PAGE_SZ
+	cmp	r0, r1
+	blo	1b
+	mov	ip, #0
+	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
+	dsb
+	mov	pc, lr
+ENDPROC(v7wbi_flush_user_tlb_range_up)
+#endif
+
 /*
  *	v7wbi_flush_kern_tlb_range(start,end)
  *
@@ -93,6 +115,26 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	pc, lr
 ENDPROC(v7wbi_flush_kern_tlb_range)
 
+#ifdef CONFIG_SMP_ON_UP
+ENTRY(v7wbi_flush_kern_tlb_range_up)
+	dsb
+	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
+	mov	r1, r1, lsr #PAGE_SHIFT
+	mov	r0, r0, lsl #PAGE_SHIFT
+	mov	r1, r1, lsl #PAGE_SHIFT
+1:
+	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
+	add	r0, r0, #PAGE_SZ
+	cmp	r0, r1
+	blo	1b
+	mov	r2, #0
+	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
+	dsb
+	isb
+	mov	pc, lr
+ENDPROC(v7wbi_flush_kern_tlb_range_up)
+#endif
+
 	__INIT
 
 	.type	v7wbi_tlb_fns, #object
@@ -101,3 +143,12 @@ ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_kern_tlb_range
 	.long	v7wbi_tlb_flags
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
+
+#ifdef CONFIG_SMP_ON_UP
+	.type	v7wbi_tlb_fns_up, #object
+ENTRY(v7wbi_tlb_fns_up)
+	.long	v7wbi_flush_user_tlb_range_up
+	.long	v7wbi_flush_kern_tlb_range_up
+	.long	v7wbi_tlb_flags_up
+	.size	v7wbi_tlb_fns_up, . - v7wbi_tlb_fns_up
+#endif

[PATCH 3/4] ARM: Set separate proc-v7 functions for SMP

[Tony Lindgren]

Set separate proc-v7 functions for SMP

NOTE: The v7wbi_tlb_flags need to be checked

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/tlbflush.h |   10 +++--
 arch/arm/mm/cache-v7.S          |   60 ++++++++++++++++++++++++++++++
 arch/arm/mm/proc-v7.S           |   77 ++++++++++++++++++++++++++++++++++++---
 arch/arm/mm/tlb-v7.S            |   51 ++++++++++++++++++++++++++
 4 files changed, 188 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 9b310bd..0b2087e 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -191,12 +191,14 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#else
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..acc889c 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -101,6 +101,19 @@ ENTRY(v7_flush_kern_cache_all)
 	mov	pc, lr
 ENDPROC(v7_flush_kern_cache_all)
 
+#ifdef CONFIG_SMP_ON_UP
+ENTRY(v7_flush_kern_cache_all_up)
+ ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
+ THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
+	bl	v7_flush_dcache_all
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
+ ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
+ THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
+	mov	pc, lr
+ENDPROC(v7_flush_kern_cache_all_up)
+#endif
+
 /*
  *	v7_flush_cache_all()
  *
@@ -193,6 +206,37 @@ ENTRY(v7_coherent_user_range)
 ENDPROC(v7_coherent_kern_range)
 ENDPROC(v7_coherent_user_range)
 
+#ifdef CONFIG_SMP_ON_UP
+ENTRY(v7_coherent_kern_range_up)
+ENTRY(v7_coherent_user_range_up)
+ UNWIND(.fnstart		)
+	dcache_line_size r2, r3
+	sub	r3, r2, #1
+	bic	r0, r0, r3
+1:
+ USER(	mcr	p15, 0, r0, c7, c11, 1	)	@ clean D line to the point of unification
+	dsb
+ USER(	mcr	p15, 0, r0, c7, c5, 1	)	@ invalidate I line
+	add	r0, r0, r2
+2:
+	cmp	r0, r1
+	blo	1b
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
+	dsb
+	isb
+	mov	pc, lr
+
+9001:
+	mov	r0, r0, lsr #12
+	mov	r0, r0, lsl #12
+	add	r0, r0, #4096
+	b	2b
+ UNWIND(.fnend		)
+ENDPROC(v7_coherent_kern_range_up)
+ENDPROC(v7_coherent_user_range_up)
+#endif
+
 /*
  *	v7_flush_kern_dcache_area(void *addr, size_t size)
  *
@@ -319,3 +363,19 @@ ENTRY(v7_cache_fns)
 	.long	v7_dma_unmap_area
 	.long	v7_dma_flush_range
 	.size	v7_cache_fns, . - v7_cache_fns
+
+#ifdef CONFIG_SMP_ON_UP
+	.type	v7_cache_fns_up, #object
+ENTRY(v7_cache_fns_up)
+	.long	v7_flush_kern_cache_all_up
+	.long	v7_flush_user_cache_all
+	.long	v7_flush_user_cache_range
+	.long	v7_coherent_kern_range_up
+	.long	v7_coherent_user_range_up
+	.long	v7_flush_kern_dcache_area
+	.long	v7_dma_map_area
+	.long	v7_dma_unmap_area
+	.long	v7_dma_flush_range
+	.size	v7_cache_fns_up, . - v7_cache_fns_up
+#endif
+
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..65981c3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
 #define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
 #define PMD_FLAGS	PMD_SECT_WB
-#else
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,11 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
+#ifdef CONFIG_SMP
+	orr	r0, r0, #TTB_FLAGS_SMP
+#else
 	orr	r0, r0, #TTB_FLAGS
+#endif
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -119,6 +121,31 @@ ENTRY(cpu_v7_switch_mm)
 	mov	pc, lr
 ENDPROC(cpu_v7_switch_mm)
 
+#ifdef CONFIG_SMP_ON_UP
+/*
+ *	cpu_v7_switch_mm_up(pgd_phys, tsk)
+ *
+ *	For booting SMP kerner on uniprocessor system
+ */
+ENTRY(cpu_v7_switch_mm_up)
+#ifdef CONFIG_MMU
+	mov	r2, #0
+	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
+	orr	r0, r0, #TTB_FLAGS
+#ifdef CONFIG_ARM_ERRATA_430973
+	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
+#endif
+	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
+	isb
+1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
+	isb
+	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
+	isb
+#endif
+	mov	pc, lr
+ENDPROC(cpu_v7_switch_mm_up)
+#endif
+
 /*
  *	cpu_v7_set_pte_ext(ptep, pte)
  *
@@ -188,10 +215,17 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
+	mrc	p15, 0, r0, c0, c0, 5		@ read MPIDR
+	mov	r0, r0, lsr #30			@ get processor format and U bit
+	cmp	r0, #0				@ old style MPIDR?
+	beq	1f				@ yes, cortex-A8, uniprocessor
+	cmp	r0, #3				@ new style MPIDR uniprocessor?
+	beq	1f				@ yes, not SMP
 	mrc	p15, 0, r0, c1, c0, 1
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
+1:
 #endif
 	adr	r12, __v7_setup_stack		@ the local stack
 	stmia	r12, {r0-r5, r7, r9, r11, lr}
@@ -235,7 +269,18 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
+#ifdef CONFIG_SMP
+	mrc	p15, 0, r10, c0, c0, 5		@ read MPIDR
+	mov	r10, r10, lsr #30		@ processor format and U bit
+	cmp	r10, #0				@ old style MPIDR?
+	orreq	r4, r4, #TTB_FLAGS		@ yes, cortex-A8, uniprocessor
+	cmpne	r10, #3				@ new style MPIDR uniprocessor?
+	orreq	r4, r4, #TTB_FLAGS		@ yes, uniprocessor mode
+	orrne	r4, r4, #TTB_FLAGS_SMP		@ in SMP mode
+	mov	r10, #0
+#else
 	orr	r4, r4, #TTB_FLAGS
+#endif
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -310,6 +355,21 @@ ENTRY(v7_processor_functions)
 	.word	cpu_v7_set_pte_ext
 	.size	v7_processor_functions, . - v7_processor_functions
 
+#ifdef CONFIG_SMP_ON_UP
+	.type	v7_processor_functions_up, #object
+ENTRY(v7_processor_functions_up)
+	.word	v7_early_abort
+	.word	v7_pabort
+	.word	cpu_v7_proc_init
+	.word	cpu_v7_proc_fin
+	.word	cpu_v7_reset
+	.word	cpu_v7_do_idle
+	.word	cpu_v7_dcache_clean_area
+	.word	cpu_v7_switch_mm_up
+	.word	cpu_v7_set_pte_ext
+	.size	v7_processor_functions_up, . - v7_processor_functions_up
+#endif
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv7"
@@ -333,7 +393,7 @@ __v7_proc_info:
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS		@ UP flags on SMP during initial setup
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -347,4 +407,9 @@ __v7_proc_info:
 	.long	v7wbi_tlb_fns
 	.long	v6_user_fns
 	.long	v7_cache_fns
+#ifdef CONFIG_SMP_ON_UP
+	.long	v7_processor_functions_up
+	.long	v7wbi_tlb_fns_up
+	.long	v7_cache_fns_up
+#endif
 	.size	__v7_proc_info, . - __v7_proc_info
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..9e40b03 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -59,6 +59,28 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
 
+#ifdef CONFIG_SMP_ON_UP
+ENTRY(v7wbi_flush_user_tlb_range_up)
+	vma_vm_mm r3, r2			@ get vma->vm_mm
+	mmid	r3, r3				@ get vm_mm->context.id
+	dsb
+	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
+	mov	r1, r1, lsr #PAGE_SHIFT
+	asid	r3, r3				@ mask ASID
+	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
+	mov	r1, r1, lsl #PAGE_SHIFT
+1:
+	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
+	add	r0, r0, #PAGE_SZ
+	cmp	r0, r1
+	blo	1b
+	mov	ip, #0
+	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
+	dsb
+	mov	pc, lr
+ENDPROC(v7wbi_flush_user_tlb_range_up)
+#endif
+
 /*
  *	v7wbi_flush_kern_tlb_range(start,end)
  *
@@ -93,6 +115,26 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	pc, lr
 ENDPROC(v7wbi_flush_kern_tlb_range)
 
+#ifdef CONFIG_SMP_ON_UP
+ENTRY(v7wbi_flush_kern_tlb_range_up)
+	dsb
+	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
+	mov	r1, r1, lsr #PAGE_SHIFT
+	mov	r0, r0, lsl #PAGE_SHIFT
+	mov	r1, r1, lsl #PAGE_SHIFT
+1:
+	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
+	add	r0, r0, #PAGE_SZ
+	cmp	r0, r1
+	blo	1b
+	mov	r2, #0
+	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
+	dsb
+	isb
+	mov	pc, lr
+ENDPROC(v7wbi_flush_kern_tlb_range_up)
+#endif
+
 	__INIT
 
 	.type	v7wbi_tlb_fns, #object
@@ -101,3 +143,12 @@ ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_kern_tlb_range
 	.long	v7wbi_tlb_flags
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
+
+#ifdef CONFIG_SMP_ON_UP
+	.type	v7wbi_tlb_fns_up, #object
+ENTRY(v7wbi_tlb_fns_up)
+	.long	v7wbi_flush_user_tlb_range_up
+	.long	v7wbi_flush_kern_tlb_range_up
+	.long	v7wbi_tlb_flags_up
+	.size	v7wbi_tlb_fns_up, . - v7wbi_tlb_fns_up
+#endif

[PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

Fix SMP on UP interrupt handling for multi-omap

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
 arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
 arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
 3 files changed, 39 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1..75c67aa 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -189,17 +189,38 @@ omap_irq_base:	.word	0
 		 */
 
 		.macro test_for_ipi, irqnr, irqstat, base, tmp
+
+#ifdef MULTI_OMAP2
+		ldr	\tmp, =OMAP4_IRQ_BASE
+		cmp	\base, \tmp
+		beq	9993f
+		cmpne	\tmp, \tmp
+		beq	9994f
+9993:
+#endif
+
 		bic	\irqnr, \irqstat, #0x1c00
 		cmp	\irqnr, #16
 		it	cc
 		strcc	\irqstat, [\base, #GIC_CPU_EOI]
 		it	cs
 		cmpcs	\irqnr, \irqnr
+9994:
 		.endm
 
 		/* As above, this assumes that irqstat and base are preserved */
 
 		.macro test_for_ltirq, irqnr, irqstat, base, tmp
+
+#ifdef MULTI_OMAP2
+		ldr	\tmp, =OMAP4_IRQ_BASE
+		cmp	\base, \tmp
+		beq	9995f
+		cmpne	\tmp, \tmp
+		beq	9996f
+9995:
+#endif
+
 		bic	\irqnr, \irqstat, #0x1c00
 		mov 	\tmp, #0
 		cmp	\irqnr, #29
@@ -207,6 +228,7 @@ omap_irq_base:	.word	0
 		moveq	\tmp, #1
 		streq	\irqstat, [\base, #GIC_CPU_EOI]
 		cmp	\tmp, #0
+9996:
 		.endm
 #endif	/* CONFIG_SMP */
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9e9f70e..8ea16de 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -22,6 +22,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/localtimer.h>
+#include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
 {
 	unsigned int i, ncores;
 
-	/* Never released */
-	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
-	BUG_ON(!scu_base);
+	if (smp_on_up()) {
+		ncores = 1;
+	} else {
+		/* Never released */
+		scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
+		BUG_ON(!scu_base);
 
-	ncores = get_core_count();
+		ncores = get_core_count();
+	}
 
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
@@ -146,6 +151,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 	}
 	smp_store_cpu_info(cpu);
 
+	if (smp_on_up())
+		ncores = 1;
+
 	/*
 	 * are we trying to boot more cores than exist?
 	 */
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8..badf5f2 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -37,6 +37,7 @@
 #include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
+#include <asm/smp_plat.h>
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 
@@ -228,8 +229,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-	BUG_ON(!twd_base);
+	if (smp_on_up()) {
+		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+		BUG_ON(!twd_base);
+	}
 #endif
 	omap_dm_timer_init();
 

[PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

Fix SMP on UP interrupt handling for multi-omap

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
 arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
 arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
 3 files changed, 39 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1..75c67aa 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -189,17 +189,38 @@ omap_irq_base:	.word	0
 		 */
 
 		.macro test_for_ipi, irqnr, irqstat, base, tmp
+
+#ifdef MULTI_OMAP2
+		ldr	\tmp, =OMAP4_IRQ_BASE
+		cmp	\base, \tmp
+		beq	9993f
+		cmpne	\tmp, \tmp
+		beq	9994f
+9993:
+#endif
+
 		bic	\irqnr, \irqstat, #0x1c00
 		cmp	\irqnr, #16
 		it	cc
 		strcc	\irqstat, [\base, #GIC_CPU_EOI]
 		it	cs
 		cmpcs	\irqnr, \irqnr
+9994:
 		.endm
 
 		/* As above, this assumes that irqstat and base are preserved */
 
 		.macro test_for_ltirq, irqnr, irqstat, base, tmp
+
+#ifdef MULTI_OMAP2
+		ldr	\tmp, =OMAP4_IRQ_BASE
+		cmp	\base, \tmp
+		beq	9995f
+		cmpne	\tmp, \tmp
+		beq	9996f
+9995:
+#endif
+
 		bic	\irqnr, \irqstat, #0x1c00
 		mov 	\tmp, #0
 		cmp	\irqnr, #29
@@ -207,6 +228,7 @@ omap_irq_base:	.word	0
 		moveq	\tmp, #1
 		streq	\irqstat, [\base, #GIC_CPU_EOI]
 		cmp	\tmp, #0
+9996:
 		.endm
 #endif	/* CONFIG_SMP */
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9e9f70e..8ea16de 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -22,6 +22,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/localtimer.h>
+#include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
 {
 	unsigned int i, ncores;
 
-	/* Never released */
-	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
-	BUG_ON(!scu_base);
+	if (smp_on_up()) {
+		ncores = 1;
+	} else {
+		/* Never released */
+		scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
+		BUG_ON(!scu_base);
 
-	ncores = get_core_count();
+		ncores = get_core_count();
+	}
 
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
@@ -146,6 +151,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 	}
 	smp_store_cpu_info(cpu);
 
+	if (smp_on_up())
+		ncores = 1;
+
 	/*
 	 * are we trying to boot more cores than exist?
 	 */
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8..badf5f2 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -37,6 +37,7 @@
 #include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
+#include <asm/smp_plat.h>
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 
@@ -228,8 +229,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-	BUG_ON(!twd_base);
+	if (smp_on_up()) {
+		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+		BUG_ON(!twd_base);
+	}
 #endif
 	omap_dm_timer_init();
 

Re: [PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[srinidhi]

On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> Fix SMP on UP interrupt handling for multi-omap
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
>  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
>  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
>  3 files changed, 39 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> index 06e64e1..75c67aa 100644
> --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S

There is one patch lying in Russell's tracker (6284/1) which attempts to
use the common IRQ helper macros instead of platforms duplicating this
file. Perhaps you may need to re-base to that if Russell is ok with that
patch, of course.

srinidhi

[PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[srinidhi]

On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> Fix SMP on UP interrupt handling for multi-omap
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
>  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
>  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
>  3 files changed, 39 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> index 06e64e1..75c67aa 100644
> --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S

There is one patch lying in Russell's tracker (6284/1) which attempts to
use the common IRQ helper macros instead of platforms duplicating this
file. Perhaps you may need to re-base to that if Russell is ok with that
patch, of course.

srinidhi

Re: [PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > Fix SMP on UP interrupt handling for multi-omap
> > 
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > ---
> >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
> >  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
> >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> >  3 files changed, 39 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > index 06e64e1..75c67aa 100644
> > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> 
> There is one patch lying in Russell's tracker (6284/1) which attempts to
> use the common IRQ helper macros instead of platforms duplicating this
> file. Perhaps you may need to re-base to that if Russell is ok with that
> patch, of course.

Nice to see. Ideally test_for_ipi and test_for_ltirq would return
early automatically when running SMP kernel on UP.

BTW, did you test patch 6284/1 with omap3_defconfig to make sure
that still boots on omap3 & 4?

Regards,

Tony

[PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > Fix SMP on UP interrupt handling for multi-omap
> > 
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > ---
> >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
> >  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
> >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> >  3 files changed, 39 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > index 06e64e1..75c67aa 100644
> > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> 
> There is one patch lying in Russell's tracker (6284/1) which attempts to
> use the common IRQ helper macros instead of platforms duplicating this
> file. Perhaps you may need to re-base to that if Russell is ok with that
> patch, of course.

Nice to see. Ideally test_for_ipi and test_for_ltirq would return
early automatically when running SMP kernel on UP.

BTW, did you test patch 6284/1 with omap3_defconfig to make sure
that still boots on omap3 & 4?

Regards,

Tony

Re: [PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[srinidhi]

On Tue, 2010-08-17 at 13:30 +0200, Tony Lindgren wrote:
> * srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> > On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > > Fix SMP on UP interrupt handling for multi-omap
> > > 
> > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > ---
> > >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
> > >  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
> > >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> > >  3 files changed, 39 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > index 06e64e1..75c67aa 100644
> > > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > 
> > There is one patch lying in Russell's tracker (6284/1) which attempts to
> > use the common IRQ helper macros instead of platforms duplicating this
> > file. Perhaps you may need to re-base to that if Russell is ok with that
> > patch, of course.
> 
> Nice to see. Ideally test_for_ipi and test_for_ltirq would return
> early automatically when running SMP kernel on UP.
> 
> BTW, did you test patch 6284/1 with omap3_defconfig to make sure
> that still boots on omap3 & 4?

Just build tested for all other machines and boot tested on ux500
machine. I do not have omap and other boards :(

Srinidhi

[PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[srinidhi]

On Tue, 2010-08-17 at 13:30 +0200, Tony Lindgren wrote:
> * srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> > On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > > Fix SMP on UP interrupt handling for multi-omap
> > > 
> > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > ---
> > >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
> > >  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
> > >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> > >  3 files changed, 39 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > index 06e64e1..75c67aa 100644
> > > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > 
> > There is one patch lying in Russell's tracker (6284/1) which attempts to
> > use the common IRQ helper macros instead of platforms duplicating this
> > file. Perhaps you may need to re-base to that if Russell is ok with that
> > patch, of course.
> 
> Nice to see. Ideally test_for_ipi and test_for_ltirq would return
> early automatically when running SMP kernel on UP.
> 
> BTW, did you test patch 6284/1 with omap3_defconfig to make sure
> that still boots on omap3 & 4?

Just build tested for all other machines and boot tested on ux500
machine. I do not have omap and other boards :(

Srinidhi

Re: [PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* srinidhi <srinidhi.kasagar@stericsson.com> [100817 15:07]:
> On Tue, 2010-08-17 at 13:30 +0200, Tony Lindgren wrote:
> > * srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> > > On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > > > Fix SMP on UP interrupt handling for multi-omap
> > > > 
> > > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > > ---
> > > >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
> > > >  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
> > > >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> > > >  3 files changed, 39 insertions(+), 6 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > > index 06e64e1..75c67aa 100644
> > > > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > 
> > > There is one patch lying in Russell's tracker (6284/1) which attempts to
> > > use the common IRQ helper macros instead of platforms duplicating this
> > > file. Perhaps you may need to re-base to that if Russell is ok with that
> > > patch, of course.
> > 
> > Nice to see. Ideally test_for_ipi and test_for_ltirq would return
> > early automatically when running SMP kernel on UP.
> > 
> > BTW, did you test patch 6284/1 with omap3_defconfig to make sure
> > that still boots on omap3 & 4?
> 
> Just build tested for all other machines and boot tested on ux500
> machine. I do not have omap and other boards :(

OK, I'll give your patch a try on some omap3 board, maybe Santosh
can test it on omap4.

Regards,

Tony

[PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* srinidhi <srinidhi.kasagar@stericsson.com> [100817 15:07]:
> On Tue, 2010-08-17 at 13:30 +0200, Tony Lindgren wrote:
> > * srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> > > On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > > > Fix SMP on UP interrupt handling for multi-omap
> > > > 
> > > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > > ---
> > > >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
> > > >  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
> > > >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> > > >  3 files changed, 39 insertions(+), 6 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > > index 06e64e1..75c67aa 100644
> > > > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > 
> > > There is one patch lying in Russell's tracker (6284/1) which attempts to
> > > use the common IRQ helper macros instead of platforms duplicating this
> > > file. Perhaps you may need to re-base to that if Russell is ok with that
> > > patch, of course.
> > 
> > Nice to see. Ideally test_for_ipi and test_for_ltirq would return
> > early automatically when running SMP kernel on UP.
> > 
> > BTW, did you test patch 6284/1 with omap3_defconfig to make sure
> > that still boots on omap3 & 4?
> 
> Just build tested for all other machines and boot tested on ux500
> machine. I do not have omap and other boards :(

OK, I'll give your patch a try on some omap3 board, maybe Santosh
can test it on omap4.

Regards,

Tony

RE: [PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Tuesday, August 17, 2010 7:44 PM
> To: srinidhi
> Cc: linux-arm-kernel@lists.infradead.org; linux-omap@vger.kernel.org;
> bryan.wu@canonical.com; Shilimkar, Santosh
> Subject: Re: [PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-
> omap
> 
> * srinidhi <srinidhi.kasagar@stericsson.com> [100817 15:07]:
> > On Tue, 2010-08-17 at 13:30 +0200, Tony Lindgren wrote:
> > > * srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> > > > On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > > > > Fix SMP on UP interrupt handling for multi-omap
> > > > >
> > > > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > > > ---
> > > > >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22
> ++++++++++++++++++++++
> > > > >  arch/arm/mach-omap2/omap-smp.c                 |   16
> ++++++++++++----
> > > > >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> > > > >  3 files changed, 39 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S
> b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > > > index 06e64e1..75c67aa 100644
> > > > > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > > > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > >
> > > > There is one patch lying in Russell's tracker (6284/1) which
> attempts to
> > > > use the common IRQ helper macros instead of platforms duplicating
> this
> > > > file. Perhaps you may need to re-base to that if Russell is ok with
> that
> > > > patch, of course.
> > >
> > > Nice to see. Ideally test_for_ipi and test_for_ltirq would return
> > > early automatically when running SMP kernel on UP.
> > >
> > > BTW, did you test patch 6284/1 with omap3_defconfig to make sure
> > > that still boots on omap3 & 4?
> >
> > Just build tested for all other machines and boot tested on ux500
> > machine. I do not have omap and other boards :(
> 
> OK, I'll give your patch a try on some omap3 board, maybe Santosh
> can test it on omap4.
> 
I tested patch 6284/1 on OMAP4 and OMAP3 SDPs with multi-omap and
normal build. Both boots well

Regards,
Santosh

[PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Tuesday, August 17, 2010 7:44 PM
> To: srinidhi
> Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org;
> bryan.wu at canonical.com; Shilimkar, Santosh
> Subject: Re: [PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-
> omap
> 
> * srinidhi <srinidhi.kasagar@stericsson.com> [100817 15:07]:
> > On Tue, 2010-08-17 at 13:30 +0200, Tony Lindgren wrote:
> > > * srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> > > > On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > > > > Fix SMP on UP interrupt handling for multi-omap
> > > > >
> > > > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > > > ---
> > > > >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22
> ++++++++++++++++++++++
> > > > >  arch/arm/mach-omap2/omap-smp.c                 |   16
> ++++++++++++----
> > > > >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> > > > >  3 files changed, 39 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S
> b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > > > index 06e64e1..75c67aa 100644
> > > > > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > > > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > >
> > > > There is one patch lying in Russell's tracker (6284/1) which
> attempts to
> > > > use the common IRQ helper macros instead of platforms duplicating
> this
> > > > file. Perhaps you may need to re-base to that if Russell is ok with
> that
> > > > patch, of course.
> > >
> > > Nice to see. Ideally test_for_ipi and test_for_ltirq would return
> > > early automatically when running SMP kernel on UP.
> > >
> > > BTW, did you test patch 6284/1 with omap3_defconfig to make sure
> > > that still boots on omap3 & 4?
> >
> > Just build tested for all other machines and boot tested on ux500
> > machine. I do not have omap and other boards :(
> 
> OK, I'll give your patch a try on some omap3 board, maybe Santosh
> can test it on omap4.
> 
I tested patch 6284/1 on OMAP4 and OMAP3 SDPs with multi-omap and
normal build. Both boots well

Regards,
Santosh

Re: [PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100817 04:23]:
> * srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> > On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > > Fix SMP on UP interrupt handling for multi-omap
> > > 
> > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > ---
> > >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
> > >  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
> > >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> > >  3 files changed, 39 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > index 06e64e1..75c67aa 100644
> > > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > 
> > There is one patch lying in Russell's tracker (6284/1) which attempts to
> > use the common IRQ helper macros instead of platforms duplicating this
> > file. Perhaps you may need to re-base to that if Russell is ok with that
> > patch, of course.
> 
> Nice to see. Ideally test_for_ipi and test_for_ltirq would return
> early automatically when running SMP kernel on UP.

For the record, posted a patch to return early, so no more hacks
needed for the entry-macro.S.

Regards,

Tony

[PATCH 4/4] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100817 04:23]:
> * srinidhi <srinidhi.kasagar@stericsson.com> [100817 14:00]:
> > On Tue, 2010-08-17 at 12:53 +0200, Tony Lindgren wrote:
> > > Fix SMP on UP interrupt handling for multi-omap
> > > 
> > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > ---
> > >  arch/arm/mach-omap2/include/mach/entry-macro.S |   22 ++++++++++++++++++++++
> > >  arch/arm/mach-omap2/omap-smp.c                 |   16 ++++++++++++----
> > >  arch/arm/mach-omap2/timer-gp.c                 |    7 +++++--
> > >  3 files changed, 39 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > index 06e64e1..75c67aa 100644
> > > --- a/arch/arm/mach-omap2/include/mach/entry-macro.S
> > > +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
> > 
> > There is one patch lying in Russell's tracker (6284/1) which attempts to
> > use the common IRQ helper macros instead of platforms duplicating this
> > file. Perhaps you may need to re-base to that if Russell is ok with that
> > patch, of course.
> 
> Nice to see. Ideally test_for_ipi and test_for_ltirq would return
> early automatically when running SMP kernel on UP.

For the record, posted a patch to return early, so no more hacks
needed for the entry-macro.S.

Regards,

Tony

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Tue, Aug 17, 2010 at 01:53:12PM +0300, Tony Lindgren wrote:
> Here are some experimental patches to allow booting ARMv7 SMP
> kernel on UP to some extent. Posting these early in case it is
> of any help as I know at least Bryan Wu is working on similar
> issues.

I think these are compeltely the wrong direction.  First thing to realise
is that XIP in the "SMP and UP in one kernel" is not really practical -
I'm not sure that many people who want that kind of flexibility also want
XIP too.

So let's forget about the kernel text being read-only.

The second thing to realise is that most of the SMP dependencies are in
assembly - and we can make lists of instructions and their modified
versions that would be necessary to boot a SMP kernel on UP.

So something like this will do (though note that not everywhere has been
fixed up - such as the page table flags - or this patch tested yet.)

If we don't want the SMP-on-UP support for SMP kernels (it's not actually
all that big - around 512 bytes) then we can discard the .smpalt.init
section and the __fixup_smp code.

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/smp_midr.h b/arch/arm/include/asm/smp_midr.h
index e69de29..4538ba4 100644
--- a/arch/arm/include/asm/smp_midr.h
+++ b/arch/arm/include/asm/smp_midr.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_SMP_MIDR_H
+#define ASMARM_SMP_MIDR_H
+
+#define hard_smp_processor_id()						\
+	({								\
+		unsigned int cpunum;					\
+		__asm__("\n"						\
+			"1:	mrc p15, 0, %0, c0, c0, 5\n"		\
+			"	.pushsection \".smpalt.init\", \"a\"\n"	\
+			"	.word	1b\n"				\
+			"	mov	%0, #0\n"			\
+			"	.popsection"				\
+			: "=r" (cpunum));				\
+		cpunum &= 0x0F;						\
+	})
+
+#endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..0644860 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -185,12 +185,15 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#else
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..feabbf0 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	moveq	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r1, r2, r3}
+	sub	r1, r0, r1
+	add	r2, r2, r1
+	add	r3, r3, r1
+2:	cmp	r2, r3
+	ldmia	r2!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r1]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..89858be 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,9 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
 
 		INIT_SETUP(16)
 
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..692d22e 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -169,7 +167,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +224,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +254,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..c04f9c1 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -235,7 +234,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +330,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 6a3ff65..ed96907 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /*
  * set_event() is used to wake up secondary core from wfe using sev. ROM
@@ -40,15 +41,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Tue, Aug 17, 2010 at 01:53:12PM +0300, Tony Lindgren wrote:
> Here are some experimental patches to allow booting ARMv7 SMP
> kernel on UP to some extent. Posting these early in case it is
> of any help as I know at least Bryan Wu is working on similar
> issues.

I think these are compeltely the wrong direction.  First thing to realise
is that XIP in the "SMP and UP in one kernel" is not really practical -
I'm not sure that many people who want that kind of flexibility also want
XIP too.

So let's forget about the kernel text being read-only.

The second thing to realise is that most of the SMP dependencies are in
assembly - and we can make lists of instructions and their modified
versions that would be necessary to boot a SMP kernel on UP.

So something like this will do (though note that not everywhere has been
fixed up - such as the page table flags - or this patch tested yet.)

If we don't want the SMP-on-UP support for SMP kernels (it's not actually
all that big - around 512 bytes) then we can discard the .smpalt.init
section and the __fixup_smp code.

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/smp_midr.h b/arch/arm/include/asm/smp_midr.h
index e69de29..4538ba4 100644
--- a/arch/arm/include/asm/smp_midr.h
+++ b/arch/arm/include/asm/smp_midr.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_SMP_MIDR_H
+#define ASMARM_SMP_MIDR_H
+
+#define hard_smp_processor_id()						\
+	({								\
+		unsigned int cpunum;					\
+		__asm__("\n"						\
+			"1:	mrc p15, 0, %0, c0, c0, 5\n"		\
+			"	.pushsection \".smpalt.init\", \"a\"\n"	\
+			"	.word	1b\n"				\
+			"	mov	%0, #0\n"			\
+			"	.popsection"				\
+			: "=r" (cpunum));				\
+		cpunum &= 0x0F;						\
+	})
+
+#endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..0644860 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -185,12 +185,15 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#else
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..feabbf0 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	moveq	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r1, r2, r3}
+	sub	r1, r0, r1
+	add	r2, r2, r1
+	add	r3, r3, r1
+2:	cmp	r2, r3
+	ldmia	r2!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r1]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..89858be 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,9 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
 
 		INIT_SETUP(16)
 
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..692d22e 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -169,7 +167,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +224,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +254,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..c04f9c1 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -235,7 +234,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +330,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 6a3ff65..ed96907 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /*
  * set_event() is used to wake up secondary core from wfe using sev. ROM
@@ -40,15 +41,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 16:44]:
> On Tue, Aug 17, 2010 at 01:53:12PM +0300, Tony Lindgren wrote:
> > Here are some experimental patches to allow booting ARMv7 SMP
> > kernel on UP to some extent. Posting these early in case it is
> > of any help as I know at least Bryan Wu is working on similar
> > issues.
> 
> I think these are compeltely the wrong direction.  First thing to realise
> is that XIP in the "SMP and UP in one kernel" is not really practical -
> I'm not sure that many people who want that kind of flexibility also want
> XIP too.
> 
> So let's forget about the kernel text being read-only.

OK, at least for me.
 
> The second thing to realise is that most of the SMP dependencies are in
> assembly - and we can make lists of instructions and their modified
> versions that would be necessary to boot a SMP kernel on UP.

OK cool.
 
> So something like this will do (though note that not everywhere has been
> fixed up - such as the page table flags - or this patch tested yet.)

Great, will give it a try hopefully tomorrow. Sounds like that's the way
to deal with fixing up things when booting up older UP ARMv6 without the
32v6 support :)
 
> If we don't want the SMP-on-UP support for SMP kernels (it's not actually
> all that big - around 512 bytes) then we can discard the .smpalt.init
> section and the __fixup_smp code.

OK

Regards,

Tony

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 16:44]:
> On Tue, Aug 17, 2010 at 01:53:12PM +0300, Tony Lindgren wrote:
> > Here are some experimental patches to allow booting ARMv7 SMP
> > kernel on UP to some extent. Posting these early in case it is
> > of any help as I know at least Bryan Wu is working on similar
> > issues.
> 
> I think these are compeltely the wrong direction.  First thing to realise
> is that XIP in the "SMP and UP in one kernel" is not really practical -
> I'm not sure that many people who want that kind of flexibility also want
> XIP too.
> 
> So let's forget about the kernel text being read-only.

OK, at least for me.
 
> The second thing to realise is that most of the SMP dependencies are in
> assembly - and we can make lists of instructions and their modified
> versions that would be necessary to boot a SMP kernel on UP.

OK cool.
 
> So something like this will do (though note that not everywhere has been
> fixed up - such as the page table flags - or this patch tested yet.)

Great, will give it a try hopefully tomorrow. Sounds like that's the way
to deal with fixing up things when booting up older UP ARMv6 without the
32v6 support :)
 
> If we don't want the SMP-on-UP support for SMP kernels (it's not actually
> all that big - around 512 bytes) then we can discard the .smpalt.init
> section and the __fixup_smp code.

OK

Regards,

Tony

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> Great, will give it a try hopefully tomorrow. Sounds like that's the way
> to deal with fixing up things when booting up older UP ARMv6 without the
> 32v6 support :)

What I've also been debating about is adding another word to the
smpalt structure, that being a set of flags which denote the situation
where the alternative should be used.

That means we can use it to do individual word replacements for SMP vs
UP, ARMv6 vs ARMv6k etc.

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> Great, will give it a try hopefully tomorrow. Sounds like that's the way
> to deal with fixing up things when booting up older UP ARMv6 without the
> 32v6 support :)

What I've also been debating about is adding another word to the
smpalt structure, that being a set of flags which denote the situation
where the alternative should be used.

That means we can use it to do individual word replacements for SMP vs
UP, ARMv6 vs ARMv6k etc.

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 922 bytes --]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> > Great, will give it a try hopefully tomorrow. Sounds like that's the way
> > to deal with fixing up things when booting up older UP ARMv6 without the
> > 32v6 support :)
> 
> What I've also been debating about is adding another word to the
> smpalt structure, that being a set of flags which denote the situation
> where the alternative should be used.
> 
> That means we can use it to do individual word replacements for SMP vs
> UP, ARMv6 vs ARMv6k etc.

Sounds good to me. Maybe it should then be called cpualt instead of smpalt?

Tried booting your patch and needed the following fix for Cortex-A8 UP.

Now it boots to the following error:

Machine configuration botched (nr -1073741824), unable to continue.

Does some struct size need to be changed or something?

Regards,

Tony

[-- Attachment #2: smp-on-up-fix.patch --]
[-- Type: text/x-diff, Size: 667 bytes --]

From: Tony Lindgren <tony@atomide.com>
Date: Thu, 19 Aug 2010 10:22:23 +0300
Subject: [PATCH] Fix smp_on_up detection

This is needed to detect UP properly on older ARMv7 like Cortex-A8.

Signed-off-by: Tony Lindgren <tony@atomide.com>

--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -346,8 +346,10 @@ __fixup_smp:
 	bne	smp_on_up		@ no, assume UP
 	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
 	movs	r0, r0, lsr #30
-	teqne	r0, #3			@ check top two bits 00 or 11
-	moveq	pc, lr
+	teq	r0, #0			@ check two top bits 00
+	beq	smp_on_up		@ yes, assume UP
+	teq	r0, #3			@ check top two bits 11
+	movne	pc, lr			@ no, running on SMP hw
 
 smp_on_up:
 	adr	r0, 1f

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> > Great, will give it a try hopefully tomorrow. Sounds like that's the way
> > to deal with fixing up things when booting up older UP ARMv6 without the
> > 32v6 support :)
> 
> What I've also been debating about is adding another word to the
> smpalt structure, that being a set of flags which denote the situation
> where the alternative should be used.
> 
> That means we can use it to do individual word replacements for SMP vs
> UP, ARMv6 vs ARMv6k etc.

Sounds good to me. Maybe it should then be called cpualt instead of smpalt?

Tried booting your patch and needed the following fix for Cortex-A8 UP.

Now it boots to the following error:

Machine configuration botched (nr -1073741824), unable to continue.

Does some struct size need to be changed or something?

Regards,

Tony
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Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Bryan Wu]

On 08/19/2010 03:38 PM, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
>> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
>>> Great, will give it a try hopefully tomorrow. Sounds like that's the way
>>> to deal with fixing up things when booting up older UP ARMv6 without the
>>> 32v6 support :)
>>
>> What I've also been debating about is adding another word to the
>> smpalt structure, that being a set of flags which denote the situation
>> where the alternative should be used.
>>
>> That means we can use it to do individual word replacements for SMP vs
>> UP, ARMv6 vs ARMv6k etc.
> 
> Sounds good to me. Maybe it should then be called cpualt instead of smpalt?
> 
> Tried booting your patch and needed the following fix for Cortex-A8 UP.
> 
> Now it boots to the following error:
> 
> Machine configuration botched (nr -1073741824), unable to continue.
> 
> Does some struct size need to be changed or something?
> 

I also tested these 2 patches on my beagle board based on -for-next branch for
linux-omap tree. I don't have debug hardware to find the kernel boot failure. It
looks like it stops at very early stage.

Do you know where is the message (nr -1073741824) coming from?

Thanks,
-- 
Bryan Wu <bryan.wu@canonical.com>
Kernel Developer    +86.138-1617-6545 Mobile
Ubuntu Kernel Team | Hardware Enablement Team
Canonical Ltd.      www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Bryan Wu]

On 08/19/2010 03:38 PM, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
>> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
>>> Great, will give it a try hopefully tomorrow. Sounds like that's the way
>>> to deal with fixing up things when booting up older UP ARMv6 without the
>>> 32v6 support :)
>>
>> What I've also been debating about is adding another word to the
>> smpalt structure, that being a set of flags which denote the situation
>> where the alternative should be used.
>>
>> That means we can use it to do individual word replacements for SMP vs
>> UP, ARMv6 vs ARMv6k etc.
> 
> Sounds good to me. Maybe it should then be called cpualt instead of smpalt?
> 
> Tried booting your patch and needed the following fix for Cortex-A8 UP.
> 
> Now it boots to the following error:
> 
> Machine configuration botched (nr -1073741824), unable to continue.
> 
> Does some struct size need to be changed or something?
> 

I also tested these 2 patches on my beagle board based on -for-next branch for
linux-omap tree. I don't have debug hardware to find the kernel boot failure. It
looks like it stops at very early stage.

Do you know where is the message (nr -1073741824) coming from?

Thanks,
-- 
Bryan Wu <bryan.wu@canonical.com>
Kernel Developer    +86.138-1617-6545 Mobile
Ubuntu Kernel Team | Hardware Enablement Team
Canonical Ltd.      www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Bryan Wu <bryan.wu@canonical.com> [100819 12:31]:
> On 08/19/2010 03:38 PM, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
> >> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> >>> Great, will give it a try hopefully tomorrow. Sounds like that's the way
> >>> to deal with fixing up things when booting up older UP ARMv6 without the
> >>> 32v6 support :)
> >>
> >> What I've also been debating about is adding another word to the
> >> smpalt structure, that being a set of flags which denote the situation
> >> where the alternative should be used.
> >>
> >> That means we can use it to do individual word replacements for SMP vs
> >> UP, ARMv6 vs ARMv6k etc.
> > 
> > Sounds good to me. Maybe it should then be called cpualt instead of smpalt?
> > 
> > Tried booting your patch and needed the following fix for Cortex-A8 UP.
> > 
> > Now it boots to the following error:
> > 
> > Machine configuration botched (nr -1073741824), unable to continue.
> > 
> > Does some struct size need to be changed or something?
> > 
> 
> I also tested these 2 patches on my beagle board based on -for-next branch for
> linux-omap tree. I don't have debug hardware to find the kernel boot failure. It
> looks like it stops at very early stage.
> 
> Do you know where is the message (nr -1073741824) coming from?

Looks like something is not quite right with smp_on_up part of __fixup_smp,
returning early before smp_on_up does not produce that.

Regards,

Tony

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Bryan Wu <bryan.wu@canonical.com> [100819 12:31]:
> On 08/19/2010 03:38 PM, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
> >> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> >>> Great, will give it a try hopefully tomorrow. Sounds like that's the way
> >>> to deal with fixing up things when booting up older UP ARMv6 without the
> >>> 32v6 support :)
> >>
> >> What I've also been debating about is adding another word to the
> >> smpalt structure, that being a set of flags which denote the situation
> >> where the alternative should be used.
> >>
> >> That means we can use it to do individual word replacements for SMP vs
> >> UP, ARMv6 vs ARMv6k etc.
> > 
> > Sounds good to me. Maybe it should then be called cpualt instead of smpalt?
> > 
> > Tried booting your patch and needed the following fix for Cortex-A8 UP.
> > 
> > Now it boots to the following error:
> > 
> > Machine configuration botched (nr -1073741824), unable to continue.
> > 
> > Does some struct size need to be changed or something?
> > 
> 
> I also tested these 2 patches on my beagle board based on -for-next branch for
> linux-omap tree. I don't have debug hardware to find the kernel boot failure. It
> looks like it stops at very early stage.
> 
> Do you know where is the message (nr -1073741824) coming from?

Looks like something is not quite right with smp_on_up part of __fixup_smp,
returning early before smp_on_up does not produce that.

Regards,

Tony

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> Looks like something is not quite right with smp_on_up part of __fixup_smp,
> returning early before smp_on_up does not produce that.

It's probably overwriting some register it shouldn't be.  I might be
able to look at this sometime during the coming week... assuming that
the weather is as bad as they forecast and I have 'net connectivity.

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> Looks like something is not quite right with smp_on_up part of __fixup_smp,
> returning early before smp_on_up does not produce that.

It's probably overwriting some register it shouldn't be.  I might be
able to look at this sometime during the coming week... assuming that
the weather is as bad as they forecast and I have 'net connectivity.

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > returning early before smp_on_up does not produce that.
> 
> It's probably overwriting some register it shouldn't be.  I might be
> able to look at this sometime during the coming week... assuming that
> the weather is as bad as they forecast and I have 'net connectivity.

OK, I'll be offline too probably until late next week.

Tony

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > returning early before smp_on_up does not produce that.
> 
> It's probably overwriting some register it shouldn't be.  I might be
> able to look at this sometime during the coming week... assuming that
> the weather is as bad as they forecast and I have 'net connectivity.

OK, I'll be offline too probably until late next week.

Tony

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 586 bytes --]

* Tony Lindgren <tony@atomide.com> [100820 04:59]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > returning early before smp_on_up does not produce that.
> > 
> > It's probably overwriting some register it shouldn't be.  I might be
> > able to look at this sometime during the coming week... assuming that
> > the weather is as bad as they forecast and I have 'net connectivity.

This seems to fix it.

Tony

[-- Attachment #2: fix-smp-on-up.patch --]
[-- Type: text/x-diff, Size: 788 bytes --]

From: Tony Lindgren <tony@atomide.com>
Date: Mon, 30 Aug 2010 13:52:52 -0700
Subject: [PATCH] ARM: Fix smp_on_up to not trash r1 and r2

We need to preserve r1 and r2 for __mmap_switched. So
use r3, r6, r7 instead of r1, r2, r3. We can trash
r3, r6, r7 as they get corrupted in __create_page_tables
anyways.

Signed-off-by: Tony Lindgren <tony@atomide.com>

--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -353,14 +353,14 @@ __fixup_smp:
 
 smp_on_up:
 	adr	r0, 1f
-	ldmia	r0, {r1, r2, r3}
-	sub	r1, r0, r1
-	add	r2, r2, r1
-	add	r3, r3, r1
-2:	cmp	r2, r3
-	ldmia	r2!, {r0, r4}
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
 	movhs	pc, lr
-	str	r4, [r0, r1]
+	str	r4, [r0, r3]
 	b	2b
 ENDPROC(__fixup_smp)
 

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100820 04:59]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > returning early before smp_on_up does not produce that.
> > 
> > It's probably overwriting some register it shouldn't be.  I might be
> > able to look at this sometime during the coming week... assuming that
> > the weather is as bad as they forecast and I have 'net connectivity.

This seems to fix it.

Tony
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Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [100820 04:59]:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > > returning early before smp_on_up does not produce that.
> > > 
> > > It's probably overwriting some register it shouldn't be.  I might be
> > > able to look at this sometime during the coming week... assuming that
> > > the weather is as bad as they forecast and I have 'net connectivity.
> 
> This seems to fix it.

Thanks, merged that into my original patch - so here it is again with
everything updated.

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9295110..725a463 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,18 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don' tknow what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/smp_midr.h b/arch/arm/include/asm/smp_midr.h
index e69de29..4538ba4 100644
--- a/arch/arm/include/asm/smp_midr.h
+++ b/arch/arm/include/asm/smp_midr.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_SMP_MIDR_H
+#define ASMARM_SMP_MIDR_H
+
+#define hard_smp_processor_id()						\
+	({								\
+		unsigned int cpunum;					\
+		__asm__("\n"						\
+			"1:	mrc p15, 0, %0, c0, c0, 5\n"		\
+			"	.pushsection \".smpalt.init\", \"a\"\n"	\
+			"	.word	1b\n"				\
+			"	mov	%0, #0\n"			\
+			"	.popsection"				\
+			: "=r" (cpunum));				\
+		cpunum &= 0x0F;						\
+	})
+
+#endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..1fd0db9 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,12 +189,15 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#else
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..cf76484 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	movne	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r3]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 6a3ff65..ed96907 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [100820 04:59]:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > > returning early before smp_on_up does not produce that.
> > > 
> > > It's probably overwriting some register it shouldn't be.  I might be
> > > able to look at this sometime during the coming week... assuming that
> > > the weather is as bad as they forecast and I have 'net connectivity.
> 
> This seems to fix it.

Thanks, merged that into my original patch - so here it is again with
everything updated.

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9295110..725a463 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,18 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don' tknow what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/smp_midr.h b/arch/arm/include/asm/smp_midr.h
index e69de29..4538ba4 100644
--- a/arch/arm/include/asm/smp_midr.h
+++ b/arch/arm/include/asm/smp_midr.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_SMP_MIDR_H
+#define ASMARM_SMP_MIDR_H
+
+#define hard_smp_processor_id()						\
+	({								\
+		unsigned int cpunum;					\
+		__asm__("\n"						\
+			"1:	mrc p15, 0, %0, c0, c0, 5\n"		\
+			"	.pushsection \".smpalt.init\", \"a\"\n"	\
+			"	.word	1b\n"				\
+			"	mov	%0, #0\n"			\
+			"	.popsection"				\
+			: "=r" (cpunum));				\
+		cpunum &= 0x0F;						\
+	})
+
+#endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..1fd0db9 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,12 +189,15 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#else
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..cf76484 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	movne	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r3]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 6a3ff65..ed96907 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:29]:
> On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [100820 04:59]:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > > > returning early before smp_on_up does not produce that.
> > > > 
> > > > It's probably overwriting some register it shouldn't be.  I might be
> > > > able to look at this sometime during the coming week... assuming that
> > > > the weather is as bad as they forecast and I have 'net connectivity.
> > 
> > This seems to fix it.
> 
> Thanks, merged that into my original patch - so here it is again with
> everything updated.

Your patch sure makes things simpler! The problem still is the
V6 vs V7 SMP code though.

Will post my six patches that apply on top of your patch as a reply to
this mail. With those, everything seems to work, at least after testing
on omap3630 (Cortex-A8 UP) and omap4430 (Cortex-A9 SMP).

Will, maybe see if there are some parts in your patchset that should
be used instead? I noticed pretty much all the earlier hacks are no
longer needed :)

Regards,

Tony

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:29]:
> On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [100820 04:59]:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > > > returning early before smp_on_up does not produce that.
> > > > 
> > > > It's probably overwriting some register it shouldn't be.  I might be
> > > > able to look at this sometime during the coming week... assuming that
> > > > the weather is as bad as they forecast and I have 'net connectivity.
> > 
> > This seems to fix it.
> 
> Thanks, merged that into my original patch - so here it is again with
> everything updated.

Your patch sure makes things simpler! The problem still is the
V6 vs V7 SMP code though.

Will post my six patches that apply on top of your patch as a reply to
this mail. With those, everything seems to work, at least after testing
on omap3630 (Cortex-A8 UP) and omap4430 (Cortex-A9 SMP).

Will, maybe see if there are some parts in your patchset that should
be used instead? I noticed pretty much all the earlier hacks are no
longer needed :)

Regards,

Tony

[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

>From 7044c13594c3023da6095f8d432eda260bc3207f Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Mon, 30 Aug 2010 14:00:54 -0700
Subject: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

Add inline function smp_on_up() for early init checks, and
change build_mem_type_table to use it.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/smp_plat.h |   16 ++++++++++++++++
 arch/arm/mm/mmu.c               |   20 +++++++++++---------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 8db3512..5ef4114 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
 #define UP(instr...)	_str(instr)
 #endif
 
+static inline int smp_on_up(void)
+{
+#ifdef CONFIG_SMP_ON_UP
+	int smp_on_up;
+
+	asm(							\
+		SMP(mov	%0, #0)					\
+		UP(mov	%0, #1)					\
+		: "=r" (smp_on_up));
+
+	return smp_on_up;
+#else
+	return 0;
+#endif
+}
+
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..f320901 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -430,15 +430,17 @@ static void __init build_mem_type_table(void)
 		/*
 		 * Mark memory with the "shared" attribute for SMP systems
 		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		if (!smp_on_up()) {
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 #endif
 	}
 
-- 
1.7.1

[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> >From 7044c13594c3023da6095f8d432eda260bc3207f Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Mon, 30 Aug 2010 14:00:54 -0700
> Subject: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing
> 
> Add inline function smp_on_up() for early init checks, and
> change build_mem_type_table to use it.

Isn't something missing from this - such as a C-mode definition of
SMP() and UP() ?

> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index 8db3512..5ef4114 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
>  #define UP(instr...)	_str(instr)
>  #endif
>  
> +static inline int smp_on_up(void)
> +{
> +#ifdef CONFIG_SMP_ON_UP
> +	int smp_on_up;
> +
> +	asm(							\
> +		SMP(mov	%0, #0)					\
> +		UP(mov	%0, #1)					\
> +		: "=r" (smp_on_up));
> +
> +	return smp_on_up;
> +#else
> +	return 0;
> +#endif

I think this is the wrong approach - rather than a function which tells us
just if we are a SMP kernel running on UP, why not something which returns
whether we're running on SMP and use that to eliminate some of these ifdefs?

[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> >From 7044c13594c3023da6095f8d432eda260bc3207f Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Mon, 30 Aug 2010 14:00:54 -0700
> Subject: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing
> 
> Add inline function smp_on_up() for early init checks, and
> change build_mem_type_table to use it.

Isn't something missing from this - such as a C-mode definition of
SMP() and UP() ?

> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index 8db3512..5ef4114 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
>  #define UP(instr...)	_str(instr)
>  #endif
>  
> +static inline int smp_on_up(void)
> +{
> +#ifdef CONFIG_SMP_ON_UP
> +	int smp_on_up;
> +
> +	asm(							\
> +		SMP(mov	%0, #0)					\
> +		UP(mov	%0, #1)					\
> +		: "=r" (smp_on_up));
> +
> +	return smp_on_up;
> +#else
> +	return 0;
> +#endif

I think this is the wrong approach - rather than a function which tells us
just if we are a SMP kernel running on UP, why not something which returns
whether we're running on SMP and use that to eliminate some of these ifdefs?

[PATCH 0/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> > >From 7044c13594c3023da6095f8d432eda260bc3207f Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Mon, 30 Aug 2010 14:00:54 -0700
> > Subject: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing
> > 
> > Add inline function smp_on_up() for early init checks, and
> > change build_mem_type_table to use it.
> 
> Isn't something missing from this - such as a C-mode definition of
> SMP() and UP() ?

Oops, here's the missing patch.

Tony
>From e52db459dba0088fcff66904069630a24a811db8 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Wed, 1 Sep 2010 15:02:50 -0700
Subject: [PATCH] ARM: Add SMP and UP macros for inline assembly

We can't use the macros in asm/assembler.h in C inline functions.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 55974d2..340795c 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,6 +154,10 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+/*
+ * SMP and UP defines for assembly code. See also asm/smp_plat.h
+ * for the SMP and UP defines for inline code.
+ */
 #ifdef CONFIG_SMP
 #define SMP(instr...)						\
 9998:	instr
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..8db3512 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -18,4 +18,25 @@ static inline int cache_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 
+/*
+ * SMP and UP defines for inline functions. See also asm/assembler.h
+ * for the SMP and UP defines for assembly code.
+ */
+#ifdef CONFIG_SMP
+#define _str(s...)	#s
+#define _9998(s...)	_str(9998:	s\n)
+
+#define SMP(instr...)						\
+	_9998(instr)
+
+#define UP(instr...)						\
+	_str(.pushsection ".smpalt.init", "a"\n)		\
+	_str(.word	9998b\n)				\
+	_str(instr\n)						\
+	_str(.popsection\n)
+#else
+#define SMP(instr...)
+#define UP(instr...)	_str(instr)
+#endif
+
 #endif

[PATCH 0/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> > >From 7044c13594c3023da6095f8d432eda260bc3207f Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Mon, 30 Aug 2010 14:00:54 -0700
> > Subject: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing
> > 
> > Add inline function smp_on_up() for early init checks, and
> > change build_mem_type_table to use it.
> 
> Isn't something missing from this - such as a C-mode definition of
> SMP() and UP() ?

Oops, here's the missing patch.

Tony

Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> 
> > --- a/arch/arm/include/asm/smp_plat.h
> > +++ b/arch/arm/include/asm/smp_plat.h
> > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
> >  #define UP(instr...)	_str(instr)
> >  #endif
> >  
> > +static inline int smp_on_up(void)
> > +{
> > +#ifdef CONFIG_SMP_ON_UP
> > +	int smp_on_up;
> > +
> > +	asm(							\
> > +		SMP(mov	%0, #0)					\
> > +		UP(mov	%0, #1)					\
> > +		: "=r" (smp_on_up));
> > +
> > +	return smp_on_up;
> > +#else
> > +	return 0;
> > +#endif
> 
> I think this is the wrong approach - rather than a function which tells us
> just if we are a SMP kernel running on UP, why not something which returns
> whether we're running on SMP and use that to eliminate some of these ifdefs?

Sure. Will has something like this in his patches:

static inline int cpu_is_part_of_mp_system(void)
{
	u32 mpidr;
	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
	return (mpidr >> 31) ? !(mpidr >> 30) : 0;
}

BTW, so far looks like we should only need this during init to set up things.

Regards,

Tony

[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> 
> > --- a/arch/arm/include/asm/smp_plat.h
> > +++ b/arch/arm/include/asm/smp_plat.h
> > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
> >  #define UP(instr...)	_str(instr)
> >  #endif
> >  
> > +static inline int smp_on_up(void)
> > +{
> > +#ifdef CONFIG_SMP_ON_UP
> > +	int smp_on_up;
> > +
> > +	asm(							\
> > +		SMP(mov	%0, #0)					\
> > +		UP(mov	%0, #1)					\
> > +		: "=r" (smp_on_up));
> > +
> > +	return smp_on_up;
> > +#else
> > +	return 0;
> > +#endif
> 
> I think this is the wrong approach - rather than a function which tells us
> just if we are a SMP kernel running on UP, why not something which returns
> whether we're running on SMP and use that to eliminate some of these ifdefs?

Sure. Will has something like this in his patches:

static inline int cpu_is_part_of_mp_system(void)
{
	u32 mpidr;
	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
	return (mpidr >> 31) ? !(mpidr >> 30) : 0;
}

BTW, so far looks like we should only need this during init to set up things.

Regards,

Tony

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 1362 bytes --]

* Tony Lindgren <tony@atomide.com> [100902 10:35]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> > On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> > 
> > > --- a/arch/arm/include/asm/smp_plat.h
> > > +++ b/arch/arm/include/asm/smp_plat.h
> > > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
> > >  #define UP(instr...)	_str(instr)
> > >  #endif
> > >  
> > > +static inline int smp_on_up(void)
> > > +{
> > > +#ifdef CONFIG_SMP_ON_UP
> > > +	int smp_on_up;
> > > +
> > > +	asm(							\
> > > +		SMP(mov	%0, #0)					\
> > > +		UP(mov	%0, #1)					\
> > > +		: "=r" (smp_on_up));
> > > +
> > > +	return smp_on_up;
> > > +#else
> > > +	return 0;
> > > +#endif
> > 
> > I think this is the wrong approach - rather than a function which tells us
> > just if we are a SMP kernel running on UP, why not something which returns
> > whether we're running on SMP and use that to eliminate some of these ifdefs?
> 
> Sure. Will has something like this in his patches:
> 
> static inline int cpu_is_part_of_mp_system(void)
> {
> 	u32 mpidr;
> 	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> 	return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> }
> 
> BTW, so far looks like we should only need this during init to set up things.

Here's this one updated to replace smp_cpu() instead of smp_on_up().

Tony

[-- Attachment #2: smp-cpu.patch --]
[-- Type: text/x-diff, Size: 2042 bytes --]

From: Tony Lindgren <tony@atomide.com>
Date: Mon, 30 Aug 2010 14:00:54 -0700
Subject: [PATCH] ARM: Add inline function smp_cpu() for early init testing

Add inline function smp_cpu() for early init checks, and
change build_mem_type_table to use it.

Inline function copied from cpu_is_part_of_mp_system() by
Will Deacon <will.deacon@arm.com>.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 8db3512..82bc488 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
 #define UP(instr...)	_str(instr)
 #endif
 
+static inline int smp_cpu(void)
+{
+        u32 mpidr;
+        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
+        return (mpidr >> 31) ? !(mpidr >> 30) : 0;
+}
+
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..2bfaefd 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -430,15 +430,17 @@ static void __init build_mem_type_table(void)
 		/*
 		 * Mark memory with the "shared" attribute for SMP systems
 		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		if (smp_cpu()) {
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 #endif
 	}
 

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100902 10:35]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> > On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> > 
> > > --- a/arch/arm/include/asm/smp_plat.h
> > > +++ b/arch/arm/include/asm/smp_plat.h
> > > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
> > >  #define UP(instr...)	_str(instr)
> > >  #endif
> > >  
> > > +static inline int smp_on_up(void)
> > > +{
> > > +#ifdef CONFIG_SMP_ON_UP
> > > +	int smp_on_up;
> > > +
> > > +	asm(							\
> > > +		SMP(mov	%0, #0)					\
> > > +		UP(mov	%0, #1)					\
> > > +		: "=r" (smp_on_up));
> > > +
> > > +	return smp_on_up;
> > > +#else
> > > +	return 0;
> > > +#endif
> > 
> > I think this is the wrong approach - rather than a function which tells us
> > just if we are a SMP kernel running on UP, why not something which returns
> > whether we're running on SMP and use that to eliminate some of these ifdefs?
> 
> Sure. Will has something like this in his patches:
> 
> static inline int cpu_is_part_of_mp_system(void)
> {
> 	u32 mpidr;
> 	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> 	return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> }
> 
> BTW, so far looks like we should only need this during init to set up things.

Here's this one updated to replace smp_cpu() instead of smp_on_up().

Tony
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Re: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 1647 bytes --]

* Tony Lindgren <tony@atomide.com> [100902 12:20]:
> * Tony Lindgren <tony@atomide.com> [100902 10:35]:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> > > On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> > > 
> > > > --- a/arch/arm/include/asm/smp_plat.h
> > > > +++ b/arch/arm/include/asm/smp_plat.h
> > > > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
> > > >  #define UP(instr...)	_str(instr)
> > > >  #endif
> > > >  
> > > > +static inline int smp_on_up(void)
> > > > +{
> > > > +#ifdef CONFIG_SMP_ON_UP
> > > > +	int smp_on_up;
> > > > +
> > > > +	asm(							\
> > > > +		SMP(mov	%0, #0)					\
> > > > +		UP(mov	%0, #1)					\
> > > > +		: "=r" (smp_on_up));
> > > > +
> > > > +	return smp_on_up;
> > > > +#else
> > > > +	return 0;
> > > > +#endif
> > > 
> > > I think this is the wrong approach - rather than a function which tells us
> > > just if we are a SMP kernel running on UP, why not something which returns
> > > whether we're running on SMP and use that to eliminate some of these ifdefs?
> > 
> > Sure. Will has something like this in his patches:
> > 
> > static inline int cpu_is_part_of_mp_system(void)
> > {
> > 	u32 mpidr;
> > 	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> > 	return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> > }
> > 
> > BTW, so far looks like we should only need this during init to set up things.
> 
> Here's this one updated to replace smp_cpu() instead of smp_on_up().

Heh, turns out there's a bit of a bug in the code snippet above :) It should
be !((mpidr >> 30) & 1) instead, otherwise it always returns 0.

Regards,

Tony

[-- Attachment #2: smp-cpu.patch --]
[-- Type: text/x-diff, Size: 2048 bytes --]

From: Tony Lindgren <tony@atomide.com>
Date: Mon, 30 Aug 2010 14:00:54 -0700
Subject: [PATCH] ARM: Add inline function smp_cpu() for early init testing

Add inline function smp_cpu() for early init checks, and
change build_mem_type_table to use it.

Inline function copied from cpu_is_part_of_mp_system() by
Will Deacon <will.deacon@arm.com>.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 8db3512..060213e 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
 #define UP(instr...)	_str(instr)
 #endif
 
+static inline int smp_cpu(void)
+{
+        u32 mpidr;
+        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
+        return (mpidr >> 31) ? !((mpidr >> 30) & 1) : 0;
+}
+
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..2bfaefd 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -430,15 +430,17 @@ static void __init build_mem_type_table(void)
 		/*
 		 * Mark memory with the "shared" attribute for SMP systems
 		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		if (smp_cpu()) {
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 #endif
 	}
 

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100902 12:20]:
> * Tony Lindgren <tony@atomide.com> [100902 10:35]:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> > > On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> > > 
> > > > --- a/arch/arm/include/asm/smp_plat.h
> > > > +++ b/arch/arm/include/asm/smp_plat.h
> > > > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
> > > >  #define UP(instr...)	_str(instr)
> > > >  #endif
> > > >  
> > > > +static inline int smp_on_up(void)
> > > > +{
> > > > +#ifdef CONFIG_SMP_ON_UP
> > > > +	int smp_on_up;
> > > > +
> > > > +	asm(							\
> > > > +		SMP(mov	%0, #0)					\
> > > > +		UP(mov	%0, #1)					\
> > > > +		: "=r" (smp_on_up));
> > > > +
> > > > +	return smp_on_up;
> > > > +#else
> > > > +	return 0;
> > > > +#endif
> > > 
> > > I think this is the wrong approach - rather than a function which tells us
> > > just if we are a SMP kernel running on UP, why not something which returns
> > > whether we're running on SMP and use that to eliminate some of these ifdefs?
> > 
> > Sure. Will has something like this in his patches:
> > 
> > static inline int cpu_is_part_of_mp_system(void)
> > {
> > 	u32 mpidr;
> > 	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> > 	return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> > }
> > 
> > BTW, so far looks like we should only need this during init to set up things.
> 
> Here's this one updated to replace smp_cpu() instead of smp_on_up().

Heh, turns out there's a bit of a bug in the code snippet above :) It should
be !((mpidr >> 30) & 1) instead, otherwise it always returns 0.

Regards,

Tony
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Re: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 368 bytes --]

* Tony Lindgren <tony@atomide.com> [100902 17:00]:
> * Tony Lindgren <tony@atomide.com> [100902 12:20]:
> 
> Heh, turns out there's a bit of a bug in the code snippet above :) It should
> be !((mpidr >> 30) & 1) instead, otherwise it always returns 0.

This too can check for value of 2. Also we probably want to do the
CPU type checks too. Updated patch below.

Tony

[-- Attachment #2: smp-cpu.patch --]
[-- Type: text/x-diff, Size: 2233 bytes --]

From: Tony Lindgren <tony@atomide.com>
Date: Mon, 30 Aug 2010 14:00:54 -0700
Subject: [PATCH] ARM: Add inline function smp_cpu() for early init testing

Add inline function smp_cpu() for early init checks, and
change build_mem_type_table to use it.

Inline function copied from cpu_is_part_of_mp_system() by
Will Deacon <will.deacon@arm.com>.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 8db3512..50a4f0b 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -39,4 +39,24 @@ static inline int cache_ops_need_broadcast(void)
 #define UP(instr...)	_str(instr)
 #endif
 
+static inline int smp_cpu(void)
+{
+        u32 val;
+
+	val = read_cpuid(CPUID_ID);
+
+	/* Check for ARM CPU */
+	if ((val & 0xff000000) != 0x41000000)
+		return 0;
+
+	/* Check for ARMv6 or 7 */
+	if ((val & 0x00070000) != 0x00070000)
+		return 0;
+
+	/* Check MPIDR */
+        asm ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+        return (val >> 30) == 2;
+}
+
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..2bfaefd 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -430,15 +430,17 @@ static void __init build_mem_type_table(void)
 		/*
 		 * Mark memory with the "shared" attribute for SMP systems
 		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		if (smp_cpu()) {
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 #endif
 	}
 

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100902 17:00]:
> * Tony Lindgren <tony@atomide.com> [100902 12:20]:
> 
> Heh, turns out there's a bit of a bug in the code snippet above :) It should
> be !((mpidr >> 30) & 1) instead, otherwise it always returns 0.

This too can check for value of 2. Also we probably want to do the
CPU type checks too. Updated patch below.

Tony
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[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Will Deacon]

Hi Tony,

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: 03 September 2010 03:22
> To: Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Bryan Wu; Will Deacon
> Subject: Re: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing
> 
> * Tony Lindgren <tony@atomide.com> [100902 17:00]:
> > * Tony Lindgren <tony@atomide.com> [100902 12:20]:
> >
> > Heh, turns out there's a bit of a bug in the code snippet above :) It should
> > be !((mpidr >> 30) & 1) instead, otherwise it always returns 0.

Gah! Well spotted! I think I was getting away with this because the platforms
I was using for testing didn't need tlb ops to be broadcast.

> This too can check for value of 2. Also we probably want to do the
> CPU type checks too. Updated patch below.

Your patches are turning up as attachments here, so I can't comment
inline. The only problem I can see is for SMP v6 platforms (ARM11MPCore)
where the MPIDR is actually the `CPU ID register' with bits 31:12 set to
zero, so we'll say it's a UP core.

Since 11MPCore is the only ARM SMP v6 processor and you're checking
the implementor ID anyway, it might be easier to check for the 11MPCore
explicitly, ((read_cpuid_id() & 0xfff0) == 0xB020) rather than check for v6/v7.

Or we could just ignore v6 for now.

Will

Re: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 09:58:23AM +0100, Will Deacon wrote:
> Your patches are turning up as attachments here, so I can't comment
> inline. The only problem I can see is for SMP v6 platforms (ARM11MPCore)
> where the MPIDR is actually the `CPU ID register' with bits 31:12 set to
> zero, so we'll say it's a UP core.
> 
> Since 11MPCore is the only ARM SMP v6 processor and you're checking
> the implementor ID anyway, it might be easier to check for the 11MPCore
> explicitly, ((read_cpuid_id() & 0xfff0) == 0xB020) rather than check for v6/v7.
> 
> Or we could just ignore v6 for now.

We can't.  We need to get this correct so the head.S code can also get it
right.

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 09:58:23AM +0100, Will Deacon wrote:
> Your patches are turning up as attachments here, so I can't comment
> inline. The only problem I can see is for SMP v6 platforms (ARM11MPCore)
> where the MPIDR is actually the `CPU ID register' with bits 31:12 set to
> zero, so we'll say it's a UP core.
> 
> Since 11MPCore is the only ARM SMP v6 processor and you're checking
> the implementor ID anyway, it might be easier to check for the 11MPCore
> explicitly, ((read_cpuid_id() & 0xfff0) == 0xB020) rather than check for v6/v7.
> 
> Or we could just ignore v6 for now.

We can't.  We need to get this correct so the head.S code can also get it
right.

RE: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Will Deacon]

> On Fri, Sep 03, 2010 at 09:58:23AM +0100, Will Deacon wrote:
> > Your patches are turning up as attachments here, so I can't comment
> > inline. The only problem I can see is for SMP v6 platforms (ARM11MPCore)
> > where the MPIDR is actually the `CPU ID register' with bits 31:12 set to
> > zero, so we'll say it's a UP core.
> >
> > Since 11MPCore is the only ARM SMP v6 processor and you're checking
> > the implementor ID anyway, it might be easier to check for the 11MPCore
> > explicitly, ((read_cpuid_id() & 0xfff0) == 0xB020) rather than check for v6/v7.
> >
> > Or we could just ignore v6 for now.
> 
> We can't.  We need to get this correct so the head.S code can also get it
> right.

Damn. Then I guess we assume a core is UP unless it's an 11MPCore or a v7
with the relevant mpidr bits set. Actually, special casing the 11MPCore
means that we can use cpu_architecture() to check for v7 rather than masking
out fields from the cpuid ourselves.

Will

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Will Deacon]

> On Fri, Sep 03, 2010 at 09:58:23AM +0100, Will Deacon wrote:
> > Your patches are turning up as attachments here, so I can't comment
> > inline. The only problem I can see is for SMP v6 platforms (ARM11MPCore)
> > where the MPIDR is actually the `CPU ID register' with bits 31:12 set to
> > zero, so we'll say it's a UP core.
> >
> > Since 11MPCore is the only ARM SMP v6 processor and you're checking
> > the implementor ID anyway, it might be easier to check for the 11MPCore
> > explicitly, ((read_cpuid_id() & 0xfff0) == 0xB020) rather than check for v6/v7.
> >
> > Or we could just ignore v6 for now.
> 
> We can't.  We need to get this correct so the head.S code can also get it
> right.

Damn. Then I guess we assume a core is UP unless it's an 11MPCore or a v7
with the relevant mpidr bits set. Actually, special casing the 11MPCore
means that we can use cpu_architecture() to check for v7 rather than masking
out fields from the cpuid ourselves.

Will

RE: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Will Deacon]

Hi Tony,

> -----Original Message-----
> From: Tony Lindgren [mailto:tony@atomide.com]
> Sent: 03 September 2010 03:22
> To: Russell King - ARM Linux
> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Bryan Wu; Will Deacon
> Subject: Re: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing
> 
> * Tony Lindgren <tony@atomide.com> [100902 17:00]:
> > * Tony Lindgren <tony@atomide.com> [100902 12:20]:
> >
> > Heh, turns out there's a bit of a bug in the code snippet above :) It should
> > be !((mpidr >> 30) & 1) instead, otherwise it always returns 0.

Gah! Well spotted! I think I was getting away with this because the platforms
I was using for testing didn't need tlb ops to be broadcast.

> This too can check for value of 2. Also we probably want to do the
> CPU type checks too. Updated patch below.

Your patches are turning up as attachments here, so I can't comment
inline. The only problem I can see is for SMP v6 platforms (ARM11MPCore)
where the MPIDR is actually the `CPU ID register' with bits 31:12 set to
zero, so we'll say it's a UP core.

Since 11MPCore is the only ARM SMP v6 processor and you're checking
the implementor ID anyway, it might be easier to check for the 11MPCore
explicitly, ((read_cpuid_id() & 0xfff0) == 0xB020) rather than check for v6/v7.

Or we could just ignore v6 for now.

Will

RE: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Shilimkar, Santosh]

> > BTW, so far looks like we should only need this during init to set up
> things.
> 
> Here's this one updated to replace smp_cpu() instead of smp_on_up().
> 


diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 8db3512..82bc488 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
 #define UP(instr...)	_str(instr)
 #endif
 
+static inline int smp_cpu(void)
+{
+        u32 mpidr;
+        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
+        return (mpidr >> 31) ? !(mpidr >> 30) : 0;
+}
+
Will this be called on UP machines ?? if yes, then mpidr register is not
available on those
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..2bfaefd 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -430,15 +430,17 @@ static void __init build_mem_type_table(void)
 		/*
 		 * Mark memory with the "shared" attribute for SMP systems
 		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		if (smp_cpu()) {
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 #endif
 	}

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Shilimkar, Santosh]

> > BTW, so far looks like we should only need this during init to set up
> things.
> 
> Here's this one updated to replace smp_cpu() instead of smp_on_up().
> 


diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 8db3512..82bc488 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
 #define UP(instr...)	_str(instr)
 #endif
 
+static inline int smp_cpu(void)
+{
+        u32 mpidr;
+        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
+        return (mpidr >> 31) ? !(mpidr >> 30) : 0;
+}
+
Will this be called on UP machines ?? if yes, then mpidr register is not
available on those
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..2bfaefd 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -430,15 +430,17 @@ static void __init build_mem_type_table(void)
 		/*
 		 * Mark memory with the "shared" attribute for SMP systems
 		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		if (smp_cpu()) {
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 #endif
 	}

RE: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Will Deacon]

Santosh,

> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index 8db3512..82bc488 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
>  #define UP(instr...)	_str(instr)
>  #endif
> 
> +static inline int smp_cpu(void)
> +{
> +        u32 mpidr;
> +        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> +        return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> +}
> +
> Will this be called on UP machines ?? if yes, then mpidr register is not
> available on those

The multiprocessor affinity register (MPIDR) is defined as part of ARMv7.
ARM recommends that it returns 0 on UP systems. If bit 31 is set, then the
multiprocessing extensions are available.

The quirk (as discussed early) is that that 11MPCore has the CPUID register
at this location in the coprocessor space, with bit 31 set to 0. This means
that we have to check for it explicitly otherwise we will identify it as a
UP machine.

Will

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Will Deacon]

Santosh,

> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index 8db3512..82bc488 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
>  #define UP(instr...)	_str(instr)
>  #endif
> 
> +static inline int smp_cpu(void)
> +{
> +        u32 mpidr;
> +        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> +        return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> +}
> +
> Will this be called on UP machines ?? if yes, then mpidr register is not
> available on those

The multiprocessor affinity register (MPIDR) is defined as part of ARMv7.
ARM recommends that it returns 0 on UP systems. If bit 31 is set, then the
multiprocessing extensions are available.

The quirk (as discussed early) is that that 11MPCore has the CPUID register
at this location in the coprocessor space, with bit 31 set to 0. This means
that we have to check for it explicitly otherwise we will identify it as a
UP machine.

Will

RE: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Shilimkar, Santosh]

> -----Original Message-----
> From: Will Deacon [mailto:will.deacon@arm.com]
> Sent: Friday, September 03, 2010 5:54 PM
> To: Shilimkar, Santosh; Tony Lindgren; Russell King - ARM Linux
> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Bryan Wu
> Subject: RE: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init
> testing
> 
> Santosh,
> 
> > diff --git a/arch/arm/include/asm/smp_plat.h
> b/arch/arm/include/asm/smp_plat.h
> > index 8db3512..82bc488 100644
> > --- a/arch/arm/include/asm/smp_plat.h
> > +++ b/arch/arm/include/asm/smp_plat.h
> > @@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
> >  #define UP(instr...)	_str(instr)
> >  #endif
> >
> > +static inline int smp_cpu(void)
> > +{
> > +        u32 mpidr;
> > +        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> > +        return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> > +}
> > +
> > Will this be called on UP machines ?? if yes, then mpidr register is not
> > available on those
> 
> The multiprocessor affinity register (MPIDR) is defined as part of ARMv7.
> ARM recommends that it returns 0 on UP systems. If bit 31 is set, then the
> multiprocessing extensions are available.
> 
I might be wrong but  didn't find this register on Cortex-A8(ARMv7).

> The quirk (as discussed early) is that that 11MPCore has the CPUID
> register
> at this location in the coprocessor space, with bit 31 set to 0. This
> means
> that we have to check for it explicitly otherwise we will identify it as a
> UP machine.
> 
> Will
> 

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Shilimkar, Santosh]

> -----Original Message-----
> From: Will Deacon [mailto:will.deacon at arm.com]
> Sent: Friday, September 03, 2010 5:54 PM
> To: Shilimkar, Santosh; Tony Lindgren; Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Bryan Wu
> Subject: RE: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init
> testing
> 
> Santosh,
> 
> > diff --git a/arch/arm/include/asm/smp_plat.h
> b/arch/arm/include/asm/smp_plat.h
> > index 8db3512..82bc488 100644
> > --- a/arch/arm/include/asm/smp_plat.h
> > +++ b/arch/arm/include/asm/smp_plat.h
> > @@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
> >  #define UP(instr...)	_str(instr)
> >  #endif
> >
> > +static inline int smp_cpu(void)
> > +{
> > +        u32 mpidr;
> > +        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> > +        return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> > +}
> > +
> > Will this be called on UP machines ?? if yes, then mpidr register is not
> > available on those
> 
> The multiprocessor affinity register (MPIDR) is defined as part of ARMv7.
> ARM recommends that it returns 0 on UP systems. If bit 31 is set, then the
> multiprocessing extensions are available.
> 
I might be wrong but  didn't find this register on Cortex-A8(ARMv7).

> The quirk (as discussed early) is that that 11MPCore has the CPUID
> register
> at this location in the coprocessor space, with bit 31 set to 0. This
> means
> that we have to check for it explicitly otherwise we will identify it as a
> UP machine.
> 
> Will
> 

Re: [PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Michał Nazarewicz]

On Fri, 03 Sep 2010 14:12:22 +0200, Shilimkar, Santosh <santosh.shilimkar@ti.com> wrote:
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index 8db3512..82bc488 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
>  #define UP(instr...)	_str(instr)
>  #endif
> +static inline int smp_cpu(void)
> +{
> +        u32 mpidr;
> +        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> +        return (mpidr >> 31) ? !(mpidr >> 30) : 0;

This always returns 0.  If (mpdir >> 31) is true then (mpidr >> 30) is
either 2 or 3.  Did you mean:

+	return (mpidr >> 30) == 2;

> +}
> +

-- 
Best regards,                                        _     _
| Humble Liege of Serenely Enlightened Majesty of  o' \,=./ `o
| Computer Science,  Michał "mina86" Nazarewicz       (o o)
+----[mina86*mina86.com]---[mina86*jabber.org]----ooO--(_)--Ooo--

--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 1/6] ARM: Add inline function smp_cpu() for early init testing

[Michał Nazarewicz]

On Fri, 03 Sep 2010 14:12:22 +0200, Shilimkar, Santosh <santosh.shilimkar@ti.com> wrote:
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index 8db3512..82bc488 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -39,4 +39,11 @@ static inline int cache_ops_need_broadcast(void)
>  #define UP(instr...)	_str(instr)
>  #endif
> +static inline int smp_cpu(void)
> +{
> +        u32 mpidr;
> +        asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> +        return (mpidr >> 31) ? !(mpidr >> 30) : 0;

This always returns 0.  If (mpdir >> 31) is true then (mpidr >> 30) is
either 2 or 3.  Did you mean:

+	return (mpidr >> 30) == 2;

> +}
> +

-- 
Best regards,                                        _     _
| Humble Liege of Serenely Enlightened Majesty of  o' \,=./ `o
| Computer Science,  Micha? "mina86" Nazarewicz       (o o)
+----[mina86*mina86.com]---[mina86*jabber.org]----ooO--(_)--Ooo--

RE: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 11:13 PM
> To: Russell King - ARM Linux
> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early
> init testing
> 
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> > On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> >
> > > --- a/arch/arm/include/asm/smp_plat.h
> > > +++ b/arch/arm/include/asm/smp_plat.h
> > > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
> > >  #define UP(instr...)	_str(instr)
> > >  #endif
> > >
> > > +static inline int smp_on_up(void)
> > > +{
> > > +#ifdef CONFIG_SMP_ON_UP
> > > +	int smp_on_up;
> > > +
> > > +	asm(							\
> > > +		SMP(mov	%0, #0)					\
> > > +		UP(mov	%0, #1)					\
> > > +		: "=r" (smp_on_up));
> > > +
> > > +	return smp_on_up;
> > > +#else
> > > +	return 0;
> > > +#endif
> >
> > I think this is the wrong approach - rather than a function which tells
> us
> > just if we are a SMP kernel running on UP, why not something which
> returns
> > whether we're running on SMP and use that to eliminate some of these
> ifdefs?
> 
> Sure. Will has something like this in his patches:
> 
> static inline int cpu_is_part_of_mp_system(void)
> {
> 	u32 mpidr;
> 	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> 	return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> }

I guess this register is only available on MP Core extensions.

Regards,
Santosh

[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 11:13 PM
> To: Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early
> init testing
> 
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
> > On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
> >
> > > --- a/arch/arm/include/asm/smp_plat.h
> > > +++ b/arch/arm/include/asm/smp_plat.h
> > > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
> > >  #define UP(instr...)	_str(instr)
> > >  #endif
> > >
> > > +static inline int smp_on_up(void)
> > > +{
> > > +#ifdef CONFIG_SMP_ON_UP
> > > +	int smp_on_up;
> > > +
> > > +	asm(							\
> > > +		SMP(mov	%0, #0)					\
> > > +		UP(mov	%0, #1)					\
> > > +		: "=r" (smp_on_up));
> > > +
> > > +	return smp_on_up;
> > > +#else
> > > +	return 0;
> > > +#endif
> >
> > I think this is the wrong approach - rather than a function which tells
> us
> > just if we are a SMP kernel running on UP, why not something which
> returns
> > whether we're running on SMP and use that to eliminate some of these
> ifdefs?
> 
> Sure. Will has something like this in his patches:
> 
> static inline int cpu_is_part_of_mp_system(void)
> {
> 	u32 mpidr;
> 	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
> 	return (mpidr >> 31) ? !(mpidr >> 30) : 0;
> }

I guess this register is only available on MP Core extensions.

Regards,
Santosh

Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Bryan Wu]

Tony,

I tried your latest branch: devel-smp-on-unicore, kernel boots up but
got lots of WARN_ON fired:

---
------------[ cut here ]------------
[    1.149719] WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
[    1.149780] Modules linked in:
[    1.149841] [<c01b34c8>] (unwind_backtrace+0x0/0xe4) from
[<c01e939c>] (warn_slowpath_common+0x4c/0x64)
[    1.149902] [<c01e939c>] (warn_slowpath_common+0x4c/0x64) from
[<c01e93cc>] (warn_slowpath_null+0x18/0x1c)
[    1.149993] [<c01e93cc>] (warn_slowpath_null+0x18/0x1c) from
[<c0274730>] (pcpu_alloc+0x2fc/0x888)
[    1.150085] [<c0274730>] (pcpu_alloc+0x2fc/0x888) from [<c0279578>]
(sget+0x198/0x43c)
[    1.150146] [<c0279578>] (sget+0x198/0x43c) from [<c0279adc>]
(get_sb_ns+0x20/0x90)
[    1.150238] [<c0279adc>] (get_sb_ns+0x20/0x90) from [<c02791a4>]
(vfs_kern_mount+0x9c/0x18c)
[    1.150299] [<c02791a4>] (vfs_kern_mount+0x9c/0x18c) from
[<c0022280>] (init_mqueue_fs+0x68/0xc8)
[    1.150390] [<c0022280>] (init_mqueue_fs+0x68/0xc8) from
[<c01ac5d0>] (do_one_initcall+0xcc/0x1a4)
[    1.150451] [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4) from
[<c0008760>] (kernel_init+0x148/0x210)
[    1.150543] [<c0008760>] (kernel_init+0x148/0x210) from
[<c01adcf8>] (kernel_thread_exit+0x0/0x8)
[    1.150604] ---[ end trace 1b75b31a2719ed74 ]---
---

It looks like we still missed to set some flag for chuck.

-Bryan

On Fri, Sep 3, 2010 at 8:09 PM, Shilimkar, Santosh
<santosh.shilimkar@ti.com> wrote:
>
>
>> -----Original Message-----
>> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
>> owner@vger.kernel.org] On Behalf Of Tony Lindgren
>> Sent: Thursday, September 02, 2010 11:13 PM
>> To: Russell King - ARM Linux
>> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> Bryan Wu; Will Deacon
>> Subject: Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early
>> init testing
>>
>> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
>> > On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
>> >
>> > > --- a/arch/arm/include/asm/smp_plat.h
>> > > +++ b/arch/arm/include/asm/smp_plat.h
>> > > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
>> > >  #define UP(instr...)     _str(instr)
>> > >  #endif
>> > >
>> > > +static inline int smp_on_up(void)
>> > > +{
>> > > +#ifdef CONFIG_SMP_ON_UP
>> > > + int smp_on_up;
>> > > +
>> > > + asm(                                                    \
>> > > +         SMP(mov %0, #0)                                 \
>> > > +         UP(mov  %0, #1)                                 \
>> > > +         : "=r" (smp_on_up));
>> > > +
>> > > + return smp_on_up;
>> > > +#else
>> > > + return 0;
>> > > +#endif
>> >
>> > I think this is the wrong approach - rather than a function which tells
>> us
>> > just if we are a SMP kernel running on UP, why not something which
>> returns
>> > whether we're running on SMP and use that to eliminate some of these
>> ifdefs?
>>
>> Sure. Will has something like this in his patches:
>>
>> static inline int cpu_is_part_of_mp_system(void)
>> {
>>       u32 mpidr;
>>       asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
>>       return (mpidr >> 31) ? !(mpidr >> 30) : 0;
>> }
>
> I guess this register is only available on MP Core extensions.
>
> Regards,
> Santosh
>
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[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Bryan Wu]

Tony,

I tried your latest branch: devel-smp-on-unicore, kernel boots up but
got lots of WARN_ON fired:

---
------------[ cut here ]------------
[    1.149719] WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
[    1.149780] Modules linked in:
[    1.149841] [<c01b34c8>] (unwind_backtrace+0x0/0xe4) from
[<c01e939c>] (warn_slowpath_common+0x4c/0x64)
[    1.149902] [<c01e939c>] (warn_slowpath_common+0x4c/0x64) from
[<c01e93cc>] (warn_slowpath_null+0x18/0x1c)
[    1.149993] [<c01e93cc>] (warn_slowpath_null+0x18/0x1c) from
[<c0274730>] (pcpu_alloc+0x2fc/0x888)
[    1.150085] [<c0274730>] (pcpu_alloc+0x2fc/0x888) from [<c0279578>]
(sget+0x198/0x43c)
[    1.150146] [<c0279578>] (sget+0x198/0x43c) from [<c0279adc>]
(get_sb_ns+0x20/0x90)
[    1.150238] [<c0279adc>] (get_sb_ns+0x20/0x90) from [<c02791a4>]
(vfs_kern_mount+0x9c/0x18c)
[    1.150299] [<c02791a4>] (vfs_kern_mount+0x9c/0x18c) from
[<c0022280>] (init_mqueue_fs+0x68/0xc8)
[    1.150390] [<c0022280>] (init_mqueue_fs+0x68/0xc8) from
[<c01ac5d0>] (do_one_initcall+0xcc/0x1a4)
[    1.150451] [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4) from
[<c0008760>] (kernel_init+0x148/0x210)
[    1.150543] [<c0008760>] (kernel_init+0x148/0x210) from
[<c01adcf8>] (kernel_thread_exit+0x0/0x8)
[    1.150604] ---[ end trace 1b75b31a2719ed74 ]---
---

It looks like we still missed to set some flag for chuck.

-Bryan

On Fri, Sep 3, 2010 at 8:09 PM, Shilimkar, Santosh
<santosh.shilimkar@ti.com> wrote:
>
>
>> -----Original Message-----
>> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
>> owner at vger.kernel.org] On Behalf Of Tony Lindgren
>> Sent: Thursday, September 02, 2010 11:13 PM
>> To: Russell King - ARM Linux
>> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
>> Bryan Wu; Will Deacon
>> Subject: Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early
>> init testing
>>
>> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:00]:
>> > On Thu, Sep 02, 2010 at 09:18:47AM -0700, Tony Lindgren wrote:
>> >
>> > > --- a/arch/arm/include/asm/smp_plat.h
>> > > +++ b/arch/arm/include/asm/smp_plat.h
>> > > @@ -39,4 +39,20 @@ static inline int cache_ops_need_broadcast(void)
>> > > ?#define UP(instr...) ? ? _str(instr)
>> > > ?#endif
>> > >
>> > > +static inline int smp_on_up(void)
>> > > +{
>> > > +#ifdef CONFIG_SMP_ON_UP
>> > > + int smp_on_up;
>> > > +
>> > > + asm( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> > > + ? ? ? ? SMP(mov %0, #0) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> > > + ? ? ? ? UP(mov ?%0, #1) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> > > + ? ? ? ? : "=r" (smp_on_up));
>> > > +
>> > > + return smp_on_up;
>> > > +#else
>> > > + return 0;
>> > > +#endif
>> >
>> > I think this is the wrong approach - rather than a function which tells
>> us
>> > just if we are a SMP kernel running on UP, why not something which
>> returns
>> > whether we're running on SMP and use that to eliminate some of these
>> ifdefs?
>>
>> Sure. Will has something like this in his patches:
>>
>> static inline int cpu_is_part_of_mp_system(void)
>> {
>> ? ? ? u32 mpidr;
>> ? ? ? asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr));
>> ? ? ? return (mpidr >> 31) ? !(mpidr >> 30) : 0;
>> }
>
> I guess this register is only available on MP Core extensions.
>
> Regards,
> Santosh
>

Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 1864 bytes --]

* Bryan Wu <bryan.wu@canonical.com> [100906 03:09]:
> Tony,
> 
> I tried your latest branch: devel-smp-on-unicore, kernel boots up but
> got lots of WARN_ON fired:
> 
> ---
> ------------[ cut here ]------------
> [    1.149719] WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
> [    1.149780] Modules linked in:
> [    1.149841] [<c01b34c8>] (unwind_backtrace+0x0/0xe4) from
> [<c01e939c>] (warn_slowpath_common+0x4c/0x64)
> [    1.149902] [<c01e939c>] (warn_slowpath_common+0x4c/0x64) from
> [<c01e93cc>] (warn_slowpath_null+0x18/0x1c)
> [    1.149993] [<c01e93cc>] (warn_slowpath_null+0x18/0x1c) from
> [<c0274730>] (pcpu_alloc+0x2fc/0x888)
> [    1.150085] [<c0274730>] (pcpu_alloc+0x2fc/0x888) from [<c0279578>]
> (sget+0x198/0x43c)
> [    1.150146] [<c0279578>] (sget+0x198/0x43c) from [<c0279adc>]
> (get_sb_ns+0x20/0x90)
> [    1.150238] [<c0279adc>] (get_sb_ns+0x20/0x90) from [<c02791a4>]
> (vfs_kern_mount+0x9c/0x18c)
> [    1.150299] [<c02791a4>] (vfs_kern_mount+0x9c/0x18c) from
> [<c0022280>] (init_mqueue_fs+0x68/0xc8)
> [    1.150390] [<c0022280>] (init_mqueue_fs+0x68/0xc8) from
> [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4)
> [    1.150451] [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4) from
> [<c0008760>] (kernel_init+0x148/0x210)
> [    1.150543] [<c0008760>] (kernel_init+0x148/0x210) from
> [<c01adcf8>] (kernel_thread_exit+0x0/0x8)
> [    1.150604] ---[ end trace 1b75b31a2719ed74 ]---
> ---
> 
> It looks like we still missed to set some flag for chuck.

Yeah I think there's some .config option that needs to be handled
properly to fix this.

Looks like the following .config does not produce it, but fails
to boot to shell on omap2. Doing yes "" | make oldconfig
and enabling CONFIG_SMP etc on makes the warning to happen.

Also, disabling CONFIG_USB_MUSB_HDRC is needed as that driver
is still broken for multi-omap..

Regards,

Tony

[-- Attachment #2: config-tony --]
[-- Type: text/plain, Size: 55970 bytes --]

#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.36-rc3
# Tue Sep  7 18:42:21 2010
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_LOCKBREAK=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y

#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_LZO=y
# CONFIG_KERNEL_GZIP is not set
CONFIG_KERNEL_LZMA=y
# CONFIG_KERNEL_LZO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_RCU_FAST_NO_HZ is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_PERF_COUNTERS is not set
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
# CONFIG_INLINE_SPIN_UNLOCK is not set
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
# CONFIG_INLINE_READ_UNLOCK is not set
# CONFIG_INLINE_READ_UNLOCK_BH is not set
# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
# CONFIG_INLINE_WRITE_UNLOCK is not set
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
CONFIG_FREEZER=y

#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_BCMRING is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CNS3XXX is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_NUC93X is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5P6440 is not set
# CONFIG_ARCH_S5P6442 is not set
# CONFIG_ARCH_S5PC100 is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_S5PV310 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_DAVINCI is not set
CONFIG_ARCH_OMAP=y
# CONFIG_PLAT_SPEAR is not set

#
# TI OMAP Common Features
#
CONFIG_ARCH_OMAP_OTG=y
# CONFIG_ARCH_OMAP1 is not set
CONFIG_ARCH_OMAP2PLUS=y

#
# OMAP Feature Selections
#
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_OMAP_MUX=y
# CONFIG_OMAP_MUX_DEBUG is not set
CONFIG_OMAP_MUX_WARNINGS=y
CONFIG_OMAP_MCBSP=y
CONFIG_OMAP_MBOX_FWK=m
CONFIG_OMAP_MBOX_KFIFO_SIZE=256
# CONFIG_OMAP_MPU_TIMER is not set
CONFIG_OMAP_32K_TIMER=y
# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
CONFIG_OMAP_32K_TIMER_HZ=128
CONFIG_OMAP_DM_TIMER=y
# CONFIG_OMAP_PM_NONE is not set
CONFIG_OMAP_PM_NOOP=y
CONFIG_MACH_OMAP_GENERIC=y

#
# TI OMAP2/3/4 Specific Features
#
CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
CONFIG_ARCH_OMAP2=y
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y

#
# OMAP Core Type
#
CONFIG_ARCH_OMAP2420=y
CONFIG_ARCH_OMAP2430=y
CONFIG_ARCH_OMAP3430=y
CONFIG_OMAP_PACKAGE_ZAC=y
CONFIG_OMAP_PACKAGE_CBB=y
CONFIG_OMAP_PACKAGE_CBP=y

#
# OMAP Board Type
#
CONFIG_MACH_OMAP2_TUSB6010=y
# CONFIG_MACH_OMAP_H4 is not set
# CONFIG_MACH_OMAP_APOLLON is not set
CONFIG_MACH_OMAP_2430SDP=y
# CONFIG_MACH_OMAP3_BEAGLE is not set
# CONFIG_MACH_DEVKIT8000 is not set
# CONFIG_MACH_OMAP_LDP is not set
CONFIG_MACH_OVERO=y
# CONFIG_MACH_OMAP3EVM is not set
# CONFIG_MACH_OMAP3517EVM is not set
# CONFIG_MACH_OMAP3_PANDORA is not set
# CONFIG_MACH_OMAP3_TOUCHBOOK is not set
# CONFIG_MACH_OMAP_3430SDP is not set
CONFIG_MACH_NOKIA_N800=y
CONFIG_MACH_NOKIA_N810=y
CONFIG_MACH_NOKIA_N810_WIMAX=y
CONFIG_MACH_NOKIA_N8X0=y
CONFIG_MACH_NOKIA_RX51=y
# CONFIG_MACH_OMAP_ZOOM2 is not set
CONFIG_MACH_OMAP_ZOOM3=y
# CONFIG_MACH_CM_T35 is not set
# CONFIG_MACH_IGEP0020 is not set
# CONFIG_MACH_SBC3530 is not set
# CONFIG_MACH_OMAP_3630SDP is not set
CONFIG_MACH_OMAP_4430SDP=y
CONFIG_MACH_OMAP4_PANDA=y
# CONFIG_OMAP3_EMU is not set
# CONFIG_OMAP3_SDRC_AC_TIMING is not set

#
# Processor Type
#
CONFIG_CPU_V6=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v6=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV6=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V6=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V6=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y

#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_DMA_CACHE_RWFO=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_CACHE_L2X0=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
# CONFIG_PL310_ERRATA_588369 is not set
# CONFIG_ARM_ERRATA_720789 is not set
CONFIG_ARM_GIC=y
CONFIG_COMMON_CLKDEV=y

#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set

#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_HAVE_ARM_SCU=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_NR_CPUS=4
CONFIG_HOTPLUG_CPU=y
# CONFIG_LOCAL_TIMERS is not set
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_HZ=128
# CONFIG_THUMB2_KERNEL is not set
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_HIGHMEM is not set
# CONFIG_SPARSE_IRQ is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_FORCE_MAX_ZONEORDER=11
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_CC_STACKPROTECTOR is not set
# CONFIG_DEPRECATED_PARAM_STRUCT is not set

#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="init=/sbin/preinit root=/dev/mmcblk0p1 rootwait console=tty0 console=ttyS2,115200n8 omapfb.vram=0:2M,1:2M,2:2M mtdoops.mtddev=2 nosplash"
# CONFIG_CMDLINE_FORCE is not set
# CONFIG_XIP_KERNEL is not set
CONFIG_KEXEC=y
CONFIG_ATAGS_PROC=y
# CONFIG_AUTO_ZRELADDR is not set
CONFIG_ZRELADDR=0x80008000

#
# CPU Power Management
#
# CONFIG_CPU_FREQ is not set
# CONFIG_CPU_IDLE is not set

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y

#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_MISC=y

#
# Power management options
#
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
# CONFIG_PM_VERBOSE is not set
CONFIG_CAN_PM_TRACE=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_PM_SLEEP=y
# CONFIG_PM_SLEEP_ADVANCED_DEBUG is not set
CONFIG_SUSPEND_NVS=y
CONFIG_SUSPEND=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_SUSPEND_FREEZER=y
# CONFIG_APM_EMULATION is not set
CONFIG_PM_RUNTIME=y
CONFIG_PM_OPS=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_SUB_POLICY is not set
CONFIG_XFRM_MIGRATE=y
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=m
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_INET_LRO=y
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
CONFIG_PHONET=y
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
CONFIG_RPS=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
CONFIG_BT=m
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m

#
# Bluetooth device drivers
#
# CONFIG_BT_HCIBTUSB is not set
# CONFIG_BT_HCIBTSDIO is not set
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_BT_MRVL is not set
# CONFIG_AF_RXRPC is not set
CONFIG_WIRELESS=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_REG_DEBUG is not set
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
# CONFIG_CFG80211_INTERNAL_REGDB is not set
CONFIG_CFG80211_WEXT=y
CONFIG_WIRELESS_EXT_SYSFS=y
# CONFIG_LIB80211 is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_PID=y
# CONFIG_MAC80211_RC_MINSTREL is not set
CONFIG_MAC80211_RC_DEFAULT_PID=y
CONFIG_MAC80211_RC_DEFAULT="pid"
# CONFIG_MAC80211_MESH is not set
# CONFIG_MAC80211_LEDS is not set
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
# CONFIG_WIMAX is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=m
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_TESTS is not set
CONFIG_MTD_CONCAT=m
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set

#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
CONFIG_SM_FTL=m
CONFIG_MTD_OOPS=m

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
CONFIG_MTD_CFI_INTELEXT=m
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=m
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_M25P80 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_NAND_ECC=m
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND is not set
CONFIG_MTD_ONENAND=m
# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
# CONFIG_MTD_ONENAND_GENERIC is not set
CONFIG_MTD_ONENAND_OMAP2=m
# CONFIG_MTD_ONENAND_OTP is not set
# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
# CONFIG_MTD_ONENAND_SIM is not set

#
# LPDDR flash memory drivers
#
# CONFIG_MTD_LPDDR is not set

#
# UBI - Unsorted block images
#
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_RESERVE=1
# CONFIG_MTD_UBI_GLUEBI is not set

#
# UBI debugging options
#
# CONFIG_MTD_UBI_DEBUG is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m

#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MG_DISK is not set
CONFIG_MISC_DEVICES=y
# CONFIG_AD525X_DPOT is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1780 is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_BMP085 is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IWMC3200TOP is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=m
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=m
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_SCSI_WAIT_SCAN=m

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
CONFIG_MACVLAN=m
# CONFIG_MACVTAP is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=m
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
CONFIG_SMC91X=y
# CONFIG_TI_DAVINCI_EMAC is not set
# CONFIG_DM9000 is not set
# CONFIG_ENC28J60 is not set
# CONFIG_ETHOC is not set
# CONFIG_SMC911X is not set
# CONFIG_SMSC911X is not set
# CONFIG_DNET is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
# CONFIG_KS8851 is not set
# CONFIG_KS8851_MLL is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WLAN=y
# CONFIG_LIBERTAS_THINFIRM is not set
# CONFIG_AT76C50X_USB is not set
# CONFIG_USB_ZD1201 is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_RTL8187 is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_ATH_COMMON is not set
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
# CONFIG_HOSTAP is not set
# CONFIG_IWM is not set
# CONFIG_LIBERTAS is not set
# CONFIG_P54_COMMON is not set
# CONFIG_RT2X00 is not set
CONFIG_WL12XX=m
CONFIG_WL1251=m
CONFIG_WL1251_SPI=m
# CONFIG_WL1251_SDIO is not set
# CONFIG_WL1271 is not set
# CONFIG_ZD1211RW is not set

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#

#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
CONFIG_USB_HSO=m
# CONFIG_USB_CDC_PHONET is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WAN is not set

#
# CAIF transport drivers
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=m
CONFIG_INPUT_POLLDEV=m
# CONFIG_INPUT_SPARSEKMAP is not set

#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=m
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_OMAP is not set
CONFIG_KEYBOARD_TWL4030=y
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_QT602240 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_W90X900 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
CONFIG_INPUT_TWL4030_PWRBUTTON=m
CONFIG_INPUT_TWL4030_VIBRA=m
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_ADXL34X is not set

#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set

#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX3107 is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=m
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
CONFIG_HW_RANDOM_OMAP=m
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_RAMOOPS is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_OMAP=y
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_OMAP24XX=y
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set

#
# SPI Protocol Masters
#
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set

#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y

#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set

#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_SX150X is not set
CONFIG_GPIO_TWL4030=y
# CONFIG_GPIO_ADP5588 is not set

#
# PCI GPIO expanders:
#

#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_GPIO_MC33880 is not set

#
# AC97 GPIO expanders:
#

#
# MODULbus GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=m
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_LIS3_SPI is not set
CONFIG_SENSORS_LIS3_I2C=m
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_OMAP_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
CONFIG_MFD_SUPPORT=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
CONFIG_MENELAUS=y
CONFIG_TWL4030_CORE=y
CONFIG_TWL4030_POWER=y
CONFIG_TWL4030_CODEC=y
# CONFIG_TWL6030_PWM is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_TC35892 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB8500_CORE is not set
# CONFIG_MFD_TPS6586X is not set
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_DUMMY is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
CONFIG_REGULATOR_TWL4030=y
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_MEDIA_SUPPORT=m

#
# Multimedia core support
#
CONFIG_VIDEO_DEV=m
CONFIG_VIDEO_V4L2_COMMON=m
# CONFIG_VIDEO_ALLOW_V4L1 is not set
# CONFIG_VIDEO_V4L1_COMPAT is not set
# CONFIG_DVB_CORE is not set
CONFIG_VIDEO_MEDIA=m

#
# Multimedia drivers
#
CONFIG_IR_CORE=m
CONFIG_VIDEO_IR=m
CONFIG_LIRC=m
# CONFIG_RC_MAP is not set
# CONFIG_IR_NEC_DECODER is not set
# CONFIG_IR_RC5_DECODER is not set
# CONFIG_IR_RC6_DECODER is not set
# CONFIG_IR_JVC_DECODER is not set
# CONFIG_IR_SONY_DECODER is not set
CONFIG_IR_LIRC_CODEC=m
# CONFIG_IR_IMON is not set
# CONFIG_IR_MCEUSB is not set
# CONFIG_IR_STREAMZAP is not set
# CONFIG_MEDIA_ATTACH is not set
CONFIG_MEDIA_TUNER=m
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC5000=m
CONFIG_MEDIA_TUNER_MC44S803=m
CONFIG_VIDEO_V4L2=m
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_DMA_CONTIG=m
CONFIG_VIDEO_CAPTURE_DRIVERS=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
# CONFIG_VIDEO_IR_I2C is not set

#
# Encoders/decoders and other helper chips
#

#
# Audio decoders
#
# CONFIG_VIDEO_TVAUDIO is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TDA9875 is not set
# CONFIG_VIDEO_TEA6415C is not set
# CONFIG_VIDEO_TEA6420 is not set
# CONFIG_VIDEO_MSP3400 is not set
# CONFIG_VIDEO_CS5345 is not set
# CONFIG_VIDEO_CS53L32A is not set
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_TLV320AIC23B is not set
# CONFIG_VIDEO_WM8775 is not set
# CONFIG_VIDEO_WM8739 is not set
# CONFIG_VIDEO_VP27SMPX is not set

#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_MT9V011 is not set
# CONFIG_VIDEO_TCM825X is not set
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
# CONFIG_VIDEO_SAA717X is not set
# CONFIG_VIDEO_SAA7191 is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
# CONFIG_VIDEO_CX25840 is not set

#
# MPEG video encoders
#
# CONFIG_VIDEO_CX2341X is not set

#
# Video encoders
#
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_AK881X is not set

#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
# CONFIG_VIDEO_UPD64083 is not set
# CONFIG_VIDEO_VPFE_CAPTURE is not set
CONFIG_VIDEO_OMAP2_VOUT=m
# CONFIG_VIDEO_SAA5246A is not set
# CONFIG_VIDEO_SAA5249 is not set
# CONFIG_SOC_CAMERA is not set
# CONFIG_VIDEO_OMAP2 is not set
# CONFIG_V4L_USB_DRIVERS is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_RADIO_ADAPTERS is not set
# CONFIG_DAB is not set

#
# Graphics support
#
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
CONFIG_FB_CFB_FILLRECT=m
CONFIG_FB_CFB_COPYAREA=m
CONFIG_FB_CFB_IMAGEBLIT=m
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_TMIO is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
CONFIG_OMAP2_VRAM=y
CONFIG_OMAP2_VRFB=y
CONFIG_OMAP2_DSS=m
CONFIG_OMAP2_VRAM_SIZE=2
# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set
# CONFIG_OMAP2_DSS_DPI is not set
# CONFIG_OMAP2_DSS_RFBI is not set
# CONFIG_OMAP2_DSS_VENC is not set
CONFIG_OMAP2_DSS_SDI=y
# CONFIG_OMAP2_DSS_DSI is not set
# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
CONFIG_FB_OMAP2=m
# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set
CONFIG_FB_OMAP2_NUM_FBS=3

#
# OMAP2/3 Display Device Drivers
#
# CONFIG_PANEL_GENERIC is not set
# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set
# CONFIG_PANEL_TOPPOLY_TDO35S is not set
# CONFIG_PANEL_TPO_TD043MTEA1 is not set
CONFIG_PANEL_ACX565AKM=m
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
# CONFIG_BACKLIGHT_ADP8860 is not set

#
# Display device support
#
CONFIG_DISPLAY_SUPPORT=y

#
# Display hardware drivers
#

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_LOGO is not set
CONFIG_SOUND=y
# CONFIG_SOUND_OSS_CORE is not set
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_JACK=y
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_RAWMIDI_SEQ is not set
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_OMAP_SOC=y
CONFIG_SND_OMAP_SOC_MCBSP=y
# CONFIG_SND_OMAP_SOC_N810 is not set
CONFIG_SND_OMAP_SOC_RX51=y
# CONFIG_SND_OMAP_SOC_OVERO is not set
# CONFIG_SND_OMAP_SOC_SDP4430 is not set
CONFIG_SND_SOC_I2C_AND_SPI=y
# CONFIG_SND_SOC_ALL_CODECS is not set
CONFIG_SND_SOC_TLV320AIC3X=y
# CONFIG_SOUND_PRIME is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_HID=m
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_SUSPEND is not set
CONFIG_USB_OTG_WHITELIST=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MON=m
# CONFIG_USB_WUSB is not set
# CONFIG_USB_WUSB_CBAF is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HWA_HCD is not set
# CONFIG_USB_MUSB_HDRC is not set

#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=m
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
CONFIG_USB_LIBUSUAL=y

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set

#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
CONFIG_USB_GADGET=m
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_SELECTED=y
CONFIG_USB_GADGET_OMAP=y
CONFIG_USB_OMAP=m
# CONFIG_USB_GADGET_R8A66597 is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_GADGET_DUALSPEED is not set
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FUNCTIONFS is not set
CONFIG_USB_FILE_STORAGE=m
# CONFIG_USB_FILE_STORAGE_TEST is not set
# CONFIG_USB_MASS_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
CONFIG_USB_G_NOKIA=m
# CONFIG_USB_G_MULTI is not set
# CONFIG_USB_G_HID is not set
# CONFIG_USB_G_DBGP is not set
# CONFIG_USB_G_WEBCAM is not set

#
# OTG and related infrastructure
#
CONFIG_USB_OTG_UTILS=y
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_ISP1301_OMAP is not set
# CONFIG_USB_ULPI is not set
CONFIG_TWL4030_USB=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set

#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_OMAP is not set
CONFIG_MMC_OMAP_HS=y
# CONFIG_MMC_SPI is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m

#
# LED drivers
#
# CONFIG_LEDS_PCA9532 is not set
# CONFIG_LEDS_GPIO is not set
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_TRIGGERS=y

#
# LED Triggers
#
# CONFIG_LEDS_TRIGGER_TIMER is not set
# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
CONFIG_LEDS_TRIGGER_GPIO=m
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set

#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
# CONFIG_RTC_DEBUG is not set

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_TWL92330 is not set
CONFIG_RTC_DRV_TWL4030=m
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_DS3234 is not set
# CONFIG_RTC_DRV_PCF2123 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set

#
# on-CPU RTC drivers
#
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
CONFIG_STAGING=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
# CONFIG_VIDEO_TM6000 is not set
# CONFIG_USB_IP_COMMON is not set
# CONFIG_W35UND is not set
# CONFIG_PRISM2_USB is not set
# CONFIG_ECHO is not set
# CONFIG_OTUS is not set
# CONFIG_RT2870 is not set
# CONFIG_COMEDI is not set
# CONFIG_ASUS_OLED is not set
# CONFIG_TRANZPORT is not set
# CONFIG_POHMELFS is not set
# CONFIG_LINE6_USB is not set
# CONFIG_SPECTRA is not set
# CONFIG_VT6656 is not set
# CONFIG_FB_UDL is not set
CONFIG_IIO=m
# CONFIG_IIO_RING_BUFFER is not set
# CONFIG_IIO_TRIGGER is not set

#
# Accelerometers
#
# CONFIG_ADIS16209 is not set
# CONFIG_ADIS16220 is not set
# CONFIG_ADIS16240 is not set
# CONFIG_KXSD9 is not set
# CONFIG_LIS3L02DQ is not set

#
# Analog to digital convertors
#
# CONFIG_MAX1363 is not set

#
# Digital gyroscope sensors
#
# CONFIG_ADIS16260 is not set

#
# Inertial measurement units
#
# CONFIG_ADIS16300 is not set
# CONFIG_ADIS16350 is not set
# CONFIG_ADIS16400 is not set

#
# Light sensors
#
CONFIG_SENSORS_TSL2563=m

#
# Magnetometer sensors
#
# CONFIG_SENSORS_HMC5843 is not set

#
# Triggers - standalone
#
# CONFIG_ZRAM is not set
# CONFIG_BATMAN_ADV is not set
# CONFIG_FB_SM7XX is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# CONFIG_ST_BT is not set
# CONFIG_ADIS16255 is not set
# CONFIG_LIRC_STAGING is not set
# CONFIG_EASYCAP is not set
CONFIG_TIDSPBRIDGE=m
CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE=0x600000
# CONFIG_TIDSPBRIDGE_DEBUG is not set
CONFIG_TIDSPBRIDGE_RECOVERY=y
# CONFIG_TIDSPBRIDGE_CACHE_LINE_CHECK is not set
CONFIG_TIDSPBRIDGE_WDT3=y
CONFIG_TIDSPBRIDGE_WDT_TIMEOUT=5
# CONFIG_TIDSPBRIDGE_NTFY_PWRERR is not set
CONFIG_TIDSPBRIDGE_BACKTRACE=y

#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_NILFS2_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=m
# CONFIG_CUSE is not set
CONFIG_GENERIC_ACL=y

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=m
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_UBIFS_FS=m
# CONFIG_UBIFS_FS_XATTR is not set
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
# CONFIG_UBIFS_FS_DEBUG is not set
# CONFIG_LOGFS is not set
CONFIG_CRAMFS=y
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
# CONFIG_SYSV68_PARTITION is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set

#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_LOCKUP_DETECTOR is not set
# CONFIG_HARDLOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
CONFIG_SCHED_DEBUG=y
CONFIG_SCHEDSTATS=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
CONFIG_DEBUG_SLAB=y
# CONFIG_DEBUG_SLAB_LEAK is not set
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_PROVE_RCU=y
# CONFIG_PROVE_RCU_REPEATEDLY is not set
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_TRACE_IRQFLAGS=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARM_UNWIND=y
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_ERRORS is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_LL is not set
# CONFIG_EARLY_PRINTK is not set
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_OC_ETM is not set

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP=y
CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MANAGER_TESTS=y
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_NULL=m
# CONFIG_CRYPTO_PCRYPT is not set
CONFIG_CRYPTO_WORKQUEUE=y
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_SEQIV=m

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=m
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=m

#
# Hash modes
#
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m

#
# Digest
#
CONFIG_CRYPTO_CRC32C=m
CONFIG_CRYPTO_GHASH=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_ZLIB=y
CONFIG_CRYPTO_LZO=m

#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_OMAP_SHAM=m
# CONFIG_BINARY_PRINTF is not set

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
# CONFIG_CRC_T10DIF is not set
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
CONFIG_CRC7=m
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=m
CONFIG_LZO_DECOMPRESS=m
CONFIG_DECOMPRESS_GZIP=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y

[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

* Bryan Wu <bryan.wu@canonical.com> [100906 03:09]:
> Tony,
> 
> I tried your latest branch: devel-smp-on-unicore, kernel boots up but
> got lots of WARN_ON fired:
> 
> ---
> ------------[ cut here ]------------
> [    1.149719] WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
> [    1.149780] Modules linked in:
> [    1.149841] [<c01b34c8>] (unwind_backtrace+0x0/0xe4) from
> [<c01e939c>] (warn_slowpath_common+0x4c/0x64)
> [    1.149902] [<c01e939c>] (warn_slowpath_common+0x4c/0x64) from
> [<c01e93cc>] (warn_slowpath_null+0x18/0x1c)
> [    1.149993] [<c01e93cc>] (warn_slowpath_null+0x18/0x1c) from
> [<c0274730>] (pcpu_alloc+0x2fc/0x888)
> [    1.150085] [<c0274730>] (pcpu_alloc+0x2fc/0x888) from [<c0279578>]
> (sget+0x198/0x43c)
> [    1.150146] [<c0279578>] (sget+0x198/0x43c) from [<c0279adc>]
> (get_sb_ns+0x20/0x90)
> [    1.150238] [<c0279adc>] (get_sb_ns+0x20/0x90) from [<c02791a4>]
> (vfs_kern_mount+0x9c/0x18c)
> [    1.150299] [<c02791a4>] (vfs_kern_mount+0x9c/0x18c) from
> [<c0022280>] (init_mqueue_fs+0x68/0xc8)
> [    1.150390] [<c0022280>] (init_mqueue_fs+0x68/0xc8) from
> [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4)
> [    1.150451] [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4) from
> [<c0008760>] (kernel_init+0x148/0x210)
> [    1.150543] [<c0008760>] (kernel_init+0x148/0x210) from
> [<c01adcf8>] (kernel_thread_exit+0x0/0x8)
> [    1.150604] ---[ end trace 1b75b31a2719ed74 ]---
> ---
> 
> It looks like we still missed to set some flag for chuck.

Yeah I think there's some .config option that needs to be handled
properly to fix this.

Looks like the following .config does not produce it, but fails
to boot to shell on omap2. Doing yes "" | make oldconfig
and enabling CONFIG_SMP etc on makes the warning to happen.

Also, disabling CONFIG_USB_MUSB_HDRC is needed as that driver
is still broken for multi-omap..

Regards,

Tony
-------------- next part --------------
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.36-rc3
# Tue Sep  7 18:42:21 2010
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_LOCKBREAK=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y

#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_LZO=y
# CONFIG_KERNEL_GZIP is not set
CONFIG_KERNEL_LZMA=y
# CONFIG_KERNEL_LZO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_RCU_FAST_NO_HZ is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_PERF_COUNTERS is not set
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
# CONFIG_INLINE_SPIN_UNLOCK is not set
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
# CONFIG_INLINE_READ_UNLOCK is not set
# CONFIG_INLINE_READ_UNLOCK_BH is not set
# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
# CONFIG_INLINE_WRITE_UNLOCK is not set
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
CONFIG_FREEZER=y

#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_BCMRING is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CNS3XXX is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_NUC93X is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5P6440 is not set
# CONFIG_ARCH_S5P6442 is not set
# CONFIG_ARCH_S5PC100 is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_S5PV310 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_DAVINCI is not set
CONFIG_ARCH_OMAP=y
# CONFIG_PLAT_SPEAR is not set

#
# TI OMAP Common Features
#
CONFIG_ARCH_OMAP_OTG=y
# CONFIG_ARCH_OMAP1 is not set
CONFIG_ARCH_OMAP2PLUS=y

#
# OMAP Feature Selections
#
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_OMAP_MUX=y
# CONFIG_OMAP_MUX_DEBUG is not set
CONFIG_OMAP_MUX_WARNINGS=y
CONFIG_OMAP_MCBSP=y
CONFIG_OMAP_MBOX_FWK=m
CONFIG_OMAP_MBOX_KFIFO_SIZE=256
# CONFIG_OMAP_MPU_TIMER is not set
CONFIG_OMAP_32K_TIMER=y
# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
CONFIG_OMAP_32K_TIMER_HZ=128
CONFIG_OMAP_DM_TIMER=y
# CONFIG_OMAP_PM_NONE is not set
CONFIG_OMAP_PM_NOOP=y
CONFIG_MACH_OMAP_GENERIC=y

#
# TI OMAP2/3/4 Specific Features
#
CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
CONFIG_ARCH_OMAP2=y
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y

#
# OMAP Core Type
#
CONFIG_ARCH_OMAP2420=y
CONFIG_ARCH_OMAP2430=y
CONFIG_ARCH_OMAP3430=y
CONFIG_OMAP_PACKAGE_ZAC=y
CONFIG_OMAP_PACKAGE_CBB=y
CONFIG_OMAP_PACKAGE_CBP=y

#
# OMAP Board Type
#
CONFIG_MACH_OMAP2_TUSB6010=y
# CONFIG_MACH_OMAP_H4 is not set
# CONFIG_MACH_OMAP_APOLLON is not set
CONFIG_MACH_OMAP_2430SDP=y
# CONFIG_MACH_OMAP3_BEAGLE is not set
# CONFIG_MACH_DEVKIT8000 is not set
# CONFIG_MACH_OMAP_LDP is not set
CONFIG_MACH_OVERO=y
# CONFIG_MACH_OMAP3EVM is not set
# CONFIG_MACH_OMAP3517EVM is not set
# CONFIG_MACH_OMAP3_PANDORA is not set
# CONFIG_MACH_OMAP3_TOUCHBOOK is not set
# CONFIG_MACH_OMAP_3430SDP is not set
CONFIG_MACH_NOKIA_N800=y
CONFIG_MACH_NOKIA_N810=y
CONFIG_MACH_NOKIA_N810_WIMAX=y
CONFIG_MACH_NOKIA_N8X0=y
CONFIG_MACH_NOKIA_RX51=y
# CONFIG_MACH_OMAP_ZOOM2 is not set
CONFIG_MACH_OMAP_ZOOM3=y
# CONFIG_MACH_CM_T35 is not set
# CONFIG_MACH_IGEP0020 is not set
# CONFIG_MACH_SBC3530 is not set
# CONFIG_MACH_OMAP_3630SDP is not set
CONFIG_MACH_OMAP_4430SDP=y
CONFIG_MACH_OMAP4_PANDA=y
# CONFIG_OMAP3_EMU is not set
# CONFIG_OMAP3_SDRC_AC_TIMING is not set

#
# Processor Type
#
CONFIG_CPU_V6=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v6=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV6=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V6=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V6=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y

#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_DMA_CACHE_RWFO=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_CACHE_L2X0=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
# CONFIG_PL310_ERRATA_588369 is not set
# CONFIG_ARM_ERRATA_720789 is not set
CONFIG_ARM_GIC=y
CONFIG_COMMON_CLKDEV=y

#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set

#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_HAVE_ARM_SCU=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_NR_CPUS=4
CONFIG_HOTPLUG_CPU=y
# CONFIG_LOCAL_TIMERS is not set
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_HZ=128
# CONFIG_THUMB2_KERNEL is not set
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_HIGHMEM is not set
# CONFIG_SPARSE_IRQ is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_FORCE_MAX_ZONEORDER=11
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_CC_STACKPROTECTOR is not set
# CONFIG_DEPRECATED_PARAM_STRUCT is not set

#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="init=/sbin/preinit root=/dev/mmcblk0p1 rootwait console=tty0 console=ttyS2,115200n8 omapfb.vram=0:2M,1:2M,2:2M mtdoops.mtddev=2 nosplash"
# CONFIG_CMDLINE_FORCE is not set
# CONFIG_XIP_KERNEL is not set
CONFIG_KEXEC=y
CONFIG_ATAGS_PROC=y
# CONFIG_AUTO_ZRELADDR is not set
CONFIG_ZRELADDR=0x80008000

#
# CPU Power Management
#
# CONFIG_CPU_FREQ is not set
# CONFIG_CPU_IDLE is not set

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y

#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_MISC=y

#
# Power management options
#
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
# CONFIG_PM_VERBOSE is not set
CONFIG_CAN_PM_TRACE=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_PM_SLEEP=y
# CONFIG_PM_SLEEP_ADVANCED_DEBUG is not set
CONFIG_SUSPEND_NVS=y
CONFIG_SUSPEND=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_SUSPEND_FREEZER=y
# CONFIG_APM_EMULATION is not set
CONFIG_PM_RUNTIME=y
CONFIG_PM_OPS=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_SUB_POLICY is not set
CONFIG_XFRM_MIGRATE=y
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=m
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_INET_LRO=y
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
CONFIG_PHONET=y
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
CONFIG_RPS=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
CONFIG_BT=m
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m

#
# Bluetooth device drivers
#
# CONFIG_BT_HCIBTUSB is not set
# CONFIG_BT_HCIBTSDIO is not set
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_BT_MRVL is not set
# CONFIG_AF_RXRPC is not set
CONFIG_WIRELESS=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_REG_DEBUG is not set
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
# CONFIG_CFG80211_INTERNAL_REGDB is not set
CONFIG_CFG80211_WEXT=y
CONFIG_WIRELESS_EXT_SYSFS=y
# CONFIG_LIB80211 is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_PID=y
# CONFIG_MAC80211_RC_MINSTREL is not set
CONFIG_MAC80211_RC_DEFAULT_PID=y
CONFIG_MAC80211_RC_DEFAULT="pid"
# CONFIG_MAC80211_MESH is not set
# CONFIG_MAC80211_LEDS is not set
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
# CONFIG_WIMAX is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=m
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_TESTS is not set
CONFIG_MTD_CONCAT=m
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set

#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
CONFIG_SM_FTL=m
CONFIG_MTD_OOPS=m

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
CONFIG_MTD_CFI_INTELEXT=m
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=m
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_M25P80 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_NAND_ECC=m
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND is not set
CONFIG_MTD_ONENAND=m
# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
# CONFIG_MTD_ONENAND_GENERIC is not set
CONFIG_MTD_ONENAND_OMAP2=m
# CONFIG_MTD_ONENAND_OTP is not set
# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
# CONFIG_MTD_ONENAND_SIM is not set

#
# LPDDR flash memory drivers
#
# CONFIG_MTD_LPDDR is not set

#
# UBI - Unsorted block images
#
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_RESERVE=1
# CONFIG_MTD_UBI_GLUEBI is not set

#
# UBI debugging options
#
# CONFIG_MTD_UBI_DEBUG is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m

#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MG_DISK is not set
CONFIG_MISC_DEVICES=y
# CONFIG_AD525X_DPOT is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1780 is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_BMP085 is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IWMC3200TOP is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=m
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=m
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_SCSI_WAIT_SCAN=m

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
CONFIG_MACVLAN=m
# CONFIG_MACVTAP is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=m
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
CONFIG_SMC91X=y
# CONFIG_TI_DAVINCI_EMAC is not set
# CONFIG_DM9000 is not set
# CONFIG_ENC28J60 is not set
# CONFIG_ETHOC is not set
# CONFIG_SMC911X is not set
# CONFIG_SMSC911X is not set
# CONFIG_DNET is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
# CONFIG_KS8851 is not set
# CONFIG_KS8851_MLL is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WLAN=y
# CONFIG_LIBERTAS_THINFIRM is not set
# CONFIG_AT76C50X_USB is not set
# CONFIG_USB_ZD1201 is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_RTL8187 is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_ATH_COMMON is not set
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
# CONFIG_HOSTAP is not set
# CONFIG_IWM is not set
# CONFIG_LIBERTAS is not set
# CONFIG_P54_COMMON is not set
# CONFIG_RT2X00 is not set
CONFIG_WL12XX=m
CONFIG_WL1251=m
CONFIG_WL1251_SPI=m
# CONFIG_WL1251_SDIO is not set
# CONFIG_WL1271 is not set
# CONFIG_ZD1211RW is not set

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#

#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
CONFIG_USB_HSO=m
# CONFIG_USB_CDC_PHONET is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WAN is not set

#
# CAIF transport drivers
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=m
CONFIG_INPUT_POLLDEV=m
# CONFIG_INPUT_SPARSEKMAP is not set

#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=m
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_OMAP is not set
CONFIG_KEYBOARD_TWL4030=y
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_QT602240 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_W90X900 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
CONFIG_INPUT_TWL4030_PWRBUTTON=m
CONFIG_INPUT_TWL4030_VIBRA=m
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_ADXL34X is not set

#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set

#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX3107 is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=m
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
CONFIG_HW_RANDOM_OMAP=m
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_RAMOOPS is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_OMAP=y
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_OMAP24XX=y
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set

#
# SPI Protocol Masters
#
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set

#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y

#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set

#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_SX150X is not set
CONFIG_GPIO_TWL4030=y
# CONFIG_GPIO_ADP5588 is not set

#
# PCI GPIO expanders:
#

#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_GPIO_MC33880 is not set

#
# AC97 GPIO expanders:
#

#
# MODULbus GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=m
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_LIS3_SPI is not set
CONFIG_SENSORS_LIS3_I2C=m
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_OMAP_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
CONFIG_MFD_SUPPORT=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
CONFIG_MENELAUS=y
CONFIG_TWL4030_CORE=y
CONFIG_TWL4030_POWER=y
CONFIG_TWL4030_CODEC=y
# CONFIG_TWL6030_PWM is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_TC35892 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB8500_CORE is not set
# CONFIG_MFD_TPS6586X is not set
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_DUMMY is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
CONFIG_REGULATOR_TWL4030=y
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_MEDIA_SUPPORT=m

#
# Multimedia core support
#
CONFIG_VIDEO_DEV=m
CONFIG_VIDEO_V4L2_COMMON=m
# CONFIG_VIDEO_ALLOW_V4L1 is not set
# CONFIG_VIDEO_V4L1_COMPAT is not set
# CONFIG_DVB_CORE is not set
CONFIG_VIDEO_MEDIA=m

#
# Multimedia drivers
#
CONFIG_IR_CORE=m
CONFIG_VIDEO_IR=m
CONFIG_LIRC=m
# CONFIG_RC_MAP is not set
# CONFIG_IR_NEC_DECODER is not set
# CONFIG_IR_RC5_DECODER is not set
# CONFIG_IR_RC6_DECODER is not set
# CONFIG_IR_JVC_DECODER is not set
# CONFIG_IR_SONY_DECODER is not set
CONFIG_IR_LIRC_CODEC=m
# CONFIG_IR_IMON is not set
# CONFIG_IR_MCEUSB is not set
# CONFIG_IR_STREAMZAP is not set
# CONFIG_MEDIA_ATTACH is not set
CONFIG_MEDIA_TUNER=m
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC5000=m
CONFIG_MEDIA_TUNER_MC44S803=m
CONFIG_VIDEO_V4L2=m
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_DMA_CONTIG=m
CONFIG_VIDEO_CAPTURE_DRIVERS=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
# CONFIG_VIDEO_IR_I2C is not set

#
# Encoders/decoders and other helper chips
#

#
# Audio decoders
#
# CONFIG_VIDEO_TVAUDIO is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TDA9875 is not set
# CONFIG_VIDEO_TEA6415C is not set
# CONFIG_VIDEO_TEA6420 is not set
# CONFIG_VIDEO_MSP3400 is not set
# CONFIG_VIDEO_CS5345 is not set
# CONFIG_VIDEO_CS53L32A is not set
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_TLV320AIC23B is not set
# CONFIG_VIDEO_WM8775 is not set
# CONFIG_VIDEO_WM8739 is not set
# CONFIG_VIDEO_VP27SMPX is not set

#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_MT9V011 is not set
# CONFIG_VIDEO_TCM825X is not set
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
# CONFIG_VIDEO_SAA717X is not set
# CONFIG_VIDEO_SAA7191 is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
# CONFIG_VIDEO_CX25840 is not set

#
# MPEG video encoders
#
# CONFIG_VIDEO_CX2341X is not set

#
# Video encoders
#
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_AK881X is not set

#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
# CONFIG_VIDEO_UPD64083 is not set
# CONFIG_VIDEO_VPFE_CAPTURE is not set
CONFIG_VIDEO_OMAP2_VOUT=m
# CONFIG_VIDEO_SAA5246A is not set
# CONFIG_VIDEO_SAA5249 is not set
# CONFIG_SOC_CAMERA is not set
# CONFIG_VIDEO_OMAP2 is not set
# CONFIG_V4L_USB_DRIVERS is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_RADIO_ADAPTERS is not set
# CONFIG_DAB is not set

#
# Graphics support
#
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
CONFIG_FB_CFB_FILLRECT=m
CONFIG_FB_CFB_COPYAREA=m
CONFIG_FB_CFB_IMAGEBLIT=m
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_TMIO is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
CONFIG_OMAP2_VRAM=y
CONFIG_OMAP2_VRFB=y
CONFIG_OMAP2_DSS=m
CONFIG_OMAP2_VRAM_SIZE=2
# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set
# CONFIG_OMAP2_DSS_DPI is not set
# CONFIG_OMAP2_DSS_RFBI is not set
# CONFIG_OMAP2_DSS_VENC is not set
CONFIG_OMAP2_DSS_SDI=y
# CONFIG_OMAP2_DSS_DSI is not set
# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
CONFIG_FB_OMAP2=m
# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set
CONFIG_FB_OMAP2_NUM_FBS=3

#
# OMAP2/3 Display Device Drivers
#
# CONFIG_PANEL_GENERIC is not set
# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set
# CONFIG_PANEL_TOPPOLY_TDO35S is not set
# CONFIG_PANEL_TPO_TD043MTEA1 is not set
CONFIG_PANEL_ACX565AKM=m
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
# CONFIG_BACKLIGHT_ADP8860 is not set

#
# Display device support
#
CONFIG_DISPLAY_SUPPORT=y

#
# Display hardware drivers
#

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_LOGO is not set
CONFIG_SOUND=y
# CONFIG_SOUND_OSS_CORE is not set
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_JACK=y
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_RAWMIDI_SEQ is not set
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_OMAP_SOC=y
CONFIG_SND_OMAP_SOC_MCBSP=y
# CONFIG_SND_OMAP_SOC_N810 is not set
CONFIG_SND_OMAP_SOC_RX51=y
# CONFIG_SND_OMAP_SOC_OVERO is not set
# CONFIG_SND_OMAP_SOC_SDP4430 is not set
CONFIG_SND_SOC_I2C_AND_SPI=y
# CONFIG_SND_SOC_ALL_CODECS is not set
CONFIG_SND_SOC_TLV320AIC3X=y
# CONFIG_SOUND_PRIME is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_HID=m
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_SUSPEND is not set
CONFIG_USB_OTG_WHITELIST=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MON=m
# CONFIG_USB_WUSB is not set
# CONFIG_USB_WUSB_CBAF is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HWA_HCD is not set
# CONFIG_USB_MUSB_HDRC is not set

#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=m
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
CONFIG_USB_LIBUSUAL=y

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set

#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
CONFIG_USB_GADGET=m
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_SELECTED=y
CONFIG_USB_GADGET_OMAP=y
CONFIG_USB_OMAP=m
# CONFIG_USB_GADGET_R8A66597 is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_GADGET_DUALSPEED is not set
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FUNCTIONFS is not set
CONFIG_USB_FILE_STORAGE=m
# CONFIG_USB_FILE_STORAGE_TEST is not set
# CONFIG_USB_MASS_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
CONFIG_USB_G_NOKIA=m
# CONFIG_USB_G_MULTI is not set
# CONFIG_USB_G_HID is not set
# CONFIG_USB_G_DBGP is not set
# CONFIG_USB_G_WEBCAM is not set

#
# OTG and related infrastructure
#
CONFIG_USB_OTG_UTILS=y
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_ISP1301_OMAP is not set
# CONFIG_USB_ULPI is not set
CONFIG_TWL4030_USB=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set

#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_OMAP is not set
CONFIG_MMC_OMAP_HS=y
# CONFIG_MMC_SPI is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m

#
# LED drivers
#
# CONFIG_LEDS_PCA9532 is not set
# CONFIG_LEDS_GPIO is not set
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_TRIGGERS=y

#
# LED Triggers
#
# CONFIG_LEDS_TRIGGER_TIMER is not set
# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
CONFIG_LEDS_TRIGGER_GPIO=m
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set

#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
# CONFIG_RTC_DEBUG is not set

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_TWL92330 is not set
CONFIG_RTC_DRV_TWL4030=m
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_DS3234 is not set
# CONFIG_RTC_DRV_PCF2123 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set

#
# on-CPU RTC drivers
#
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
CONFIG_STAGING=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
# CONFIG_VIDEO_TM6000 is not set
# CONFIG_USB_IP_COMMON is not set
# CONFIG_W35UND is not set
# CONFIG_PRISM2_USB is not set
# CONFIG_ECHO is not set
# CONFIG_OTUS is not set
# CONFIG_RT2870 is not set
# CONFIG_COMEDI is not set
# CONFIG_ASUS_OLED is not set
# CONFIG_TRANZPORT is not set
# CONFIG_POHMELFS is not set
# CONFIG_LINE6_USB is not set
# CONFIG_SPECTRA is not set
# CONFIG_VT6656 is not set
# CONFIG_FB_UDL is not set
CONFIG_IIO=m
# CONFIG_IIO_RING_BUFFER is not set
# CONFIG_IIO_TRIGGER is not set

#
# Accelerometers
#
# CONFIG_ADIS16209 is not set
# CONFIG_ADIS16220 is not set
# CONFIG_ADIS16240 is not set
# CONFIG_KXSD9 is not set
# CONFIG_LIS3L02DQ is not set

#
# Analog to digital convertors
#
# CONFIG_MAX1363 is not set

#
# Digital gyroscope sensors
#
# CONFIG_ADIS16260 is not set

#
# Inertial measurement units
#
# CONFIG_ADIS16300 is not set
# CONFIG_ADIS16350 is not set
# CONFIG_ADIS16400 is not set

#
# Light sensors
#
CONFIG_SENSORS_TSL2563=m

#
# Magnetometer sensors
#
# CONFIG_SENSORS_HMC5843 is not set

#
# Triggers - standalone
#
# CONFIG_ZRAM is not set
# CONFIG_BATMAN_ADV is not set
# CONFIG_FB_SM7XX is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# CONFIG_ST_BT is not set
# CONFIG_ADIS16255 is not set
# CONFIG_LIRC_STAGING is not set
# CONFIG_EASYCAP is not set
CONFIG_TIDSPBRIDGE=m
CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE=0x600000
# CONFIG_TIDSPBRIDGE_DEBUG is not set
CONFIG_TIDSPBRIDGE_RECOVERY=y
# CONFIG_TIDSPBRIDGE_CACHE_LINE_CHECK is not set
CONFIG_TIDSPBRIDGE_WDT3=y
CONFIG_TIDSPBRIDGE_WDT_TIMEOUT=5
# CONFIG_TIDSPBRIDGE_NTFY_PWRERR is not set
CONFIG_TIDSPBRIDGE_BACKTRACE=y

#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_NILFS2_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=m
# CONFIG_CUSE is not set
CONFIG_GENERIC_ACL=y

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=m
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_UBIFS_FS=m
# CONFIG_UBIFS_FS_XATTR is not set
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
# CONFIG_UBIFS_FS_DEBUG is not set
# CONFIG_LOGFS is not set
CONFIG_CRAMFS=y
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
# CONFIG_SYSV68_PARTITION is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set

#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_LOCKUP_DETECTOR is not set
# CONFIG_HARDLOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
CONFIG_SCHED_DEBUG=y
CONFIG_SCHEDSTATS=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
CONFIG_DEBUG_SLAB=y
# CONFIG_DEBUG_SLAB_LEAK is not set
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_PROVE_RCU=y
# CONFIG_PROVE_RCU_REPEATEDLY is not set
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_TRACE_IRQFLAGS=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARM_UNWIND=y
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_ERRORS is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_LL is not set
# CONFIG_EARLY_PRINTK is not set
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_OC_ETM is not set

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP=y
CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MANAGER_TESTS=y
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_NULL=m
# CONFIG_CRYPTO_PCRYPT is not set
CONFIG_CRYPTO_WORKQUEUE=y
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_SEQIV=m

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=m
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=m

#
# Hash modes
#
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m

#
# Digest
#
CONFIG_CRYPTO_CRC32C=m
CONFIG_CRYPTO_GHASH=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_ZLIB=y
CONFIG_CRYPTO_LZO=m

#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_OMAP_SHAM=m
# CONFIG_BINARY_PRINTF is not set

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
# CONFIG_CRC_T10DIF is not set
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
CONFIG_CRC7=m
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=m
CONFIG_LZO_DECOMPRESS=m
CONFIG_DECOMPRESS_GZIP=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y

Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100907 20:19]:
> * Bryan Wu <bryan.wu@canonical.com> [100906 03:09]:
> > Tony,
> > 
> > I tried your latest branch: devel-smp-on-unicore, kernel boots up but
> > got lots of WARN_ON fired:
> > 
> > ---
> > ------------[ cut here ]------------
> > [    1.149719] WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
> > [    1.149780] Modules linked in:
> > [    1.149841] [<c01b34c8>] (unwind_backtrace+0x0/0xe4) from
> > [<c01e939c>] (warn_slowpath_common+0x4c/0x64)
> > [    1.149902] [<c01e939c>] (warn_slowpath_common+0x4c/0x64) from
> > [<c01e93cc>] (warn_slowpath_null+0x18/0x1c)
> > [    1.149993] [<c01e93cc>] (warn_slowpath_null+0x18/0x1c) from
> > [<c0274730>] (pcpu_alloc+0x2fc/0x888)
> > [    1.150085] [<c0274730>] (pcpu_alloc+0x2fc/0x888) from [<c0279578>]
> > (sget+0x198/0x43c)
> > [    1.150146] [<c0279578>] (sget+0x198/0x43c) from [<c0279adc>]
> > (get_sb_ns+0x20/0x90)
> > [    1.150238] [<c0279adc>] (get_sb_ns+0x20/0x90) from [<c02791a4>]
> > (vfs_kern_mount+0x9c/0x18c)
> > [    1.150299] [<c02791a4>] (vfs_kern_mount+0x9c/0x18c) from
> > [<c0022280>] (init_mqueue_fs+0x68/0xc8)
> > [    1.150390] [<c0022280>] (init_mqueue_fs+0x68/0xc8) from
> > [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4)
> > [    1.150451] [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4) from
> > [<c0008760>] (kernel_init+0x148/0x210)
> > [    1.150543] [<c0008760>] (kernel_init+0x148/0x210) from
> > [<c01adcf8>] (kernel_thread_exit+0x0/0x8)
> > [    1.150604] ---[ end trace 1b75b31a2719ed74 ]---
> > ---
> > 
> > It looks like we still missed to set some flag for chuck.
> 
> Yeah I think there's some .config option that needs to be handled
> properly to fix this.

This seems to disappear when CONFIG_LOCK_STAT is disabled,
I wonder why?

Here are my current changes to omap3_defconfig that I use for testing.

Tony
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap3_defconfig
@@ -55,6 +55,7 @@ CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
 CONFIG_AEABI=y
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -218,9 +219,9 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 CONFIG_USB_MUSB_DEBUG=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
@@ -276,7 +277,7 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
-CONFIG_LOCK_STAT=y
+# CONFIG_LOCK_STAT is not set
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y

[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100907 20:19]:
> * Bryan Wu <bryan.wu@canonical.com> [100906 03:09]:
> > Tony,
> > 
> > I tried your latest branch: devel-smp-on-unicore, kernel boots up but
> > got lots of WARN_ON fired:
> > 
> > ---
> > ------------[ cut here ]------------
> > [    1.149719] WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
> > [    1.149780] Modules linked in:
> > [    1.149841] [<c01b34c8>] (unwind_backtrace+0x0/0xe4) from
> > [<c01e939c>] (warn_slowpath_common+0x4c/0x64)
> > [    1.149902] [<c01e939c>] (warn_slowpath_common+0x4c/0x64) from
> > [<c01e93cc>] (warn_slowpath_null+0x18/0x1c)
> > [    1.149993] [<c01e93cc>] (warn_slowpath_null+0x18/0x1c) from
> > [<c0274730>] (pcpu_alloc+0x2fc/0x888)
> > [    1.150085] [<c0274730>] (pcpu_alloc+0x2fc/0x888) from [<c0279578>]
> > (sget+0x198/0x43c)
> > [    1.150146] [<c0279578>] (sget+0x198/0x43c) from [<c0279adc>]
> > (get_sb_ns+0x20/0x90)
> > [    1.150238] [<c0279adc>] (get_sb_ns+0x20/0x90) from [<c02791a4>]
> > (vfs_kern_mount+0x9c/0x18c)
> > [    1.150299] [<c02791a4>] (vfs_kern_mount+0x9c/0x18c) from
> > [<c0022280>] (init_mqueue_fs+0x68/0xc8)
> > [    1.150390] [<c0022280>] (init_mqueue_fs+0x68/0xc8) from
> > [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4)
> > [    1.150451] [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4) from
> > [<c0008760>] (kernel_init+0x148/0x210)
> > [    1.150543] [<c0008760>] (kernel_init+0x148/0x210) from
> > [<c01adcf8>] (kernel_thread_exit+0x0/0x8)
> > [    1.150604] ---[ end trace 1b75b31a2719ed74 ]---
> > ---
> > 
> > It looks like we still missed to set some flag for chuck.
> 
> Yeah I think there's some .config option that needs to be handled
> properly to fix this.

This seems to disappear when CONFIG_LOCK_STAT is disabled,
I wonder why?

Here are my current changes to omap3_defconfig that I use for testing.

Tony
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap3_defconfig
@@ -55,6 +55,7 @@ CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
 CONFIG_AEABI=y
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -218,9 +219,9 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 CONFIG_USB_MUSB_DEBUG=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
@@ -276,7 +277,7 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
-CONFIG_LOCK_STAT=y
+# CONFIG_LOCK_STAT is not set
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y

Re: [PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Bryan Wu]

Tony,

Awesome, this makes SMP kernel work on my omap3 board.
Thanks a lot. I will test the same kernel on my omap4 one.

-Bryan.

On Thu, Sep 9, 2010 at 4:26 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Tony Lindgren <tony@atomide.com> [100907 20:19]:
>> * Bryan Wu <bryan.wu@canonical.com> [100906 03:09]:
>> > Tony,
>> >
>> > I tried your latest branch: devel-smp-on-unicore, kernel boots up but
>> > got lots of WARN_ON fired:
>> >
>> > ---
>> > ------------[ cut here ]------------
>> > [    1.149719] WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
>> > [    1.149780] Modules linked in:
>> > [    1.149841] [<c01b34c8>] (unwind_backtrace+0x0/0xe4) from
>> > [<c01e939c>] (warn_slowpath_common+0x4c/0x64)
>> > [    1.149902] [<c01e939c>] (warn_slowpath_common+0x4c/0x64) from
>> > [<c01e93cc>] (warn_slowpath_null+0x18/0x1c)
>> > [    1.149993] [<c01e93cc>] (warn_slowpath_null+0x18/0x1c) from
>> > [<c0274730>] (pcpu_alloc+0x2fc/0x888)
>> > [    1.150085] [<c0274730>] (pcpu_alloc+0x2fc/0x888) from [<c0279578>]
>> > (sget+0x198/0x43c)
>> > [    1.150146] [<c0279578>] (sget+0x198/0x43c) from [<c0279adc>]
>> > (get_sb_ns+0x20/0x90)
>> > [    1.150238] [<c0279adc>] (get_sb_ns+0x20/0x90) from [<c02791a4>]
>> > (vfs_kern_mount+0x9c/0x18c)
>> > [    1.150299] [<c02791a4>] (vfs_kern_mount+0x9c/0x18c) from
>> > [<c0022280>] (init_mqueue_fs+0x68/0xc8)
>> > [    1.150390] [<c0022280>] (init_mqueue_fs+0x68/0xc8) from
>> > [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4)
>> > [    1.150451] [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4) from
>> > [<c0008760>] (kernel_init+0x148/0x210)
>> > [    1.150543] [<c0008760>] (kernel_init+0x148/0x210) from
>> > [<c01adcf8>] (kernel_thread_exit+0x0/0x8)
>> > [    1.150604] ---[ end trace 1b75b31a2719ed74 ]---
>> > ---
>> >
>> > It looks like we still missed to set some flag for chuck.
>>
>> Yeah I think there's some .config option that needs to be handled
>> properly to fix this.
>
> This seems to disappear when CONFIG_LOCK_STAT is disabled,
> I wonder why?
>
> Here are my current changes to omap3_defconfig that I use for testing.
>
> Tony
> --- a/arch/arm/configs/omap3_defconfig
> +++ b/arch/arm/configs/omap3_defconfig
> @@ -55,6 +55,7 @@ CONFIG_MACH_OMAP_4430SDP=y
>  CONFIG_ARM_THUMBEE=y
>  CONFIG_NO_HZ=y
>  CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_SMP=y
>  CONFIG_AEABI=y
>  CONFIG_LEDS=y
>  CONFIG_ZBOOT_ROM_TEXT=0x0
> @@ -218,9 +219,9 @@ CONFIG_USB_DEVICEFS=y
>  CONFIG_USB_SUSPEND=y
>  # CONFIG_USB_OTG_WHITELIST is not set
>  CONFIG_USB_MON=y
> -CONFIG_USB_MUSB_HDRC=y
> -CONFIG_USB_MUSB_OTG=y
> -CONFIG_USB_GADGET_MUSB_HDRC=y
> +# CONFIG_USB_MUSB_HDRC is not set
> +# CONFIG_USB_MUSB_OTG is not set
> +# CONFIG_USB_GADGET_MUSB_HDRC is not set
>  CONFIG_USB_MUSB_DEBUG=y
>  CONFIG_USB_WDM=y
>  CONFIG_USB_STORAGE=y
> @@ -276,7 +277,7 @@ CONFIG_DEBUG_KERNEL=y
>  CONFIG_SCHEDSTATS=y
>  CONFIG_TIMER_STATS=y
>  CONFIG_PROVE_LOCKING=y
> -CONFIG_LOCK_STAT=y
> +# CONFIG_LOCK_STAT is not set
>  CONFIG_DEBUG_SPINLOCK_SLEEP=y
>  # CONFIG_DEBUG_BUGVERBOSE is not set
>  CONFIG_DEBUG_INFO=y
>



-- 
Bryan Wu <bryan.wu@canonical.com>
Kernel Developer    +86.138-1617-6545 Mobile
Ubuntu Kernel Team
Canonical Ltd.      www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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[PATCH 1/6] ARM: Add inline function smp_on_up() for early init testing

[Bryan Wu]

Tony,

Awesome, this makes SMP kernel work on my omap3 board.
Thanks a lot. I will test the same kernel on my omap4 one.

-Bryan.

On Thu, Sep 9, 2010 at 4:26 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Tony Lindgren <tony@atomide.com> [100907 20:19]:
>> * Bryan Wu <bryan.wu@canonical.com> [100906 03:09]:
>> > Tony,
>> >
>> > I tried your latest branch: devel-smp-on-unicore, kernel boots up but
>> > got lots of WARN_ON fired:
>> >
>> > ---
>> > ------------[ cut here ]------------
>> > [ ? ?1.149719] WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
>> > [ ? ?1.149780] Modules linked in:
>> > [ ? ?1.149841] [<c01b34c8>] (unwind_backtrace+0x0/0xe4) from
>> > [<c01e939c>] (warn_slowpath_common+0x4c/0x64)
>> > [ ? ?1.149902] [<c01e939c>] (warn_slowpath_common+0x4c/0x64) from
>> > [<c01e93cc>] (warn_slowpath_null+0x18/0x1c)
>> > [ ? ?1.149993] [<c01e93cc>] (warn_slowpath_null+0x18/0x1c) from
>> > [<c0274730>] (pcpu_alloc+0x2fc/0x888)
>> > [ ? ?1.150085] [<c0274730>] (pcpu_alloc+0x2fc/0x888) from [<c0279578>]
>> > (sget+0x198/0x43c)
>> > [ ? ?1.150146] [<c0279578>] (sget+0x198/0x43c) from [<c0279adc>]
>> > (get_sb_ns+0x20/0x90)
>> > [ ? ?1.150238] [<c0279adc>] (get_sb_ns+0x20/0x90) from [<c02791a4>]
>> > (vfs_kern_mount+0x9c/0x18c)
>> > [ ? ?1.150299] [<c02791a4>] (vfs_kern_mount+0x9c/0x18c) from
>> > [<c0022280>] (init_mqueue_fs+0x68/0xc8)
>> > [ ? ?1.150390] [<c0022280>] (init_mqueue_fs+0x68/0xc8) from
>> > [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4)
>> > [ ? ?1.150451] [<c01ac5d0>] (do_one_initcall+0xcc/0x1a4) from
>> > [<c0008760>] (kernel_init+0x148/0x210)
>> > [ ? ?1.150543] [<c0008760>] (kernel_init+0x148/0x210) from
>> > [<c01adcf8>] (kernel_thread_exit+0x0/0x8)
>> > [ ? ?1.150604] ---[ end trace 1b75b31a2719ed74 ]---
>> > ---
>> >
>> > It looks like we still missed to set some flag for chuck.
>>
>> Yeah I think there's some .config option that needs to be handled
>> properly to fix this.
>
> This seems to disappear when CONFIG_LOCK_STAT is disabled,
> I wonder why?
>
> Here are my current changes to omap3_defconfig that I use for testing.
>
> Tony
> --- a/arch/arm/configs/omap3_defconfig
> +++ b/arch/arm/configs/omap3_defconfig
> @@ -55,6 +55,7 @@ CONFIG_MACH_OMAP_4430SDP=y
> ?CONFIG_ARM_THUMBEE=y
> ?CONFIG_NO_HZ=y
> ?CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_SMP=y
> ?CONFIG_AEABI=y
> ?CONFIG_LEDS=y
> ?CONFIG_ZBOOT_ROM_TEXT=0x0
> @@ -218,9 +219,9 @@ CONFIG_USB_DEVICEFS=y
> ?CONFIG_USB_SUSPEND=y
> ?# CONFIG_USB_OTG_WHITELIST is not set
> ?CONFIG_USB_MON=y
> -CONFIG_USB_MUSB_HDRC=y
> -CONFIG_USB_MUSB_OTG=y
> -CONFIG_USB_GADGET_MUSB_HDRC=y
> +# CONFIG_USB_MUSB_HDRC is not set
> +# CONFIG_USB_MUSB_OTG is not set
> +# CONFIG_USB_GADGET_MUSB_HDRC is not set
> ?CONFIG_USB_MUSB_DEBUG=y
> ?CONFIG_USB_WDM=y
> ?CONFIG_USB_STORAGE=y
> @@ -276,7 +277,7 @@ CONFIG_DEBUG_KERNEL=y
> ?CONFIG_SCHEDSTATS=y
> ?CONFIG_TIMER_STATS=y
> ?CONFIG_PROVE_LOCKING=y
> -CONFIG_LOCK_STAT=y
> +# CONFIG_LOCK_STAT is not set
> ?CONFIG_DEBUG_SPINLOCK_SLEEP=y
> ?# CONFIG_DEBUG_BUGVERBOSE is not set
> ?CONFIG_DEBUG_INFO=y
>



-- 
Bryan Wu <bryan.wu@canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Ubuntu Kernel Team
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Tony Lindgren]

>From 16c866489613ef8ea9d28ecf861f5a7ff4d60377 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Thu, 2 Sep 2010 08:20:02 -0700
Subject: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

Use SMP and UP macros for cacheflush. Note that __flush_icache_all
currently won't work properly on ARMv7 SMP if support for ARMv6 is
compiled in.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/cacheflush.h |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..09a893e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
 #include <asm/outercache.h>
+#include <asm/smp_plat.h>
 
 #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
@@ -372,8 +373,10 @@ static inline void __flush_icache_all(void)
 	extern void v6_icache_inval_all(void);
 	v6_icache_inval_all();
 #elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
+	asm(								\
+	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)	\
+	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
+	    :								\
 	    : "r" (0));
 #else
 	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-- 
1.7.1

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Tony Lindgren]

RE: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 9:50 PM
> To: Russell King - ARM Linux
> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> From 16c866489613ef8ea9d28ecf861f5a7ff4d60377 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Thu, 2 Sep 2010 08:20:02 -0700
> Subject: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> Use SMP and UP macros for cacheflush. Note that __flush_icache_all
> currently won't work properly on ARMv7 SMP if support for ARMv6 is
> compiled in.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/include/asm/cacheflush.h |    7 +++++--
>  1 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/cacheflush.h
> b/arch/arm/include/asm/cacheflush.h
> index 4656a24..09a893e 100644
> --- a/arch/arm/include/asm/cacheflush.h
> +++ b/arch/arm/include/asm/cacheflush.h
> @@ -16,6 +16,7 @@
>  #include <asm/shmparam.h>
>  #include <asm/cachetype.h>
>  #include <asm/outercache.h>
> +#include <asm/smp_plat.h>
> 
>  #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
> 
> @@ -372,8 +373,10 @@ static inline void __flush_icache_all(void)
>  	extern void v6_icache_inval_all(void);
>  	v6_icache_inval_all();
>  #elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
> -	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner
> shareable\n"
> -	    :
> +	asm(								\
> +	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)
> 	\
> +	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
> +	    :								\
>  	    : "r" (0));
>  #else
>  	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"

Since UP/SMP both cases are handled, the above patch can be something like this now... 

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 9792a71..ebdff42 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
 #include <asm/outercache.h>
+#include <asm/smp_plat.h>
 
 #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
@@ -394,13 +395,11 @@ static inline void __flush_icache_all(void)
 #ifdef CONFIG_ARM_ERRATA_411920
 	extern void v6_icache_inval_all(void);
 	v6_icache_inval_all();
-#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
-	    : "r" (0));
 #else
-	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-	    :
+	asm(								\
+	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)	\
+	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
+	    :								\
 	    : "r" (0));
 #endif
 }
-- 
1.6.0.4

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 9:50 PM
> To: Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> From 16c866489613ef8ea9d28ecf861f5a7ff4d60377 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Thu, 2 Sep 2010 08:20:02 -0700
> Subject: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> Use SMP and UP macros for cacheflush. Note that __flush_icache_all
> currently won't work properly on ARMv7 SMP if support for ARMv6 is
> compiled in.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/include/asm/cacheflush.h |    7 +++++--
>  1 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/cacheflush.h
> b/arch/arm/include/asm/cacheflush.h
> index 4656a24..09a893e 100644
> --- a/arch/arm/include/asm/cacheflush.h
> +++ b/arch/arm/include/asm/cacheflush.h
> @@ -16,6 +16,7 @@
>  #include <asm/shmparam.h>
>  #include <asm/cachetype.h>
>  #include <asm/outercache.h>
> +#include <asm/smp_plat.h>
> 
>  #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
> 
> @@ -372,8 +373,10 @@ static inline void __flush_icache_all(void)
>  	extern void v6_icache_inval_all(void);
>  	v6_icache_inval_all();
>  #elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
> -	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner
> shareable\n"
> -	    :
> +	asm(								\
> +	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)
> 	\
> +	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
> +	    :								\
>  	    : "r" (0));
>  #else
>  	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"

Since UP/SMP both cases are handled, the above patch can be something like this now... 

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 9792a71..ebdff42 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
 #include <asm/outercache.h>
+#include <asm/smp_plat.h>
 
 #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
@@ -394,13 +395,11 @@ static inline void __flush_icache_all(void)
 #ifdef CONFIG_ARM_ERRATA_411920
 	extern void v6_icache_inval_all(void);
 	v6_icache_inval_all();
-#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
-	    : "r" (0));
 #else
-	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-	    :
+	asm(								\
+	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)	\
+	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
+	    :								\
 	    : "r" (0));
 #endif
 }
-- 
1.6.0.4

Re: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 05:27:25PM +0530, Shilimkar, Santosh wrote:
> Since UP/SMP both cases are handled, the above patch can be something
> like this now... 

No - this results in the instruction used for ARMv6 SMP systems being
changed to the ARMv7 instruction, which probably won't work.

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 05:27:25PM +0530, Shilimkar, Santosh wrote:
> Since UP/SMP both cases are handled, the above patch can be something
> like this now... 

No - this results in the instruction used for ARMv6 SMP systems being
changed to the ARMv7 instruction, which probably won't work.

RE: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Shilimkar, Santosh]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> Sent: Saturday, September 04, 2010 4:28 PM
> To: Shilimkar, Santosh
> Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Bryan Wu; Will Deacon
> Subject: Re: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> On Fri, Sep 03, 2010 at 05:27:25PM +0530, Shilimkar, Santosh wrote:
> > Since UP/SMP both cases are handled, the above patch can be something
> > like this now...
> 
> No - this results in the instruction used for ARMv6 SMP systems being
> changed to the ARMv7 instruction, which probably won't work.
Ok. I get it now

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Shilimkar, Santosh]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Saturday, September 04, 2010 4:28 PM
> To: Shilimkar, Santosh
> Cc: Tony Lindgren; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Bryan Wu; Will Deacon
> Subject: Re: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> On Fri, Sep 03, 2010 at 05:27:25PM +0530, Shilimkar, Santosh wrote:
> > Since UP/SMP both cases are handled, the above patch can be something
> > like this now...
> 
> No - this results in the instruction used for ARMv6 SMP systems being
> changed to the ARMv7 instruction, which probably won't work.
Ok. I get it now

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Tony Lindgren]

>From 253e91b76e104dbdf05c5c3eaf9cbf426972c938 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Wed, 1 Sep 2010 16:49:13 -0700
Subject: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

Fix v7wbi_tlb_flags for SMP on UP. Note that we must enable MULTI_TLB
to avoid undefined reference to cpu_tlb error.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/tlbflush.h |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 1fd0db9..55e1dd9 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -189,20 +189,32 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
+#define v7wbi_tlb_flags_common (TLB_WB | TLB_DCLEAN)
 #define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
 #define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
 
 #ifdef CONFIG_SMP
+#ifdef CONFIG_SMP_ON_UP
+#define v7wbi_tlb_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#else
 #define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#endif
 #else
 #define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
 # define v7wbi_possible_flags	v7wbi_tlb_flags
-# define v7wbi_always_flags	v7wbi_tlb_flags
+# ifdef CONFIG_SMP_ON_UP
+#  define v7wbi_always_flags	v7wbi_tlb_flags_common
+#  ifndef MULTI_TLB
+#   define MULTI_TLB 1
+#  endif
+# else
+#  define v7wbi_always_flags	v7wbi_tlb_flags
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
-- 
1.7.1

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Tony Lindgren]

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 09:20:40AM -0700, Tony Lindgren wrote:
> >From 253e91b76e104dbdf05c5c3eaf9cbf426972c938 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Wed, 1 Sep 2010 16:49:13 -0700
> Subject: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP
> 
> Fix v7wbi_tlb_flags for SMP on UP. Note that we must enable MULTI_TLB
> to avoid undefined reference to cpu_tlb error.

This isn't required, as it is already covered by my patch.

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 09:20:40AM -0700, Tony Lindgren wrote:
> >From 253e91b76e104dbdf05c5c3eaf9cbf426972c938 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Wed, 1 Sep 2010 16:49:13 -0700
> Subject: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP
> 
> Fix v7wbi_tlb_flags for SMP on UP. Note that we must enable MULTI_TLB
> to avoid undefined reference to cpu_tlb error.

This isn't required, as it is already covered by my patch.

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:18]:
> On Thu, Sep 02, 2010 at 09:20:40AM -0700, Tony Lindgren wrote:
> > >From 253e91b76e104dbdf05c5c3eaf9cbf426972c938 Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Wed, 1 Sep 2010 16:49:13 -0700
> > Subject: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP
> > 
> > Fix v7wbi_tlb_flags for SMP on UP. Note that we must enable MULTI_TLB
> > to avoid undefined reference to cpu_tlb error.
> 
> This isn't required, as it is already covered by my patch.

Yup, seems to be working without this patch.

Tony

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:18]:
> On Thu, Sep 02, 2010 at 09:20:40AM -0700, Tony Lindgren wrote:
> > >From 253e91b76e104dbdf05c5c3eaf9cbf426972c938 Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Wed, 1 Sep 2010 16:49:13 -0700
> > Subject: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP
> > 
> > Fix v7wbi_tlb_flags for SMP on UP. Note that we must enable MULTI_TLB
> > to avoid undefined reference to cpu_tlb error.
> 
> This isn't required, as it is already covered by my patch.

Yup, seems to be working without this patch.

Tony

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 962 bytes --]

* Tony Lindgren <tony@atomide.com> [100902 09:29]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:18]:
> > On Thu, Sep 02, 2010 at 09:20:40AM -0700, Tony Lindgren wrote:
> > > >From 253e91b76e104dbdf05c5c3eaf9cbf426972c938 Mon Sep 17 00:00:00 2001
> > > From: Tony Lindgren <tony@atomide.com>
> > > Date: Wed, 1 Sep 2010 16:49:13 -0700
> > > Subject: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP
> > > 
> > > Fix v7wbi_tlb_flags for SMP on UP. Note that we must enable MULTI_TLB
> > > to avoid undefined reference to cpu_tlb error.
> > 
> > This isn't required, as it is already covered by my patch.
> 
> Yup, seems to be working without this patch.

Correction, only boots on SMP hardawre. On UP hardware I still
need the following patch.

Left out forcing MULTI_TLB as looks like your patch already
does that.

Also noticed I'm now getting unhandled fault on SMP system
which I was not getting earlier. Will try to track it down.

Tony

[-- Attachment #2: tlbflush-fix-smp-on-up-flags.patch --]
[-- Type: text/x-diff, Size: 1386 bytes --]

From: Tony Lindgren <tony@atomide.com>
Date: Wed, 1 Sep 2010 16:49:13 -0700
Subject: [PATCH] ARM: Fix v7wbi_tlb_flags for SMP on UP

Fix v7wbi_tlb_flags for SMP on UP. Note that depends on MULTI_TLB
to avoid undefined reference to cpu_tlb error.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 1fd0db9..692e9cf 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -189,20 +189,29 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
+#define v7wbi_tlb_flags_common (TLB_WB | TLB_DCLEAN)
 #define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
 #define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
 
 #ifdef CONFIG_SMP
+#ifdef CONFIG_SMP_ON_UP
+#define v7wbi_tlb_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#else
 #define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#endif
 #else
 #define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
 # define v7wbi_possible_flags	v7wbi_tlb_flags
-# define v7wbi_always_flags	v7wbi_tlb_flags
+# ifdef CONFIG_SMP_ON_UP
+#  define v7wbi_always_flags	v7wbi_tlb_flags_common
+# else
+#  define v7wbi_always_flags	v7wbi_tlb_flags
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100902 09:29]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:18]:
> > On Thu, Sep 02, 2010 at 09:20:40AM -0700, Tony Lindgren wrote:
> > > >From 253e91b76e104dbdf05c5c3eaf9cbf426972c938 Mon Sep 17 00:00:00 2001
> > > From: Tony Lindgren <tony@atomide.com>
> > > Date: Wed, 1 Sep 2010 16:49:13 -0700
> > > Subject: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP
> > > 
> > > Fix v7wbi_tlb_flags for SMP on UP. Note that we must enable MULTI_TLB
> > > to avoid undefined reference to cpu_tlb error.
> > 
> > This isn't required, as it is already covered by my patch.
> 
> Yup, seems to be working without this patch.

Correction, only boots on SMP hardawre. On UP hardware I still
need the following patch.

Left out forcing MULTI_TLB as looks like your patch already
does that.

Also noticed I'm now getting unhandled fault on SMP system
which I was not getting earlier. Will try to track it down.

Tony
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Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 04:47:46PM -0700, Tony Lindgren wrote:
> Correction, only boots on SMP hardawre. On UP hardware I still
> need the following patch.

This should fix that properly.

 arch/arm/Kconfig                          |   12 ++++++++
 arch/arm/include/asm/assembler.h          |   20 ++++++++++++-
 arch/arm/include/asm/tlbflush.h           |   24 +++++++++++-----
 arch/arm/kernel/entry-armv.S              |    7 +---
 arch/arm/kernel/head.S                    |   34 +++++++++++++++++++++++
 arch/arm/kernel/vmlinux.lds.S             |   11 +++++++
 arch/arm/mach-realview/include/mach/smp.h |   10 +------
 arch/arm/mach-s5pv310/include/mach/smp.h  |    9 +-----
 arch/arm/mach-tegra/include/mach/smp.h    |   10 +------
 arch/arm/mach-ux500/include/mach/smp.h    |    9 +-----
 arch/arm/mach-vexpress/include/mach/smp.h |    9 +-----
 arch/arm/mm/cache-v7.S                    |   14 +++-------
 arch/arm/mm/proc-v6.S                     |   43 +++++++++++++++++++----------
 arch/arm/mm/proc-v7.S                     |   31 +++++++++++++--------
 arch/arm/mm/tlb-v7.S                      |   33 ++++++++--------------
 arch/arm/plat-omap/include/plat/smp.h     |   12 +-------
 16 files changed, 163 insertions(+), 125 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab2536c..4575e4a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,18 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don't know what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..c344c34 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,17 +189,23 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
-#endif
 
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags	v7wbi_tlb_flags
-# define v7wbi_always_flags	v7wbi_tlb_flags
+
+# ifdef CONFIG_SMP
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
+#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
+# elif defined(CONFIG_SMP_ON_UP)
+#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
+# else
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
+#  define v7wbi_always_flags	v7wbi_tlb_flags_up
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..0b4a626 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	movne	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r3]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c..99d7e6b 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 04:47:46PM -0700, Tony Lindgren wrote:
> Correction, only boots on SMP hardawre. On UP hardware I still
> need the following patch.

This should fix that properly.

 arch/arm/Kconfig                          |   12 ++++++++
 arch/arm/include/asm/assembler.h          |   20 ++++++++++++-
 arch/arm/include/asm/tlbflush.h           |   24 +++++++++++-----
 arch/arm/kernel/entry-armv.S              |    7 +---
 arch/arm/kernel/head.S                    |   34 +++++++++++++++++++++++
 arch/arm/kernel/vmlinux.lds.S             |   11 +++++++
 arch/arm/mach-realview/include/mach/smp.h |   10 +------
 arch/arm/mach-s5pv310/include/mach/smp.h  |    9 +-----
 arch/arm/mach-tegra/include/mach/smp.h    |   10 +------
 arch/arm/mach-ux500/include/mach/smp.h    |    9 +-----
 arch/arm/mach-vexpress/include/mach/smp.h |    9 +-----
 arch/arm/mm/cache-v7.S                    |   14 +++-------
 arch/arm/mm/proc-v6.S                     |   43 +++++++++++++++++++----------
 arch/arm/mm/proc-v7.S                     |   31 +++++++++++++--------
 arch/arm/mm/tlb-v7.S                      |   33 ++++++++--------------
 arch/arm/plat-omap/include/plat/smp.h     |   12 +-------
 16 files changed, 163 insertions(+), 125 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab2536c..4575e4a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,18 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don't know what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..c344c34 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,17 +189,23 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
-#endif
 
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags	v7wbi_tlb_flags
-# define v7wbi_always_flags	v7wbi_tlb_flags
+
+# ifdef CONFIG_SMP
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
+#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
+# elif defined(CONFIG_SMP_ON_UP)
+#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
+# else
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
+#  define v7wbi_always_flags	v7wbi_tlb_flags_up
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..0b4a626 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	movne	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r3]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c..99d7e6b 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 10:07:34AM +0100, Russell King - ARM Linux wrote:
> On Thu, Sep 02, 2010 at 04:47:46PM -0700, Tony Lindgren wrote:
> > Correction, only boots on SMP hardawre. On UP hardware I still
> > need the following patch.
> 
> This should fix that properly.

Correction - the order of the config tests was wrong.

 arch/arm/Kconfig                          |   12 ++++++++
 arch/arm/include/asm/assembler.h          |   20 ++++++++++++-
 arch/arm/include/asm/tlbflush.h           |   24 +++++++++++-----
 arch/arm/kernel/entry-armv.S              |    7 +---
 arch/arm/kernel/head.S                    |   34 +++++++++++++++++++++++
 arch/arm/kernel/vmlinux.lds.S             |   11 +++++++
 arch/arm/mach-realview/include/mach/smp.h |   10 +------
 arch/arm/mach-s5pv310/include/mach/smp.h  |    9 +-----
 arch/arm/mach-tegra/include/mach/smp.h    |   10 +------
 arch/arm/mach-ux500/include/mach/smp.h    |    9 +-----
 arch/arm/mach-vexpress/include/mach/smp.h |    9 +-----
 arch/arm/mm/cache-v7.S                    |   14 +++-------
 arch/arm/mm/proc-v6.S                     |   43 +++++++++++++++++++----------
 arch/arm/mm/proc-v7.S                     |   31 +++++++++++++--------
 arch/arm/mm/tlb-v7.S                      |   33 ++++++++--------------
 arch/arm/plat-omap/include/plat/smp.h     |   12 +-------
 16 files changed, 163 insertions(+), 125 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab2536c..4575e4a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,18 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don't know what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..cf2f018 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,17 +189,23 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
-#endif
 
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags	v7wbi_tlb_flags
-# define v7wbi_always_flags	v7wbi_tlb_flags
+
+# ifdef CONFIG_SMP_ON_UP
+#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
+# elif defined(CONFIG_SMP)
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
+#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
+# else
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
+#  define v7wbi_always_flags	v7wbi_tlb_flags_up
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..0b4a626 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	movne	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r3]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c..99d7e6b 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 10:07:34AM +0100, Russell King - ARM Linux wrote:
> On Thu, Sep 02, 2010 at 04:47:46PM -0700, Tony Lindgren wrote:
> > Correction, only boots on SMP hardawre. On UP hardware I still
> > need the following patch.
> 
> This should fix that properly.

Correction - the order of the config tests was wrong.

 arch/arm/Kconfig                          |   12 ++++++++
 arch/arm/include/asm/assembler.h          |   20 ++++++++++++-
 arch/arm/include/asm/tlbflush.h           |   24 +++++++++++-----
 arch/arm/kernel/entry-armv.S              |    7 +---
 arch/arm/kernel/head.S                    |   34 +++++++++++++++++++++++
 arch/arm/kernel/vmlinux.lds.S             |   11 +++++++
 arch/arm/mach-realview/include/mach/smp.h |   10 +------
 arch/arm/mach-s5pv310/include/mach/smp.h  |    9 +-----
 arch/arm/mach-tegra/include/mach/smp.h    |   10 +------
 arch/arm/mach-ux500/include/mach/smp.h    |    9 +-----
 arch/arm/mach-vexpress/include/mach/smp.h |    9 +-----
 arch/arm/mm/cache-v7.S                    |   14 +++-------
 arch/arm/mm/proc-v6.S                     |   43 +++++++++++++++++++----------
 arch/arm/mm/proc-v7.S                     |   31 +++++++++++++--------
 arch/arm/mm/tlb-v7.S                      |   33 ++++++++--------------
 arch/arm/plat-omap/include/plat/smp.h     |   12 +-------
 16 files changed, 163 insertions(+), 125 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab2536c..4575e4a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,18 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don't know what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..cf2f018 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,17 +189,23 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
-#endif
 
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags	v7wbi_tlb_flags
-# define v7wbi_always_flags	v7wbi_tlb_flags
+
+# ifdef CONFIG_SMP_ON_UP
+#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
+# elif defined(CONFIG_SMP)
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
+#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
+# else
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
+#  define v7wbi_always_flags	v7wbi_tlb_flags_up
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..0b4a626 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	movne	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r3]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c..99d7e6b 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100903 02:02]:
> On Fri, Sep 03, 2010 at 10:07:34AM +0100, Russell King - ARM Linux wrote:
> > On Thu, Sep 02, 2010 at 04:47:46PM -0700, Tony Lindgren wrote:
> > > Correction, only boots on SMP hardawre. On UP hardware I still
> > > need the following patch.
> > 
> > This should fix that properly.
> 
> Correction - the order of the config tests was wrong.

OK that works now.

Looks like your new patch is missing smp_midr.h BTW.

Tony

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100903 02:02]:
> On Fri, Sep 03, 2010 at 10:07:34AM +0100, Russell King - ARM Linux wrote:
> > On Thu, Sep 02, 2010 at 04:47:46PM -0700, Tony Lindgren wrote:
> > > Correction, only boots on SMP hardawre. On UP hardware I still
> > > need the following patch.
> > 
> > This should fix that properly.
> 
> Correction - the order of the config tests was wrong.

OK that works now.

Looks like your new patch is missing smp_midr.h BTW.

Tony

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 10:04:03AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100903 02:02]:
> > On Fri, Sep 03, 2010 at 10:07:34AM +0100, Russell King - ARM Linux wrote:
> > > On Thu, Sep 02, 2010 at 04:47:46PM -0700, Tony Lindgren wrote:
> > > > Correction, only boots on SMP hardawre. On UP hardware I still
> > > > need the following patch.
> > > 
> > > This should fix that properly.
> > 
> > Correction - the order of the config tests was wrong.
> 
> OK that works now.
> 
> Looks like your new patch is missing smp_midr.h BTW.

Damn git.  Hate it when keeping patches external to git, even in git diff
form.  Luckily the file is just sitting around in my tree rather than
having been deleted entirely...

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 10:04:03AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100903 02:02]:
> > On Fri, Sep 03, 2010 at 10:07:34AM +0100, Russell King - ARM Linux wrote:
> > > On Thu, Sep 02, 2010 at 04:47:46PM -0700, Tony Lindgren wrote:
> > > > Correction, only boots on SMP hardawre. On UP hardware I still
> > > > need the following patch.
> > > 
> > > This should fix that properly.
> > 
> > Correction - the order of the config tests was wrong.
> 
> OK that works now.
> 
> Looks like your new patch is missing smp_midr.h BTW.

Damn git.  Hate it when keeping patches external to git, even in git diff
form.  Luckily the file is just sitting around in my tree rather than
having been deleted entirely...

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Catalin Marinas]

Russell,

I can see you posted another version while writing this e-mail. But I
think most comments still apply. 

On Fri, 2010-09-03 at 10:10 +0100, Russell King - ARM Linux wrote:
> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> index 6e8f05c..55974d2 100644
> --- a/arch/arm/include/asm/assembler.h
> +++ b/arch/arm/include/asm/assembler.h
> @@ -154,16 +154,32 @@
>         .long   9999b,9001f;                    \
>         .popsection
> 
> +#ifdef CONFIG_SMP
> +#define SMP(instr...)                                          \
> +9998:  instr
> +#define UP(instr...)                                           \
> +       .pushsection ".smpalt.init", "a"                        ;\
> +       .word   9998b                                           ;\
> +       instr                                                   ;\
> +       .popsection
> +#else
> +#define SMP(instr...)
> +#define UP(instr...) instr
> +#endif

Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
in the SMP/UP macros to make sure that the instruction is always 32-bit
wide.

> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index bb8e93a..bb2ef60 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
>         beq     1b
>         rsbs    r0, r3, #0
>         /* beware -- each __kuser slot must be 8 instructions max */
> -#ifdef CONFIG_SMP
> -       b       __kuser_memory_barrier
> -#else
> -       usr_ret lr
> -#endif
> +       SMP(b   __kuser_memory_barrier)
> +       UP(usr_ret      lr)

Ah, the automatic W() I mentioned above wouldn't work for macros.

> @@ -333,4 +336,35 @@ __create_page_tables:
>  ENDPROC(__create_page_tables)
>         .ltorg
> 
> +#ifdef CONFIG_SMP_ON_UP
> +__fixup_smp:
> +       and     r0, r9, #0xff000000
> +       teq     r0, #0x41000000         @ ARM CPU?
> +       bne     smp_on_up               @ no, assume UP

That's a bit restricting but I'm not sure we have a better way. If we
have the new CPUID format (MIDR[19:16] = 0xf), we can check MMFR0[31:28]
for 1 which means "implemented with hardware coherency support".

> +       and     r0, r9, #0x00070000
> +       teq     r0, #0x00070000         @ ARMv6/v7?
> +       bne     smp_on_up               @ no, assume UP
> +       mrc     p15, 0, r0, c0, c0, 5   @ read MIDR

Typo in comment - MPIDR.

I think this applies to the smp_midr.h file. Should we call it
smp_mpidr.h or just mpidr.h?

> +       movs    r0, r0, lsr #30
> +       teqne   r0, #3                  @ check top two bits 00 or 11
> +       movne   pc, lr
> +
> +smp_on_up:
> +       adr     r0, 1f
> +       ldmia   r0, {r3, r6, r7}
> +       sub     r3, r0, r3
> +       add     r6, r6, r3
> +       add     r7, r7, r3
> +2:     cmp     r6, r7
> +       ldmia   r6!, {r0, r4}
> +       movhs   pc, lr
> +       str     r4, [r0, r3]
> +       b       2b
> +ENDPROC(__fixup_smp)
> +
> +1:     .word   .
> +       .word   __smpalt_begin
> +       .word   __smpalt_end

I think a '.align 2' would be useful as Thumb-2 code may break the
alignment of 1f.

-- 
Catalin

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Catalin Marinas]

Russell,

I can see you posted another version while writing this e-mail. But I
think most comments still apply. 

On Fri, 2010-09-03 at 10:10 +0100, Russell King - ARM Linux wrote:
> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> index 6e8f05c..55974d2 100644
> --- a/arch/arm/include/asm/assembler.h
> +++ b/arch/arm/include/asm/assembler.h
> @@ -154,16 +154,32 @@
>         .long   9999b,9001f;                    \
>         .popsection
> 
> +#ifdef CONFIG_SMP
> +#define SMP(instr...)                                          \
> +9998:  instr
> +#define UP(instr...)                                           \
> +       .pushsection ".smpalt.init", "a"                        ;\
> +       .word   9998b                                           ;\
> +       instr                                                   ;\
> +       .popsection
> +#else
> +#define SMP(instr...)
> +#define UP(instr...) instr
> +#endif

Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
in the SMP/UP macros to make sure that the instruction is always 32-bit
wide.

> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index bb8e93a..bb2ef60 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
>         beq     1b
>         rsbs    r0, r3, #0
>         /* beware -- each __kuser slot must be 8 instructions max */
> -#ifdef CONFIG_SMP
> -       b       __kuser_memory_barrier
> -#else
> -       usr_ret lr
> -#endif
> +       SMP(b   __kuser_memory_barrier)
> +       UP(usr_ret      lr)

Ah, the automatic W() I mentioned above wouldn't work for macros.

> @@ -333,4 +336,35 @@ __create_page_tables:
>  ENDPROC(__create_page_tables)
>         .ltorg
> 
> +#ifdef CONFIG_SMP_ON_UP
> +__fixup_smp:
> +       and     r0, r9, #0xff000000
> +       teq     r0, #0x41000000         @ ARM CPU?
> +       bne     smp_on_up               @ no, assume UP

That's a bit restricting but I'm not sure we have a better way. If we
have the new CPUID format (MIDR[19:16] = 0xf), we can check MMFR0[31:28]
for 1 which means "implemented with hardware coherency support".

> +       and     r0, r9, #0x00070000
> +       teq     r0, #0x00070000         @ ARMv6/v7?
> +       bne     smp_on_up               @ no, assume UP
> +       mrc     p15, 0, r0, c0, c0, 5   @ read MIDR

Typo in comment - MPIDR.

I think this applies to the smp_midr.h file. Should we call it
smp_mpidr.h or just mpidr.h?

> +       movs    r0, r0, lsr #30
> +       teqne   r0, #3                  @ check top two bits 00 or 11
> +       movne   pc, lr
> +
> +smp_on_up:
> +       adr     r0, 1f
> +       ldmia   r0, {r3, r6, r7}
> +       sub     r3, r0, r3
> +       add     r6, r6, r3
> +       add     r7, r7, r3
> +2:     cmp     r6, r7
> +       ldmia   r6!, {r0, r4}
> +       movhs   pc, lr
> +       str     r4, [r0, r3]
> +       b       2b
> +ENDPROC(__fixup_smp)
> +
> +1:     .word   .
> +       .word   __smpalt_begin
> +       .word   __smpalt_end

I think a '.align 2' would be useful as Thumb-2 code may break the
alignment of 1f.

-- 
Catalin

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
> Russell,
> 
> I can see you posted another version while writing this e-mail. But I
> think most comments still apply. 
> 
> On Fri, 2010-09-03 at 10:10 +0100, Russell King - ARM Linux wrote:
> > diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> > index 6e8f05c..55974d2 100644
> > --- a/arch/arm/include/asm/assembler.h
> > +++ b/arch/arm/include/asm/assembler.h
> > @@ -154,16 +154,32 @@
> >         .long   9999b,9001f;                    \
> >         .popsection
> > 
> > +#ifdef CONFIG_SMP
> > +#define SMP(instr...)                                          \
> > +9998:  instr
> > +#define UP(instr...)                                           \
> > +       .pushsection ".smpalt.init", "a"                        ;\
> > +       .word   9998b                                           ;\
> > +       instr                                                   ;\
> > +       .popsection
> > +#else
> > +#define SMP(instr...)
> > +#define UP(instr...) instr
> > +#endif
> 
> Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
> in the SMP/UP macros to make sure that the instruction is always 32-bit
> wide.

Probably not, and it's not obvious how to make it work for T2 kernel
builds.  For the time being, I'm going to make this available only for
native ARM builds.  We can think about how to make this work for T2
sometime later.

> > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> > index bb8e93a..bb2ef60 100644
> > --- a/arch/arm/kernel/entry-armv.S
> > +++ b/arch/arm/kernel/entry-armv.S
> > @@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
> >         beq     1b
> >         rsbs    r0, r3, #0
> >         /* beware -- each __kuser slot must be 8 instructions max */
> > -#ifdef CONFIG_SMP
> > -       b       __kuser_memory_barrier
> > -#else
> > -       usr_ret lr
> > -#endif
> > +       SMP(b   __kuser_memory_barrier)
> > +       UP(usr_ret      lr)
> 
> Ah, the automatic W() I mentioned above wouldn't work for macros.

Indeed, that's only half of the problem.  On T2, some of these may be
16-bit values, others may be 32-bit values, and this mechanism has no
way to know the size of the areas.

> > @@ -333,4 +336,35 @@ __create_page_tables:
> >  ENDPROC(__create_page_tables)
> >         .ltorg
> > 
> > +#ifdef CONFIG_SMP_ON_UP
> > +__fixup_smp:
> > +       and     r0, r9, #0xff000000
> > +       teq     r0, #0x41000000         @ ARM CPU?
> > +       bne     smp_on_up               @ no, assume UP
> 
> That's a bit restricting but I'm not sure we have a better way. If we
> have the new CPUID format (MIDR[19:16] = 0xf), we can check MMFR0[31:28]
> for 1 which means "implemented with hardware coherency support".
> 
> > +       and     r0, r9, #0x00070000
> > +       teq     r0, #0x00070000         @ ARMv6/v7?
> > +       bne     smp_on_up               @ no, assume UP
> > +       mrc     p15, 0, r0, c0, c0, 5   @ read MIDR
> 
> Typo in comment - MPIDR.

Fixed.

> I think this applies to the smp_midr.h file. Should we call it
> smp_mpidr.h or just mpidr.h?

Already fixed.

> I think a '.align 2' would be useful as Thumb-2 code may break the
> alignment of 1f.

Maybe, but if we restrict this to only ARM builds for the time being,
there isn't a problem.

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
> Russell,
> 
> I can see you posted another version while writing this e-mail. But I
> think most comments still apply. 
> 
> On Fri, 2010-09-03 at 10:10 +0100, Russell King - ARM Linux wrote:
> > diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> > index 6e8f05c..55974d2 100644
> > --- a/arch/arm/include/asm/assembler.h
> > +++ b/arch/arm/include/asm/assembler.h
> > @@ -154,16 +154,32 @@
> >         .long   9999b,9001f;                    \
> >         .popsection
> > 
> > +#ifdef CONFIG_SMP
> > +#define SMP(instr...)                                          \
> > +9998:  instr
> > +#define UP(instr...)                                           \
> > +       .pushsection ".smpalt.init", "a"                        ;\
> > +       .word   9998b                                           ;\
> > +       instr                                                   ;\
> > +       .popsection
> > +#else
> > +#define SMP(instr...)
> > +#define UP(instr...) instr
> > +#endif
> 
> Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
> in the SMP/UP macros to make sure that the instruction is always 32-bit
> wide.

Probably not, and it's not obvious how to make it work for T2 kernel
builds.  For the time being, I'm going to make this available only for
native ARM builds.  We can think about how to make this work for T2
sometime later.

> > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> > index bb8e93a..bb2ef60 100644
> > --- a/arch/arm/kernel/entry-armv.S
> > +++ b/arch/arm/kernel/entry-armv.S
> > @@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
> >         beq     1b
> >         rsbs    r0, r3, #0
> >         /* beware -- each __kuser slot must be 8 instructions max */
> > -#ifdef CONFIG_SMP
> > -       b       __kuser_memory_barrier
> > -#else
> > -       usr_ret lr
> > -#endif
> > +       SMP(b   __kuser_memory_barrier)
> > +       UP(usr_ret      lr)
> 
> Ah, the automatic W() I mentioned above wouldn't work for macros.

Indeed, that's only half of the problem.  On T2, some of these may be
16-bit values, others may be 32-bit values, and this mechanism has no
way to know the size of the areas.

> > @@ -333,4 +336,35 @@ __create_page_tables:
> >  ENDPROC(__create_page_tables)
> >         .ltorg
> > 
> > +#ifdef CONFIG_SMP_ON_UP
> > +__fixup_smp:
> > +       and     r0, r9, #0xff000000
> > +       teq     r0, #0x41000000         @ ARM CPU?
> > +       bne     smp_on_up               @ no, assume UP
> 
> That's a bit restricting but I'm not sure we have a better way. If we
> have the new CPUID format (MIDR[19:16] = 0xf), we can check MMFR0[31:28]
> for 1 which means "implemented with hardware coherency support".
> 
> > +       and     r0, r9, #0x00070000
> > +       teq     r0, #0x00070000         @ ARMv6/v7?
> > +       bne     smp_on_up               @ no, assume UP
> > +       mrc     p15, 0, r0, c0, c0, 5   @ read MIDR
> 
> Typo in comment - MPIDR.

Fixed.

> I think this applies to the smp_midr.h file. Should we call it
> smp_mpidr.h or just mpidr.h?

Already fixed.

> I think a '.align 2' would be useful as Thumb-2 code may break the
> alignment of 1f.

Maybe, but if we restrict this to only ARM builds for the time being,
there isn't a problem.

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Catalin Marinas]

On Mon, 2010-09-06 at 16:34 +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
> > Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
> > in the SMP/UP macros to make sure that the instruction is always 32-bit
> > wide.
> 
> Probably not, and it's not obvious how to make it work for T2 kernel
> builds.  For the time being, I'm going to make this available only for
> native ARM builds.  We can think about how to make this work for T2
> sometime later.
[...]
> Indeed, that's only half of the problem.  On T2, some of these may be
> 16-bit values, others may be 32-bit values, and this mechanism has no
> way to know the size of the areas.

We can add the W() macro and they are guaranteed to be 32-bit wide or
get a compilation error. Something like using "UP(W(nop))", though it's
doesn't look as nice.

The usr_ret macro is always compiled to ARM mode anyway.

It may be easier to do it in this patch patch rather than at a later
time trying to grep for SMP/UP macros.

-- 
Catalin

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Catalin Marinas]

On Mon, 2010-09-06 at 16:34 +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
> > Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
> > in the SMP/UP macros to make sure that the instruction is always 32-bit
> > wide.
> 
> Probably not, and it's not obvious how to make it work for T2 kernel
> builds.  For the time being, I'm going to make this available only for
> native ARM builds.  We can think about how to make this work for T2
> sometime later.
[...]
> Indeed, that's only half of the problem.  On T2, some of these may be
> 16-bit values, others may be 32-bit values, and this mechanism has no
> way to know the size of the areas.

We can add the W() macro and they are guaranteed to be 32-bit wide or
get a compilation error. Something like using "UP(W(nop))", though it's
doesn't look as nice.

The usr_ret macro is always compiled to ARM mode anyway.

It may be easier to do it in this patch patch rather than at a later
time trying to grep for SMP/UP macros.

-- 
Catalin

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Mon, Sep 06, 2010 at 04:53:47PM +0100, Catalin Marinas wrote:
> On Mon, 2010-09-06 at 16:34 +0100, Russell King - ARM Linux wrote:
> > On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
> > > Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
> > > in the SMP/UP macros to make sure that the instruction is always 32-bit
> > > wide.
> > 
> > Probably not, and it's not obvious how to make it work for T2 kernel
> > builds.  For the time being, I'm going to make this available only for
> > native ARM builds.  We can think about how to make this work for T2
> > sometime later.
> [...]
> > Indeed, that's only half of the problem.  On T2, some of these may be
> > 16-bit values, others may be 32-bit values, and this mechanism has no
> > way to know the size of the areas.
> 
> We can add the W() macro and they are guaranteed to be 32-bit wide or
> get a compilation error. Something like using "UP(W(nop))", though it's
> doesn't look as nice.
> 
> The usr_ret macro is always compiled to ARM mode anyway.

That's not the only place - here's another:

+       ALT_SMP(test_for_ipi r0, r6, r5, lr)
+       ALT_UP_B(9997f)

test_for_ipi may be thumb code, which could be 16-bit aligned.

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Russell King - ARM Linux]

On Mon, Sep 06, 2010 at 04:53:47PM +0100, Catalin Marinas wrote:
> On Mon, 2010-09-06 at 16:34 +0100, Russell King - ARM Linux wrote:
> > On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
> > > Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
> > > in the SMP/UP macros to make sure that the instruction is always 32-bit
> > > wide.
> > 
> > Probably not, and it's not obvious how to make it work for T2 kernel
> > builds.  For the time being, I'm going to make this available only for
> > native ARM builds.  We can think about how to make this work for T2
> > sometime later.
> [...]
> > Indeed, that's only half of the problem.  On T2, some of these may be
> > 16-bit values, others may be 32-bit values, and this mechanism has no
> > way to know the size of the areas.
> 
> We can add the W() macro and they are guaranteed to be 32-bit wide or
> get a compilation error. Something like using "UP(W(nop))", though it's
> doesn't look as nice.
> 
> The usr_ret macro is always compiled to ARM mode anyway.

That's not the only place - here's another:

+       ALT_SMP(test_for_ipi r0, r6, r5, lr)
+       ALT_UP_B(9997f)

test_for_ipi may be thumb code, which could be 16-bit aligned.

Re: [PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Catalin Marinas]

On Mon, 2010-09-06 at 17:36 +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 06, 2010 at 04:53:47PM +0100, Catalin Marinas wrote:
> > On Mon, 2010-09-06 at 16:34 +0100, Russell King - ARM Linux wrote:
> > > On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
> > > > Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
> > > > in the SMP/UP macros to make sure that the instruction is always 32-bit
> > > > wide.
> > >
> > > Probably not, and it's not obvious how to make it work for T2 kernel
> > > builds.  For the time being, I'm going to make this available only for
> > > native ARM builds.  We can think about how to make this work for T2
> > > sometime later.
> > [...]
> > > Indeed, that's only half of the problem.  On T2, some of these may be
> > > 16-bit values, others may be 32-bit values, and this mechanism has no
> > > way to know the size of the areas.
> >
> > We can add the W() macro and they are guaranteed to be 32-bit wide or
> > get a compilation error. Something like using "UP(W(nop))", though it's
> > doesn't look as nice.
> >
> > The usr_ret macro is always compiled to ARM mode anyway.
> 
> That's not the only place - here's another:
> 
> +       ALT_SMP(test_for_ipi r0, r6, r5, lr)
> +       ALT_UP_B(9997f)
> 
> test_for_ipi may be thumb code, which could be 16-bit aligned.

The branch can be 16-bit aligned as well but we would have to change the
fixup loop for Thumb-2 to load/store 2 half-words and avoid an alignment
fault.

Anyway, I agree that for now we should get the ARM builds working and we
can change the Thumb-2 afterwards, as time allows. It doesn't look like
something fundamental would prevent this.

-- 
Catalin

[PATCH 3/6] ARM: Fix v7wbi_tlb_flags for SMP on UP

[Catalin Marinas]

On Mon, 2010-09-06 at 17:36 +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 06, 2010 at 04:53:47PM +0100, Catalin Marinas wrote:
> > On Mon, 2010-09-06 at 16:34 +0100, Russell King - ARM Linux wrote:
> > > On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
> > > > Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
> > > > in the SMP/UP macros to make sure that the instruction is always 32-bit
> > > > wide.
> > >
> > > Probably not, and it's not obvious how to make it work for T2 kernel
> > > builds.  For the time being, I'm going to make this available only for
> > > native ARM builds.  We can think about how to make this work for T2
> > > sometime later.
> > [...]
> > > Indeed, that's only half of the problem.  On T2, some of these may be
> > > 16-bit values, others may be 32-bit values, and this mechanism has no
> > > way to know the size of the areas.
> >
> > We can add the W() macro and they are guaranteed to be 32-bit wide or
> > get a compilation error. Something like using "UP(W(nop))", though it's
> > doesn't look as nice.
> >
> > The usr_ret macro is always compiled to ARM mode anyway.
> 
> That's not the only place - here's another:
> 
> +       ALT_SMP(test_for_ipi r0, r6, r5, lr)
> +       ALT_UP_B(9997f)
> 
> test_for_ipi may be thumb code, which could be 16-bit aligned.

The branch can be 16-bit aligned as well but we would have to change the
fixup loop for Thumb-2 to load/store 2 half-words and avoid an alignment
fault.

Anyway, I agree that for now we should get the ARM builds working and we
can change the Thumb-2 afterwards, as time allows. It doesn't look like
something fundamental would prevent this.

-- 
Catalin

[PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

[Tony Lindgren]

>From f80d3cc85327ba84748646bb44a0c45103ef66bc Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Wed, 1 Sep 2010 20:40:47 -0700
Subject: [PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

Do not call test_for_ipi or test_for_ltrirq on UP systems.

Note that we can't put test_for_ltriq into SMP statement as
it's inlined into the code and the remaining lines of the
macro would still run before UP macro line.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/kernel/entry-armv.S |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb2ef60..b8c1ec7 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -40,6 +40,11 @@
 	bne	asm_do_IRQ
 
 #ifdef CONFIG_SMP
+#ifdef CONFIG_SMP_ON_UP
+	adr	lr, BSYM(2f)	@ set lr to end of macro for early return
+	SMP(nop)		@ continue on SMP hardware
+	UP(mov	pc, lr)		@ return early on UP
+#endif
 	/*
 	 * XXX
 	 *
@@ -57,6 +62,7 @@
 	adrne	lr, BSYM(1b)
 	bne	do_local_timer
 #endif
+2:
 #endif
 
 	.endm
-- 
1.7.1

[PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

[Tony Lindgren]

RE: [PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 9:51 PM
> To: Russell King - ARM Linux
> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: [PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on
> UP systems
> 
> From f80d3cc85327ba84748646bb44a0c45103ef66bc Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Wed, 1 Sep 2010 20:40:47 -0700
> Subject: [PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on
> UP systems
> 
> Do not call test_for_ipi or test_for_ltrirq on UP systems.
> 
> Note that we can't put test_for_ltriq into SMP statement as
> it's inlined into the code and the remaining lines of the
> macro would still run before UP macro line.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/kernel/entry-armv.S |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index bb2ef60..b8c1ec7 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -40,6 +40,11 @@
>  	bne	asm_do_IRQ
> 
>  #ifdef CONFIG_SMP
Do we need this code to be under " CONFIG_SMP" now ?
> +#ifdef CONFIG_SMP_ON_UP
> +	adr	lr, BSYM(2f)	@ set lr to end of macro for early return
> +	SMP(nop)		@ continue on SMP hardware
> +	UP(mov	pc, lr)		@ return early on UP
> +#endif
>  	/*
>  	 * XXX
>  	 *
> @@ -57,6 +62,7 @@
>  	adrne	lr, BSYM(1b)
>  	bne	do_local_timer
>  #endif
> +2:
>  #endif
> 
>  	.endm
> --
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 9:51 PM
> To: Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: [PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on
> UP systems
> 
> From f80d3cc85327ba84748646bb44a0c45103ef66bc Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Wed, 1 Sep 2010 20:40:47 -0700
> Subject: [PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on
> UP systems
> 
> Do not call test_for_ipi or test_for_ltrirq on UP systems.
> 
> Note that we can't put test_for_ltriq into SMP statement as
> it's inlined into the code and the remaining lines of the
> macro would still run before UP macro line.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/kernel/entry-armv.S |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index bb2ef60..b8c1ec7 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -40,6 +40,11 @@
>  	bne	asm_do_IRQ
> 
>  #ifdef CONFIG_SMP
Do we need this code to be under " CONFIG_SMP" now ?
> +#ifdef CONFIG_SMP_ON_UP
> +	adr	lr, BSYM(2f)	@ set lr to end of macro for early return
> +	SMP(nop)		@ continue on SMP hardware
> +	UP(mov	pc, lr)		@ return early on UP
> +#endif
>  	/*
>  	 * XXX
>  	 *
> @@ -57,6 +62,7 @@
>  	adrne	lr, BSYM(1b)
>  	bne	do_local_timer
>  #endif
> +2:
>  #endif
> 
>  	.endm
> --
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 05:30:57PM +0530, Shilimkar, Santosh wrote:
> > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> > index bb2ef60..b8c1ec7 100644
> > --- a/arch/arm/kernel/entry-armv.S
> > +++ b/arch/arm/kernel/entry-armv.S
> > @@ -40,6 +40,11 @@
> >  	bne	asm_do_IRQ
> > 
> >  #ifdef CONFIG_SMP
> Do we need this code to be under " CONFIG_SMP" now ?

Yes, otherwise we get link errors for things like do_IPI and do_local_timer.

[PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 05:30:57PM +0530, Shilimkar, Santosh wrote:
> > diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> > index bb2ef60..b8c1ec7 100644
> > --- a/arch/arm/kernel/entry-armv.S
> > +++ b/arch/arm/kernel/entry-armv.S
> > @@ -40,6 +40,11 @@
> >  	bne	asm_do_IRQ
> > 
> >  #ifdef CONFIG_SMP
> Do we need this code to be under " CONFIG_SMP" now ?

Yes, otherwise we get link errors for things like do_IPI and do_local_timer.

Re: [PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 09:21:24AM -0700, Tony Lindgren wrote:
> Do not call test_for_ipi or test_for_ltrirq on UP systems.
> 
> Note that we can't put test_for_ltriq into SMP statement as
> it's inlined into the code and the remaining lines of the
> macro would still run before UP macro line.

I think we can do better than this - unfortunately the assembler gets
a little difficult (complaining about symbols in different sections),
but it's relatively easy to work-around by precomputing the offset
using .equ.  I'm debating about making this a UP_B(label) and hiding
these details beneath this macro, rather than having this kind of thing
exposed every time we need to do something like this.

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb2ef60..947b3ab 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -46,7 +46,9 @@
 	 * this macro assumes that irqstat (r6) and base (r5) are
 	 * preserved from get_irqnr_and_base above
 	 */
-	test_for_ipi r0, r6, r5, lr
+	SMP(test_for_ipi r0, r6, r5, lr)
+	.equ	off, 9997f - 9998b
+	UP(b	. + off)
 	movne	r0, sp
 	adrne	lr, BSYM(1b)
 	bne	do_IPI
@@ -57,6 +59,7 @@
 	adrne	lr, BSYM(1b)
 	bne	do_local_timer
 #endif
+9997:
 #endif
 
 	.endm

[PATCH 4/6] ARM: Do not call test_for_ipi or test_for_ltrirq on UP systems

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 09:21:24AM -0700, Tony Lindgren wrote:
> Do not call test_for_ipi or test_for_ltrirq on UP systems.
> 
> Note that we can't put test_for_ltriq into SMP statement as
> it's inlined into the code and the remaining lines of the
> macro would still run before UP macro line.

I think we can do better than this - unfortunately the assembler gets
a little difficult (complaining about symbols in different sections),
but it's relatively easy to work-around by precomputing the offset
using .equ.  I'm debating about making this a UP_B(label) and hiding
these details beneath this macro, rather than having this kind of thing
exposed every time we need to do something like this.

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb2ef60..947b3ab 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -46,7 +46,9 @@
 	 * this macro assumes that irqstat (r6) and base (r5) are
 	 * preserved from get_irqnr_and_base above
 	 */
-	test_for_ipi r0, r6, r5, lr
+	SMP(test_for_ipi r0, r6, r5, lr)
+	.equ	off, 9997f - 9998b
+	UP(b	. + off)
 	movne	r0, sp
 	adrne	lr, BSYM(1b)
 	bne	do_IPI
@@ -57,6 +59,7 @@
 	adrne	lr, BSYM(1b)
 	bne	do_local_timer
 #endif
+9997:
 #endif
 
 	.endm

[PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Tony Lindgren]

>From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Mon, 30 Aug 2010 14:03:28 -0700
Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
are also different on A8 and A9.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mm/proc-v7.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 07fc660..51a063d 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -191,7 +191,8 @@ __v7_setup:
 	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
-	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
+	SMP(mcreq	p15, 0, r0, c1, c0, 1)	@ TLB ops broadcasting
+	UP(nop)					@ Don't enable on UP 
 #endif
 	adr	r12, __v7_setup_stack		@ the local stack
 	stmia	r12, {r0-r5, r7, r9, r11, lr}
-- 
1.7.1

[PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Tony Lindgren]

Re: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Mon, 30 Aug 2010 14:03:28 -0700
> Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7
> 
> Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
> are also different on A8 and A9.

This is already taken care of.

> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 07fc660..51a063d 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -191,7 +191,8 @@ __v7_setup:
>  	UP(mov	r0, #(1 << 6))			@ fake it for UP

If it's UP, we set r0 to 1 << 6, which...

>  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?

means this test produces a non-zero result.

>  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting

And therefore these instructions will not be executed.

[PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Mon, 30 Aug 2010 14:03:28 -0700
> Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7
> 
> Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
> are also different on A8 and A9.

This is already taken care of.

> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 07fc660..51a063d 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -191,7 +191,8 @@ __v7_setup:
>  	UP(mov	r0, #(1 << 6))			@ fake it for UP

If it's UP, we set r0 to 1 << 6, which...

>  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?

means this test produces a non-zero result.

>  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting

And therefore these instructions will not be executed.

Re: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:50]:
> On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> > >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Mon, 30 Aug 2010 14:03:28 -0700
> > Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7
> > 
> > Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
> > are also different on A8 and A9.
> 
> This is already taken care of.
> 
> > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > index 07fc660..51a063d 100644
> > --- a/arch/arm/mm/proc-v7.S
> > +++ b/arch/arm/mm/proc-v7.S
> > @@ -191,7 +191,8 @@ __v7_setup:
> >  	UP(mov	r0, #(1 << 6))			@ fake it for UP
> 
> If it's UP, we set r0 to 1 << 6, which...
> 
> >  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> 
> means this test produces a non-zero result.
> 
> >  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> > -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> 
> And therefore these instructions will not be executed.

AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8.

Tony

[PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:50]:
> On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> > >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Mon, 30 Aug 2010 14:03:28 -0700
> > Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7
> > 
> > Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
> > are also different on A8 and A9.
> 
> This is already taken care of.
> 
> > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > index 07fc660..51a063d 100644
> > --- a/arch/arm/mm/proc-v7.S
> > +++ b/arch/arm/mm/proc-v7.S
> > @@ -191,7 +191,8 @@ __v7_setup:
> >  	UP(mov	r0, #(1 << 6))			@ fake it for UP
> 
> If it's UP, we set r0 to 1 << 6, which...
> 
> >  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> 
> means this test produces a non-zero result.
> 
> >  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> > -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> 
> And therefore these instructions will not be executed.

AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8.

Tony

Re: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 10:21:33AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:50]:
> > On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> > > >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
> > > From: Tony Lindgren <tony@atomide.com>
> > > Date: Mon, 30 Aug 2010 14:03:28 -0700
> > > Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7
> > > 
> > > Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
> > > are also different on A8 and A9.
> > 
> > This is already taken care of.
> > 
> > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > > index 07fc660..51a063d 100644
> > > --- a/arch/arm/mm/proc-v7.S
> > > +++ b/arch/arm/mm/proc-v7.S
> > > @@ -191,7 +191,8 @@ __v7_setup:
> > >  	UP(mov	r0, #(1 << 6))			@ fake it for UP
> > 
> > If it's UP, we set r0 to 1 << 6, which...
> > 
> > >  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> > 
> > means this test produces a non-zero result.
> > 
> > >  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> > > -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> > 
> > And therefore these instructions will not be executed.
> 
> AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8.

So what?

[PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 10:21:33AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:50]:
> > On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> > > >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
> > > From: Tony Lindgren <tony@atomide.com>
> > > Date: Mon, 30 Aug 2010 14:03:28 -0700
> > > Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7
> > > 
> > > Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
> > > are also different on A8 and A9.
> > 
> > This is already taken care of.
> > 
> > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > > index 07fc660..51a063d 100644
> > > --- a/arch/arm/mm/proc-v7.S
> > > +++ b/arch/arm/mm/proc-v7.S
> > > @@ -191,7 +191,8 @@ __v7_setup:
> > >  	UP(mov	r0, #(1 << 6))			@ fake it for UP
> > 
> > If it's UP, we set r0 to 1 << 6, which...
> > 
> > >  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> > 
> > means this test produces a non-zero result.
> > 
> > >  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> > > -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> > 
> > And therefore these instructions will not be executed.
> 
> AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8.

So what?

Re: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:54]:
> On Thu, Sep 02, 2010 at 10:21:33AM -0700, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:50]:
> > > On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> > > > >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
> > > > From: Tony Lindgren <tony@atomide.com>
> > > > Date: Mon, 30 Aug 2010 14:03:28 -0700
> > > > Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7
> > > > 
> > > > Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
> > > > are also different on A8 and A9.
> > > 
> > > This is already taken care of.
> > > 
> > > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > > > index 07fc660..51a063d 100644
> > > > --- a/arch/arm/mm/proc-v7.S
> > > > +++ b/arch/arm/mm/proc-v7.S
> > > > @@ -191,7 +191,8 @@ __v7_setup:
> > > >  	UP(mov	r0, #(1 << 6))			@ fake it for UP
> > > 
> > > If it's UP, we set r0 to 1 << 6, which...
> > > 
> > > >  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> > > 
> > > means this test produces a non-zero result.
> > > 
> > > >  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> > > > -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> > > 
> > > And therefore these instructions will not be executed.
> > 
> > AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8.
> 
> So what?

Ah right, sorry I should have looked more carefully. You're right, this patch
is no longer needed either.

Tony

[PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:54]:
> On Thu, Sep 02, 2010 at 10:21:33AM -0700, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:50]:
> > > On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> > > > >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001
> > > > From: Tony Lindgren <tony@atomide.com>
> > > > Date: Mon, 30 Aug 2010 14:03:28 -0700
> > > > Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7
> > > > 
> > > > Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits
> > > > are also different on A8 and A9.
> > > 
> > > This is already taken care of.
> > > 
> > > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > > > index 07fc660..51a063d 100644
> > > > --- a/arch/arm/mm/proc-v7.S
> > > > +++ b/arch/arm/mm/proc-v7.S
> > > > @@ -191,7 +191,8 @@ __v7_setup:
> > > >  	UP(mov	r0, #(1 << 6))			@ fake it for UP
> > > 
> > > If it's UP, we set r0 to 1 << 6, which...
> > > 
> > > >  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> > > 
> > > means this test produces a non-zero result.
> > > 
> > > >  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> > > > -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> > > 
> > > And therefore these instructions will not be executed.
> > 
> > AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8.
> 
> So what?

Ah right, sorry I should have looked more carefully. You're right, this patch
is no longer needed either.

Tony

Re: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 11:13:17AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:54]:
> > On Thu, Sep 02, 2010 at 10:21:33AM -0700, Tony Lindgren wrote:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:50]:
> > > > On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> > > > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > > > > index 07fc660..51a063d 100644
> > > > > --- a/arch/arm/mm/proc-v7.S
> > > > > +++ b/arch/arm/mm/proc-v7.S
> > > > > @@ -191,7 +191,8 @@ __v7_setup:
> > > > >  	UP(mov	r0, #(1 << 6))			@ fake it for UP
> > > > 
> > > > If it's UP, we set r0 to 1 << 6, which...
> > > > 
> > > > >  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> > > > 
> > > > means this test produces a non-zero result.
> > > > 
> > > > >  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> > > > > -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> > > > 
> > > > And therefore these instructions will not be executed.
> > > 
> > > AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8.
> > 
> > So what?
> 
> Ah right, sorry I should have looked more carefully. You're right, this patch
> is no longer needed either.

Thanks - I was wondering whether I was missing something.

[PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7

[Russell King - ARM Linux]

On Thu, Sep 02, 2010 at 11:13:17AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 10:54]:
> > On Thu, Sep 02, 2010 at 10:21:33AM -0700, Tony Lindgren wrote:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 09:50]:
> > > > On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote:
> > > > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> > > > > index 07fc660..51a063d 100644
> > > > > --- a/arch/arm/mm/proc-v7.S
> > > > > +++ b/arch/arm/mm/proc-v7.S
> > > > > @@ -191,7 +191,8 @@ __v7_setup:
> > > > >  	UP(mov	r0, #(1 << 6))			@ fake it for UP
> > > > 
> > > > If it's UP, we set r0 to 1 << 6, which...
> > > > 
> > > > >  	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
> > > > 
> > > > means this test produces a non-zero result.
> > > > 
> > > > >  	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
> > > > > -	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
> > > > 
> > > > And therefore these instructions will not be executed.
> > > 
> > > AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8.
> > 
> > So what?
> 
> Ah right, sorry I should have looked more carefully. You're right, this patch
> is no longer needed either.

Thanks - I was wondering whether I was missing something.

[PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

>From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Tue, 17 Aug 2010 13:33:23 +0300
Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

Fix SMP on UP interrupt handling for multi-omap

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/mach-omap2/omap-smp.c |   13 +++++++++----
 arch/arm/mach-omap2/timer-gp.c |    7 +++++--
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9e9f70e..a8bb49c 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -22,6 +22,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/localtimer.h>
+#include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
 {
 	unsigned int i, ncores;
 
-	/* Never released */
-	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
-	BUG_ON(!scu_base);
+	if (smp_on_up()) {
+		ncores = 1;
+	} else {
+		/* Never released */
+		scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
+		BUG_ON(!scu_base);
 
-	ncores = get_core_count();
+		ncores = get_core_count();
+	}
 
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8..badf5f2 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -37,6 +37,7 @@
 #include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
+#include <asm/smp_plat.h>
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 
@@ -228,8 +229,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-	BUG_ON(!twd_base);
+	if (smp_on_up()) {
+		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+		BUG_ON(!twd_base);
+	}
 #endif
 	omap_dm_timer_init();
 
-- 
1.7.1

[PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 475 bytes --]

* Tony Lindgren <tony@atomide.com> [100902 09:16]:
> From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Tue, 17 Aug 2010 13:33:23 +0300
> Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> 
> Fix SMP on UP interrupt handling for multi-omap

Here's this one updated to use !smp_cpu() instead of smp_on_up().
Looks like the description and subject needed some refreshing too.

Tony

[-- Attachment #2: smp-on-up-omap.patch --]
[-- Type: text/x-diff, Size: 1838 bytes --]

>From e791c682fe2e3989e76f0bce7e0c9d97e65c2137 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Tue, 17 Aug 2010 13:33:23 +0300
Subject: [PATCH] omap: Fix SMP on UP initialization for multi-omap

Fix SMP on UP initialization for multi-omap.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9e9f70e..3695232 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -22,6 +22,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/localtimer.h>
+#include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
 {
 	unsigned int i, ncores;
 
-	/* Never released */
-	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
-	BUG_ON(!scu_base);
+	if (!smp_cpu()) {
+		ncores = 1;
+	} else {
+		/* Never released */
+		scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
+		BUG_ON(!scu_base);
 
-	ncores = get_core_count();
+		ncores = get_core_count();
+	}
 
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8..a21b4a4 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -37,6 +37,7 @@
 #include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
+#include <asm/smp_plat.h>
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 
@@ -228,8 +229,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-	BUG_ON(!twd_base);
+	if (!smp_cpu()) {
+		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+		BUG_ON(!twd_base);
+	}
 #endif
 	omap_dm_timer_init();
 

[PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100902 09:16]:
> From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Tue, 17 Aug 2010 13:33:23 +0300
> Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> 
> Fix SMP on UP interrupt handling for multi-omap

Here's this one updated to use !smp_cpu() instead of smp_on_up().
Looks like the description and subject needed some refreshing too.

Tony

RE: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Friday, September 03, 2010 1:00 AM
> To: Russell King - ARM Linux
> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> 
> * Tony Lindgren <tony@atomide.com> [100902 09:16]:
> > From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Tue, 17 Aug 2010 13:33:23 +0300
> > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> >
> > Fix SMP on UP interrupt handling for multi-omap
> 
> Here's this one updated to use !smp_cpu() instead of smp_on_up().
> Looks like the description and subject needed some refreshing too.
> 
As I commented on other patch we should just avoid doing anything
When the CPU is not OMAP4. 

Regards,
Santosh

[PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Friday, September 03, 2010 1:00 AM
> To: Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> 
> * Tony Lindgren <tony@atomide.com> [100902 09:16]:
> > From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Tue, 17 Aug 2010 13:33:23 +0300
> > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> >
> > Fix SMP on UP interrupt handling for multi-omap
> 
> Here's this one updated to use !smp_cpu() instead of smp_on_up().
> Looks like the description and subject needed some refreshing too.
> 
As I commented on other patch we should just avoid doing anything
When the CPU is not OMAP4. 

Regards,
Santosh

Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100903 05:07]:
> 
> 
> > -----Original Message-----
> > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > owner@vger.kernel.org] On Behalf Of Tony Lindgren
> > Sent: Friday, September 03, 2010 1:00 AM
> > To: Russell King - ARM Linux
> > Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > Bryan Wu; Will Deacon
> > Subject: Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> > omap
> > 
> > * Tony Lindgren <tony@atomide.com> [100902 09:16]:
> > > From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> > > From: Tony Lindgren <tony@atomide.com>
> > > Date: Tue, 17 Aug 2010 13:33:23 +0300
> > > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> > omap
> > >
> > > Fix SMP on UP interrupt handling for multi-omap
> > 
> > Here's this one updated to use !smp_cpu() instead of smp_on_up().
> > Looks like the description and subject needed some refreshing too.
> > 
> As I commented on other patch we should just avoid doing anything
> When the CPU is not OMAP4. 

Looks like the only fix needed now is the localtimer fix. Posted
a patch that uses cpu_is_omap44xx() to test for that.

Tony

[PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100903 05:07]:
> 
> 
> > -----Original Message-----
> > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> > owner at vger.kernel.org] On Behalf Of Tony Lindgren
> > Sent: Friday, September 03, 2010 1:00 AM
> > To: Russell King - ARM Linux
> > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> > Bryan Wu; Will Deacon
> > Subject: Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> > omap
> > 
> > * Tony Lindgren <tony@atomide.com> [100902 09:16]:
> > > From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> > > From: Tony Lindgren <tony@atomide.com>
> > > Date: Tue, 17 Aug 2010 13:33:23 +0300
> > > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> > omap
> > >
> > > Fix SMP on UP interrupt handling for multi-omap
> > 
> > Here's this one updated to use !smp_cpu() instead of smp_on_up().
> > Looks like the description and subject needed some refreshing too.
> > 
> As I commented on other patch we should just avoid doing anything
> When the CPU is not OMAP4. 

Looks like the only fix needed now is the localtimer fix. Posted
a patch that uses cpu_is_omap44xx() to test for that.

Tony

RE: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 9:54 PM
> To: Russell King - ARM Linux
> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> 
> From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Tue, 17 Aug 2010 13:33:23 +0300
> Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> 
> Fix SMP on UP interrupt handling for multi-omap
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/mach-omap2/omap-smp.c |   13 +++++++++----
>  arch/arm/mach-omap2/timer-gp.c |    7 +++++--
>  2 files changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-
> smp.c
> index 9e9f70e..a8bb49c 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -22,6 +22,7 @@
> 
>  #include <asm/cacheflush.h>
>  #include <asm/localtimer.h>
> +#include <asm/smp_plat.h>
>  #include <asm/smp_scu.h>
>  #include <mach/hardware.h>
>  #include <mach/omap4-common.h>
> @@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
>  {
>  	unsigned int i, ncores;
> 
> -	/* Never released */
> -	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
> -	BUG_ON(!scu_base);
> +	if (smp_on_up()) {
> +		ncores = 1;
I am not sure if this is the correct approach. The SCU 
hardware is not present other than OMAP4. So we should
just return here when the silicon is not omap4.
	if (!cpu_is_omap44xx())
		return -ENODEV;
> +	} else {
> +		/* Never released */
> +		scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
> +		BUG_ON(!scu_base);
> 
> -	ncores = get_core_count();
> +		ncores = get_core_count();
> +	}
> 
>  	for (i = 0; i < ncores; i++)
>  		set_cpu_possible(i, true);
> diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-
> gp.c
> index 74fbed8..badf5f2 100644
> --- a/arch/arm/mach-omap2/timer-gp.c
> +++ b/arch/arm/mach-omap2/timer-gp.c
> @@ -37,6 +37,7 @@
>  #include <linux/clockchips.h>
> 
>  #include <asm/mach/time.h>
> +#include <asm/smp_plat.h>
>  #include <plat/dmtimer.h>
>  #include <asm/localtimer.h>
> 
> @@ -228,8 +229,10 @@ static void __init omap2_gp_clocksource_init(void)
>  static void __init omap2_gp_timer_init(void)
>  {
>  #ifdef CONFIG_LOCAL_TIMERS
> -	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> -	BUG_ON(!twd_base);
> +	if (smp_on_up()) {
> +		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> +		BUG_ON(!twd_base);
> +	}
>  #endif
>  	omap_dm_timer_init();
> 
> --
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 9:54 PM
> To: Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> 
> From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Tue, 17 Aug 2010 13:33:23 +0300
> Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> 
> Fix SMP on UP interrupt handling for multi-omap
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/mach-omap2/omap-smp.c |   13 +++++++++----
>  arch/arm/mach-omap2/timer-gp.c |    7 +++++--
>  2 files changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-
> smp.c
> index 9e9f70e..a8bb49c 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -22,6 +22,7 @@
> 
>  #include <asm/cacheflush.h>
>  #include <asm/localtimer.h>
> +#include <asm/smp_plat.h>
>  #include <asm/smp_scu.h>
>  #include <mach/hardware.h>
>  #include <mach/omap4-common.h>
> @@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
>  {
>  	unsigned int i, ncores;
> 
> -	/* Never released */
> -	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
> -	BUG_ON(!scu_base);
> +	if (smp_on_up()) {
> +		ncores = 1;
I am not sure if this is the correct approach. The SCU 
hardware is not present other than OMAP4. So we should
just return here when the silicon is not omap4.
	if (!cpu_is_omap44xx())
		return -ENODEV;
> +	} else {
> +		/* Never released */
> +		scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
> +		BUG_ON(!scu_base);
> 
> -	ncores = get_core_count();
> +		ncores = get_core_count();
> +	}
> 
>  	for (i = 0; i < ncores; i++)
>  		set_cpu_possible(i, true);
> diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-
> gp.c
> index 74fbed8..badf5f2 100644
> --- a/arch/arm/mach-omap2/timer-gp.c
> +++ b/arch/arm/mach-omap2/timer-gp.c
> @@ -37,6 +37,7 @@
>  #include <linux/clockchips.h>
> 
>  #include <asm/mach/time.h>
> +#include <asm/smp_plat.h>
>  #include <plat/dmtimer.h>
>  #include <asm/localtimer.h>
> 
> @@ -228,8 +229,10 @@ static void __init omap2_gp_clocksource_init(void)
>  static void __init omap2_gp_timer_init(void)
>  {
>  #ifdef CONFIG_LOCAL_TIMERS
> -	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> -	BUG_ON(!twd_base);
> +	if (smp_on_up()) {
> +		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> +		BUG_ON(!twd_base);
> +	}
>  #endif
>  	omap_dm_timer_init();
> 
> --
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 05:36:27PM +0530, Shilimkar, Santosh wrote:
> > -----Original Message-----
> > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > owner@vger.kernel.org] On Behalf Of Tony Lindgren
> > Sent: Thursday, September 02, 2010 9:54 PM
> > To: Russell King - ARM Linux
> > Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > Bryan Wu; Will Deacon
> > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> > 
> > From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Tue, 17 Aug 2010 13:33:23 +0300
> > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> > 
> > Fix SMP on UP interrupt handling for multi-omap
> > 
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > ---
> >  arch/arm/mach-omap2/omap-smp.c |   13 +++++++++----
> >  arch/arm/mach-omap2/timer-gp.c |    7 +++++--
> >  2 files changed, 14 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-
> > smp.c
> > index 9e9f70e..a8bb49c 100644
> > --- a/arch/arm/mach-omap2/omap-smp.c
> > +++ b/arch/arm/mach-omap2/omap-smp.c
> > @@ -22,6 +22,7 @@
> > 
> >  #include <asm/cacheflush.h>
> >  #include <asm/localtimer.h>
> > +#include <asm/smp_plat.h>
> >  #include <asm/smp_scu.h>
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > @@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
> >  {
> >  	unsigned int i, ncores;
> > 
> > -	/* Never released */
> > -	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
> > -	BUG_ON(!scu_base);
> > +	if (smp_on_up()) {
> > +		ncores = 1;
> I am not sure if this is the correct approach. The SCU 
> hardware is not present other than OMAP4. So we should
> just return here when the silicon is not omap4.
> 	if (!cpu_is_omap44xx())
> 		return -ENODEV;

void function returning a value?  Just a simple return statement will do.

[PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 05:36:27PM +0530, Shilimkar, Santosh wrote:
> > -----Original Message-----
> > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> > owner at vger.kernel.org] On Behalf Of Tony Lindgren
> > Sent: Thursday, September 02, 2010 9:54 PM
> > To: Russell King - ARM Linux
> > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> > Bryan Wu; Will Deacon
> > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> > 
> > From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> > From: Tony Lindgren <tony@atomide.com>
> > Date: Tue, 17 Aug 2010 13:33:23 +0300
> > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap
> > 
> > Fix SMP on UP interrupt handling for multi-omap
> > 
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > ---
> >  arch/arm/mach-omap2/omap-smp.c |   13 +++++++++----
> >  arch/arm/mach-omap2/timer-gp.c |    7 +++++--
> >  2 files changed, 14 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-
> > smp.c
> > index 9e9f70e..a8bb49c 100644
> > --- a/arch/arm/mach-omap2/omap-smp.c
> > +++ b/arch/arm/mach-omap2/omap-smp.c
> > @@ -22,6 +22,7 @@
> > 
> >  #include <asm/cacheflush.h>
> >  #include <asm/localtimer.h>
> > +#include <asm/smp_plat.h>
> >  #include <asm/smp_scu.h>
> >  #include <mach/hardware.h>
> >  #include <mach/omap4-common.h>
> > @@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
> >  {
> >  	unsigned int i, ncores;
> > 
> > -	/* Never released */
> > -	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
> > -	BUG_ON(!scu_base);
> > +	if (smp_on_up()) {
> > +		ncores = 1;
> I am not sure if this is the correct approach. The SCU 
> hardware is not present other than OMAP4. So we should
> just return here when the silicon is not omap4.
> 	if (!cpu_is_omap44xx())
> 		return -ENODEV;

void function returning a value?  Just a simple return statement will do.

RE: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> Sent: Saturday, September 04, 2010 4:35 PM
> To: Shilimkar, Santosh
> Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Bryan Wu; Will Deacon
> Subject: Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> 
> On Fri, Sep 03, 2010 at 05:36:27PM +0530, Shilimkar, Santosh wrote:
> > > -----Original Message-----
> > > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > > owner@vger.kernel.org] On Behalf Of Tony Lindgren
> > > Sent: Thursday, September 02, 2010 9:54 PM
> > > To: Russell King - ARM Linux
> > > Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > Bryan Wu; Will Deacon
> > > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> > >
> > > From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> > > From: Tony Lindgren <tony@atomide.com>
> > > Date: Tue, 17 Aug 2010 13:33:23 +0300
> > > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> > >
> > > Fix SMP on UP interrupt handling for multi-omap
> > >
> > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > ---
> > >  arch/arm/mach-omap2/omap-smp.c |   13 +++++++++----
> > >  arch/arm/mach-omap2/timer-gp.c |    7 +++++--
> > >  2 files changed, 14 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-
> omap2/omap-
> > > smp.c
> > > index 9e9f70e..a8bb49c 100644
> > > --- a/arch/arm/mach-omap2/omap-smp.c
> > > +++ b/arch/arm/mach-omap2/omap-smp.c
> > > @@ -22,6 +22,7 @@
> > >
> > >  #include <asm/cacheflush.h>
> > >  #include <asm/localtimer.h>
> > > +#include <asm/smp_plat.h>
> > >  #include <asm/smp_scu.h>
> > >  #include <mach/hardware.h>
> > >  #include <mach/omap4-common.h>
> > > @@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
> > >  {
> > >  	unsigned int i, ncores;
> > >
> > > -	/* Never released */
> > > -	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
> > > -	BUG_ON(!scu_base);
> > > +	if (smp_on_up()) {
> > > +		ncores = 1;
> > I am not sure if this is the correct approach. The SCU
> > hardware is not present other than OMAP4. So we should
> > just return here when the silicon is not omap4.
> > 	if (!cpu_is_omap44xx())
> > 		return -ENODEV;
> 
> void function returning a value?  Just a simple return statement will do.
Oh yes.

[PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Saturday, September 04, 2010 4:35 PM
> To: Shilimkar, Santosh
> Cc: Tony Lindgren; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Bryan Wu; Will Deacon
> Subject: Re: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> 
> On Fri, Sep 03, 2010 at 05:36:27PM +0530, Shilimkar, Santosh wrote:
> > > -----Original Message-----
> > > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> > > owner at vger.kernel.org] On Behalf Of Tony Lindgren
> > > Sent: Thursday, September 02, 2010 9:54 PM
> > > To: Russell King - ARM Linux
> > > Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> > > Bryan Wu; Will Deacon
> > > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> > >
> > > From c04a57fc3b41d886f56ccdc27cf9758de0c95202 Mon Sep 17 00:00:00 2001
> > > From: Tony Lindgren <tony@atomide.com>
> > > Date: Tue, 17 Aug 2010 13:33:23 +0300
> > > Subject: [PATCH 6/6] omap: Fix SMP on UP interrupt handling for multi-
> omap
> > >
> > > Fix SMP on UP interrupt handling for multi-omap
> > >
> > > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > > ---
> > >  arch/arm/mach-omap2/omap-smp.c |   13 +++++++++----
> > >  arch/arm/mach-omap2/timer-gp.c |    7 +++++--
> > >  2 files changed, 14 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-
> omap2/omap-
> > > smp.c
> > > index 9e9f70e..a8bb49c 100644
> > > --- a/arch/arm/mach-omap2/omap-smp.c
> > > +++ b/arch/arm/mach-omap2/omap-smp.c
> > > @@ -22,6 +22,7 @@
> > >
> > >  #include <asm/cacheflush.h>
> > >  #include <asm/localtimer.h>
> > > +#include <asm/smp_plat.h>
> > >  #include <asm/smp_scu.h>
> > >  #include <mach/hardware.h>
> > >  #include <mach/omap4-common.h>
> > > @@ -114,11 +115,15 @@ void __init smp_init_cpus(void)
> > >  {
> > >  	unsigned int i, ncores;
> > >
> > > -	/* Never released */
> > > -	scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
> > > -	BUG_ON(!scu_base);
> > > +	if (smp_on_up()) {
> > > +		ncores = 1;
> > I am not sure if this is the correct approach. The SCU
> > hardware is not present other than OMAP4. So we should
> > just return here when the silicon is not omap4.
> > 	if (!cpu_is_omap44xx())
> > 		return -ENODEV;
> 
> void function returning a value?  Just a simple return statement will do.
Oh yes.

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Bryan Wu]

On Fri, Sep 3, 2010 at 12:16 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:29]:
>> On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
>> > * Tony Lindgren <tony@atomide.com> [100820 04:59]:
>> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
>> > > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
>> > > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
>> > > > > returning early before smp_on_up does not produce that.
>> > > >
>> > > > It's probably overwriting some register it shouldn't be.  I might be
>> > > > able to look at this sometime during the coming week... assuming that
>> > > > the weather is as bad as they forecast and I have 'net connectivity.
>> >
>> > This seems to fix it.
>>
>> Thanks, merged that into my original patch - so here it is again with
>> everything updated.
>
> Your patch sure makes things simpler! The problem still is the
> V6 vs V7 SMP code though.
>
> Will post my six patches that apply on top of your patch as a reply to
> this mail. With those, everything seems to work, at least after testing
> on omap3630 (Cortex-A8 UP) and omap4430 (Cortex-A9 SMP).

Awesome, where can get those finalize the patches for testing? After
that I can test our Ubuntu kernel on both boards.

Thanks,
-Bryan
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[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Bryan Wu]

On Fri, Sep 3, 2010 at 12:16 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:29]:
>> On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
>> > * Tony Lindgren <tony@atomide.com> [100820 04:59]:
>> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
>> > > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
>> > > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
>> > > > > returning early before smp_on_up does not produce that.
>> > > >
>> > > > It's probably overwriting some register it shouldn't be. ?I might be
>> > > > able to look at this sometime during the coming week... assuming that
>> > > > the weather is as bad as they forecast and I have 'net connectivity.
>> >
>> > This seems to fix it.
>>
>> Thanks, merged that into my original patch - so here it is again with
>> everything updated.
>
> Your patch sure makes things simpler! The problem still is the
> V6 vs V7 SMP code though.
>
> Will post my six patches that apply on top of your patch as a reply to
> this mail. With those, everything seems to work, at least after testing
> on omap3630 (Cortex-A8 UP) and omap4430 (Cortex-A9 SMP).

Awesome, where can get those finalize the patches for testing? After
that I can test our Ubuntu kernel on both boards.

Thanks,
-Bryan

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 12:20:26PM +0800, Bryan Wu wrote:
> Awesome, where can get those finalize the patches for testing? After
> that I can test our Ubuntu kernel on both boards.

Not yet - they're work in progress.  Final patches will probably be a
few days yet.

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 12:20:26PM +0800, Bryan Wu wrote:
> Awesome, where can get those finalize the patches for testing? After
> that I can test our Ubuntu kernel on both boards.

Not yet - they're work in progress.  Final patches will probably be a
few days yet.

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Catalin Marinas]

On Thu, 2010-09-02 at 17:16 +0100, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:29]:
> > On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
> > > * Tony Lindgren <tony@atomide.com> [100820 04:59]:
> > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > > > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > > > > returning early before smp_on_up does not produce that.
> > > > >
> > > > > It's probably overwriting some register it shouldn't be.  I might be
> > > > > able to look at this sometime during the coming week... assuming that
> > > > > the weather is as bad as they forecast and I have 'net connectivity.
> > >
> > > This seems to fix it.
> >
> > Thanks, merged that into my original patch - so here it is again with
> > everything updated.
> 
> Your patch sure makes things simpler! The problem still is the
> V6 vs V7 SMP code though.

I haven't followed your patches closely but can we restrict the ARMv6
SMP/UP support to only those cores that have TEX remapping (most of them
probably)?

-- 
Catalin

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Catalin Marinas]

On Thu, 2010-09-02 at 17:16 +0100, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:29]:
> > On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
> > > * Tony Lindgren <tony@atomide.com> [100820 04:59]:
> > > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > > > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > > > > returning early before smp_on_up does not produce that.
> > > > >
> > > > > It's probably overwriting some register it shouldn't be.  I might be
> > > > > able to look at this sometime during the coming week... assuming that
> > > > > the weather is as bad as they forecast and I have 'net connectivity.
> > >
> > > This seems to fix it.
> >
> > Thanks, merged that into my original patch - so here it is again with
> > everything updated.
> 
> Your patch sure makes things simpler! The problem still is the
> V6 vs V7 SMP code though.

I haven't followed your patches closely but can we restrict the ARMv6
SMP/UP support to only those cores that have TEX remapping (most of them
probably)?

-- 
Catalin

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Mon, Sep 06, 2010 at 10:28:53AM +0100, Catalin Marinas wrote:
> I haven't followed your patches closely but can we restrict the ARMv6
> SMP/UP support to only those cores that have TEX remapping (most of them
> probably)?

We don't support TEX remapping on ARMv6.

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Mon, Sep 06, 2010 at 10:28:53AM +0100, Catalin Marinas wrote:
> I haven't followed your patches closely but can we restrict the ARMv6
> SMP/UP support to only those cores that have TEX remapping (most of them
> probably)?

We don't support TEX remapping on ARMv6.

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Catalin Marinas]

On Mon, 2010-09-06 at 10:34 +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 06, 2010 at 10:28:53AM +0100, Catalin Marinas wrote:
> > I haven't followed your patches closely but can we restrict the ARMv6
> > SMP/UP support to only those cores that have TEX remapping (most of them
> > probably)?
> 
> We don't support TEX remapping on ARMv6.

I know but it's easy to enable if useful for the SMP/UP v6/v7
combination (with some restrictions).

-- 
Catalin

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Catalin Marinas]

On Mon, 2010-09-06 at 10:34 +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 06, 2010 at 10:28:53AM +0100, Catalin Marinas wrote:
> > I haven't followed your patches closely but can we restrict the ARMv6
> > SMP/UP support to only those cores that have TEX remapping (most of them
> > probably)?
> 
> We don't support TEX remapping on ARMv6.

I know but it's easy to enable if useful for the SMP/UP v6/v7
combination (with some restrictions).

-- 
Catalin

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Mon, Sep 06, 2010 at 10:38:30AM +0100, Catalin Marinas wrote:
> On Mon, 2010-09-06 at 10:34 +0100, Russell King - ARM Linux wrote:
> > On Mon, Sep 06, 2010 at 10:28:53AM +0100, Catalin Marinas wrote:
> > > I haven't followed your patches closely but can we restrict the ARMv6
> > > SMP/UP support to only those cores that have TEX remapping (most of them
> > > probably)?
> > 
> > We don't support TEX remapping on ARMv6.
> 
> I know but it's easy to enable if useful for the SMP/UP v6/v7
> combination (with some restrictions).

It'll make proc-v6.S much more complicated than it already is, requiring
it to carry both the non-remap and remapping code selected via an ifdef.

Is it worth it?  For the sake of one conditional in mmu.c, I don't think
so - and the view is that using TEX remapping to get rid of the shared
bit is a horrible hack anyway.

In any case, it's unnecessary.  We can use my word-replacement to modify
a variable to indicate whether we're running on SMP or not, and so have
the test for SMP-on-UP in just one place.  Like this:

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..7de5aa5 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -18,4 +18,19 @@ static inline int cache_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 
+/*
+ * Return true if we are running on a SMP platform
+ */
+static inline bool is_smp(void)
+{
+#ifndef CONFIG_SMP
+	return false;
+#elif defined(CONFIG_SMP_ON_UP)
+	extern unsigned int smp_on_up;
+	return !!smp_on_up;
+#else
+	return true;
+#endif
+}
+
 #endif
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 26ec521..360bf06 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -343,7 +343,7 @@ __fixup_smp:
 	orr	r7, r7, #0x41000000	@ val 0x41070000
 	and	r0, r9, r6
 	teq	r0, r7			@ ARM CPU and ARMv6/v7?
-	bne	smp_on_up		@ no, assume UP
+	bne	fixup_smp_on_up		@ no, assume UP
 
 	orr	r6, r6, #0x0000ff00
 	orr	r6, r6, #0x000000f0	@ mask 0xff07fff0
@@ -357,7 +357,7 @@ __fixup_smp:
 	tst	r0, #1 << 31
 	movne	pc, lr			@ bit 31 => SMP
 
-smp_on_up:
+fixup_smp_on_up:
 	adr	r0, 1f
 	ldmia	r0, {r3, r6, r7}
 	sub	r3, r0, r3
@@ -373,6 +373,14 @@ ENDPROC(__fixup_smp)
 1:	.word	.
 	.word	__smpalt_begin
 	.word	__smpalt_end
+
+	.pushsection .data
+	.globl	smp_on_up
+smp_on_up:
+	SMP(.long	1)
+	UP(.long	0)
+	.popsection
+
 #endif
 
 #include "head-common.S"
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d5231ae..fe94467 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -36,6 +36,7 @@
 #include <asm/procinfo.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
+#include <asm/smp_plat.h>
 #include <asm/mach-types.h>
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
@@ -824,9 +825,8 @@ void __init setup_arch(char **cmdline_p)
 	paging_init(mdesc);
 	request_standard_resources(&meminfo, mdesc);
 
-#ifdef CONFIG_SMP
-	smp_init_cpus();
-#endif
+	if (is_smp())
+		smp_init_cpus();
 	reserve_crashkernel();
 
 	cpu_init();
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..a789320 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -303,9 +303,8 @@ static void __init build_mem_type_table(void)
 			cachepolicy = CPOLICY_WRITEBACK;
 		ecc_mask = 0;
 	}
-#ifdef CONFIG_SMP
-	cachepolicy = CPOLICY_WRITEALLOC;
-#endif
+	if (is_smp())
+		cachepolicy = CPOLICY_WRITEALLOC;
 
 	/*
 	 * Strip out features not present on earlier architectures.
@@ -399,13 +398,11 @@ static void __init build_mem_type_table(void)
 	cp = &cache_policies[cachepolicy];
 	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
-#ifndef CONFIG_SMP
 	/*
 	 * Only use write-through for non-SMP systems
 	 */
-	if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
+	if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 		vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
-#endif
 
 	/*
 	 * Enable CPU-specific coherency if supported.
@@ -426,20 +423,21 @@ static void __init build_mem_type_table(void)
 		mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 
-#ifdef CONFIG_SMP
-		/*
-		 * Mark memory with the "shared" attribute for SMP systems
-		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-#endif
+		if (is_smp()) {
+			/*
+			 * Mark memory with the "shared" attribute
+			 * for SMP systems
+			 */
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 	}
 
 	/*
@@ -802,8 +800,7 @@ static void __init sanity_check_meminfo(void)
 			 * rather difficult.
 			 */
 			reason = "with VIPT aliasing cache";
-#ifdef CONFIG_SMP
-		} else if (tlb_ops_need_broadcast()) {
+		} else if (is_smp() && tlb_ops_need_broadcast()) {
 			/*
 			 * kmap_high needs to occasionally flush TLB entries,
 			 * however, if the TLB entries need to be broadcast
@@ -813,7 +810,6 @@ static void __init sanity_check_meminfo(void)
 			 *   (must not be called with irqs off)
 			 */
 			reason = "without hardware TLB ops broadcasting";
-#endif
 		}
 		if (reason) {
 			printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Mon, Sep 06, 2010 at 10:38:30AM +0100, Catalin Marinas wrote:
> On Mon, 2010-09-06 at 10:34 +0100, Russell King - ARM Linux wrote:
> > On Mon, Sep 06, 2010 at 10:28:53AM +0100, Catalin Marinas wrote:
> > > I haven't followed your patches closely but can we restrict the ARMv6
> > > SMP/UP support to only those cores that have TEX remapping (most of them
> > > probably)?
> > 
> > We don't support TEX remapping on ARMv6.
> 
> I know but it's easy to enable if useful for the SMP/UP v6/v7
> combination (with some restrictions).

It'll make proc-v6.S much more complicated than it already is, requiring
it to carry both the non-remap and remapping code selected via an ifdef.

Is it worth it?  For the sake of one conditional in mmu.c, I don't think
so - and the view is that using TEX remapping to get rid of the shared
bit is a horrible hack anyway.

In any case, it's unnecessary.  We can use my word-replacement to modify
a variable to indicate whether we're running on SMP or not, and so have
the test for SMP-on-UP in just one place.  Like this:

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..7de5aa5 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -18,4 +18,19 @@ static inline int cache_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 
+/*
+ * Return true if we are running on a SMP platform
+ */
+static inline bool is_smp(void)
+{
+#ifndef CONFIG_SMP
+	return false;
+#elif defined(CONFIG_SMP_ON_UP)
+	extern unsigned int smp_on_up;
+	return !!smp_on_up;
+#else
+	return true;
+#endif
+}
+
 #endif
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 26ec521..360bf06 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -343,7 +343,7 @@ __fixup_smp:
 	orr	r7, r7, #0x41000000	@ val 0x41070000
 	and	r0, r9, r6
 	teq	r0, r7			@ ARM CPU and ARMv6/v7?
-	bne	smp_on_up		@ no, assume UP
+	bne	fixup_smp_on_up		@ no, assume UP
 
 	orr	r6, r6, #0x0000ff00
 	orr	r6, r6, #0x000000f0	@ mask 0xff07fff0
@@ -357,7 +357,7 @@ __fixup_smp:
 	tst	r0, #1 << 31
 	movne	pc, lr			@ bit 31 => SMP
 
-smp_on_up:
+fixup_smp_on_up:
 	adr	r0, 1f
 	ldmia	r0, {r3, r6, r7}
 	sub	r3, r0, r3
@@ -373,6 +373,14 @@ ENDPROC(__fixup_smp)
 1:	.word	.
 	.word	__smpalt_begin
 	.word	__smpalt_end
+
+	.pushsection .data
+	.globl	smp_on_up
+smp_on_up:
+	SMP(.long	1)
+	UP(.long	0)
+	.popsection
+
 #endif
 
 #include "head-common.S"
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d5231ae..fe94467 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -36,6 +36,7 @@
 #include <asm/procinfo.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
+#include <asm/smp_plat.h>
 #include <asm/mach-types.h>
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
@@ -824,9 +825,8 @@ void __init setup_arch(char **cmdline_p)
 	paging_init(mdesc);
 	request_standard_resources(&meminfo, mdesc);
 
-#ifdef CONFIG_SMP
-	smp_init_cpus();
-#endif
+	if (is_smp())
+		smp_init_cpus();
 	reserve_crashkernel();
 
 	cpu_init();
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..a789320 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -303,9 +303,8 @@ static void __init build_mem_type_table(void)
 			cachepolicy = CPOLICY_WRITEBACK;
 		ecc_mask = 0;
 	}
-#ifdef CONFIG_SMP
-	cachepolicy = CPOLICY_WRITEALLOC;
-#endif
+	if (is_smp())
+		cachepolicy = CPOLICY_WRITEALLOC;
 
 	/*
 	 * Strip out features not present on earlier architectures.
@@ -399,13 +398,11 @@ static void __init build_mem_type_table(void)
 	cp = &cache_policies[cachepolicy];
 	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
-#ifndef CONFIG_SMP
 	/*
 	 * Only use write-through for non-SMP systems
 	 */
-	if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
+	if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 		vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
-#endif
 
 	/*
 	 * Enable CPU-specific coherency if supported.
@@ -426,20 +423,21 @@ static void __init build_mem_type_table(void)
 		mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 
-#ifdef CONFIG_SMP
-		/*
-		 * Mark memory with the "shared" attribute for SMP systems
-		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-#endif
+		if (is_smp()) {
+			/*
+			 * Mark memory with the "shared" attribute
+			 * for SMP systems
+			 */
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 	}
 
 	/*
@@ -802,8 +800,7 @@ static void __init sanity_check_meminfo(void)
 			 * rather difficult.
 			 */
 			reason = "with VIPT aliasing cache";
-#ifdef CONFIG_SMP
-		} else if (tlb_ops_need_broadcast()) {
+		} else if (is_smp() && tlb_ops_need_broadcast()) {
 			/*
 			 * kmap_high needs to occasionally flush TLB entries,
 			 * however, if the TLB entries need to be broadcast
@@ -813,7 +810,6 @@ static void __init sanity_check_meminfo(void)
 			 *   (must not be called with irqs off)
 			 */
 			reason = "without hardware TLB ops broadcasting";
-#endif
 		}
 		if (reason) {
 			printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Catalin Marinas]

On Mon, 2010-09-06 at 11:06 +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 06, 2010 at 10:38:30AM +0100, Catalin Marinas wrote:
> > On Mon, 2010-09-06 at 10:34 +0100, Russell King - ARM Linux wrote:
> > > On Mon, Sep 06, 2010 at 10:28:53AM +0100, Catalin Marinas wrote:
> > > > I haven't followed your patches closely but can we restrict the ARMv6
> > > > SMP/UP support to only those cores that have TEX remapping (most of them
> > > > probably)?
> > >
> > > We don't support TEX remapping on ARMv6.
> >
> > I know but it's easy to enable if useful for the SMP/UP v6/v7
> > combination (with some restrictions).
> 
> It'll make proc-v6.S much more complicated than it already is, requiring
> it to carry both the non-remap and remapping code selected via an ifdef.
> 
> Is it worth it?  For the sake of one conditional in mmu.c, I don't think
> so - and the view is that using TEX remapping to get rid of the shared
> bit is a horrible hack anyway.
> 
> In any case, it's unnecessary.  We can use my word-replacement to modify
> a variable to indicate whether we're running on SMP or not, and so have
> the test for SMP-on-UP in just one place.  Like this:

It looks fine to me. Thanks.

-- 
Catalin

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Catalin Marinas]

On Mon, 2010-09-06 at 11:06 +0100, Russell King - ARM Linux wrote:
> On Mon, Sep 06, 2010 at 10:38:30AM +0100, Catalin Marinas wrote:
> > On Mon, 2010-09-06 at 10:34 +0100, Russell King - ARM Linux wrote:
> > > On Mon, Sep 06, 2010 at 10:28:53AM +0100, Catalin Marinas wrote:
> > > > I haven't followed your patches closely but can we restrict the ARMv6
> > > > SMP/UP support to only those cores that have TEX remapping (most of them
> > > > probably)?
> > >
> > > We don't support TEX remapping on ARMv6.
> >
> > I know but it's easy to enable if useful for the SMP/UP v6/v7
> > combination (with some restrictions).
> 
> It'll make proc-v6.S much more complicated than it already is, requiring
> it to carry both the non-remap and remapping code selected via an ifdef.
> 
> Is it worth it?  For the sake of one conditional in mmu.c, I don't think
> so - and the view is that using TEX remapping to get rid of the shared
> bit is a horrible hack anyway.
> 
> In any case, it's unnecessary.  We can use my word-replacement to modify
> a variable to indicate whether we're running on SMP or not, and so have
> the test for SMP-on-UP in just one place.  Like this:

It looks fine to me. Thanks.

-- 
Catalin

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Thu, Aug 19, 2010 at 10:38:11AM +0300, Tony Lindgren wrote:
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -346,8 +346,10 @@ __fixup_smp:
>  	bne	smp_on_up		@ no, assume UP
>  	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
>  	movs	r0, r0, lsr #30
> -	teqne	r0, #3			@ check top two bits 00 or 11
> -	moveq	pc, lr
> +	teq	r0, #0			@ check two top bits 00
> +	beq	smp_on_up		@ yes, assume UP
> +	teq	r0, #3			@ check top two bits 11
> +	movne	pc, lr			@ no, running on SMP hw

This should be:

	movs	r0, r0, lsr #30
	teqne	r0, #3
	movne	pc, lr

so that 0 or 3 avoids the return.

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Thu, Aug 19, 2010 at 10:38:11AM +0300, Tony Lindgren wrote:
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -346,8 +346,10 @@ __fixup_smp:
>  	bne	smp_on_up		@ no, assume UP
>  	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
>  	movs	r0, r0, lsr #30
> -	teqne	r0, #3			@ check top two bits 00 or 11
> -	moveq	pc, lr
> +	teq	r0, #0			@ check two top bits 00
> +	beq	smp_on_up		@ yes, assume UP
> +	teq	r0, #3			@ check top two bits 11
> +	movne	pc, lr			@ no, running on SMP hw

This should be:

	movs	r0, r0, lsr #30
	teqne	r0, #3
	movne	pc, lr

so that 0 or 3 avoids the return.

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 951 bytes --]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:25]:
> On Thu, Aug 19, 2010 at 10:38:11AM +0300, Tony Lindgren wrote:
> > --- a/arch/arm/kernel/head.S
> > +++ b/arch/arm/kernel/head.S
> > @@ -346,8 +346,10 @@ __fixup_smp:
> >  	bne	smp_on_up		@ no, assume UP
> >  	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
> >  	movs	r0, r0, lsr #30
> > -	teqne	r0, #3			@ check top two bits 00 or 11
> > -	moveq	pc, lr
> > +	teq	r0, #0			@ check two top bits 00
> > +	beq	smp_on_up		@ yes, assume UP
> > +	teq	r0, #3			@ check top two bits 11
> > +	movne	pc, lr			@ no, running on SMP hw
> 
> This should be:
> 
> 	movs	r0, r0, lsr #30
> 	teqne	r0, #3
> 	movne	pc, lr
> 
> so that 0 or 3 avoids the return.

Actually should also handle value of 1:

31	30
0	0	Not using new register, assume not SMP
0	1	Not using new register, assume not SMP
1	0	Using new register, SMP
1	1	Using new register, UP

So we should return early only if it's 2.

Regards,

Tony

[-- Attachment #2: fix-assembly-smp-detection.patch --]
[-- Type: text/x-diff, Size: 738 bytes --]

>From 22aaafd2659b95dc1434c5d6dbb7403329d51b90 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Thu, 2 Sep 2010 17:51:42 -0700
Subject: [PATCH] Fix smp_on_up detection

This is needed to detect UP properly on older ARMv7 like Cortex-A8.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 0b4a626..86aa36d 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -346,8 +346,8 @@ __fixup_smp:
 	bne	smp_on_up		@ no, assume UP
 	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
 	movs	r0, r0, lsr #30
-	teqne	r0, #3			@ check top two bits 00 or 11
-	movne	pc, lr
+	teq	r0, #2			@ check top two bits, 10 for SMP
+	moveq	pc, lr
 
 smp_on_up:
 	adr	r0, 1f

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:25]:
> On Thu, Aug 19, 2010 at 10:38:11AM +0300, Tony Lindgren wrote:
> > --- a/arch/arm/kernel/head.S
> > +++ b/arch/arm/kernel/head.S
> > @@ -346,8 +346,10 @@ __fixup_smp:
> >  	bne	smp_on_up		@ no, assume UP
> >  	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
> >  	movs	r0, r0, lsr #30
> > -	teqne	r0, #3			@ check top two bits 00 or 11
> > -	moveq	pc, lr
> > +	teq	r0, #0			@ check two top bits 00
> > +	beq	smp_on_up		@ yes, assume UP
> > +	teq	r0, #3			@ check top two bits 11
> > +	movne	pc, lr			@ no, running on SMP hw
> 
> This should be:
> 
> 	movs	r0, r0, lsr #30
> 	teqne	r0, #3
> 	movne	pc, lr
> 
> so that 0 or 3 avoids the return.

Actually should also handle value of 1:

31	30
0	0	Not using new register, assume not SMP
0	1	Not using new register, assume not SMP
1	0	Using new register, SMP
1	1	Using new register, UP

So we should return early only if it's 2.

Regards,

Tony

RE: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Will Deacon]

Hi Tony,

> Hi all,
> 
> Here are some experimental patches to allow booting ARMv7 SMP
> kernel on UP to some extent. Posting these early in case it is
> of any help as I know at least Bryan Wu is working on similar
> issues.
> 
> The patches are very much work in progress, and does not quite
> boot to init yet so there's all kinds of things to fix. But at
> least these patches allow booting to the point where the fixing
> issues might be a bit easier.. Currently it boots to the point
> where there are tons of "WARNING: at mm/percpu-vm.c:320 pcpu_alloc"
> prints.

I've got some similar hacks for the RealView boards which I've used
to build a Kernel that can boot on the PB-A8 and PBX-A9. Whilst this
is the wrong way of going about solving the problem [Russell's code
patching is a lot neater and more scaleable] you might be interested
in looking at the code anyway:

http://www.linux-arm.org/git?p=linux-2.6-wd.git;a=shortlog;h=refs/heads/smp-up-hacks

Only v7 cores are supported and TEX remapping is used to avoid having
to worry about setting the shared attribute at runtime. Yuck!

Will

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Will Deacon]

Hi Tony,

> Hi all,
> 
> Here are some experimental patches to allow booting ARMv7 SMP
> kernel on UP to some extent. Posting these early in case it is
> of any help as I know at least Bryan Wu is working on similar
> issues.
> 
> The patches are very much work in progress, and does not quite
> boot to init yet so there's all kinds of things to fix. But at
> least these patches allow booting to the point where the fixing
> issues might be a bit easier.. Currently it boots to the point
> where there are tons of "WARNING: at mm/percpu-vm.c:320 pcpu_alloc"
> prints.

I've got some similar hacks for the RealView boards which I've used
to build a Kernel that can boot on the PB-A8 and PBX-A9. Whilst this
is the wrong way of going about solving the problem [Russell's code
patching is a lot neater and more scaleable] you might be interested
in looking at the code anyway:

http://www.linux-arm.org/git?p=linux-2.6-wd.git;a=shortlog;h=refs/heads/smp-up-hacks

Only v7 cores are supported and TEX remapping is used to avoid having
to worry about setting the shared attribute at runtime. Yuck!

Will

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Will Deacon <will.deacon@arm.com> [100823 09:51]:
> Hi Tony,
> 
> > Hi all,
> > 
> > Here are some experimental patches to allow booting ARMv7 SMP
> > kernel on UP to some extent. Posting these early in case it is
> > of any help as I know at least Bryan Wu is working on similar
> > issues.
> > 
> > The patches are very much work in progress, and does not quite
> > boot to init yet so there's all kinds of things to fix. But at
> > least these patches allow booting to the point where the fixing
> > issues might be a bit easier.. Currently it boots to the point
> > where there are tons of "WARNING: at mm/percpu-vm.c:320 pcpu_alloc"
> > prints.
> 
> I've got some similar hacks for the RealView boards which I've used
> to build a Kernel that can boot on the PB-A8 and PBX-A9. Whilst this
> is the wrong way of going about solving the problem [Russell's code
> patching is a lot neater and more scaleable] you might be interested
> in looking at the code anyway:
> 
> http://www.linux-arm.org/git?p=linux-2.6-wd.git;a=shortlog;h=refs/heads/smp-up-hacks
> 
> Only v7 cores are supported and TEX remapping is used to avoid having
> to worry about setting the shared attribute at runtime. Yuck!

Heh cool, I'll take a look at those :)

Tony

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Will Deacon <will.deacon@arm.com> [100823 09:51]:
> Hi Tony,
> 
> > Hi all,
> > 
> > Here are some experimental patches to allow booting ARMv7 SMP
> > kernel on UP to some extent. Posting these early in case it is
> > of any help as I know at least Bryan Wu is working on similar
> > issues.
> > 
> > The patches are very much work in progress, and does not quite
> > boot to init yet so there's all kinds of things to fix. But at
> > least these patches allow booting to the point where the fixing
> > issues might be a bit easier.. Currently it boots to the point
> > where there are tons of "WARNING: at mm/percpu-vm.c:320 pcpu_alloc"
> > prints.
> 
> I've got some similar hacks for the RealView boards which I've used
> to build a Kernel that can boot on the PB-A8 and PBX-A9. Whilst this
> is the wrong way of going about solving the problem [Russell's code
> patching is a lot neater and more scaleable] you might be interested
> in looking at the code anyway:
> 
> http://www.linux-arm.org/git?p=linux-2.6-wd.git;a=shortlog;h=refs/heads/smp-up-hacks
> 
> Only v7 cores are supported and TEX remapping is used to avoid having
> to worry about setting the shared attribute at runtime. Yuck!

Heh cool, I'll take a look at those :)

Tony

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

Here's my latest patch (which is combined from two patches.)

Tony, could you follow up with patches for anything which is still
required - I think there's two things you've addressed which this
currently misses:

1. not initializing twd_base (I'm not convinced this is safe - rather
   making smp_prepare_cpus() return early is probably a better idea.)
2. __flush_icache_all()

Note that (2) seems to be complicated by the instruction only being
available on ARMv7 and later.

Also note that this should only be used for comparing SMP vs UP versions
of the same architecture - in other words, not ARMv6 vs ARMv6K.

Lastly, what's happening about ARMv6 and ARMv7 processor setup functions?
Are we going to split them into those which need SMP bits twiddled and
those which don't?  If we are going to split them, someone needs to follow
up on this email with patches to do it (preferably to be slotted in
before these changes.)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 836a3e5..11daea0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,19 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on EXPERIMENTAL
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don't know what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..e2bd8c6 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,39 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.long	9998b						;\
+	instr							;\
+	.popsection
+#define UP_B(label)						\
+	.equ	up_b_offset, label - 9998b			;\
+	.pushsection ".smpalt.init", "a"			;\
+	.long	9998b						;\
+	b	. + up_b_offset					;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#define UP_B(label) b label
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/smp_mpidr.h b/arch/arm/include/asm/smp_mpidr.h
new file mode 100644
index 0000000..18f2117
--- /dev/null
+++ b/arch/arm/include/asm/smp_mpidr.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_SMP_MIDR_H
+#define ASMARM_SMP_MIDR_H
+
+#define hard_smp_processor_id()						\
+	({								\
+		unsigned int cpunum;					\
+		__asm__("\n"						\
+			"1:	mrc p15, 0, %0, c0, c0, 5\n"		\
+			"	.pushsection \".smpalt.init\", \"a\"\n"	\
+			"	.long	1b\n"				\
+			"	mov	%0, #0\n"			\
+			"	.popsection"				\
+			: "=r" (cpunum));				\
+		cpunum &= 0x0F;						\
+	})
+
+#endif
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..7de5aa5 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -18,4 +18,19 @@ static inline int cache_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 
+/*
+ * Return true if we are running on a SMP platform
+ */
+static inline bool is_smp(void)
+{
+#ifndef CONFIG_SMP
+	return false;
+#elif defined(CONFIG_SMP_ON_UP)
+	extern unsigned int smp_on_up;
+	return !!smp_on_up;
+#else
+	return true;
+#endif
+}
+
 #endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..cf2f018 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,17 +189,23 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
-#endif
 
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags	v7wbi_tlb_flags
-# define v7wbi_always_flags	v7wbi_tlb_flags
+
+# ifdef CONFIG_SMP_ON_UP
+#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
+# elif defined(CONFIG_SMP)
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
+#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
+# else
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
+#  define v7wbi_always_flags	v7wbi_tlb_flags_up
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..a42f267 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -46,7 +46,8 @@
 	 * this macro assumes that irqstat (r6) and base (r5) are
 	 * preserved from get_irqnr_and_base above
 	 */
-	test_for_ipi r0, r6, r5, lr
+	SMP(test_for_ipi r0, r6, r5, lr)
+	UP_B(9997f)
 	movne	r0, sp
 	adrne	lr, BSYM(1b)
 	bne	do_IPI
@@ -57,6 +58,7 @@
 	adrne	lr, BSYM(1b)
 	bne	do_local_timer
 #endif
+9997:
 #endif
 
 	.endm
@@ -965,11 +967,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..e15dc0f 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,51 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	mov	r7, #0x00070000
+	orr	r6, r7, #0xff000000	@ mask 0xff070000
+	orr	r7, r7, #0x41000000	@ val 0x41070000
+	and	r0, r9, r6
+	teq	r0, r7			@ ARM CPU and ARMv6/v7?
+	bne	__fixup_smp_on_up	@ no, assume UP
+
+	orr	r6, r6, #0x0000ff00
+	orr	r6, r6, #0x000000f0	@ mask 0xff07fff0
+	orr	r7, r7, #0x0000b000
+	orr	r7, r7, #0x00000020	@ val 0x4107b020
+	and	r0, r9, r6
+	teq	r0, r7			@ ARM 11MPCore?
+	moveq	pc, lr			@ yes, assume SMP
+
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	tst	r0, #1 << 31
+	movne	pc, lr			@ bit 31 => SMP
+
+__fixup_smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	strlo	r4, [r0, r3]
+	blo	2b
+	mov	pc, lr
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+
+	.pushsection .data
+	.globl	smp_on_up
+smp_on_up:
+	SMP(.long	1)
+	UP(.long	0)
+	.popsection
+
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d5231ae..fe94467 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -36,6 +36,7 @@
 #include <asm/procinfo.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
+#include <asm/smp_plat.h>
 #include <asm/mach-types.h>
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
@@ -824,9 +825,8 @@ void __init setup_arch(char **cmdline_p)
 	paging_init(mdesc);
 	request_standard_resources(&meminfo, mdesc);
 
-#ifdef CONFIG_SMP
-	smp_init_cpus();
-#endif
+	if (is_smp())
+		smp_init_cpus();
 	reserve_crashkernel();
 
 	cpu_init();
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..d3cd265 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..b7ec252 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..e4a34a3 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..197e841 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..5a6da4f 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..a789320 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -303,9 +303,8 @@ static void __init build_mem_type_table(void)
 			cachepolicy = CPOLICY_WRITEBACK;
 		ecc_mask = 0;
 	}
-#ifdef CONFIG_SMP
-	cachepolicy = CPOLICY_WRITEALLOC;
-#endif
+	if (is_smp())
+		cachepolicy = CPOLICY_WRITEALLOC;
 
 	/*
 	 * Strip out features not present on earlier architectures.
@@ -399,13 +398,11 @@ static void __init build_mem_type_table(void)
 	cp = &cache_policies[cachepolicy];
 	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
-#ifndef CONFIG_SMP
 	/*
 	 * Only use write-through for non-SMP systems
 	 */
-	if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
+	if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 		vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
-#endif
 
 	/*
 	 * Enable CPU-specific coherency if supported.
@@ -426,20 +423,21 @@ static void __init build_mem_type_table(void)
 		mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 
-#ifdef CONFIG_SMP
-		/*
-		 * Mark memory with the "shared" attribute for SMP systems
-		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-#endif
+		if (is_smp()) {
+			/*
+			 * Mark memory with the "shared" attribute
+			 * for SMP systems
+			 */
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 	}
 
 	/*
@@ -802,8 +800,7 @@ static void __init sanity_check_meminfo(void)
 			 * rather difficult.
 			 */
 			reason = "with VIPT aliasing cache";
-#ifdef CONFIG_SMP
-		} else if (tlb_ops_need_broadcast()) {
+		} else if (is_smp() && tlb_ops_need_broadcast()) {
 			/*
 			 * kmap_high needs to occasionally flush TLB entries,
 			 * however, if the TLB entries need to be broadcast
@@ -813,7 +810,6 @@ static void __init sanity_check_meminfo(void)
 			 *   (must not be called with irqs off)
 			 */
 			reason = "without hardware TLB ops broadcasting";
-#endif
 		}
 		if (reason) {
 			printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..4671c8f 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c..ecd6a48 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

Here's my latest patch (which is combined from two patches.)

Tony, could you follow up with patches for anything which is still
required - I think there's two things you've addressed which this
currently misses:

1. not initializing twd_base (I'm not convinced this is safe - rather
   making smp_prepare_cpus() return early is probably a better idea.)
2. __flush_icache_all()

Note that (2) seems to be complicated by the instruction only being
available on ARMv7 and later.

Also note that this should only be used for comparing SMP vs UP versions
of the same architecture - in other words, not ARMv6 vs ARMv6K.

Lastly, what's happening about ARMv6 and ARMv7 processor setup functions?
Are we going to split them into those which need SMP bits twiddled and
those which don't?  If we are going to split them, someone needs to follow
up on this email with patches to do it (preferably to be slotted in
before these changes.)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 836a3e5..11daea0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,19 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on EXPERIMENTAL
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don't know what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..e2bd8c6 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,39 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.long	9998b						;\
+	instr							;\
+	.popsection
+#define UP_B(label)						\
+	.equ	up_b_offset, label - 9998b			;\
+	.pushsection ".smpalt.init", "a"			;\
+	.long	9998b						;\
+	b	. + up_b_offset					;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#define UP_B(label) b label
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/smp_mpidr.h b/arch/arm/include/asm/smp_mpidr.h
new file mode 100644
index 0000000..18f2117
--- /dev/null
+++ b/arch/arm/include/asm/smp_mpidr.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_SMP_MIDR_H
+#define ASMARM_SMP_MIDR_H
+
+#define hard_smp_processor_id()						\
+	({								\
+		unsigned int cpunum;					\
+		__asm__("\n"						\
+			"1:	mrc p15, 0, %0, c0, c0, 5\n"		\
+			"	.pushsection \".smpalt.init\", \"a\"\n"	\
+			"	.long	1b\n"				\
+			"	mov	%0, #0\n"			\
+			"	.popsection"				\
+			: "=r" (cpunum));				\
+		cpunum &= 0x0F;						\
+	})
+
+#endif
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..7de5aa5 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -18,4 +18,19 @@ static inline int cache_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 
+/*
+ * Return true if we are running on a SMP platform
+ */
+static inline bool is_smp(void)
+{
+#ifndef CONFIG_SMP
+	return false;
+#elif defined(CONFIG_SMP_ON_UP)
+	extern unsigned int smp_on_up;
+	return !!smp_on_up;
+#else
+	return true;
+#endif
+}
+
 #endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..cf2f018 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,17 +189,23 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
-#endif
 
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags	v7wbi_tlb_flags
-# define v7wbi_always_flags	v7wbi_tlb_flags
+
+# ifdef CONFIG_SMP_ON_UP
+#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
+# elif defined(CONFIG_SMP)
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
+#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
+# else
+#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
+#  define v7wbi_always_flags	v7wbi_tlb_flags_up
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..a42f267 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -46,7 +46,8 @@
 	 * this macro assumes that irqstat (r6) and base (r5) are
 	 * preserved from get_irqnr_and_base above
 	 */
-	test_for_ipi r0, r6, r5, lr
+	SMP(test_for_ipi r0, r6, r5, lr)
+	UP_B(9997f)
 	movne	r0, sp
 	adrne	lr, BSYM(1b)
 	bne	do_IPI
@@ -57,6 +58,7 @@
 	adrne	lr, BSYM(1b)
 	bne	do_local_timer
 #endif
+9997:
 #endif
 
 	.endm
@@ -965,11 +967,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..e15dc0f 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,51 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	mov	r7, #0x00070000
+	orr	r6, r7, #0xff000000	@ mask 0xff070000
+	orr	r7, r7, #0x41000000	@ val 0x41070000
+	and	r0, r9, r6
+	teq	r0, r7			@ ARM CPU and ARMv6/v7?
+	bne	__fixup_smp_on_up	@ no, assume UP
+
+	orr	r6, r6, #0x0000ff00
+	orr	r6, r6, #0x000000f0	@ mask 0xff07fff0
+	orr	r7, r7, #0x0000b000
+	orr	r7, r7, #0x00000020	@ val 0x4107b020
+	and	r0, r9, r6
+	teq	r0, r7			@ ARM 11MPCore?
+	moveq	pc, lr			@ yes, assume SMP
+
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	tst	r0, #1 << 31
+	movne	pc, lr			@ bit 31 => SMP
+
+__fixup_smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	strlo	r4, [r0, r3]
+	blo	2b
+	mov	pc, lr
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+
+	.pushsection .data
+	.globl	smp_on_up
+smp_on_up:
+	SMP(.long	1)
+	UP(.long	0)
+	.popsection
+
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d5231ae..fe94467 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -36,6 +36,7 @@
 #include <asm/procinfo.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
+#include <asm/smp_plat.h>
 #include <asm/mach-types.h>
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
@@ -824,9 +825,8 @@ void __init setup_arch(char **cmdline_p)
 	paging_init(mdesc);
 	request_standard_resources(&meminfo, mdesc);
 
-#ifdef CONFIG_SMP
-	smp_init_cpus();
-#endif
+	if (is_smp())
+		smp_init_cpus();
 	reserve_crashkernel();
 
 	cpu_init();
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..d3cd265 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..b7ec252 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..e4a34a3 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..197e841 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..5a6da4f 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..a789320 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -303,9 +303,8 @@ static void __init build_mem_type_table(void)
 			cachepolicy = CPOLICY_WRITEBACK;
 		ecc_mask = 0;
 	}
-#ifdef CONFIG_SMP
-	cachepolicy = CPOLICY_WRITEALLOC;
-#endif
+	if (is_smp())
+		cachepolicy = CPOLICY_WRITEALLOC;
 
 	/*
 	 * Strip out features not present on earlier architectures.
@@ -399,13 +398,11 @@ static void __init build_mem_type_table(void)
 	cp = &cache_policies[cachepolicy];
 	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
-#ifndef CONFIG_SMP
 	/*
 	 * Only use write-through for non-SMP systems
 	 */
-	if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
+	if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 		vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
-#endif
 
 	/*
 	 * Enable CPU-specific coherency if supported.
@@ -426,20 +423,21 @@ static void __init build_mem_type_table(void)
 		mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 
-#ifdef CONFIG_SMP
-		/*
-		 * Mark memory with the "shared" attribute for SMP systems
-		 */
-		user_pgprot |= L_PTE_SHARED;
-		kern_pgprot |= L_PTE_SHARED;
-		vecs_pgprot |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-#endif
+		if (is_smp()) {
+			/*
+			 * Mark memory with the "shared" attribute
+			 * for SMP systems
+			 */
+			user_pgprot |= L_PTE_SHARED;
+			kern_pgprot |= L_PTE_SHARED;
+			vecs_pgprot |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+			mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+			mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+			mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+		}
 	}
 
 	/*
@@ -802,8 +800,7 @@ static void __init sanity_check_meminfo(void)
 			 * rather difficult.
 			 */
 			reason = "with VIPT aliasing cache";
-#ifdef CONFIG_SMP
-		} else if (tlb_ops_need_broadcast()) {
+		} else if (is_smp() && tlb_ops_need_broadcast()) {
 			/*
 			 * kmap_high needs to occasionally flush TLB entries,
 			 * however, if the TLB entries need to be broadcast
@@ -813,7 +810,6 @@ static void __init sanity_check_meminfo(void)
 			 *   (must not be called with irqs off)
 			 */
 			reason = "without hardware TLB ops broadcasting";
-#endif
 		}
 		if (reason) {
 			printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..4671c8f 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c..ecd6a48 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Catalin Marinas]

Russell,

On Mon, 2010-09-06 at 11:44 +0100, Russell King - ARM Linux wrote:
> +#ifdef CONFIG_SMP_ON_UP
> +__fixup_smp:
> +       mov     r7, #0x00070000
> +       orr     r6, r7, #0xff000000     @ mask 0xff070000
> +       orr     r7, r7, #0x41000000     @ val 0x41070000
> +       and     r0, r9, r6
> +       teq     r0, r7                  @ ARM CPU and ARMv6/v7?
> +       bne     __fixup_smp_on_up       @ no, assume UP
> +
> +       orr     r6, r6, #0x0000ff00
> +       orr     r6, r6, #0x000000f0     @ mask 0xff07fff0
> +       orr     r7, r7, #0x0000b000
> +       orr     r7, r7, #0x00000020     @ val 0x4107b020
> +       and     r0, r9, r6
> +       teq     r0, r7                  @ ARM 11MPCore?
> +       moveq   pc, lr                  @ yes, assume SMP
> +
> +       mrc     p15, 0, r0, c0, c0, 5   @ read MIDR
> +       tst     r0, #1 << 31
> +       movne   pc, lr                  @ bit 31 => SMP

An alternative would be to check for hardware coherency support in the
shareability domain using the MMFR0 register. If we have the new CPUID
format (all MP systems):

	if (ID_MMFR0<15:12> == 0) 
		HWCoherency = (ID_MMFR0<11:8> == 1)
	else 
		HWCoherency = (ID_MMFR0<31:28> == 1)

The hw coherency is built for MP systems and this register should be
valid for both ARMv6 and ARMv7 configurations.

Something like below, untested:

	mov	r6, #0x000f0000		@ mask/val new CPUID
	and	r0, r9, r6
	teq	r0, r6			@ ARMv6/v7 new CPUID
	bne	__fixup_smp_on_up	@ no, assume UP

	mrc	p15, 0, r0, c0, c1, 4	@ MMFR0
	mov	r6, #0x0000f000		@ mask shareability levels
	tst	r0, r6
	moveq	r0, r0, lsr #8		@ outermost shareability
	movne	r0, r0, lsr #28		@ innermost shareability
	and	r0, r0, #15
	cmp	r0, #1			@ check hw coherency support
	bne	__fixup_smp_on_up	@ no, assume UP

We still cannot optimise the case where you have an MP capable processor
but in a UP-only configuration (maxcpus=1).

For the availability of the Inner Shareable cache and TLB operations, we
would need to check for the MMFR3<15:12> bits.

-- 
Catalin

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Catalin Marinas]

Russell,

On Mon, 2010-09-06 at 11:44 +0100, Russell King - ARM Linux wrote:
> +#ifdef CONFIG_SMP_ON_UP
> +__fixup_smp:
> +       mov     r7, #0x00070000
> +       orr     r6, r7, #0xff000000     @ mask 0xff070000
> +       orr     r7, r7, #0x41000000     @ val 0x41070000
> +       and     r0, r9, r6
> +       teq     r0, r7                  @ ARM CPU and ARMv6/v7?
> +       bne     __fixup_smp_on_up       @ no, assume UP
> +
> +       orr     r6, r6, #0x0000ff00
> +       orr     r6, r6, #0x000000f0     @ mask 0xff07fff0
> +       orr     r7, r7, #0x0000b000
> +       orr     r7, r7, #0x00000020     @ val 0x4107b020
> +       and     r0, r9, r6
> +       teq     r0, r7                  @ ARM 11MPCore?
> +       moveq   pc, lr                  @ yes, assume SMP
> +
> +       mrc     p15, 0, r0, c0, c0, 5   @ read MIDR
> +       tst     r0, #1 << 31
> +       movne   pc, lr                  @ bit 31 => SMP

An alternative would be to check for hardware coherency support in the
shareability domain using the MMFR0 register. If we have the new CPUID
format (all MP systems):

	if (ID_MMFR0<15:12> == 0) 
		HWCoherency = (ID_MMFR0<11:8> == 1)
	else 
		HWCoherency = (ID_MMFR0<31:28> == 1)

The hw coherency is built for MP systems and this register should be
valid for both ARMv6 and ARMv7 configurations.

Something like below, untested:

	mov	r6, #0x000f0000		@ mask/val new CPUID
	and	r0, r9, r6
	teq	r0, r6			@ ARMv6/v7 new CPUID
	bne	__fixup_smp_on_up	@ no, assume UP

	mrc	p15, 0, r0, c0, c1, 4	@ MMFR0
	mov	r6, #0x0000f000		@ mask shareability levels
	tst	r0, r6
	moveq	r0, r0, lsr #8		@ outermost shareability
	movne	r0, r0, lsr #28		@ innermost shareability
	and	r0, r0, #15
	cmp	r0, #1			@ check hw coherency support
	bne	__fixup_smp_on_up	@ no, assume UP

We still cannot optimise the case where you have an MP capable processor
but in a UP-only configuration (maxcpus=1).

For the availability of the Inner Shareable cache and TLB operations, we
would need to check for the MMFR3<15:12> bits.

-- 
Catalin

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100906 03:36]:
> Here's my latest patch (which is combined from two patches.)
> 
> Tony, could you follow up with patches for anything which is still
> required - I think there's two things you've addressed which this
> currently misses:
> 
> 1. not initializing twd_base (I'm not convinced this is safe - rather
>    making smp_prepare_cpus() return early is probably a better idea.)
> 2. __flush_icache_all()
> 
> Note that (2) seems to be complicated by the instruction only being
> available on ARMv7 and later.

Yeah will check probably on Tuesday, heading to a BBQ as it's a holiday
here. Also my laptop cooling fan broke a few days ago, got it patched up
temporarily though: An external fan duct taped to the side of the machine
until the replacement arrives :)
 
> Also note that this should only be used for comparing SMP vs UP versions
> of the same architecture - in other words, not ARMv6 vs ARMv6K.

Right, ARMv6 vs ARMv6K can be dealt with in another patch once this
is done.
 
> Lastly, what's happening about ARMv6 and ARMv7 processor setup functions?
> Are we going to split them into those which need SMP bits twiddled and
> those which don't?  If we are going to split them, someone needs to follow
> up on this email with patches to do it (preferably to be slotted in
> before these changes.)

No need to split them any longer AFAIK. Or do you have some case in mind
that's not being handled now, maybe I don't follow you?

Regards,

Tony 

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100906 03:36]:
> Here's my latest patch (which is combined from two patches.)
> 
> Tony, could you follow up with patches for anything which is still
> required - I think there's two things you've addressed which this
> currently misses:
> 
> 1. not initializing twd_base (I'm not convinced this is safe - rather
>    making smp_prepare_cpus() return early is probably a better idea.)
> 2. __flush_icache_all()
> 
> Note that (2) seems to be complicated by the instruction only being
> available on ARMv7 and later.

Yeah will check probably on Tuesday, heading to a BBQ as it's a holiday
here. Also my laptop cooling fan broke a few days ago, got it patched up
temporarily though: An external fan duct taped to the side of the machine
until the replacement arrives :)
 
> Also note that this should only be used for comparing SMP vs UP versions
> of the same architecture - in other words, not ARMv6 vs ARMv6K.

Right, ARMv6 vs ARMv6K can be dealt with in another patch once this
is done.
 
> Lastly, what's happening about ARMv6 and ARMv7 processor setup functions?
> Are we going to split them into those which need SMP bits twiddled and
> those which don't?  If we are going to split them, someone needs to follow
> up on this email with patches to do it (preferably to be slotted in
> before these changes.)

No need to split them any longer AFAIK. Or do you have some case in mind
that's not being handled now, maybe I don't follow you?

Regards,

Tony 

Re: [PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100906 10:56]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100906 03:36]:
> > Here's my latest patch (which is combined from two patches.)
> > 
> > Tony, could you follow up with patches for anything which is still
> > required - I think there's two things you've addressed which this
> > currently misses:
> > 
> > 1. not initializing twd_base (I'm not convinced this is safe - rather
> >    making smp_prepare_cpus() return early is probably a better idea.)

Looks like the omap spefific fix needed now is for the localtimer, and
that can be now checked with cpu_is_omap44xx() as Santosh suggested
earlier. Will post that shortly.

> > 2. __flush_icache_all()
> > 
> > Note that (2) seems to be complicated by the instruction only being
> > available on ARMv7 and later.

This is still open and needs to be fixed somehow..

Then the following patch is needed to fix compile if CONFIG_SMP is not set.

Other than that, things are actually quite close to working. Will post
three more patches as a reply to this mail that allow me to boot to
shell with the same SMP kernel binary on omap2, 3 & 4 more or less.

Need to track down some .config file strangeness though tomorrow to
figure out what is causing the WARNING: at mm/percpu-vm.c:320 pcpu_alloc
messages again.

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Tue, 7 Sep 2010 19:09:57 -0700
Subject: [PATCH] ARM: Fix smp_on_up compile when CONFIG_SMP is not set

Fix undefined reference to smp_init_cpus()
and error for the discarded section:

ld:arch/arm/kernel/vmlinux.lds:517: syntax error

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index fe94467..5a82c39 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -825,8 +825,10 @@ void __init setup_arch(char **cmdline_p)
 	paging_init(mdesc);
 	request_standard_resources(&meminfo, mdesc);
 
+#ifdef CONFIG_SMP
 	if (is_smp())
 		smp_init_cpus();
+#endif
 	reserve_crashkernel();
 
 	cpu_init();
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 53cb57e..b721e8b 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -244,7 +244,7 @@ SECTIONS
 	DISCARDS
 
 #ifndef CONFIG_SMP_ON_UP
-	/DISCARD/ {
+	/DISCARD/ : {
 		*(.smpalt.init)
 	}
 #endif

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100906 10:56]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100906 03:36]:
> > Here's my latest patch (which is combined from two patches.)
> > 
> > Tony, could you follow up with patches for anything which is still
> > required - I think there's two things you've addressed which this
> > currently misses:
> > 
> > 1. not initializing twd_base (I'm not convinced this is safe - rather
> >    making smp_prepare_cpus() return early is probably a better idea.)

Looks like the omap spefific fix needed now is for the localtimer, and
that can be now checked with cpu_is_omap44xx() as Santosh suggested
earlier. Will post that shortly.

> > 2. __flush_icache_all()
> > 
> > Note that (2) seems to be complicated by the instruction only being
> > available on ARMv7 and later.

This is still open and needs to be fixed somehow..

Then the following patch is needed to fix compile if CONFIG_SMP is not set.

Other than that, things are actually quite close to working. Will post
three more patches as a reply to this mail that allow me to boot to
shell with the same SMP kernel binary on omap2, 3 & 4 more or less.

Need to track down some .config file strangeness though tomorrow to
figure out what is causing the WARNING: at mm/percpu-vm.c:320 pcpu_alloc
messages again.

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Tue, 7 Sep 2010 19:09:57 -0700
Subject: [PATCH] ARM: Fix smp_on_up compile when CONFIG_SMP is not set

Fix undefined reference to smp_init_cpus()
and error for the discarded section:

ld:arch/arm/kernel/vmlinux.lds:517: syntax error

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index fe94467..5a82c39 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -825,8 +825,10 @@ void __init setup_arch(char **cmdline_p)
 	paging_init(mdesc);
 	request_standard_resources(&meminfo, mdesc);
 
+#ifdef CONFIG_SMP
 	if (is_smp())
 		smp_init_cpus();
+#endif
 	reserve_crashkernel();
 
 	cpu_init();
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 53cb57e..b721e8b 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -244,7 +244,7 @@ SECTIONS
 	DISCARDS
 
 #ifndef CONFIG_SMP_ON_UP
-	/DISCARD/ {
+	/DISCARD/ : {
 		*(.smpalt.init)
 	}
 #endif

[PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Tony Lindgren]

This should not be needed when running on UP systems.

Additionally we will also get an undefined instruction on ARM cores
without the extended CPUID registers with CONFIG_SMP_ON_UP.

Also, we can now remove the is_smp() test from mmu.c.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 7de5aa5..7f4e663 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -7,17 +7,6 @@
 
 #include <asm/cputype.h>
 
-/* all SMP configurations have the extended CPUID registers */
-static inline int tlb_ops_need_broadcast(void)
-{
-	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
-}
-
-static inline int cache_ops_need_broadcast(void)
-{
-	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
-}
-
 /*
  * Return true if we are running on a SMP platform
  */
@@ -33,4 +22,21 @@ static inline bool is_smp(void)
 #endif
 }
 
+/* all SMP configurations have the extended CPUID registers */
+static inline int tlb_ops_need_broadcast(void)
+{
+	if (!is_smp())
+		return 0;
+
+	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
+}
+
+static inline int cache_ops_need_broadcast(void)
+{
+	if (!is_smp())
+		return 0;
+
+	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
+}
+
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index a789320..34df905 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -800,7 +800,7 @@ static void __init sanity_check_meminfo(void)
 			 * rather difficult.
 			 */
 			reason = "with VIPT aliasing cache";
-		} else if (is_smp() && tlb_ops_need_broadcast()) {
+		} else if (tlb_ops_need_broadcast()) {
 			/*
 			 * kmap_high needs to occasionally flush TLB entries,
 			 * however, if the TLB entries need to be broadcast

[PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Tony Lindgren]

This should not be needed when running on UP systems.

Additionally we will also get an undefined instruction on ARM cores
without the extended CPUID registers with CONFIG_SMP_ON_UP.

Also, we can now remove the is_smp() test from mmu.c.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 7de5aa5..7f4e663 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -7,17 +7,6 @@
 
 #include <asm/cputype.h>
 
-/* all SMP configurations have the extended CPUID registers */
-static inline int tlb_ops_need_broadcast(void)
-{
-	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
-}
-
-static inline int cache_ops_need_broadcast(void)
-{
-	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
-}
-
 /*
  * Return true if we are running on a SMP platform
  */
@@ -33,4 +22,21 @@ static inline bool is_smp(void)
 #endif
 }
 
+/* all SMP configurations have the extended CPUID registers */
+static inline int tlb_ops_need_broadcast(void)
+{
+	if (!is_smp())
+		return 0;
+
+	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
+}
+
+static inline int cache_ops_need_broadcast(void)
+{
+	if (!is_smp())
+		return 0;
+
+	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
+}
+
 #endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index a789320..34df905 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -800,7 +800,7 @@ static void __init sanity_check_meminfo(void)
 			 * rather difficult.
 			 */
 			reason = "with VIPT aliasing cache";
-		} else if (is_smp() && tlb_ops_need_broadcast()) {
+		} else if (tlb_ops_need_broadcast()) {
 			/*
 			 * kmap_high needs to occasionally flush TLB entries,
 			 * however, if the TLB entries need to be broadcast

[PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP

[Tony Lindgren]

This is not needed on UP. Additionally with will cause issues when
booting CONFIG_SMP_ON_UP kernel on earlier ARM cores.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 401e38b..5facdbe 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -207,9 +207,7 @@ __setup("reboot=", reboot_setup);
 
 void machine_shutdown(void)
 {
-#ifdef CONFIG_SMP
 	smp_send_stop();
-#endif
 }
 
 void machine_halt(void)
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 40dc74f..16ca27b 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -560,12 +560,17 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs)
 
 void smp_send_reschedule(int cpu)
 {
-	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+	if (is_smp())
+		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
 void smp_send_stop(void)
 {
 	cpumask_t mask = cpu_online_map;
+
+	if (!is_smp())
+		return;
+
 	cpu_clear(smp_processor_id(), mask);
 	send_ipi_message(&mask, IPI_CPU_STOP);
 }

[PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP

[Tony Lindgren]

This is not needed on UP. Additionally with will cause issues when
booting CONFIG_SMP_ON_UP kernel on earlier ARM cores.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 401e38b..5facdbe 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -207,9 +207,7 @@ __setup("reboot=", reboot_setup);
 
 void machine_shutdown(void)
 {
-#ifdef CONFIG_SMP
 	smp_send_stop();
-#endif
 }
 
 void machine_halt(void)
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 40dc74f..16ca27b 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -560,12 +560,17 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs)
 
 void smp_send_reschedule(int cpu)
 {
-	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+	if (is_smp())
+		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
 void smp_send_stop(void)
 {
 	cpumask_t mask = cpu_online_map;
+
+	if (!is_smp())
+		return;
+
 	cpu_clear(smp_processor_id(), mask);
 	send_ipi_message(&mask, IPI_CPU_STOP);
 }

[PATCH] omap: Fix CONFIG_LOCAL_TIMERS initialization for multi-omap

[Tony Lindgren]

Fix CONFIG_LOCAL_TIMERS initialization for multi-omap

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8..5a3e606 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -228,8 +228,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-	BUG_ON(!twd_base);
+	if (cpu_is_omap44xx()) {
+		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+		BUG_ON(!twd_base);
+	}
 #endif
 	omap_dm_timer_init();
 

[PATCH] omap: Fix CONFIG_LOCAL_TIMERS initialization for multi-omap

[Tony Lindgren]

Fix CONFIG_LOCAL_TIMERS initialization for multi-omap

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8..5a3e606 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -228,8 +228,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-	BUG_ON(!twd_base);
+	if (cpu_is_omap44xx()) {
+		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+		BUG_ON(!twd_base);
+	}
 #endif
 	omap_dm_timer_init();
 

RE: [PATCH] omap: Fix CONFIG_LOCAL_TIMERS initialization for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Wednesday, September 08, 2010 8:48 AM
> To: Russell King - ARM Linux
> Cc: linux-arm-kernel@lists.infradead.org; linux-omap@vger.kernel.org;
> bryan.wu@canonical.com
> Subject: [PATCH] omap: Fix CONFIG_LOCAL_TIMERS initialization for multi-
> omap
> 
> Fix CONFIG_LOCAL_TIMERS initialization for multi-omap
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-
> gp.c
> index 74fbed8..5a3e606 100644
> --- a/arch/arm/mach-omap2/timer-gp.c
> +++ b/arch/arm/mach-omap2/timer-gp.c
> @@ -228,8 +228,10 @@ static void __init omap2_gp_clocksource_init(void)
>  static void __init omap2_gp_timer_init(void)
>  {
>  #ifdef CONFIG_LOCAL_TIMERS
> -	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> -	BUG_ON(!twd_base);
> +	if (cpu_is_omap44xx()) {
> +		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> +		BUG_ON(!twd_base);
> +	}
>  #endif
>  	omap_dm_timer_init();
> 
Acked-By: Santosh Shilimkar <santosh.shilimkar@ti.com>

Regards,
Santosh

[PATCH] omap: Fix CONFIG_LOCAL_TIMERS initialization for multi-omap

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Wednesday, September 08, 2010 8:48 AM
> To: Russell King - ARM Linux
> Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org;
> bryan.wu at canonical.com
> Subject: [PATCH] omap: Fix CONFIG_LOCAL_TIMERS initialization for multi-
> omap
> 
> Fix CONFIG_LOCAL_TIMERS initialization for multi-omap
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-
> gp.c
> index 74fbed8..5a3e606 100644
> --- a/arch/arm/mach-omap2/timer-gp.c
> +++ b/arch/arm/mach-omap2/timer-gp.c
> @@ -228,8 +228,10 @@ static void __init omap2_gp_clocksource_init(void)
>  static void __init omap2_gp_timer_init(void)
>  {
>  #ifdef CONFIG_LOCAL_TIMERS
> -	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> -	BUG_ON(!twd_base);
> +	if (cpu_is_omap44xx()) {
> +		twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> +		BUG_ON(!twd_base);
> +	}
>  #endif
>  	omap_dm_timer_init();
> 
Acked-By: Santosh Shilimkar <santosh.shilimkar@ti.com>

Regards,
Santosh

RE: [PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Wednesday, September 08, 2010 8:44 AM
> To: Russell King - ARM Linux
> Cc: linux-arm-kernel@lists.infradead.org; linux-omap@vger.kernel.org;
> bryan.wu@canonical.com
> Subject: [PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP
> 
> This is not needed on UP. Additionally with will cause issues when
> booting CONFIG_SMP_ON_UP kernel on earlier ARM cores.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index 401e38b..5facdbe 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -207,9 +207,7 @@ __setup("reboot=", reboot_setup);
> 
>  void machine_shutdown(void)
>  {
> -#ifdef CONFIG_SMP
>  	smp_send_stop();
> -#endif
>  }
> 
>  void machine_halt(void)
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 40dc74f..16ca27b 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -560,12 +560,17 @@ asmlinkage void __exception do_IPI(struct pt_regs
> *regs)
> 
>  void smp_send_reschedule(int cpu)
>  {
> -	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
> +	if (is_smp())
> +		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
>  }
> 
>  void smp_send_stop(void)
>  {
>  	cpumask_t mask = cpu_online_map;
> +
> +	if (!is_smp())
> +		return;
> +
>  	cpu_clear(smp_processor_id(), mask);
>  	send_ipi_message(&mask, IPI_CPU_STOP);
>  }
The IPI is called too many times, and a check in this path
might be an overhead.

Can we runtime make " smp_send_reschedule" etc NULL based
on it's UP or SMP boot ?

Regards
Santosh 

[PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Wednesday, September 08, 2010 8:44 AM
> To: Russell King - ARM Linux
> Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org;
> bryan.wu at canonical.com
> Subject: [PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP
> 
> This is not needed on UP. Additionally with will cause issues when
> booting CONFIG_SMP_ON_UP kernel on earlier ARM cores.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index 401e38b..5facdbe 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -207,9 +207,7 @@ __setup("reboot=", reboot_setup);
> 
>  void machine_shutdown(void)
>  {
> -#ifdef CONFIG_SMP
>  	smp_send_stop();
> -#endif
>  }
> 
>  void machine_halt(void)
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 40dc74f..16ca27b 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -560,12 +560,17 @@ asmlinkage void __exception do_IPI(struct pt_regs
> *regs)
> 
>  void smp_send_reschedule(int cpu)
>  {
> -	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
> +	if (is_smp())
> +		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
>  }
> 
>  void smp_send_stop(void)
>  {
>  	cpumask_t mask = cpu_online_map;
> +
> +	if (!is_smp())
> +		return;
> +
>  	cpu_clear(smp_processor_id(), mask);
>  	send_ipi_message(&mask, IPI_CPU_STOP);
>  }
The IPI is called too many times, and a check in this path
might be an overhead.

Can we runtime make " smp_send_reschedule" etc NULL based
on it's UP or SMP boot ?

Regards
Santosh 

Re: [PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP

[Russell King - ARM Linux]

On Tue, Sep 07, 2010 at 08:14:05PM -0700, Tony Lindgren wrote:
> This is not needed on UP. Additionally with will cause issues when
> booting CONFIG_SMP_ON_UP kernel on earlier ARM cores.

Doesn't make sense.

> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index 401e38b..5facdbe 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -207,9 +207,7 @@ __setup("reboot=", reboot_setup);
>  
>  void machine_shutdown(void)
>  {
> -#ifdef CONFIG_SMP
>  	smp_send_stop();
> -#endif

This will cause a link error as smp.c is not built for uniprocessor
builds.

>  }
>  
>  void machine_halt(void)
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 40dc74f..16ca27b 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -560,12 +560,17 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs)
>  
>  void smp_send_reschedule(int cpu)
>  {
> -	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
> +	if (is_smp())
> +		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);

There won't be any other CPUs to send an IPI to - and all places which
call this are protected by a check for cpu == smp_processor_id() - in
other words, this will never be called for the current CPU.

>  }
>  
>  void smp_send_stop(void)
>  {
>  	cpumask_t mask = cpu_online_map;
> +
> +	if (!is_smp())
> +		return;
> +
>  	cpu_clear(smp_processor_id(), mask);

This results in an empty CPU mask.  It might be better to do instead:

	if (!cpus_empty(mask))

>  	send_ipi_message(&mask, IPI_CPU_STOP);
>  }

[PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP

[Russell King - ARM Linux]

On Tue, Sep 07, 2010 at 08:14:05PM -0700, Tony Lindgren wrote:
> This is not needed on UP. Additionally with will cause issues when
> booting CONFIG_SMP_ON_UP kernel on earlier ARM cores.

Doesn't make sense.

> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
> index 401e38b..5facdbe 100644
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -207,9 +207,7 @@ __setup("reboot=", reboot_setup);
>  
>  void machine_shutdown(void)
>  {
> -#ifdef CONFIG_SMP
>  	smp_send_stop();
> -#endif

This will cause a link error as smp.c is not built for uniprocessor
builds.

>  }
>  
>  void machine_halt(void)
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 40dc74f..16ca27b 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -560,12 +560,17 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs)
>  
>  void smp_send_reschedule(int cpu)
>  {
> -	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
> +	if (is_smp())
> +		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);

There won't be any other CPUs to send an IPI to - and all places which
call this are protected by a check for cpu == smp_processor_id() - in
other words, this will never be called for the current CPU.

>  }
>  
>  void smp_send_stop(void)
>  {
>  	cpumask_t mask = cpu_online_map;
> +
> +	if (!is_smp())
> +		return;
> +
>  	cpu_clear(smp_processor_id(), mask);

This results in an empty CPU mask.  It might be better to do instead:

	if (!cpus_empty(mask))

>  	send_ipi_message(&mask, IPI_CPU_STOP);
>  }

Re: [PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100908 01:49]:
> On Tue, Sep 07, 2010 at 08:14:05PM -0700, Tony Lindgren wrote:
> > This is not needed on UP. Additionally with will cause issues when
> > booting CONFIG_SMP_ON_UP kernel on earlier ARM cores.
> 
> Doesn't make sense.

Updated below. Basically it's unnecessary to send IPI for one CPU,
and IPI may not be even supported when booting earlier cores
with CONFIG_SMP_ON_UP.
 
> > 
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > 
> > --- a/arch/arm/kernel/process.c
> > +++ b/arch/arm/kernel/process.c
> > @@ -207,9 +207,7 @@ __setup("reboot=", reboot_setup);
> >  
> >  void machine_shutdown(void)
> >  {
> > -#ifdef CONFIG_SMP
> >  	smp_send_stop();
> > -#endif
> 
> This will cause a link error as smp.c is not built for uniprocessor
> builds.

Right that should have not made it to the patch.
 
> > --- a/arch/arm/kernel/smp.c
> > +++ b/arch/arm/kernel/smp.c
> > @@ -560,12 +560,17 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs)
> >  
> >  void smp_send_reschedule(int cpu)
> >  {
> > -	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
> > +	if (is_smp())
> > +		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
> 
> There won't be any other CPUs to send an IPI to - and all places which
> call this are protected by a check for cpu == smp_processor_id() - in
> other words, this will never be called for the current CPU.
 
Good point, it's not needed.

> >  void smp_send_stop(void)
> >  {
> >  	cpumask_t mask = cpu_online_map;
> > +
> > +	if (!is_smp())
> > +		return;
> > +
> >  	cpu_clear(smp_processor_id(), mask);
> 
> This results in an empty CPU mask.  It might be better to do instead:
> 
> 	if (!cpus_empty(mask))
> 
> >  	send_ipi_message(&mask, IPI_CPU_STOP);
> >  }

OK, so this patch shrinks to the one change below.

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Tue, 7 Sep 2010 18:41:33 -0700
Subject: [PATCH] ARM: Don't send IPI in smp_send_stop if there's only one CPU

No need to send IPI if there's one CPU, especially when booting
systems with CONFIG_SMP_ON_UP that may not even support IPI.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 40dc74f..32e16da 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -567,7 +567,8 @@ void smp_send_stop(void)
 {
 	cpumask_t mask = cpu_online_map;
 	cpu_clear(smp_processor_id(), mask);
-	send_ipi_message(&mask, IPI_CPU_STOP);
+	if (!cpus_empty(mask))
+		send_ipi_message(&mask, IPI_CPU_STOP);
 }
 
 /*

[PATCH] ARM: Don't try to send IPI on UP systems with CONFIG_SMP

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100908 01:49]:
> On Tue, Sep 07, 2010 at 08:14:05PM -0700, Tony Lindgren wrote:
> > This is not needed on UP. Additionally with will cause issues when
> > booting CONFIG_SMP_ON_UP kernel on earlier ARM cores.
> 
> Doesn't make sense.

Updated below. Basically it's unnecessary to send IPI for one CPU,
and IPI may not be even supported when booting earlier cores
with CONFIG_SMP_ON_UP.
 
> > 
> > Signed-off-by: Tony Lindgren <tony@atomide.com>
> > 
> > --- a/arch/arm/kernel/process.c
> > +++ b/arch/arm/kernel/process.c
> > @@ -207,9 +207,7 @@ __setup("reboot=", reboot_setup);
> >  
> >  void machine_shutdown(void)
> >  {
> > -#ifdef CONFIG_SMP
> >  	smp_send_stop();
> > -#endif
> 
> This will cause a link error as smp.c is not built for uniprocessor
> builds.

Right that should have not made it to the patch.
 
> > --- a/arch/arm/kernel/smp.c
> > +++ b/arch/arm/kernel/smp.c
> > @@ -560,12 +560,17 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs)
> >  
> >  void smp_send_reschedule(int cpu)
> >  {
> > -	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
> > +	if (is_smp())
> > +		send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
> 
> There won't be any other CPUs to send an IPI to - and all places which
> call this are protected by a check for cpu == smp_processor_id() - in
> other words, this will never be called for the current CPU.
 
Good point, it's not needed.

> >  void smp_send_stop(void)
> >  {
> >  	cpumask_t mask = cpu_online_map;
> > +
> > +	if (!is_smp())
> > +		return;
> > +
> >  	cpu_clear(smp_processor_id(), mask);
> 
> This results in an empty CPU mask.  It might be better to do instead:
> 
> 	if (!cpus_empty(mask))
> 
> >  	send_ipi_message(&mask, IPI_CPU_STOP);
> >  }

OK, so this patch shrinks to the one change below.

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Tue, 7 Sep 2010 18:41:33 -0700
Subject: [PATCH] ARM: Don't send IPI in smp_send_stop if there's only one CPU

No need to send IPI if there's one CPU, especially when booting
systems with CONFIG_SMP_ON_UP that may not even support IPI.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 40dc74f..32e16da 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -567,7 +567,8 @@ void smp_send_stop(void)
 {
 	cpumask_t mask = cpu_online_map;
 	cpu_clear(smp_processor_id(), mask);
-	send_ipi_message(&mask, IPI_CPU_STOP);
+	if (!cpus_empty(mask))
+		send_ipi_message(&mask, IPI_CPU_STOP);
 }
 
 /*

Re: [PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100907 20:04]:
> This should not be needed when running on UP systems.
> 
> Additionally we will also get an undefined instruction on ARM cores
> without the extended CPUID registers with CONFIG_SMP_ON_UP.
> 
> Also, we can now remove the is_smp() test from mmu.c.

Just FYI, I've updated this one more time with to use cpus_empty
instead of !smp_on_up() here as well.

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Tue, 5 Oct 2010 08:28:32 -0700
Subject: [PATCH] ARM: Check for is_smp for tlb_ops and cache_ops broadcast

Broadcast should not be needed when running SMP kernel on UP systems.

Also, this fixes an undefined instruction for SMP_ON_UP on earlier ARM
cores without the extended CPUID_EXT_MMFR3 register.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 7de5aa5..c8f7a08 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -10,11 +10,23 @@
 /* all SMP configurations have the extended CPUID registers */
 static inline int tlb_ops_need_broadcast(void)
 {
+	cpumask_t mask = cpu_online_map;
+
+	cpu_clear(smp_processor_id(), mask);
+	if (cpus_empty(mask))
+		return 0;
+
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
 static inline int cache_ops_need_broadcast(void)
 {
+	cpumask_t mask = cpu_online_map;
+
+	cpu_clear(smp_processor_id(), mask);
+	if (cpus_empty(mask))
+		return 0;
+
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 

[PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100907 20:04]:
> This should not be needed when running on UP systems.
> 
> Additionally we will also get an undefined instruction on ARM cores
> without the extended CPUID registers with CONFIG_SMP_ON_UP.
> 
> Also, we can now remove the is_smp() test from mmu.c.

Just FYI, I've updated this one more time with to use cpus_empty
instead of !smp_on_up() here as well.

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Tue, 5 Oct 2010 08:28:32 -0700
Subject: [PATCH] ARM: Check for is_smp for tlb_ops and cache_ops broadcast

Broadcast should not be needed when running SMP kernel on UP systems.

Also, this fixes an undefined instruction for SMP_ON_UP on earlier ARM
cores without the extended CPUID_EXT_MMFR3 register.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 7de5aa5..c8f7a08 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -10,11 +10,23 @@
 /* all SMP configurations have the extended CPUID registers */
 static inline int tlb_ops_need_broadcast(void)
 {
+	cpumask_t mask = cpu_online_map;
+
+	cpu_clear(smp_processor_id(), mask);
+	if (cpus_empty(mask))
+		return 0;
+
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
 static inline int cache_ops_need_broadcast(void)
 {
+	cpumask_t mask = cpu_online_map;
+
+	cpu_clear(smp_processor_id(), mask);
+	if (cpus_empty(mask))
+		return 0;
+
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
 

Re: [PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Russell King - ARM Linux]

On Tue, Oct 05, 2010 at 03:19:52PM -0700, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [100907 20:04]:
> > This should not be needed when running on UP systems.
> > 
> > Additionally we will also get an undefined instruction on ARM cores
> > without the extended CPUID registers with CONFIG_SMP_ON_UP.
> > 
> > Also, we can now remove the is_smp() test from mmu.c.
> 
> Just FYI, I've updated this one more time with to use cpus_empty
> instead of !smp_on_up() here as well.

What's the rationale?

[PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Russell King - ARM Linux]

On Tue, Oct 05, 2010 at 03:19:52PM -0700, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [100907 20:04]:
> > This should not be needed when running on UP systems.
> > 
> > Additionally we will also get an undefined instruction on ARM cores
> > without the extended CPUID registers with CONFIG_SMP_ON_UP.
> > 
> > Also, we can now remove the is_smp() test from mmu.c.
> 
> Just FYI, I've updated this one more time with to use cpus_empty
> instead of !smp_on_up() here as well.

What's the rationale?

Re: [PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [101005 15:24]:
> On Tue, Oct 05, 2010 at 03:19:52PM -0700, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [100907 20:04]:
> > > This should not be needed when running on UP systems.
> > > 
> > > Additionally we will also get an undefined instruction on ARM cores
> > > without the extended CPUID registers with CONFIG_SMP_ON_UP.
> > > 
> > > Also, we can now remove the is_smp() test from mmu.c.
> > 
> > Just FYI, I've updated this one more time with to use cpus_empty
> > instead of !smp_on_up() here as well.
> 
> What's the rationale?

With CPU hotplug if the other SMP cores are unplugged for PM or
other reasons, no need to do the broadcast.

Regards,

Tony

[PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [101005 15:24]:
> On Tue, Oct 05, 2010 at 03:19:52PM -0700, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [100907 20:04]:
> > > This should not be needed when running on UP systems.
> > > 
> > > Additionally we will also get an undefined instruction on ARM cores
> > > without the extended CPUID registers with CONFIG_SMP_ON_UP.
> > > 
> > > Also, we can now remove the is_smp() test from mmu.c.
> > 
> > Just FYI, I've updated this one more time with to use cpus_empty
> > instead of !smp_on_up() here as well.
> 
> What's the rationale?

With CPU hotplug if the other SMP cores are unplugged for PM or
other reasons, no need to do the broadcast.

Regards,

Tony

Re: [PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Russell King - ARM Linux]

On Wed, Oct 06, 2010 at 07:44:14AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [101005 15:24]:
> > On Tue, Oct 05, 2010 at 03:19:52PM -0700, Tony Lindgren wrote:
> > > * Tony Lindgren <tony@atomide.com> [100907 20:04]:
> > > > This should not be needed when running on UP systems.
> > > > 
> > > > Additionally we will also get an undefined instruction on ARM cores
> > > > without the extended CPUID registers with CONFIG_SMP_ON_UP.
> > > > 
> > > > Also, we can now remove the is_smp() test from mmu.c.
> > > 
> > > Just FYI, I've updated this one more time with to use cpus_empty
> > > instead of !smp_on_up() here as well.
> > 
> > What's the rationale?
> 
> With CPU hotplug if the other SMP cores are unplugged for PM or
> other reasons, no need to do the broadcast.

Yes, but why this expensive test when the smp_on_up() is much cheaper?

smp_call_function_many() already takes care of the "no other CPUs"
case, which is used by on_each_cpu_mask() and on_each_cpu(), which
means these functions won't broadcast the operations to other CPUs
when they're offline.

In any case, if you think that we broadcast every operation to all
CPUs, you're mistaken - TLB and cache ops are broadcast to only
those CPUs which the thread is running on, or in the case of non-MM
specific, to all online CPUs.

So the only thing we have to worry about is "is there an ID register
available" which is covered by the is_smp() test.  Checking the CPU
mask is far more expensive and imho ends up needlessly adding to the
complexity.

[PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Russell King - ARM Linux]

On Wed, Oct 06, 2010 at 07:44:14AM -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [101005 15:24]:
> > On Tue, Oct 05, 2010 at 03:19:52PM -0700, Tony Lindgren wrote:
> > > * Tony Lindgren <tony@atomide.com> [100907 20:04]:
> > > > This should not be needed when running on UP systems.
> > > > 
> > > > Additionally we will also get an undefined instruction on ARM cores
> > > > without the extended CPUID registers with CONFIG_SMP_ON_UP.
> > > > 
> > > > Also, we can now remove the is_smp() test from mmu.c.
> > > 
> > > Just FYI, I've updated this one more time with to use cpus_empty
> > > instead of !smp_on_up() here as well.
> > 
> > What's the rationale?
> 
> With CPU hotplug if the other SMP cores are unplugged for PM or
> other reasons, no need to do the broadcast.

Yes, but why this expensive test when the smp_on_up() is much cheaper?

smp_call_function_many() already takes care of the "no other CPUs"
case, which is used by on_each_cpu_mask() and on_each_cpu(), which
means these functions won't broadcast the operations to other CPUs
when they're offline.

In any case, if you think that we broadcast every operation to all
CPUs, you're mistaken - TLB and cache ops are broadcast to only
those CPUs which the thread is running on, or in the case of non-MM
specific, to all online CPUs.

So the only thing we have to worry about is "is there an ID register
available" which is covered by the is_smp() test.  Checking the CPU
mask is far more expensive and imho ends up needlessly adding to the
complexity.

Re: [PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [101006 15:25]:
> On Wed, Oct 06, 2010 at 07:44:14AM -0700, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [101005 15:24]:
> > > On Tue, Oct 05, 2010 at 03:19:52PM -0700, Tony Lindgren wrote:
> > > > * Tony Lindgren <tony@atomide.com> [100907 20:04]:
> > > > > This should not be needed when running on UP systems.
> > > > > 
> > > > > Additionally we will also get an undefined instruction on ARM cores
> > > > > without the extended CPUID registers with CONFIG_SMP_ON_UP.
> > > > > 
> > > > > Also, we can now remove the is_smp() test from mmu.c.
> > > > 
> > > > Just FYI, I've updated this one more time with to use cpus_empty
> > > > instead of !smp_on_up() here as well.
> > > 
> > > What's the rationale?
> > 
> > With CPU hotplug if the other SMP cores are unplugged for PM or
> > other reasons, no need to do the broadcast.
> 
> Yes, but why this expensive test when the smp_on_up() is much cheaper?
> 
> smp_call_function_many() already takes care of the "no other CPUs"
> case, which is used by on_each_cpu_mask() and on_each_cpu(), which
> means these functions won't broadcast the operations to other CPUs
> when they're offline.
> 
> In any case, if you think that we broadcast every operation to all
> CPUs, you're mistaken - TLB and cache ops are broadcast to only
> those CPUs which the thread is running on, or in the case of non-MM
> specific, to all online CPUs.

OK thanks, that's what I was missing.
 
> So the only thing we have to worry about is "is there an ID register
> available" which is covered by the is_smp() test.  Checking the CPU
> mask is far more expensive and imho ends up needlessly adding to the
> complexity.

OK. In that case, the patch to use is the previous one:

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6429/1

Regards,

Tony

[PATCH] ARM: Check for is_smp for tlb_ops and cache_ops boardcast

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [101006 15:25]:
> On Wed, Oct 06, 2010 at 07:44:14AM -0700, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [101005 15:24]:
> > > On Tue, Oct 05, 2010 at 03:19:52PM -0700, Tony Lindgren wrote:
> > > > * Tony Lindgren <tony@atomide.com> [100907 20:04]:
> > > > > This should not be needed when running on UP systems.
> > > > > 
> > > > > Additionally we will also get an undefined instruction on ARM cores
> > > > > without the extended CPUID registers with CONFIG_SMP_ON_UP.
> > > > > 
> > > > > Also, we can now remove the is_smp() test from mmu.c.
> > > > 
> > > > Just FYI, I've updated this one more time with to use cpus_empty
> > > > instead of !smp_on_up() here as well.
> > > 
> > > What's the rationale?
> > 
> > With CPU hotplug if the other SMP cores are unplugged for PM or
> > other reasons, no need to do the broadcast.
> 
> Yes, but why this expensive test when the smp_on_up() is much cheaper?
> 
> smp_call_function_many() already takes care of the "no other CPUs"
> case, which is used by on_each_cpu_mask() and on_each_cpu(), which
> means these functions won't broadcast the operations to other CPUs
> when they're offline.
> 
> In any case, if you think that we broadcast every operation to all
> CPUs, you're mistaken - TLB and cache ops are broadcast to only
> those CPUs which the thread is running on, or in the case of non-MM
> specific, to all online CPUs.

OK thanks, that's what I was missing.
 
> So the only thing we have to worry about is "is there an ID register
> available" which is covered by the is_smp() test.  Checking the CPU
> mask is far more expensive and imho ends up needlessly adding to the
> complexity.

OK. In that case, the patch to use is the previous one:

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6429/1

Regards,

Tony

[PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100906 03:36]:
> Here's my latest patch (which is combined from two patches.)

I think that patch is now done assuming the fixes I've posted are
merged, so here's my S-O-B for the bits I've contributed:

Signed-off-by: Tony Lindgren <tony@atomide.com>

Anybody else care to ack?

> 2. __flush_icache_all()
> 
> Note that (2) seems to be complicated by the instruction only being
> available on ARMv7 and later.
> 
> Also note that this should only be used for comparing SMP vs UP versions
> of the same architecture - in other words, not ARMv6 vs ARMv6K.

Here's a patch for __flush_icache_all. I believe this is the last
remaining patch we need.

The only other thing I can think of are the conflicts with
CONFIG_CPU_32v6K, on early ARM1136 and later ARM11 systems if somebody
wants to compile a kernel that supports both. But that's not needed for
omap2, so we can boot now omap2, 3 and 4 with a single defconfig :)

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Tue, 14 Sep 2010 11:33:09 -0700
Subject: [PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

Do this by adding flush_icache_all to cache_fns for ARMv6 and 7.
As flush_icache_all may neeed to be called from flush_kern_cache_all,
add it as the first entry in the cache_fns.

Note that now we can remove the ARM_ERRATA_411920 dependency
to !SMP so it can be selected on UP ARMv6 processors, such
as omap2.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f274300..8853cc0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1003,7 +1003,7 @@ endif
 
 config ARM_ERRATA_411920
 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
-	depends on CPU_V6 && !SMP
+	depends on CPU_V6
 	help
 	  Invalidation of the Instruction Cache operation can
 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..22902b5 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -156,6 +156,12 @@
  *	Please note that the implementation of these, and the required
  *	effects are cache-type (VIVT/VIPT/PIPT) specific.
  *
+ *	flush_icache_all()
+ *
+ *		Unconditionally clean and invalidate the entire icache.
+ *		Currently only needed for cache-v6.S and cache-v7.S, see
+ *		__flush_icache_all for the generic implementation.
+ *
  *	flush_kern_all()
  *
  *		Unconditionally clean and invalidate the entire cache.
@@ -206,6 +212,7 @@
  */
 
 struct cpu_cache_fns {
+	void (*flush_icache_all)(void);
 	void (*flush_kern_all)(void);
 	void (*flush_user_all)(void);
 	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
@@ -227,6 +234,7 @@ struct cpu_cache_fns {
 
 extern struct cpu_cache_fns cpu_cache;
 
+#define __cpuc_flush_icache_all		cpu_cache.flush_icache_all
 #define __cpuc_flush_kern_all		cpu_cache.flush_kern_all
 #define __cpuc_flush_user_all		cpu_cache.flush_user_all
 #define __cpuc_flush_user_range		cpu_cache.flush_user_range
@@ -246,6 +254,7 @@ extern struct cpu_cache_fns cpu_cache;
 
 #else
 
+#define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
 #define __cpuc_flush_user_all		__glue(_CACHE,_flush_user_cache_all)
 #define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
@@ -253,6 +262,7 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
 #define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
 
+extern void __cpuc_flush_icache_all(void);
 extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
@@ -291,6 +301,37 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 /*
  * Convert calls to our calling convention.
  */
+
+/* Invalidate I-cache */
+#define __flush_icache_all_generic()					\
+	asm("mcr	p15, 0, %0, c7, c5, 0"				\
+	    : : "r" (0));
+
+/* Invalidate I-cache inner shareable */
+#define __flush_icache_all_v7_smp()					\
+	asm("mcr	p15, 0, %0, c7, c1, 0"				\
+	    : : "r" (0));
+
+/*
+ * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
+ * will fall through to use __flush_icache_all_generic.
+ */
+#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) ||		\
+	defined(CONFIG_SMP_ON_UP)
+#define __flush_icache_preferred	__cpuc_flush_icache_all
+#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
+#define __flush_icache_preferred	__flush_icache_all_v7_smp
+#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
+#define __flush_icache_preferred	__cpuc_flush_icache_all
+#else
+#define __fluch_icache_preferred	__flush_icache_all_generic
+#endif
+
+static inline void __flush_icache_all(void)
+{
+	__flush_icache_preferred();
+}
+
 #define flush_cache_all()		__cpuc_flush_kern_all()
 
 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
@@ -366,21 +407,6 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 extern void flush_dcache_page(struct page *);
 
-static inline void __flush_icache_all(void)
-{
-#ifdef CONFIG_ARM_ERRATA_411920
-	extern void v6_icache_inval_all(void);
-	v6_icache_inval_all();
-#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
-	    : "r" (0));
-#else
-	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-	    :
-	    : "r" (0));
-#endif
-}
 static inline void flush_kernel_vmap_range(void *addr, int size)
 {
 	if ((cache_is_vivt() || cache_is_vipt_aliasing()))
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 86aa689..99fa688 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -21,18 +21,22 @@
 #define D_CACHE_LINE_SIZE	32
 #define BTB_FLUSH_SIZE		8
 
-#ifdef CONFIG_ARM_ERRATA_411920
 /*
- * Invalidate the entire I cache (this code is a workaround for the ARM1136
- * erratum 411920 - Invalidate Instruction Cache operation can fail. This
- * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
+ *	v6_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
  *
- * Registers:
- *   r0 - set to 0
- *   r1 - corrupted
+ *	ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
+ *	This erratum is present in 1136, 1156 and 1176. It does not affect the
+ *	MPCore.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ *	r1 - corrupted
  */
-ENTRY(v6_icache_inval_all)
+ENTRY(v6_flush_icache_all)
 	mov	r0, #0
+#ifdef CONFIG_ARM_ERRATA_411920
 	mrs	r1, cpsr
 	cpsid	ifa				@ disable interrupts
 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
@@ -43,8 +47,11 @@ ENTRY(v6_icache_inval_all)
 	.rept	11				@ ARM Ltd recommends at least
 	nop					@ 11 NOPs
 	.endr
-	mov	pc, lr
+#else
+	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I-cache
 #endif
+	mov	pc, lr
+ENDPROC(v6_flush_icache_all)
 
 /*
  *	v6_flush_cache_all()
@@ -60,7 +67,7 @@ ENTRY(v6_flush_kern_cache_all)
 #ifndef CONFIG_ARM_ERRATA_411920
 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 #else
-	b	v6_icache_inval_all
+	b	v6_flush_icache_all
 #endif
 #else
 	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
@@ -138,7 +145,7 @@ ENTRY(v6_coherent_user_range)
 #ifndef CONFIG_ARM_ERRATA_411920
 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 #else
-	b	v6_icache_inval_all
+	b	v6_flush_icache_all
 #endif
 #else
 	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
@@ -312,6 +319,7 @@ ENDPROC(v6_dma_unmap_area)
 
 	.type	v6_cache_fns, #object
 ENTRY(v6_cache_fns)
+	.long	v6_flush_icache_all
 	.long	v6_flush_kern_cache_all
 	.long	v6_flush_user_cache_all
 	.long	v6_flush_user_cache_range
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 2aa59d5..2a02ade 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -18,6 +18,21 @@
 #include "proc-macros.S"
 
 /*
+ *	v7_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ */
+ENTRY(v7_flush_icache_all)
+	mov	r0, #0
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
+	mov	pc, lr
+ENDPROC(v7_flush_icache_all)
+
+/*
  *	v7_flush_dcache_all()
  *
  *	Flush the whole D-cache.
@@ -303,6 +318,7 @@ ENDPROC(v7_dma_unmap_area)
 
 	.type	v7_cache_fns, #object
 ENTRY(v7_cache_fns)
+	.long	v7_flush_icache_all
 	.long	v7_flush_kern_cache_all
 	.long	v7_flush_user_cache_all
 	.long	v7_flush_user_cache_range

[PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100906 03:36]:
> Here's my latest patch (which is combined from two patches.)

I think that patch is now done assuming the fixes I've posted are
merged, so here's my S-O-B for the bits I've contributed:

Signed-off-by: Tony Lindgren <tony@atomide.com>

Anybody else care to ack?

> 2. __flush_icache_all()
> 
> Note that (2) seems to be complicated by the instruction only being
> available on ARMv7 and later.
> 
> Also note that this should only be used for comparing SMP vs UP versions
> of the same architecture - in other words, not ARMv6 vs ARMv6K.

Here's a patch for __flush_icache_all. I believe this is the last
remaining patch we need.

The only other thing I can think of are the conflicts with
CONFIG_CPU_32v6K, on early ARM1136 and later ARM11 systems if somebody
wants to compile a kernel that supports both. But that's not needed for
omap2, so we can boot now omap2, 3 and 4 with a single defconfig :)

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Tue, 14 Sep 2010 11:33:09 -0700
Subject: [PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

Do this by adding flush_icache_all to cache_fns for ARMv6 and 7.
As flush_icache_all may neeed to be called from flush_kern_cache_all,
add it as the first entry in the cache_fns.

Note that now we can remove the ARM_ERRATA_411920 dependency
to !SMP so it can be selected on UP ARMv6 processors, such
as omap2.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f274300..8853cc0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1003,7 +1003,7 @@ endif
 
 config ARM_ERRATA_411920
 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
-	depends on CPU_V6 && !SMP
+	depends on CPU_V6
 	help
 	  Invalidation of the Instruction Cache operation can
 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..22902b5 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -156,6 +156,12 @@
  *	Please note that the implementation of these, and the required
  *	effects are cache-type (VIVT/VIPT/PIPT) specific.
  *
+ *	flush_icache_all()
+ *
+ *		Unconditionally clean and invalidate the entire icache.
+ *		Currently only needed for cache-v6.S and cache-v7.S, see
+ *		__flush_icache_all for the generic implementation.
+ *
  *	flush_kern_all()
  *
  *		Unconditionally clean and invalidate the entire cache.
@@ -206,6 +212,7 @@
  */
 
 struct cpu_cache_fns {
+	void (*flush_icache_all)(void);
 	void (*flush_kern_all)(void);
 	void (*flush_user_all)(void);
 	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
@@ -227,6 +234,7 @@ struct cpu_cache_fns {
 
 extern struct cpu_cache_fns cpu_cache;
 
+#define __cpuc_flush_icache_all		cpu_cache.flush_icache_all
 #define __cpuc_flush_kern_all		cpu_cache.flush_kern_all
 #define __cpuc_flush_user_all		cpu_cache.flush_user_all
 #define __cpuc_flush_user_range		cpu_cache.flush_user_range
@@ -246,6 +254,7 @@ extern struct cpu_cache_fns cpu_cache;
 
 #else
 
+#define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
 #define __cpuc_flush_user_all		__glue(_CACHE,_flush_user_cache_all)
 #define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
@@ -253,6 +262,7 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
 #define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
 
+extern void __cpuc_flush_icache_all(void);
 extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
@@ -291,6 +301,37 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 /*
  * Convert calls to our calling convention.
  */
+
+/* Invalidate I-cache */
+#define __flush_icache_all_generic()					\
+	asm("mcr	p15, 0, %0, c7, c5, 0"				\
+	    : : "r" (0));
+
+/* Invalidate I-cache inner shareable */
+#define __flush_icache_all_v7_smp()					\
+	asm("mcr	p15, 0, %0, c7, c1, 0"				\
+	    : : "r" (0));
+
+/*
+ * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
+ * will fall through to use __flush_icache_all_generic.
+ */
+#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) ||		\
+	defined(CONFIG_SMP_ON_UP)
+#define __flush_icache_preferred	__cpuc_flush_icache_all
+#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
+#define __flush_icache_preferred	__flush_icache_all_v7_smp
+#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
+#define __flush_icache_preferred	__cpuc_flush_icache_all
+#else
+#define __fluch_icache_preferred	__flush_icache_all_generic
+#endif
+
+static inline void __flush_icache_all(void)
+{
+	__flush_icache_preferred();
+}
+
 #define flush_cache_all()		__cpuc_flush_kern_all()
 
 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
@@ -366,21 +407,6 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 extern void flush_dcache_page(struct page *);
 
-static inline void __flush_icache_all(void)
-{
-#ifdef CONFIG_ARM_ERRATA_411920
-	extern void v6_icache_inval_all(void);
-	v6_icache_inval_all();
-#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
-	    : "r" (0));
-#else
-	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-	    :
-	    : "r" (0));
-#endif
-}
 static inline void flush_kernel_vmap_range(void *addr, int size)
 {
 	if ((cache_is_vivt() || cache_is_vipt_aliasing()))
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 86aa689..99fa688 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -21,18 +21,22 @@
 #define D_CACHE_LINE_SIZE	32
 #define BTB_FLUSH_SIZE		8
 
-#ifdef CONFIG_ARM_ERRATA_411920
 /*
- * Invalidate the entire I cache (this code is a workaround for the ARM1136
- * erratum 411920 - Invalidate Instruction Cache operation can fail. This
- * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
+ *	v6_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
  *
- * Registers:
- *   r0 - set to 0
- *   r1 - corrupted
+ *	ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
+ *	This erratum is present in 1136, 1156 and 1176. It does not affect the
+ *	MPCore.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ *	r1 - corrupted
  */
-ENTRY(v6_icache_inval_all)
+ENTRY(v6_flush_icache_all)
 	mov	r0, #0
+#ifdef CONFIG_ARM_ERRATA_411920
 	mrs	r1, cpsr
 	cpsid	ifa				@ disable interrupts
 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
@@ -43,8 +47,11 @@ ENTRY(v6_icache_inval_all)
 	.rept	11				@ ARM Ltd recommends at least
 	nop					@ 11 NOPs
 	.endr
-	mov	pc, lr
+#else
+	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I-cache
 #endif
+	mov	pc, lr
+ENDPROC(v6_flush_icache_all)
 
 /*
  *	v6_flush_cache_all()
@@ -60,7 +67,7 @@ ENTRY(v6_flush_kern_cache_all)
 #ifndef CONFIG_ARM_ERRATA_411920
 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 #else
-	b	v6_icache_inval_all
+	b	v6_flush_icache_all
 #endif
 #else
 	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
@@ -138,7 +145,7 @@ ENTRY(v6_coherent_user_range)
 #ifndef CONFIG_ARM_ERRATA_411920
 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 #else
-	b	v6_icache_inval_all
+	b	v6_flush_icache_all
 #endif
 #else
 	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
@@ -312,6 +319,7 @@ ENDPROC(v6_dma_unmap_area)
 
 	.type	v6_cache_fns, #object
 ENTRY(v6_cache_fns)
+	.long	v6_flush_icache_all
 	.long	v6_flush_kern_cache_all
 	.long	v6_flush_user_cache_all
 	.long	v6_flush_user_cache_range
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 2aa59d5..2a02ade 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -18,6 +18,21 @@
 #include "proc-macros.S"
 
 /*
+ *	v7_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ */
+ENTRY(v7_flush_icache_all)
+	mov	r0, #0
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
+	mov	pc, lr
+ENDPROC(v7_flush_icache_all)
+
+/*
  *	v7_flush_dcache_all()
  *
  *	Flush the whole D-cache.
@@ -303,6 +318,7 @@ ENDPROC(v7_dma_unmap_area)
 
 	.type	v7_cache_fns, #object
 ENTRY(v7_cache_fns)
+	.long	v7_flush_icache_all
 	.long	v7_flush_kern_cache_all
 	.long	v7_flush_user_cache_all
 	.long	v7_flush_user_cache_range

[PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Tony Lindgren]

With the recent changes to core ARM kernel code, we can now
boot SMP kernel on UP systems. Update omap3_defconfig to
enable SMP. This allows us to remove omap_4430sdp_defconfig.

In addition to enabling SMP, we also need to disable some
options to make the system boot:

- For some reason LOCK_STAT causes tons of
  WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
  so disable it for now.

- MUSB init fails for multi-omap, disable it for now.

- LOCAL_TIMERS hangs on omap4, disable it for now.

Also disable DEBUG_LL as this should be only enabled for
debugging.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig
index 5db9a6b..833a9bc 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap3_defconfig
@@ -55,6 +55,8 @@ CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+# CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -218,9 +220,9 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 CONFIG_USB_MUSB_DEBUG=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
@@ -276,12 +278,11 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
-CONFIG_LOCK_STAT=y
+# CONFIG_LOCK_STAT is not set
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
 CONFIG_SECURITY=y
 CONFIG_CRYPTO_MICHAEL_MIC=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
deleted file mode 100644
index 14c1e18..0000000
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ /dev/null
@@ -1,125 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP4=y
-# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
-# CONFIG_ARCH_OMAP2 is not set
-# CONFIG_ARCH_OMAP3 is not set
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_MACH_OMAP_4430SDP=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-# CONFIG_LOCAL_TIMERS is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_KS8851=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-# CONFIG_ARM_UNWIND is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_LIBCRC32C=y

[PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Tony Lindgren]

With the recent changes to core ARM kernel code, we can now
boot SMP kernel on UP systems. Update omap3_defconfig to
enable SMP. This allows us to remove omap_4430sdp_defconfig.

In addition to enabling SMP, we also need to disable some
options to make the system boot:

- For some reason LOCK_STAT causes tons of
  WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
  so disable it for now.

- MUSB init fails for multi-omap, disable it for now.

- LOCAL_TIMERS hangs on omap4, disable it for now.

Also disable DEBUG_LL as this should be only enabled for
debugging.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig
index 5db9a6b..833a9bc 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap3_defconfig
@@ -55,6 +55,8 @@ CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+# CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -218,9 +220,9 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 CONFIG_USB_MUSB_DEBUG=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
@@ -276,12 +278,11 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
-CONFIG_LOCK_STAT=y
+# CONFIG_LOCK_STAT is not set
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
 CONFIG_SECURITY=y
 CONFIG_CRYPTO_MICHAEL_MIC=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
deleted file mode 100644
index 14c1e18..0000000
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ /dev/null
@@ -1,125 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP4=y
-# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
-# CONFIG_ARCH_OMAP2 is not set
-# CONFIG_ARCH_OMAP3 is not set
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_MACH_OMAP_4430SDP=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-# CONFIG_LOCAL_TIMERS is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_KS8851=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-# CONFIG_ARM_UNWIND is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_LIBCRC32C=y

[PATCH] omap: Update omap3_defconfig for omap2

[Tony Lindgren]

We need to enable ARM_ERRATA_411920 for omap2 and
remove the omap2 specific defconfigs.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig
deleted file mode 100644
index 56aebb6..0000000
--- a/arch/arm/configs/n8x0_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MUX is not set
-# CONFIG_OMAP_MCBSP is not set
-CONFIG_OMAP_MBOX_FWK=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_MACH_NOKIA_N8X0=y
-CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x10C08000
-CONFIG_ZBOOT_ROM_BSS=0x10200000
-CONFIG_CMDLINE="root=/dev/mmcblk0p2 console=ttyS2,115200n8 debug earlyprintk rootwait"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-# CONFIG_HWMON is not set
-CONFIG_MENELAUS=y
-CONFIG_REGULATOR=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_USB_MUSB_DEBUG=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DEBUG=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_EEM=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig
index 833a9bc..d090503 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap3_defconfig
@@ -53,6 +53,7 @@ CONFIG_MACH_SBC3530=y
 CONFIG_MACH_OMAP_3630SDP=y
 CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
diff --git a/arch/arm/configs/omap_generic_2420_defconfig b/arch/arm/configs/omap_generic_2420_defconfig
deleted file mode 100644
index ac08e51..0000000
--- a/arch/arm/configs/omap_generic_2420_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x10C08000
-CONFIG_ZBOOT_ROM_BSS=0x10200000
-CONFIG_FPE_NWFPE=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_INOTIFY=y
-CONFIG_ROMFS_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRC_CCITT=y

[PATCH] omap: Update omap3_defconfig for omap2

[Tony Lindgren]

We need to enable ARM_ERRATA_411920 for omap2 and
remove the omap2 specific defconfigs.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig
deleted file mode 100644
index 56aebb6..0000000
--- a/arch/arm/configs/n8x0_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MUX is not set
-# CONFIG_OMAP_MCBSP is not set
-CONFIG_OMAP_MBOX_FWK=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_MACH_NOKIA_N8X0=y
-CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x10C08000
-CONFIG_ZBOOT_ROM_BSS=0x10200000
-CONFIG_CMDLINE="root=/dev/mmcblk0p2 console=ttyS2,115200n8 debug earlyprintk rootwait"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-# CONFIG_HWMON is not set
-CONFIG_MENELAUS=y
-CONFIG_REGULATOR=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_USB_MUSB_DEBUG=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DEBUG=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_EEM=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig
index 833a9bc..d090503 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap3_defconfig
@@ -53,6 +53,7 @@ CONFIG_MACH_SBC3530=y
 CONFIG_MACH_OMAP_3630SDP=y
 CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
diff --git a/arch/arm/configs/omap_generic_2420_defconfig b/arch/arm/configs/omap_generic_2420_defconfig
deleted file mode 100644
index ac08e51..0000000
--- a/arch/arm/configs/omap_generic_2420_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x10C08000
-CONFIG_ZBOOT_ROM_BSS=0x10200000
-CONFIG_FPE_NWFPE=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_INOTIFY=y
-CONFIG_ROMFS_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRC_CCITT=y

RE: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Wednesday, September 15, 2010 12:33 AM
> To: Russell King - ARM Linux
> Cc: linux-arm-kernel@lists.infradead.org; linux-omap@vger.kernel.org;
> bryan.wu@canonical.com
> Subject: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> 
> With the recent changes to core ARM kernel code, we can now
> boot SMP kernel on UP systems. Update omap3_defconfig to
> enable SMP. This allows us to remove omap_4430sdp_defconfig.
>
Not yet.
We still have some issues around Ethernet, bridge/syslink,
sensors but hopefully we should be able to fix those.
Will have a closer look at this and see if these can be
easily fixed.
> In addition to enabling SMP, we also need to disable some
> options to make the system boot:
> 
> - For some reason LOCK_STAT causes tons of
>   WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
>   so disable it for now.
> 
> - MUSB init fails for multi-omap, disable it for now.
> 
> - LOCAL_TIMERS hangs on omap4, disable it for now.
This is expected on omap4 ES1.0 and hence not enabled
in the omap_4430sdp_defconfig.
> 
> Also disable DEBUG_LL as this should be only enabled for
> debugging.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/configs/omap3_defconfig
> b/arch/arm/configs/omap3_defconfig
> index 5db9a6b..833a9bc 100644
> --- a/arch/arm/configs/omap3_defconfig
> +++ b/arch/arm/configs/omap3_defconfig
> @@ -55,6 +55,8 @@ CONFIG_MACH_OMAP_4430SDP=y
>  CONFIG_ARM_THUMBEE=y
>  CONFIG_NO_HZ=y
>  CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_SMP=y
> +# CONFIG_LOCAL_TIMERS is not set
>  CONFIG_AEABI=y
>  CONFIG_LEDS=y
>  CONFIG_ZBOOT_ROM_TEXT=0x0
> @@ -218,9 +220,9 @@ CONFIG_USB_DEVICEFS=y
>  CONFIG_USB_SUSPEND=y
>  # CONFIG_USB_OTG_WHITELIST is not set
>  CONFIG_USB_MON=y
> -CONFIG_USB_MUSB_HDRC=y
> -CONFIG_USB_MUSB_OTG=y
> -CONFIG_USB_GADGET_MUSB_HDRC=y
> +# CONFIG_USB_MUSB_HDRC is not set
> +# CONFIG_USB_MUSB_OTG is not set
> +# CONFIG_USB_GADGET_MUSB_HDRC is not set
>  CONFIG_USB_MUSB_DEBUG=y
>  CONFIG_USB_WDM=y
>  CONFIG_USB_STORAGE=y
> @@ -276,12 +278,11 @@ CONFIG_DEBUG_KERNEL=y
>  CONFIG_SCHEDSTATS=y
>  CONFIG_TIMER_STATS=y
>  CONFIG_PROVE_LOCKING=y
> -CONFIG_LOCK_STAT=y
> +# CONFIG_LOCK_STAT is not set
>  CONFIG_DEBUG_SPINLOCK_SLEEP=y
>  # CONFIG_DEBUG_BUGVERBOSE is not set
>  CONFIG_DEBUG_INFO=y
>  # CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -CONFIG_DEBUG_LL=y
>  CONFIG_SECURITY=y
>  CONFIG_CRYPTO_MICHAEL_MIC=y
>  # CONFIG_CRYPTO_ANSI_CPRNG is not set
> diff --git a/arch/arm/configs/omap_4430sdp_defconfig
> b/arch/arm/configs/omap_4430sdp_defconfig
> deleted file mode 100644
> index 14c1e18..0000000
> --- a/arch/arm/configs/omap_4430sdp_defconfig
> +++ /dev/null
> @@ -1,125 +0,0 @@
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_SYSVIPC=y
> -CONFIG_BSD_PROCESS_ACCT=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_EMBEDDED=y
> -# CONFIG_SYSCTL_SYSCALL is not set
> -# CONFIG_ELF_CORE is not set
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODVERSIONS=y
> -CONFIG_MODULE_SRCVERSION_ALL=y
> -# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_ARCH_OMAP=y
> -CONFIG_ARCH_OMAP4=y
> -# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
> -# CONFIG_ARCH_OMAP2 is not set
> -# CONFIG_ARCH_OMAP3 is not set
> -# CONFIG_OMAP_MUX is not set
> -CONFIG_OMAP_32K_TIMER=y
> -CONFIG_OMAP_DM_TIMER=y
> -CONFIG_MACH_OMAP_4430SDP=y
> -# CONFIG_ARM_THUMB is not set
> -CONFIG_PL310_ERRATA_588369=y
> -CONFIG_SMP=y
> -CONFIG_NR_CPUS=2
> -# CONFIG_LOCAL_TIMERS is not set
> -CONFIG_PREEMPT=y
> -CONFIG_AEABI=y
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8
> initrd=0x81600000,20M ramdisk_size=20480"
> -CONFIG_VFP=y
> -CONFIG_NEON=y
> -CONFIG_BINFMT_MISC=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_INET=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -CONFIG_IP_PNP_RARP=y
> -# CONFIG_IPV6 is not set
> -# CONFIG_WIRELESS is not set
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -# CONFIG_FW_LOADER is not set
> -CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_SIZE=16384
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_NETDEVICES=y
> -CONFIG_NET_ETHERNET=y
> -CONFIG_KS8851=y
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -# CONFIG_WLAN is not set
> -# CONFIG_INPUT_MOUSEDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_SERIO is not set
> -CONFIG_SERIAL_8250=y
> -CONFIG_SERIAL_8250_CONSOLE=y
> -CONFIG_SERIAL_8250_NR_UARTS=32
> -CONFIG_SERIAL_8250_EXTENDED=y
> -CONFIG_SERIAL_8250_MANY_PORTS=y
> -CONFIG_SERIAL_8250_SHARE_IRQ=y
> -CONFIG_SERIAL_8250_DETECT_IRQ=y
> -CONFIG_SERIAL_8250_RSA=y
> -# CONFIG_LEGACY_PTYS is not set
> -CONFIG_HW_RANDOM=y
> -CONFIG_I2C=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_I2C_OMAP=y
> -CONFIG_SPI=y
> -CONFIG_SPI_OMAP24XX=y
> -# CONFIG_HWMON is not set
> -CONFIG_WATCHDOG=y
> -CONFIG_OMAP_WATCHDOG=y
> -CONFIG_TWL4030_CORE=y
> -CONFIG_REGULATOR=y
> -CONFIG_REGULATOR_TWL4030=y
> -# CONFIG_VGA_CONSOLE is not set
> -# CONFIG_HID_SUPPORT is not set
> -# CONFIG_USB_SUPPORT is not set
> -CONFIG_MMC=y
> -CONFIG_MMC_OMAP_HS=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_DRV_TWL4030=y
> -CONFIG_EXT2_FS=y
> -CONFIG_EXT3_FS=y
> -# CONFIG_EXT3_FS_XATTR is not set
> -CONFIG_INOTIFY=y
> -CONFIG_QUOTA=y
> -CONFIG_QFMT_V2=y
> -CONFIG_MSDOS_FS=y
> -CONFIG_VFAT_FS=y
> -CONFIG_TMPFS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -CONFIG_NFS_V3_ACL=y
> -CONFIG_NFS_V4=y
> -CONFIG_ROOT_NFS=y
> -CONFIG_PARTITION_ADVANCED=y
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_ENABLE_WARN_DEPRECATED is not set
> -# CONFIG_ENABLE_MUST_CHECK is not set
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DETECT_SOFTLOCKUP is not set
> -CONFIG_DETECT_HUNG_TASK=y
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_DEBUG_PREEMPT is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -CONFIG_DEBUG_INFO=y
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_FTRACE is not set
> -# CONFIG_ARM_UNWIND is not set
> -CONFIG_CRYPTO_ECB=m
> -CONFIG_CRYPTO_PCBC=m
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -CONFIG_CRC_CCITT=y
> -CONFIG_CRC_T10DIF=y
> -CONFIG_LIBCRC32C=y
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Wednesday, September 15, 2010 12:33 AM
> To: Russell King - ARM Linux
> Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org;
> bryan.wu at canonical.com
> Subject: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> 
> With the recent changes to core ARM kernel code, we can now
> boot SMP kernel on UP systems. Update omap3_defconfig to
> enable SMP. This allows us to remove omap_4430sdp_defconfig.
>
Not yet.
We still have some issues around Ethernet, bridge/syslink,
sensors but hopefully we should be able to fix those.
Will have a closer look at this and see if these can be
easily fixed.
> In addition to enabling SMP, we also need to disable some
> options to make the system boot:
> 
> - For some reason LOCK_STAT causes tons of
>   WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
>   so disable it for now.
> 
> - MUSB init fails for multi-omap, disable it for now.
> 
> - LOCAL_TIMERS hangs on omap4, disable it for now.
This is expected on omap4 ES1.0 and hence not enabled
in the omap_4430sdp_defconfig.
> 
> Also disable DEBUG_LL as this should be only enabled for
> debugging.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> diff --git a/arch/arm/configs/omap3_defconfig
> b/arch/arm/configs/omap3_defconfig
> index 5db9a6b..833a9bc 100644
> --- a/arch/arm/configs/omap3_defconfig
> +++ b/arch/arm/configs/omap3_defconfig
> @@ -55,6 +55,8 @@ CONFIG_MACH_OMAP_4430SDP=y
>  CONFIG_ARM_THUMBEE=y
>  CONFIG_NO_HZ=y
>  CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_SMP=y
> +# CONFIG_LOCAL_TIMERS is not set
>  CONFIG_AEABI=y
>  CONFIG_LEDS=y
>  CONFIG_ZBOOT_ROM_TEXT=0x0
> @@ -218,9 +220,9 @@ CONFIG_USB_DEVICEFS=y
>  CONFIG_USB_SUSPEND=y
>  # CONFIG_USB_OTG_WHITELIST is not set
>  CONFIG_USB_MON=y
> -CONFIG_USB_MUSB_HDRC=y
> -CONFIG_USB_MUSB_OTG=y
> -CONFIG_USB_GADGET_MUSB_HDRC=y
> +# CONFIG_USB_MUSB_HDRC is not set
> +# CONFIG_USB_MUSB_OTG is not set
> +# CONFIG_USB_GADGET_MUSB_HDRC is not set
>  CONFIG_USB_MUSB_DEBUG=y
>  CONFIG_USB_WDM=y
>  CONFIG_USB_STORAGE=y
> @@ -276,12 +278,11 @@ CONFIG_DEBUG_KERNEL=y
>  CONFIG_SCHEDSTATS=y
>  CONFIG_TIMER_STATS=y
>  CONFIG_PROVE_LOCKING=y
> -CONFIG_LOCK_STAT=y
> +# CONFIG_LOCK_STAT is not set
>  CONFIG_DEBUG_SPINLOCK_SLEEP=y
>  # CONFIG_DEBUG_BUGVERBOSE is not set
>  CONFIG_DEBUG_INFO=y
>  # CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -CONFIG_DEBUG_LL=y
>  CONFIG_SECURITY=y
>  CONFIG_CRYPTO_MICHAEL_MIC=y
>  # CONFIG_CRYPTO_ANSI_CPRNG is not set
> diff --git a/arch/arm/configs/omap_4430sdp_defconfig
> b/arch/arm/configs/omap_4430sdp_defconfig
> deleted file mode 100644
> index 14c1e18..0000000
> --- a/arch/arm/configs/omap_4430sdp_defconfig
> +++ /dev/null
> @@ -1,125 +0,0 @@
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_SYSVIPC=y
> -CONFIG_BSD_PROCESS_ACCT=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_EMBEDDED=y
> -# CONFIG_SYSCTL_SYSCALL is not set
> -# CONFIG_ELF_CORE is not set
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODVERSIONS=y
> -CONFIG_MODULE_SRCVERSION_ALL=y
> -# CONFIG_BLK_DEV_BSG is not set
> -CONFIG_ARCH_OMAP=y
> -CONFIG_ARCH_OMAP4=y
> -# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
> -# CONFIG_ARCH_OMAP2 is not set
> -# CONFIG_ARCH_OMAP3 is not set
> -# CONFIG_OMAP_MUX is not set
> -CONFIG_OMAP_32K_TIMER=y
> -CONFIG_OMAP_DM_TIMER=y
> -CONFIG_MACH_OMAP_4430SDP=y
> -# CONFIG_ARM_THUMB is not set
> -CONFIG_PL310_ERRATA_588369=y
> -CONFIG_SMP=y
> -CONFIG_NR_CPUS=2
> -# CONFIG_LOCAL_TIMERS is not set
> -CONFIG_PREEMPT=y
> -CONFIG_AEABI=y
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8
> initrd=0x81600000,20M ramdisk_size=20480"
> -CONFIG_VFP=y
> -CONFIG_NEON=y
> -CONFIG_BINFMT_MISC=y
> -CONFIG_NET=y
> -CONFIG_PACKET=y
> -CONFIG_INET=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -CONFIG_IP_PNP_RARP=y
> -# CONFIG_IPV6 is not set
> -# CONFIG_WIRELESS is not set
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -# CONFIG_FW_LOADER is not set
> -CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_SIZE=16384
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_NETDEVICES=y
> -CONFIG_NET_ETHERNET=y
> -CONFIG_KS8851=y
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -# CONFIG_WLAN is not set
> -# CONFIG_INPUT_MOUSEDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_SERIO is not set
> -CONFIG_SERIAL_8250=y
> -CONFIG_SERIAL_8250_CONSOLE=y
> -CONFIG_SERIAL_8250_NR_UARTS=32
> -CONFIG_SERIAL_8250_EXTENDED=y
> -CONFIG_SERIAL_8250_MANY_PORTS=y
> -CONFIG_SERIAL_8250_SHARE_IRQ=y
> -CONFIG_SERIAL_8250_DETECT_IRQ=y
> -CONFIG_SERIAL_8250_RSA=y
> -# CONFIG_LEGACY_PTYS is not set
> -CONFIG_HW_RANDOM=y
> -CONFIG_I2C=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_I2C_OMAP=y
> -CONFIG_SPI=y
> -CONFIG_SPI_OMAP24XX=y
> -# CONFIG_HWMON is not set
> -CONFIG_WATCHDOG=y
> -CONFIG_OMAP_WATCHDOG=y
> -CONFIG_TWL4030_CORE=y
> -CONFIG_REGULATOR=y
> -CONFIG_REGULATOR_TWL4030=y
> -# CONFIG_VGA_CONSOLE is not set
> -# CONFIG_HID_SUPPORT is not set
> -# CONFIG_USB_SUPPORT is not set
> -CONFIG_MMC=y
> -CONFIG_MMC_OMAP_HS=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_DRV_TWL4030=y
> -CONFIG_EXT2_FS=y
> -CONFIG_EXT3_FS=y
> -# CONFIG_EXT3_FS_XATTR is not set
> -CONFIG_INOTIFY=y
> -CONFIG_QUOTA=y
> -CONFIG_QFMT_V2=y
> -CONFIG_MSDOS_FS=y
> -CONFIG_VFAT_FS=y
> -CONFIG_TMPFS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -CONFIG_NFS_V3_ACL=y
> -CONFIG_NFS_V4=y
> -CONFIG_ROOT_NFS=y
> -CONFIG_PARTITION_ADVANCED=y
> -CONFIG_NLS_CODEPAGE_437=y
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_ENABLE_WARN_DEPRECATED is not set
> -# CONFIG_ENABLE_MUST_CHECK is not set
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DETECT_SOFTLOCKUP is not set
> -CONFIG_DETECT_HUNG_TASK=y
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_DEBUG_PREEMPT is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -CONFIG_DEBUG_INFO=y
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_FTRACE is not set
> -# CONFIG_ARM_UNWIND is not set
> -CONFIG_CRYPTO_ECB=m
> -CONFIG_CRYPTO_PCBC=m
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -CONFIG_CRC_CCITT=y
> -CONFIG_CRC_T10DIF=y
> -CONFIG_LIBCRC32C=y
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100914 12:09]:
> > -----Original Message-----
> > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > owner@vger.kernel.org] On Behalf Of Tony Lindgren
> > Sent: Wednesday, September 15, 2010 12:33 AM
> > To: Russell King - ARM Linux
> > Cc: linux-arm-kernel@lists.infradead.org; linux-omap@vger.kernel.org;
> > bryan.wu@canonical.com
> > Subject: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> > 
> > With the recent changes to core ARM kernel code, we can now
> > boot SMP kernel on UP systems. Update omap3_defconfig to
> > enable SMP. This allows us to remove omap_4430sdp_defconfig.
> >
> Not yet.
> We still have some issues around Ethernet, bridge/syslink,
> sensors but hopefully we should be able to fix those.
> Will have a closer look at this and see if these can be
> easily fixed.

Sounds like you're having these problems anyways and they
are not related to the defconfigs?

Considering Linus' earlier comments on the defconfigs, I don't
see any reasonds not to merge this patch. If TI wants to fix up
some other things, there's still about two weeks before -rc6.

> > In addition to enabling SMP, we also need to disable some
> > options to make the system boot:
> > 
> > - For some reason LOCK_STAT causes tons of
> >   WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
> >   so disable it for now.
> > 
> > - MUSB init fails for multi-omap, disable it for now.
> > 
> > - LOCAL_TIMERS hangs on omap4, disable it for now.
>
> This is expected on omap4 ES1.0 and hence not enabled
> in the omap_4430sdp_defconfig.

Maybe add a check for ES1.0 there to the init then?

Regards,

Tony

[PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100914 12:09]:
> > -----Original Message-----
> > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> > owner at vger.kernel.org] On Behalf Of Tony Lindgren
> > Sent: Wednesday, September 15, 2010 12:33 AM
> > To: Russell King - ARM Linux
> > Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org;
> > bryan.wu at canonical.com
> > Subject: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> > 
> > With the recent changes to core ARM kernel code, we can now
> > boot SMP kernel on UP systems. Update omap3_defconfig to
> > enable SMP. This allows us to remove omap_4430sdp_defconfig.
> >
> Not yet.
> We still have some issues around Ethernet, bridge/syslink,
> sensors but hopefully we should be able to fix those.
> Will have a closer look at this and see if these can be
> easily fixed.

Sounds like you're having these problems anyways and they
are not related to the defconfigs?

Considering Linus' earlier comments on the defconfigs, I don't
see any reasonds not to merge this patch. If TI wants to fix up
some other things, there's still about two weeks before -rc6.

> > In addition to enabling SMP, we also need to disable some
> > options to make the system boot:
> > 
> > - For some reason LOCK_STAT causes tons of
> >   WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
> >   so disable it for now.
> > 
> > - MUSB init fails for multi-omap, disable it for now.
> > 
> > - LOCAL_TIMERS hangs on omap4, disable it for now.
>
> This is expected on omap4 ES1.0 and hence not enabled
> in the omap_4430sdp_defconfig.

Maybe add a check for ES1.0 there to the init then?

Regards,

Tony

RE: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Shilimkar, Santosh]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony@atomide.com]
> Sent: Wednesday, September 15, 2010 1:58 AM
> To: Shilimkar, Santosh
> Cc: Russell King - ARM Linux; linux-arm-kernel@lists.infradead.org; linux-
> omap@vger.kernel.org; bryan.wu@canonical.com
> Subject: Re: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> 
> * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100914 12:09]:
> > > -----Original Message-----
> > > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> > > owner@vger.kernel.org] On Behalf Of Tony Lindgren
> > > Sent: Wednesday, September 15, 2010 12:33 AM
> > > To: Russell King - ARM Linux
> > > Cc: linux-arm-kernel@lists.infradead.org; linux-omap@vger.kernel.org;
> > > bryan.wu@canonical.com
> > > Subject: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> > >
> > > With the recent changes to core ARM kernel code, we can now
> > > boot SMP kernel on UP systems. Update omap3_defconfig to
> > > enable SMP. This allows us to remove omap_4430sdp_defconfig.
> > >
> > Not yet.
> > We still have some issues around Ethernet, bridge/syslink,
> > sensors but hopefully we should be able to fix those.
> > Will have a closer look at this and see if these can be
> > easily fixed.
> 
> Sounds like you're having these problems anyways and they
> are not related to the defconfigs?
> 
Well the issues are because of defconfig but mostly fixable.
Will hold on my comments till I test the new defconfig on OMAP4.

> Considering Linus' earlier comments on the defconfigs, I don't
> see any reasonds not to merge this patch. If TI wants to fix up
> some other things, there's still about two weeks before -rc6.
>
Sure. I am just saying let's attempt to fix the remaining issues
and if it doesn't happen in next week, anyway this patch will
get merged.
 
> > > In addition to enabling SMP, we also need to disable some
> > > options to make the system boot:
> > >
> > > - For some reason LOCK_STAT causes tons of
> > >   WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
> > >   so disable it for now.
> > >
> > > - MUSB init fails for multi-omap, disable it for now.
> > >
> > > - LOCAL_TIMERS hangs on omap4, disable it for now.
> >
> > This is expected on omap4 ES1.0 and hence not enabled
> > in the omap_4430sdp_defconfig.
> 
> Maybe add a check for ES1.0 there to the init then?
> 
Yes but its ARM generic code and I don't want to pollute it
with omap checks.. Will see if some other trick can fix this.

Regards,
Santosh

[PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Shilimkar, Santosh]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Wednesday, September 15, 2010 1:58 AM
> To: Shilimkar, Santosh
> Cc: Russell King - ARM Linux; linux-arm-kernel at lists.infradead.org; linux-
> omap at vger.kernel.org; bryan.wu at canonical.com
> Subject: Re: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> 
> * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100914 12:09]:
> > > -----Original Message-----
> > > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> > > owner at vger.kernel.org] On Behalf Of Tony Lindgren
> > > Sent: Wednesday, September 15, 2010 12:33 AM
> > > To: Russell King - ARM Linux
> > > Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org;
> > > bryan.wu at canonical.com
> > > Subject: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> > >
> > > With the recent changes to core ARM kernel code, we can now
> > > boot SMP kernel on UP systems. Update omap3_defconfig to
> > > enable SMP. This allows us to remove omap_4430sdp_defconfig.
> > >
> > Not yet.
> > We still have some issues around Ethernet, bridge/syslink,
> > sensors but hopefully we should be able to fix those.
> > Will have a closer look at this and see if these can be
> > easily fixed.
> 
> Sounds like you're having these problems anyways and they
> are not related to the defconfigs?
> 
Well the issues are because of defconfig but mostly fixable.
Will hold on my comments till I test the new defconfig on OMAP4.

> Considering Linus' earlier comments on the defconfigs, I don't
> see any reasonds not to merge this patch. If TI wants to fix up
> some other things, there's still about two weeks before -rc6.
>
Sure. I am just saying let's attempt to fix the remaining issues
and if it doesn't happen in next week, anyway this patch will
get merged.
 
> > > In addition to enabling SMP, we also need to disable some
> > > options to make the system boot:
> > >
> > > - For some reason LOCK_STAT causes tons of
> > >   WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888()
> > >   so disable it for now.
> > >
> > > - MUSB init fails for multi-omap, disable it for now.
> > >
> > > - LOCAL_TIMERS hangs on omap4, disable it for now.
> >
> > This is expected on omap4 ES1.0 and hence not enabled
> > in the omap_4430sdp_defconfig.
> 
> Maybe add a check for ES1.0 there to the init then?
> 
Yes but its ARM generic code and I don't want to pollute it
with omap checks.. Will see if some other trick can fix this.

Regards,
Santosh

Re: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100914 23:03]:
> > 
> > Sounds like you're having these problems anyways and they
> > are not related to the defconfigs?
> > 
> Well the issues are because of defconfig but mostly fixable.
> Will hold on my comments till I test the new defconfig on OMAP4.

OK
 
> > Considering Linus' earlier comments on the defconfigs, I don't
> > see any reasonds not to merge this patch. If TI wants to fix up
> > some other things, there's still about two weeks before -rc6.
> >
> Sure. I am just saying let's attempt to fix the remaining issues
> and if it doesn't happen in next week, anyway this patch will
> get merged.

OK let's plan on doing that.
  
> > > > - LOCAL_TIMERS hangs on omap4, disable it for now.
> > >
> > > This is expected on omap4 ES1.0 and hence not enabled
> > > in the omap_4430sdp_defconfig.
> > 
> > Maybe add a check for ES1.0 there to the init then?
> > 
> Yes but its ARM generic code and I don't want to pollute it
> with omap checks.. Will see if some other trick can fix this.

Maybe in smp_twd.c return from twd_timer_setup early if twd_base
is NULL?

Regards,

Tony

[PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100914 23:03]:
> > 
> > Sounds like you're having these problems anyways and they
> > are not related to the defconfigs?
> > 
> Well the issues are because of defconfig but mostly fixable.
> Will hold on my comments till I test the new defconfig on OMAP4.

OK
 
> > Considering Linus' earlier comments on the defconfigs, I don't
> > see any reasonds not to merge this patch. If TI wants to fix up
> > some other things, there's still about two weeks before -rc6.
> >
> Sure. I am just saying let's attempt to fix the remaining issues
> and if it doesn't happen in next week, anyway this patch will
> get merged.

OK let's plan on doing that.
  
> > > > - LOCAL_TIMERS hangs on omap4, disable it for now.
> > >
> > > This is expected on omap4 ES1.0 and hence not enabled
> > > in the omap_4430sdp_defconfig.
> > 
> > Maybe add a check for ES1.0 there to the init then?
> > 
> Yes but its ARM generic code and I don't want to pollute it
> with omap checks.. Will see if some other trick can fix this.

Maybe in smp_twd.c return from twd_timer_setup early if twd_base
is NULL?

Regards,

Tony

RE: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Shilimkar, Santosh]

[-- Attachment #1: Type: text/plain, Size: 4042 bytes --]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony@atomide.com]
> Sent: Wednesday, September 15, 2010 9:41 PM
> To: Shilimkar, Santosh
> Cc: Russell King - ARM Linux; linux-arm-kernel@lists.infradead.org; linux-
> omap@vger.kernel.org; bryan.wu@canonical.com
> Subject: Re: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> 
> * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100914 23:03]:
> > >
> > > Sounds like you're having these problems anyways and they
> > > are not related to the defconfigs?
> > >
> > Well the issues are because of defconfig but mostly fixable.
> > Will hold on my comments till I test the new defconfig on OMAP4.
> 
> OK
> 
> > > Considering Linus' earlier comments on the defconfigs, I don't
> > > see any reasonds not to merge this patch. If TI wants to fix up
> > > some other things, there's still about two weeks before -rc6.
> > >
> > Sure. I am just saying let's attempt to fix the remaining issues
> > and if it doesn't happen in next week, anyway this patch will
> > get merged.
> 
> OK let's plan on doing that.
> 
Here is the patch which fixes most of the omap4 issues with common
Omap3_defconfig. 

To enable local Timers for es1.0, I made some progress but looks like 
it needs more changes in generic code. Will have a look at it tomorrow.

The patch is on top of the patches being discussed here. It's boot-tested 
with single image on OMAP3 and OMAP4 SMP.

>From 26c908cd9baf3cc0b22f04f29cbeb26e08ad05e8 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Wed, 15 Sep 2010 22:40:19 +0530
Subject: [PATCH] omap: Update and rename common defconfig for omap2plus devices

This patch addresses below things:
- Renaming existing omap3_defconfig which has OMAP2, OMAP3 and OMAP4 builds
  enabled to more appropriate name 'omap2plus_defconfig'
- L1 cache shift is suppose to be 5 on OMAP4 where as it is 6 on previous
  OMAPs. Keeping it to 5 is safer option for OMAP4 and previous OMAPs. For
  OMAP3 only build the shift would be still 6
- Enable needed Errata's for OMAP4 to work with DMA based device drivers
	CONFIG_PL310_ERRATA_588369=y
	CONFIG_ARM_ERRATA_720789=y
- Enable the Micrel ethernet controller
	CONFIG_KS8851=y
	CONFIG_KS8851_MLL=y

With above three changes, OMAP4 ethernet, mmc etc works reliably.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 .../{omap3_defconfig => omap2plus_defconfig}       |    3 +++
 arch/arm/mach-omap2/Kconfig                        |    4 +++-
 2 files changed, 6 insertions(+), 1 deletions(-)
 rename arch/arm/configs/{omap3_defconfig => omap2plus_defconfig} (99%)

diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap2plus_defconfig
similarity index 99%
rename from arch/arm/configs/omap3_defconfig
rename to arch/arm/configs/omap2plus_defconfig
index 833a9bc..3d27dd0 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -53,6 +53,7 @@ CONFIG_MACH_SBC3530=y
 CONFIG_MACH_OMAP_3630SDP=y
 CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
@@ -139,6 +140,8 @@ CONFIG_SMSC_PHY=y
 CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
 CONFIG_SMSC911X=y
+CONFIG_KS8851=y
+CONFIG_KS8851_MLL=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_USB=y
 CONFIG_LIBERTAS_SDIO=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf..bb85f24 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -35,7 +35,7 @@ config ARCH_OMAP3
 	default y
 	select CPU_V7
 	select USB_ARCH_HAS_EHCI
-	select ARM_L1_CACHE_SHIFT_6
+	select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
 
 config ARCH_OMAP4
 	bool "TI OMAP4"
@@ -43,6 +43,8 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select PL310_ERRATA_588369
+	select ARM_ERRATA_720789
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
-- 
1.6.0.4


[-- Attachment #2: 0001-omap-Update-and-rename-common-defconfig-for-omap2pl.patch --]
[-- Type: application/octet-stream, Size: 2501 bytes --]

From 26c908cd9baf3cc0b22f04f29cbeb26e08ad05e8 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Wed, 15 Sep 2010 22:40:19 +0530
Subject: [PATCH] omap: Update and rename common defconfig for omap2plus devices

This patch addresses below things

- Renaming existing omap3_defconfig which has OMAP2, OMAP3 and OMAP4 builds
  enabled to more appropriate name 'omap2plus_defconfig'
- L1 cache shift is suppose to be 5 on OMAP4 where as it is 6 on previous
  OMAPs. Keeping it to 5 is safer option for OMAP4 and previous OMAPs. For
  OMAP3 only build the shift would be still 6
- Enable needed Errata's for OMAP4 to work with DMA based device drivers
	CONFIG_PL310_ERRATA_588369=y
	CONFIG_ARM_ERRATA_720789=y
- Enable the Micrel ethernet controller
	CONFIG_KS8851=y
	CONFIG_KS8851_MLL=y

With above three changes, OMAP4 ethernet, mmc etc works reliably.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
 .../{omap3_defconfig => omap2plus_defconfig}       |    3 +++
 arch/arm/mach-omap2/Kconfig                        |    4 +++-
 2 files changed, 6 insertions(+), 1 deletions(-)
 rename arch/arm/configs/{omap3_defconfig => omap2plus_defconfig} (99%)

diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap2plus_defconfig
similarity index 99%
rename from arch/arm/configs/omap3_defconfig
rename to arch/arm/configs/omap2plus_defconfig
index 833a9bc..3d27dd0 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -53,6 +53,7 @@ CONFIG_MACH_SBC3530=y
 CONFIG_MACH_OMAP_3630SDP=y
 CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
@@ -139,6 +140,8 @@ CONFIG_SMSC_PHY=y
 CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
 CONFIG_SMSC911X=y
+CONFIG_KS8851=y
+CONFIG_KS8851_MLL=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_USB=y
 CONFIG_LIBERTAS_SDIO=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf..bb85f24 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -35,7 +35,7 @@ config ARCH_OMAP3
 	default y
 	select CPU_V7
 	select USB_ARCH_HAS_EHCI
-	select ARM_L1_CACHE_SHIFT_6
+	select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
 
 config ARCH_OMAP4
 	bool "TI OMAP4"
@@ -43,6 +43,8 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select PL310_ERRATA_588369
+	select ARM_ERRATA_720789
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
-- 
1.6.0.4

[PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Shilimkar, Santosh]

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Wednesday, September 15, 2010 9:41 PM
> To: Shilimkar, Santosh
> Cc: Russell King - ARM Linux; linux-arm-kernel at lists.infradead.org; linux-
> omap at vger.kernel.org; bryan.wu at canonical.com
> Subject: Re: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP
> 
> * Shilimkar, Santosh <santosh.shilimkar@ti.com> [100914 23:03]:
> > >
> > > Sounds like you're having these problems anyways and they
> > > are not related to the defconfigs?
> > >
> > Well the issues are because of defconfig but mostly fixable.
> > Will hold on my comments till I test the new defconfig on OMAP4.
> 
> OK
> 
> > > Considering Linus' earlier comments on the defconfigs, I don't
> > > see any reasonds not to merge this patch. If TI wants to fix up
> > > some other things, there's still about two weeks before -rc6.
> > >
> > Sure. I am just saying let's attempt to fix the remaining issues
> > and if it doesn't happen in next week, anyway this patch will
> > get merged.
> 
> OK let's plan on doing that.
> 
Here is the patch which fixes most of the omap4 issues with common
Omap3_defconfig. 

To enable local Timers for es1.0, I made some progress but looks like 
it needs more changes in generic code. Will have a look at it tomorrow.

The patch is on top of the patches being discussed here. It's boot-tested 
with single image on OMAP3 and OMAP4 SMP.

Re: [PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100915 11:18]:
> > 
> Here is the patch which fixes most of the omap4 issues with common
> Omap3_defconfig. 

Good to hear, thanks!
 
> To enable local Timers for es1.0, I made some progress but looks like 
> it needs more changes in generic code. Will have a look at it tomorrow.

OK
 
> The patch is on top of the patches being discussed here. It's boot-tested 
> with single image on OMAP3 and OMAP4 SMP.

Looks good to me.

Tony

[PATCH] omap: Update omap3_defconfig to work with SMP_ON_UP

[Tony Lindgren]

* Shilimkar, Santosh <santosh.shilimkar@ti.com> [100915 11:18]:
> > 
> Here is the patch which fixes most of the omap4 issues with common
> Omap3_defconfig. 

Good to hear, thanks!
 
> To enable local Timers for es1.0, I made some progress but looks like 
> it needs more changes in generic code. Will have a look at it tomorrow.

OK
 
> The patch is on top of the patches being discussed here. It's boot-tested 
> with single image on OMAP3 and OMAP4 SMP.

Looks good to me.

Tony

Re: [PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

[Catalin Marinas]

On Tue, 2010-09-14 at 11:59 -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100906 03:36]:
> > Here's my latest patch (which is combined from two patches.)
> 
> I think that patch is now done assuming the fixes I've posted are
> merged, so here's my S-O-B for the bits I've contributed:
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> Anybody else care to ack?

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

[PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

[Catalin Marinas]

On Tue, 2010-09-14 at 11:59 -0700, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100906 03:36]:
> > Here's my latest patch (which is combined from two patches.)
> 
> I think that patch is now done assuming the fixes I've posted are
> merged, so here's my S-O-B for the bits I've contributed:
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> 
> Anybody else care to ack?

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

Re: [PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100914 12:04]:
> 
> Here's a patch for __flush_icache_all. I believe this is the last
> remaining patch we need.
> 
> The only other thing I can think of are the conflicts with
> CONFIG_CPU_32v6K, on early ARM1136 and later ARM11 systems if somebody
> wants to compile a kernel that supports both. But that's not needed for
> omap2, so we can boot now omap2, 3 and 4 with a single defconfig :)

Here's an updated version with a typo fix s/fluch/flush/ from Anand.

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Mon, 20 Sep 2010 16:37:16 -0700
Subject: [PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

Do this by adding flush_icache_all to cache_fns for ARMv6 and 7.
As flush_icache_all may neeed to be called from flush_kern_cache_all,
add it as the first entry in the cache_fns.

Note that now we can remove the ARM_ERRATA_411920 dependency
to !SMP so it can be selected on UP ARMv6 processors, such
as omap2.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>

--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1017,7 +1017,7 @@ endif
 
 config ARM_ERRATA_411920
 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
-	depends on CPU_V6 && !SMP
+	depends on CPU_V6
 	help
 	  Invalidation of the Instruction Cache operation can
 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -156,6 +156,12 @@
  *	Please note that the implementation of these, and the required
  *	effects are cache-type (VIVT/VIPT/PIPT) specific.
  *
+ *	flush_icache_all()
+ *
+ *		Unconditionally clean and invalidate the entire icache.
+ *		Currently only needed for cache-v6.S and cache-v7.S, see
+ *		__flush_icache_all for the generic implementation.
+ *
  *	flush_kern_all()
  *
  *		Unconditionally clean and invalidate the entire cache.
@@ -206,6 +212,7 @@
  */
 
 struct cpu_cache_fns {
+	void (*flush_icache_all)(void);
 	void (*flush_kern_all)(void);
 	void (*flush_user_all)(void);
 	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
@@ -227,6 +234,7 @@ struct cpu_cache_fns {
 
 extern struct cpu_cache_fns cpu_cache;
 
+#define __cpuc_flush_icache_all		cpu_cache.flush_icache_all
 #define __cpuc_flush_kern_all		cpu_cache.flush_kern_all
 #define __cpuc_flush_user_all		cpu_cache.flush_user_all
 #define __cpuc_flush_user_range		cpu_cache.flush_user_range
@@ -246,6 +254,7 @@ extern struct cpu_cache_fns cpu_cache;
 
 #else
 
+#define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
 #define __cpuc_flush_user_all		__glue(_CACHE,_flush_user_cache_all)
 #define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
@@ -253,6 +262,7 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
 #define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
 
+extern void __cpuc_flush_icache_all(void);
 extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
@@ -291,6 +301,37 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 /*
  * Convert calls to our calling convention.
  */
+
+/* Invalidate I-cache */
+#define __flush_icache_all_generic()					\
+	asm("mcr	p15, 0, %0, c7, c5, 0"				\
+	    : : "r" (0));
+
+/* Invalidate I-cache inner shareable */
+#define __flush_icache_all_v7_smp()					\
+	asm("mcr	p15, 0, %0, c7, c1, 0"				\
+	    : : "r" (0));
+
+/*
+ * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
+ * will fall through to use __flush_icache_all_generic.
+ */
+#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) ||		\
+	defined(CONFIG_SMP_ON_UP)
+#define __flush_icache_preferred	__cpuc_flush_icache_all
+#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
+#define __flush_icache_preferred	__flush_icache_all_v7_smp
+#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
+#define __flush_icache_preferred	__cpuc_flush_icache_all
+#else
+#define __flush_icache_preferred	__flush_icache_all_generic
+#endif
+
+static inline void __flush_icache_all(void)
+{
+	__flush_icache_preferred();
+}
+
 #define flush_cache_all()		__cpuc_flush_kern_all()
 
 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
@@ -366,21 +407,6 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 extern void flush_dcache_page(struct page *);
 
-static inline void __flush_icache_all(void)
-{
-#ifdef CONFIG_ARM_ERRATA_411920
-	extern void v6_icache_inval_all(void);
-	v6_icache_inval_all();
-#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
-	    : "r" (0));
-#else
-	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-	    :
-	    : "r" (0));
-#endif
-}
 static inline void flush_kernel_vmap_range(void *addr, int size)
 {
 	if ((cache_is_vivt() || cache_is_vipt_aliasing()))
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -21,18 +21,22 @@
 #define D_CACHE_LINE_SIZE	32
 #define BTB_FLUSH_SIZE		8
 
-#ifdef CONFIG_ARM_ERRATA_411920
 /*
- * Invalidate the entire I cache (this code is a workaround for the ARM1136
- * erratum 411920 - Invalidate Instruction Cache operation can fail. This
- * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
+ *	v6_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
  *
- * Registers:
- *   r0 - set to 0
- *   r1 - corrupted
+ *	ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
+ *	This erratum is present in 1136, 1156 and 1176. It does not affect the
+ *	MPCore.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ *	r1 - corrupted
  */
-ENTRY(v6_icache_inval_all)
+ENTRY(v6_flush_icache_all)
 	mov	r0, #0
+#ifdef CONFIG_ARM_ERRATA_411920
 	mrs	r1, cpsr
 	cpsid	ifa				@ disable interrupts
 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
@@ -43,8 +47,11 @@ ENTRY(v6_icache_inval_all)
 	.rept	11				@ ARM Ltd recommends at least
 	nop					@ 11 NOPs
 	.endr
-	mov	pc, lr
+#else
+	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I-cache
 #endif
+	mov	pc, lr
+ENDPROC(v6_flush_icache_all)
 
 /*
  *	v6_flush_cache_all()
@@ -60,7 +67,7 @@ ENTRY(v6_flush_kern_cache_all)
 #ifndef CONFIG_ARM_ERRATA_411920
 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 #else
-	b	v6_icache_inval_all
+	b	v6_flush_icache_all
 #endif
 #else
 	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
@@ -138,7 +145,7 @@ ENTRY(v6_coherent_user_range)
 #ifndef CONFIG_ARM_ERRATA_411920
 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 #else
-	b	v6_icache_inval_all
+	b	v6_flush_icache_all
 #endif
 #else
 	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
@@ -312,6 +319,7 @@ ENDPROC(v6_dma_unmap_area)
 
 	.type	v6_cache_fns, #object
 ENTRY(v6_cache_fns)
+	.long	v6_flush_icache_all
 	.long	v6_flush_kern_cache_all
 	.long	v6_flush_user_cache_all
 	.long	v6_flush_user_cache_range
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -18,6 +18,21 @@
 #include "proc-macros.S"
 
 /*
+ *	v7_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ */
+ENTRY(v7_flush_icache_all)
+	mov	r0, #0
+	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	ALT_UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
+	mov	pc, lr
+ENDPROC(v7_flush_icache_all)
+
+/*
  *	v7_flush_dcache_all()
  *
  *	Flush the whole D-cache.
@@ -303,6 +318,7 @@ ENDPROC(v7_dma_unmap_area)
 
 	.type	v7_cache_fns, #object
 ENTRY(v7_cache_fns)
+	.long	v7_flush_icache_all
 	.long	v7_flush_kern_cache_all
 	.long	v7_flush_user_cache_all
 	.long	v7_flush_user_cache_range

[PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100914 12:04]:
> 
> Here's a patch for __flush_icache_all. I believe this is the last
> remaining patch we need.
> 
> The only other thing I can think of are the conflicts with
> CONFIG_CPU_32v6K, on early ARM1136 and later ARM11 systems if somebody
> wants to compile a kernel that supports both. But that's not needed for
> omap2, so we can boot now omap2, 3 and 4 with a single defconfig :)

Here's an updated version with a typo fix s/fluch/flush/ from Anand.

Regards,

Tony

From: Tony Lindgren <tony@atomide.com>
Date: Mon, 20 Sep 2010 16:37:16 -0700
Subject: [PATCH] ARM: Handle __flush_icache_all for CONFIG_SMP_ON_UP

Do this by adding flush_icache_all to cache_fns for ARMv6 and 7.
As flush_icache_all may neeed to be called from flush_kern_cache_all,
add it as the first entry in the cache_fns.

Note that now we can remove the ARM_ERRATA_411920 dependency
to !SMP so it can be selected on UP ARMv6 processors, such
as omap2.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>

--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1017,7 +1017,7 @@ endif
 
 config ARM_ERRATA_411920
 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
-	depends on CPU_V6 && !SMP
+	depends on CPU_V6
 	help
 	  Invalidation of the Instruction Cache operation can
 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -156,6 +156,12 @@
  *	Please note that the implementation of these, and the required
  *	effects are cache-type (VIVT/VIPT/PIPT) specific.
  *
+ *	flush_icache_all()
+ *
+ *		Unconditionally clean and invalidate the entire icache.
+ *		Currently only needed for cache-v6.S and cache-v7.S, see
+ *		__flush_icache_all for the generic implementation.
+ *
  *	flush_kern_all()
  *
  *		Unconditionally clean and invalidate the entire cache.
@@ -206,6 +212,7 @@
  */
 
 struct cpu_cache_fns {
+	void (*flush_icache_all)(void);
 	void (*flush_kern_all)(void);
 	void (*flush_user_all)(void);
 	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
@@ -227,6 +234,7 @@ struct cpu_cache_fns {
 
 extern struct cpu_cache_fns cpu_cache;
 
+#define __cpuc_flush_icache_all		cpu_cache.flush_icache_all
 #define __cpuc_flush_kern_all		cpu_cache.flush_kern_all
 #define __cpuc_flush_user_all		cpu_cache.flush_user_all
 #define __cpuc_flush_user_range		cpu_cache.flush_user_range
@@ -246,6 +254,7 @@ extern struct cpu_cache_fns cpu_cache;
 
 #else
 
+#define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
 #define __cpuc_flush_user_all		__glue(_CACHE,_flush_user_cache_all)
 #define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
@@ -253,6 +262,7 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
 #define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
 
+extern void __cpuc_flush_icache_all(void);
 extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
@@ -291,6 +301,37 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 /*
  * Convert calls to our calling convention.
  */
+
+/* Invalidate I-cache */
+#define __flush_icache_all_generic()					\
+	asm("mcr	p15, 0, %0, c7, c5, 0"				\
+	    : : "r" (0));
+
+/* Invalidate I-cache inner shareable */
+#define __flush_icache_all_v7_smp()					\
+	asm("mcr	p15, 0, %0, c7, c1, 0"				\
+	    : : "r" (0));
+
+/*
+ * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
+ * will fall through to use __flush_icache_all_generic.
+ */
+#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) ||		\
+	defined(CONFIG_SMP_ON_UP)
+#define __flush_icache_preferred	__cpuc_flush_icache_all
+#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
+#define __flush_icache_preferred	__flush_icache_all_v7_smp
+#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
+#define __flush_icache_preferred	__cpuc_flush_icache_all
+#else
+#define __flush_icache_preferred	__flush_icache_all_generic
+#endif
+
+static inline void __flush_icache_all(void)
+{
+	__flush_icache_preferred();
+}
+
 #define flush_cache_all()		__cpuc_flush_kern_all()
 
 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
@@ -366,21 +407,6 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 extern void flush_dcache_page(struct page *);
 
-static inline void __flush_icache_all(void)
-{
-#ifdef CONFIG_ARM_ERRATA_411920
-	extern void v6_icache_inval_all(void);
-	v6_icache_inval_all();
-#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
-	    : "r" (0));
-#else
-	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-	    :
-	    : "r" (0));
-#endif
-}
 static inline void flush_kernel_vmap_range(void *addr, int size)
 {
 	if ((cache_is_vivt() || cache_is_vipt_aliasing()))
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -21,18 +21,22 @@
 #define D_CACHE_LINE_SIZE	32
 #define BTB_FLUSH_SIZE		8
 
-#ifdef CONFIG_ARM_ERRATA_411920
 /*
- * Invalidate the entire I cache (this code is a workaround for the ARM1136
- * erratum 411920 - Invalidate Instruction Cache operation can fail. This
- * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
+ *	v6_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
  *
- * Registers:
- *   r0 - set to 0
- *   r1 - corrupted
+ *	ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
+ *	This erratum is present in 1136, 1156 and 1176. It does not affect the
+ *	MPCore.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ *	r1 - corrupted
  */
-ENTRY(v6_icache_inval_all)
+ENTRY(v6_flush_icache_all)
 	mov	r0, #0
+#ifdef CONFIG_ARM_ERRATA_411920
 	mrs	r1, cpsr
 	cpsid	ifa				@ disable interrupts
 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
@@ -43,8 +47,11 @@ ENTRY(v6_icache_inval_all)
 	.rept	11				@ ARM Ltd recommends at least
 	nop					@ 11 NOPs
 	.endr
-	mov	pc, lr
+#else
+	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I-cache
 #endif
+	mov	pc, lr
+ENDPROC(v6_flush_icache_all)
 
 /*
  *	v6_flush_cache_all()
@@ -60,7 +67,7 @@ ENTRY(v6_flush_kern_cache_all)
 #ifndef CONFIG_ARM_ERRATA_411920
 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 #else
-	b	v6_icache_inval_all
+	b	v6_flush_icache_all
 #endif
 #else
 	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
@@ -138,7 +145,7 @@ ENTRY(v6_coherent_user_range)
 #ifndef CONFIG_ARM_ERRATA_411920
 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
 #else
-	b	v6_icache_inval_all
+	b	v6_flush_icache_all
 #endif
 #else
 	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
@@ -312,6 +319,7 @@ ENDPROC(v6_dma_unmap_area)
 
 	.type	v6_cache_fns, #object
 ENTRY(v6_cache_fns)
+	.long	v6_flush_icache_all
 	.long	v6_flush_kern_cache_all
 	.long	v6_flush_user_cache_all
 	.long	v6_flush_user_cache_range
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -18,6 +18,21 @@
 #include "proc-macros.S"
 
 /*
+ *	v7_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ */
+ENTRY(v7_flush_icache_all)
+	mov	r0, #0
+	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	ALT_UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
+	mov	pc, lr
+ENDPROC(v7_flush_icache_all)
+
+/*
  *	v7_flush_dcache_all()
  *
  *	Flush the whole D-cache.
@@ -303,6 +318,7 @@ ENDPROC(v7_dma_unmap_area)
 
 	.type	v7_cache_fns, #object
 ENTRY(v7_cache_fns)
+	.long	v7_flush_icache_all
 	.long	v7_flush_kern_cache_all
 	.long	v7_flush_user_cache_all
 	.long	v7_flush_user_cache_range

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Tony Lindgren]

Use SMP and UP macros for cacheflush. Note that __flush_icache_all
currently won't work properly on ARMv7 SMP if support for ARMv6 is
compiled in.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/cacheflush.h |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..09a893e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
 #include <asm/outercache.h>
+#include <asm/smp_plat.h>
 
 #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
@@ -372,8 +373,10 @@ static inline void __flush_icache_all(void)
 	extern void v6_icache_inval_all(void);
 	v6_icache_inval_all();
 #elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
+	asm(								\
+	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)	\
+	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
+	    :								\
 	    : "r" (0));
 #else
 	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-- 
1.7.1