[PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[James Clark]

Changes since v1:

  * Split patchset into kernel side and Perf tool changes

When SVE registers are pushed onto the stack the VG register is required to
unwind because the stack offsets would vary by the SVE register width at the
time when the sample was taken.

The patches ("[PATCH v2 0/2] perf: arm64: Kernel support for Dwarf unwinding
through SVE functions") add support for sampling the VG register to the kernel
and the docs. This is the patchset to add support to userspace perf.

A small change is also required to libunwind or libdw depending on which
unwinder is used, and these will be published later. Without these changes Perf
continues to work with both libraries, although the VG register is still not
used for unwinding. 

Thanks
James

James Clark (4):
  perf tools: arm64: Copy perf_regs.h from the kernel
  perf tools: Use dynamic register set for Dwarf unwind
  perf tools: arm64: Decouple Libunwind register names from Perf
  perf tools: arm64: Add support for VG register

 tools/arch/arm64/include/uapi/asm/perf_regs.h |  7 +-
 tools/perf/arch/arm64/util/perf_regs.c        | 34 +++++++++
 tools/perf/arch/arm64/util/unwind-libunwind.c | 73 +------------------
 tools/perf/util/evsel.c                       |  2 +-
 tools/perf/util/perf_regs.c                   |  2 +
 5 files changed, 45 insertions(+), 73 deletions(-)

-- 
2.28.0


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[PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[James Clark]

Changes since v1:

  * Split patchset into kernel side and Perf tool changes

When SVE registers are pushed onto the stack the VG register is required to
unwind because the stack offsets would vary by the SVE register width at the
time when the sample was taken.

The patches ("[PATCH v2 0/2] perf: arm64: Kernel support for Dwarf unwinding
through SVE functions") add support for sampling the VG register to the kernel
and the docs. This is the patchset to add support to userspace perf.

A small change is also required to libunwind or libdw depending on which
unwinder is used, and these will be published later. Without these changes Perf
continues to work with both libraries, although the VG register is still not
used for unwinding. 

Thanks
James

James Clark (4):
  perf tools: arm64: Copy perf_regs.h from the kernel
  perf tools: Use dynamic register set for Dwarf unwind
  perf tools: arm64: Decouple Libunwind register names from Perf
  perf tools: arm64: Add support for VG register

 tools/arch/arm64/include/uapi/asm/perf_regs.h |  7 +-
 tools/perf/arch/arm64/util/perf_regs.c        | 34 +++++++++
 tools/perf/arch/arm64/util/unwind-libunwind.c | 73 +------------------
 tools/perf/util/evsel.c                       |  2 +-
 tools/perf/util/perf_regs.c                   |  2 +
 5 files changed, 45 insertions(+), 73 deletions(-)

-- 
2.28.0

[PATCH v2 1/4] perf tools: arm64: Copy perf_regs.h from the kernel

[James Clark]

Get the updated header for the newly added VG register.

Signed-off-by: James Clark <james.clark@arm.com>
---
 tools/arch/arm64/include/uapi/asm/perf_regs.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/arch/arm64/include/uapi/asm/perf_regs.h b/tools/arch/arm64/include/uapi/asm/perf_regs.h
index d54daafa89e3..fd157f46727e 100644
--- a/tools/arch/arm64/include/uapi/asm/perf_regs.h
+++ b/tools/arch/arm64/include/uapi/asm/perf_regs.h
@@ -36,6 +36,11 @@ enum perf_event_arm_regs {
 	PERF_REG_ARM64_LR,
 	PERF_REG_ARM64_SP,
 	PERF_REG_ARM64_PC,
-	PERF_REG_ARM64_MAX,
+
+	/* Extended/pseudo registers */
+	PERF_REG_ARM64_VG = 46, // SVE Vector Granule
+
+	PERF_REG_ARM64_MAX = PERF_REG_ARM64_PC + 1,
+	PERF_REG_ARM64_EXTENDED_MAX = PERF_REG_ARM64_VG + 1
 };
 #endif /* _ASM_ARM64_PERF_REGS_H */
-- 
2.28.0


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[PATCH v2 1/4] perf tools: arm64: Copy perf_regs.h from the kernel

[James Clark]

Get the updated header for the newly added VG register.

Signed-off-by: James Clark <james.clark@arm.com>
---
 tools/arch/arm64/include/uapi/asm/perf_regs.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/arch/arm64/include/uapi/asm/perf_regs.h b/tools/arch/arm64/include/uapi/asm/perf_regs.h
index d54daafa89e3..fd157f46727e 100644
--- a/tools/arch/arm64/include/uapi/asm/perf_regs.h
+++ b/tools/arch/arm64/include/uapi/asm/perf_regs.h
@@ -36,6 +36,11 @@ enum perf_event_arm_regs {
 	PERF_REG_ARM64_LR,
 	PERF_REG_ARM64_SP,
 	PERF_REG_ARM64_PC,
-	PERF_REG_ARM64_MAX,
+
+	/* Extended/pseudo registers */
+	PERF_REG_ARM64_VG = 46, // SVE Vector Granule
+
+	PERF_REG_ARM64_MAX = PERF_REG_ARM64_PC + 1,
+	PERF_REG_ARM64_EXTENDED_MAX = PERF_REG_ARM64_VG + 1
 };
 #endif /* _ASM_ARM64_PERF_REGS_H */
-- 
2.28.0

Re: [PATCH v2 1/4] perf tools: arm64: Copy perf_regs.h from the kernel

[Leo Yan]

On Tue, May 17, 2022 at 11:20:02AM +0100, James Clark wrote:
> Get the updated header for the newly added VG register.
> 
> Signed-off-by: James Clark <james.clark@arm.com>

Reviewed-by: Leo Yan <leo.yan@linaro.org>

> ---
>  tools/arch/arm64/include/uapi/asm/perf_regs.h | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/arch/arm64/include/uapi/asm/perf_regs.h b/tools/arch/arm64/include/uapi/asm/perf_regs.h
> index d54daafa89e3..fd157f46727e 100644
> --- a/tools/arch/arm64/include/uapi/asm/perf_regs.h
> +++ b/tools/arch/arm64/include/uapi/asm/perf_regs.h
> @@ -36,6 +36,11 @@ enum perf_event_arm_regs {
>  	PERF_REG_ARM64_LR,
>  	PERF_REG_ARM64_SP,
>  	PERF_REG_ARM64_PC,
> -	PERF_REG_ARM64_MAX,
> +
> +	/* Extended/pseudo registers */
> +	PERF_REG_ARM64_VG = 46, // SVE Vector Granule
> +
> +	PERF_REG_ARM64_MAX = PERF_REG_ARM64_PC + 1,
> +	PERF_REG_ARM64_EXTENDED_MAX = PERF_REG_ARM64_VG + 1
>  };
>  #endif /* _ASM_ARM64_PERF_REGS_H */
> -- 
> 2.28.0
> 

Re: [PATCH v2 1/4] perf tools: arm64: Copy perf_regs.h from the kernel

[Leo Yan]

On Tue, May 17, 2022 at 11:20:02AM +0100, James Clark wrote:
> Get the updated header for the newly added VG register.
> 
> Signed-off-by: James Clark <james.clark@arm.com>

Reviewed-by: Leo Yan <leo.yan@linaro.org>

> ---
>  tools/arch/arm64/include/uapi/asm/perf_regs.h | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/arch/arm64/include/uapi/asm/perf_regs.h b/tools/arch/arm64/include/uapi/asm/perf_regs.h
> index d54daafa89e3..fd157f46727e 100644
> --- a/tools/arch/arm64/include/uapi/asm/perf_regs.h
> +++ b/tools/arch/arm64/include/uapi/asm/perf_regs.h
> @@ -36,6 +36,11 @@ enum perf_event_arm_regs {
>  	PERF_REG_ARM64_LR,
>  	PERF_REG_ARM64_SP,
>  	PERF_REG_ARM64_PC,
> -	PERF_REG_ARM64_MAX,
> +
> +	/* Extended/pseudo registers */
> +	PERF_REG_ARM64_VG = 46, // SVE Vector Granule
> +
> +	PERF_REG_ARM64_MAX = PERF_REG_ARM64_PC + 1,
> +	PERF_REG_ARM64_EXTENDED_MAX = PERF_REG_ARM64_VG + 1
>  };
>  #endif /* _ASM_ARM64_PERF_REGS_H */
> -- 
> 2.28.0
> 

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[PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind

[James Clark]

Architectures can detect availability of extra registers at
runtime so use this more complete set for unwinding. This
will include the VG register on arm64 in a later commit.

If the function isn't implemented then PERF_REGS_MASK is
returned and there is no change.

Signed-off-by: James Clark <james.clark@arm.com>
---
 tools/perf/util/evsel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 5fd7924f8eb3..787bbcbcd2ae 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -896,7 +896,7 @@ static void __evsel__config_callchain(struct evsel *evsel, struct record_opts *o
 					   "specifying a subset with --user-regs may render DWARF unwinding unreliable, "
 					   "so the minimal registers set (IP, SP) is explicitly forced.\n");
 			} else {
-				attr->sample_regs_user |= PERF_REGS_MASK;
+				attr->sample_regs_user |= arch__user_reg_mask();
 			}
 			attr->sample_stack_user = param->dump_size;
 			attr->exclude_callchain_user = 1;
-- 
2.28.0


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[PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind

[James Clark]

Architectures can detect availability of extra registers at
runtime so use this more complete set for unwinding. This
will include the VG register on arm64 in a later commit.

If the function isn't implemented then PERF_REGS_MASK is
returned and there is no change.

Signed-off-by: James Clark <james.clark@arm.com>
---
 tools/perf/util/evsel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 5fd7924f8eb3..787bbcbcd2ae 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -896,7 +896,7 @@ static void __evsel__config_callchain(struct evsel *evsel, struct record_opts *o
 					   "specifying a subset with --user-regs may render DWARF unwinding unreliable, "
 					   "so the minimal registers set (IP, SP) is explicitly forced.\n");
 			} else {
-				attr->sample_regs_user |= PERF_REGS_MASK;
+				attr->sample_regs_user |= arch__user_reg_mask();
 			}
 			attr->sample_stack_user = param->dump_size;
 			attr->exclude_callchain_user = 1;
-- 
2.28.0

Re: [PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind

[Leo Yan]

On Tue, May 17, 2022 at 11:20:03AM +0100, James Clark wrote:
> Architectures can detect availability of extra registers at
> runtime so use this more complete set for unwinding. This
> will include the VG register on arm64 in a later commit.
> 
> If the function isn't implemented then PERF_REGS_MASK is
> returned and there is no change.
> 
> Signed-off-by: James Clark <james.clark@arm.com>

This patch looks good to me:
Reviewed-by: Leo Yan <leo.yan@linaro.org>

Just curious, do you think should update the test (e.g.
arch/arm64/tests/dwarf-unwind.c) to use arch__user_reg_mask()?

Thanks,
Leo

> ---
>  tools/perf/util/evsel.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
> index 5fd7924f8eb3..787bbcbcd2ae 100644
> --- a/tools/perf/util/evsel.c
> +++ b/tools/perf/util/evsel.c
> @@ -896,7 +896,7 @@ static void __evsel__config_callchain(struct evsel *evsel, struct record_opts *o
>  					   "specifying a subset with --user-regs may render DWARF unwinding unreliable, "
>  					   "so the minimal registers set (IP, SP) is explicitly forced.\n");
>  			} else {
> -				attr->sample_regs_user |= PERF_REGS_MASK;
> +				attr->sample_regs_user |= arch__user_reg_mask();
>  			}
>  			attr->sample_stack_user = param->dump_size;
>  			attr->exclude_callchain_user = 1;
> -- 
> 2.28.0
> 

Re: [PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind

[Leo Yan]

On Tue, May 17, 2022 at 11:20:03AM +0100, James Clark wrote:
> Architectures can detect availability of extra registers at
> runtime so use this more complete set for unwinding. This
> will include the VG register on arm64 in a later commit.
> 
> If the function isn't implemented then PERF_REGS_MASK is
> returned and there is no change.
> 
> Signed-off-by: James Clark <james.clark@arm.com>

This patch looks good to me:
Reviewed-by: Leo Yan <leo.yan@linaro.org>

Just curious, do you think should update the test (e.g.
arch/arm64/tests/dwarf-unwind.c) to use arch__user_reg_mask()?

Thanks,
Leo

> ---
>  tools/perf/util/evsel.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
> index 5fd7924f8eb3..787bbcbcd2ae 100644
> --- a/tools/perf/util/evsel.c
> +++ b/tools/perf/util/evsel.c
> @@ -896,7 +896,7 @@ static void __evsel__config_callchain(struct evsel *evsel, struct record_opts *o
>  					   "specifying a subset with --user-regs may render DWARF unwinding unreliable, "
>  					   "so the minimal registers set (IP, SP) is explicitly forced.\n");
>  			} else {
> -				attr->sample_regs_user |= PERF_REGS_MASK;
> +				attr->sample_regs_user |= arch__user_reg_mask();
>  			}
>  			attr->sample_stack_user = param->dump_size;
>  			attr->exclude_callchain_user = 1;
> -- 
> 2.28.0
> 

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Re: [PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind

[James Clark]

On 17/05/2022 12:03, Leo Yan wrote:
> On Tue, May 17, 2022 at 11:20:03AM +0100, James Clark wrote:
>> Architectures can detect availability of extra registers at
>> runtime so use this more complete set for unwinding. This
>> will include the VG register on arm64 in a later commit.
>>
>> If the function isn't implemented then PERF_REGS_MASK is
>> returned and there is no change.
>>
>> Signed-off-by: James Clark <james.clark@arm.com>
> 
> This patch looks good to me:
> Reviewed-by: Leo Yan <leo.yan@linaro.org>
> 
> Just curious, do you think should update the test (e.g.
> arch/arm64/tests/dwarf-unwind.c) to use arch__user_reg_mask()?

I don't think so because the normal set of registers is manually
loaded in tools/perf/arch/arm64/tests/regs_load.S so it wouldn't
include this pseudo register. Also there is no SVE in the call
chain of the test so it would never have an effect.

I could add a new test for SVE, but it depends on getting the
libunwind changes through first so will have to come later.

Thanks,
James

> 
> Thanks,
> Leo
> 
>> ---
>>  tools/perf/util/evsel.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
>> index 5fd7924f8eb3..787bbcbcd2ae 100644
>> --- a/tools/perf/util/evsel.c
>> +++ b/tools/perf/util/evsel.c
>> @@ -896,7 +896,7 @@ static void __evsel__config_callchain(struct evsel *evsel, struct record_opts *o
>>  					   "specifying a subset with --user-regs may render DWARF unwinding unreliable, "
>>  					   "so the minimal registers set (IP, SP) is explicitly forced.\n");
>>  			} else {
>> -				attr->sample_regs_user |= PERF_REGS_MASK;
>> +				attr->sample_regs_user |= arch__user_reg_mask();
>>  			}
>>  			attr->sample_stack_user = param->dump_size;
>>  			attr->exclude_callchain_user = 1;
>> -- 
>> 2.28.0
>>

Re: [PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind

[James Clark]

On 17/05/2022 12:03, Leo Yan wrote:
> On Tue, May 17, 2022 at 11:20:03AM +0100, James Clark wrote:
>> Architectures can detect availability of extra registers at
>> runtime so use this more complete set for unwinding. This
>> will include the VG register on arm64 in a later commit.
>>
>> If the function isn't implemented then PERF_REGS_MASK is
>> returned and there is no change.
>>
>> Signed-off-by: James Clark <james.clark@arm.com>
> 
> This patch looks good to me:
> Reviewed-by: Leo Yan <leo.yan@linaro.org>
> 
> Just curious, do you think should update the test (e.g.
> arch/arm64/tests/dwarf-unwind.c) to use arch__user_reg_mask()?

I don't think so because the normal set of registers is manually
loaded in tools/perf/arch/arm64/tests/regs_load.S so it wouldn't
include this pseudo register. Also there is no SVE in the call
chain of the test so it would never have an effect.

I could add a new test for SVE, but it depends on getting the
libunwind changes through first so will have to come later.

Thanks,
James

> 
> Thanks,
> Leo
> 
>> ---
>>  tools/perf/util/evsel.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
>> index 5fd7924f8eb3..787bbcbcd2ae 100644
>> --- a/tools/perf/util/evsel.c
>> +++ b/tools/perf/util/evsel.c
>> @@ -896,7 +896,7 @@ static void __evsel__config_callchain(struct evsel *evsel, struct record_opts *o
>>  					   "specifying a subset with --user-regs may render DWARF unwinding unreliable, "
>>  					   "so the minimal registers set (IP, SP) is explicitly forced.\n");
>>  			} else {
>> -				attr->sample_regs_user |= PERF_REGS_MASK;
>> +				attr->sample_regs_user |= arch__user_reg_mask();
>>  			}
>>  			attr->sample_stack_user = param->dump_size;
>>  			attr->exclude_callchain_user = 1;
>> -- 
>> 2.28.0
>>

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Re: [PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind

[Leo Yan]

On Wed, May 18, 2022 at 02:25:38PM +0100, James Clark wrote:
> 
> 
> On 17/05/2022 12:03, Leo Yan wrote:
> > On Tue, May 17, 2022 at 11:20:03AM +0100, James Clark wrote:
> >> Architectures can detect availability of extra registers at
> >> runtime so use this more complete set for unwinding. This
> >> will include the VG register on arm64 in a later commit.
> >>
> >> If the function isn't implemented then PERF_REGS_MASK is
> >> returned and there is no change.
> >>
> >> Signed-off-by: James Clark <james.clark@arm.com>
> > 
> > This patch looks good to me:
> > Reviewed-by: Leo Yan <leo.yan@linaro.org>
> > 
> > Just curious, do you think should update the test (e.g.
> > arch/arm64/tests/dwarf-unwind.c) to use arch__user_reg_mask()?
> 
> I don't think so because the normal set of registers is manually
> loaded in tools/perf/arch/arm64/tests/regs_load.S so it wouldn't
> include this pseudo register. Also there is no SVE in the call
> chain of the test so it would never have an effect.
> 
> I could add a new test for SVE, but it depends on getting the
> libunwind changes through first so will have to come later.

It makes sense to add new SVE test later, thanks for clarification.

So this patch series looks good for me.

Leo

Re: [PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind

[Leo Yan]

On Wed, May 18, 2022 at 02:25:38PM +0100, James Clark wrote:
> 
> 
> On 17/05/2022 12:03, Leo Yan wrote:
> > On Tue, May 17, 2022 at 11:20:03AM +0100, James Clark wrote:
> >> Architectures can detect availability of extra registers at
> >> runtime so use this more complete set for unwinding. This
> >> will include the VG register on arm64 in a later commit.
> >>
> >> If the function isn't implemented then PERF_REGS_MASK is
> >> returned and there is no change.
> >>
> >> Signed-off-by: James Clark <james.clark@arm.com>
> > 
> > This patch looks good to me:
> > Reviewed-by: Leo Yan <leo.yan@linaro.org>
> > 
> > Just curious, do you think should update the test (e.g.
> > arch/arm64/tests/dwarf-unwind.c) to use arch__user_reg_mask()?
> 
> I don't think so because the normal set of registers is manually
> loaded in tools/perf/arch/arm64/tests/regs_load.S so it wouldn't
> include this pseudo register. Also there is no SVE in the call
> chain of the test so it would never have an effect.
> 
> I could add a new test for SVE, but it depends on getting the
> libunwind changes through first so will have to come later.

It makes sense to add new SVE test later, thanks for clarification.

So this patch series looks good for me.

Leo

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[PATCH v2 3/4] perf tools: arm64: Decouple Libunwind register names from Perf

[James Clark]

Dwarf register numbers and real register numbers on aarch64 are
equivalent. Remove the references to the register names from
Libunwind so that new registers are supported without having to
add build time feature checks for each new register.

The unwinder won't ask for a register that it doesn't know about
and Perf will already report an error for an unknown or unrecorded
register in the perf_reg_value() function so extra validation
isn't needed.

After this change the new VG register can be read by libunwind.

Signed-off-by: James Clark <james.clark@arm.com>
---
 tools/perf/arch/arm64/util/unwind-libunwind.c | 73 +------------------
 1 file changed, 2 insertions(+), 71 deletions(-)

diff --git a/tools/perf/arch/arm64/util/unwind-libunwind.c b/tools/perf/arch/arm64/util/unwind-libunwind.c
index 5aecf88e3de6..871af5992298 100644
--- a/tools/perf/arch/arm64/util/unwind-libunwind.c
+++ b/tools/perf/arch/arm64/util/unwind-libunwind.c
@@ -10,77 +10,8 @@
 
 int LIBUNWIND__ARCH_REG_ID(int regnum)
 {
-	switch (regnum) {
-	case UNW_AARCH64_X0:
-		return PERF_REG_ARM64_X0;
-	case UNW_AARCH64_X1:
-		return PERF_REG_ARM64_X1;
-	case UNW_AARCH64_X2:
-		return PERF_REG_ARM64_X2;
-	case UNW_AARCH64_X3:
-		return PERF_REG_ARM64_X3;
-	case UNW_AARCH64_X4:
-		return PERF_REG_ARM64_X4;
-	case UNW_AARCH64_X5:
-		return PERF_REG_ARM64_X5;
-	case UNW_AARCH64_X6:
-		return PERF_REG_ARM64_X6;
-	case UNW_AARCH64_X7:
-		return PERF_REG_ARM64_X7;
-	case UNW_AARCH64_X8:
-		return PERF_REG_ARM64_X8;
-	case UNW_AARCH64_X9:
-		return PERF_REG_ARM64_X9;
-	case UNW_AARCH64_X10:
-		return PERF_REG_ARM64_X10;
-	case UNW_AARCH64_X11:
-		return PERF_REG_ARM64_X11;
-	case UNW_AARCH64_X12:
-		return PERF_REG_ARM64_X12;
-	case UNW_AARCH64_X13:
-		return PERF_REG_ARM64_X13;
-	case UNW_AARCH64_X14:
-		return PERF_REG_ARM64_X14;
-	case UNW_AARCH64_X15:
-		return PERF_REG_ARM64_X15;
-	case UNW_AARCH64_X16:
-		return PERF_REG_ARM64_X16;
-	case UNW_AARCH64_X17:
-		return PERF_REG_ARM64_X17;
-	case UNW_AARCH64_X18:
-		return PERF_REG_ARM64_X18;
-	case UNW_AARCH64_X19:
-		return PERF_REG_ARM64_X19;
-	case UNW_AARCH64_X20:
-		return PERF_REG_ARM64_X20;
-	case UNW_AARCH64_X21:
-		return PERF_REG_ARM64_X21;
-	case UNW_AARCH64_X22:
-		return PERF_REG_ARM64_X22;
-	case UNW_AARCH64_X23:
-		return PERF_REG_ARM64_X23;
-	case UNW_AARCH64_X24:
-		return PERF_REG_ARM64_X24;
-	case UNW_AARCH64_X25:
-		return PERF_REG_ARM64_X25;
-	case UNW_AARCH64_X26:
-		return PERF_REG_ARM64_X26;
-	case UNW_AARCH64_X27:
-		return PERF_REG_ARM64_X27;
-	case UNW_AARCH64_X28:
-		return PERF_REG_ARM64_X28;
-	case UNW_AARCH64_X29:
-		return PERF_REG_ARM64_X29;
-	case UNW_AARCH64_X30:
-		return PERF_REG_ARM64_LR;
-	case UNW_AARCH64_SP:
-		return PERF_REG_ARM64_SP;
-	case UNW_AARCH64_PC:
-		return PERF_REG_ARM64_PC;
-	default:
-		pr_err("unwind: invalid reg id %d\n", regnum);
+	if (regnum < 0 || regnum >= PERF_REG_ARM64_EXTENDED_MAX)
 		return -EINVAL;
-	}
 
-	return -EINVAL;
+	return regnum;
 }
-- 
2.28.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 3/4] perf tools: arm64: Decouple Libunwind register names from Perf

[James Clark]

Dwarf register numbers and real register numbers on aarch64 are
equivalent. Remove the references to the register names from
Libunwind so that new registers are supported without having to
add build time feature checks for each new register.

The unwinder won't ask for a register that it doesn't know about
and Perf will already report an error for an unknown or unrecorded
register in the perf_reg_value() function so extra validation
isn't needed.

After this change the new VG register can be read by libunwind.

Signed-off-by: James Clark <james.clark@arm.com>
---
 tools/perf/arch/arm64/util/unwind-libunwind.c | 73 +------------------
 1 file changed, 2 insertions(+), 71 deletions(-)

diff --git a/tools/perf/arch/arm64/util/unwind-libunwind.c b/tools/perf/arch/arm64/util/unwind-libunwind.c
index 5aecf88e3de6..871af5992298 100644
--- a/tools/perf/arch/arm64/util/unwind-libunwind.c
+++ b/tools/perf/arch/arm64/util/unwind-libunwind.c
@@ -10,77 +10,8 @@
 
 int LIBUNWIND__ARCH_REG_ID(int regnum)
 {
-	switch (regnum) {
-	case UNW_AARCH64_X0:
-		return PERF_REG_ARM64_X0;
-	case UNW_AARCH64_X1:
-		return PERF_REG_ARM64_X1;
-	case UNW_AARCH64_X2:
-		return PERF_REG_ARM64_X2;
-	case UNW_AARCH64_X3:
-		return PERF_REG_ARM64_X3;
-	case UNW_AARCH64_X4:
-		return PERF_REG_ARM64_X4;
-	case UNW_AARCH64_X5:
-		return PERF_REG_ARM64_X5;
-	case UNW_AARCH64_X6:
-		return PERF_REG_ARM64_X6;
-	case UNW_AARCH64_X7:
-		return PERF_REG_ARM64_X7;
-	case UNW_AARCH64_X8:
-		return PERF_REG_ARM64_X8;
-	case UNW_AARCH64_X9:
-		return PERF_REG_ARM64_X9;
-	case UNW_AARCH64_X10:
-		return PERF_REG_ARM64_X10;
-	case UNW_AARCH64_X11:
-		return PERF_REG_ARM64_X11;
-	case UNW_AARCH64_X12:
-		return PERF_REG_ARM64_X12;
-	case UNW_AARCH64_X13:
-		return PERF_REG_ARM64_X13;
-	case UNW_AARCH64_X14:
-		return PERF_REG_ARM64_X14;
-	case UNW_AARCH64_X15:
-		return PERF_REG_ARM64_X15;
-	case UNW_AARCH64_X16:
-		return PERF_REG_ARM64_X16;
-	case UNW_AARCH64_X17:
-		return PERF_REG_ARM64_X17;
-	case UNW_AARCH64_X18:
-		return PERF_REG_ARM64_X18;
-	case UNW_AARCH64_X19:
-		return PERF_REG_ARM64_X19;
-	case UNW_AARCH64_X20:
-		return PERF_REG_ARM64_X20;
-	case UNW_AARCH64_X21:
-		return PERF_REG_ARM64_X21;
-	case UNW_AARCH64_X22:
-		return PERF_REG_ARM64_X22;
-	case UNW_AARCH64_X23:
-		return PERF_REG_ARM64_X23;
-	case UNW_AARCH64_X24:
-		return PERF_REG_ARM64_X24;
-	case UNW_AARCH64_X25:
-		return PERF_REG_ARM64_X25;
-	case UNW_AARCH64_X26:
-		return PERF_REG_ARM64_X26;
-	case UNW_AARCH64_X27:
-		return PERF_REG_ARM64_X27;
-	case UNW_AARCH64_X28:
-		return PERF_REG_ARM64_X28;
-	case UNW_AARCH64_X29:
-		return PERF_REG_ARM64_X29;
-	case UNW_AARCH64_X30:
-		return PERF_REG_ARM64_LR;
-	case UNW_AARCH64_SP:
-		return PERF_REG_ARM64_SP;
-	case UNW_AARCH64_PC:
-		return PERF_REG_ARM64_PC;
-	default:
-		pr_err("unwind: invalid reg id %d\n", regnum);
+	if (regnum < 0 || regnum >= PERF_REG_ARM64_EXTENDED_MAX)
 		return -EINVAL;
-	}
 
-	return -EINVAL;
+	return regnum;
 }
-- 
2.28.0

Re: [PATCH v2 3/4] perf tools: arm64: Decouple Libunwind register names from Perf

[Leo Yan]

On Tue, May 17, 2022 at 11:20:04AM +0100, James Clark wrote:
> Dwarf register numbers and real register numbers on aarch64 are
> equivalent. Remove the references to the register names from
> Libunwind so that new registers are supported without having to
> add build time feature checks for each new register.
> 
> The unwinder won't ask for a register that it doesn't know about
> and Perf will already report an error for an unknown or unrecorded
> register in the perf_reg_value() function so extra validation
> isn't needed.
> 
> After this change the new VG register can be read by libunwind.
> 
> Signed-off-by: James Clark <james.clark@arm.com>

Looks good to me:

Reviewed-by: Leo Yan <leo.yan@linaro.org>

Re: [PATCH v2 3/4] perf tools: arm64: Decouple Libunwind register names from Perf

[Leo Yan]

On Tue, May 17, 2022 at 11:20:04AM +0100, James Clark wrote:
> Dwarf register numbers and real register numbers on aarch64 are
> equivalent. Remove the references to the register names from
> Libunwind so that new registers are supported without having to
> add build time feature checks for each new register.
> 
> The unwinder won't ask for a register that it doesn't know about
> and Perf will already report an error for an unknown or unrecorded
> register in the perf_reg_value() function so extra validation
> isn't needed.
> 
> After this change the new VG register can be read by libunwind.
> 
> Signed-off-by: James Clark <james.clark@arm.com>

Looks good to me:

Reviewed-by: Leo Yan <leo.yan@linaro.org>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 4/4] perf tools: arm64: Add support for VG register

[James Clark]

Add the name of the VG register so it can be used in --user-regs

The event will fail to open if the register is requested but not
available so only add it to the mask if the kernel supports sve and also
if it supports that specific register.

Signed-off-by: James Clark <james.clark@arm.com>
---
 tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++
 tools/perf/util/perf_regs.c            |  2 ++
 2 files changed, 36 insertions(+)

diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64/util/perf_regs.c
index 476b037eea1c..c0a921512a90 100644
--- a/tools/perf/arch/arm64/util/perf_regs.c
+++ b/tools/perf/arch/arm64/util/perf_regs.c
@@ -2,9 +2,11 @@
 #include <errno.h>
 #include <regex.h>
 #include <string.h>
+#include <sys/auxv.h>
 #include <linux/kernel.h>
 #include <linux/zalloc.h>
 
+#include "../../../perf-sys.h"
 #include "../../../util/debug.h"
 #include "../../../util/event.h"
 #include "../../../util/perf_regs.h"
@@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] = {
 	SMPL_REG(lr, PERF_REG_ARM64_LR),
 	SMPL_REG(sp, PERF_REG_ARM64_SP),
 	SMPL_REG(pc, PERF_REG_ARM64_PC),
+	SMPL_REG(vg, PERF_REG_ARM64_VG),
 	SMPL_REG_END
 };
 
@@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op)
 
 	return SDT_ARG_VALID;
 }
+
+uint64_t arch__user_reg_mask(void)
+{
+	struct perf_event_attr attr = {
+		.type                   = PERF_TYPE_HARDWARE,
+		.config                 = PERF_COUNT_HW_CPU_CYCLES,
+		.sample_type            = PERF_SAMPLE_REGS_USER,
+		.disabled               = 1,
+		.exclude_kernel         = 1,
+		.sample_period		= 1,
+		.sample_regs_user	= PERF_REGS_MASK
+	};
+	int fd;
+
+	if (getauxval(AT_HWCAP) & HWCAP_SVE)
+		attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
+
+	/*
+	 * Check if the pmu supports perf extended regs, before
+	 * returning the register mask to sample.
+	 */
+	if (attr.sample_regs_user != PERF_REGS_MASK) {
+		event_attr_init(&attr);
+		fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
+		if (fd != -1) {
+			close(fd);
+			return attr.sample_regs_user;
+		}
+	}
+	return PERF_REGS_MASK;
+}
diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
index a982e40ee5a9..872dd3d38782 100644
--- a/tools/perf/util/perf_regs.c
+++ b/tools/perf/util/perf_regs.c
@@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id)
 		return "lr";
 	case PERF_REG_ARM64_PC:
 		return "pc";
+	case PERF_REG_ARM64_VG:
+		return "vg";
 	default:
 		return NULL;
 	}
-- 
2.28.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 4/4] perf tools: arm64: Add support for VG register

[James Clark]

Add the name of the VG register so it can be used in --user-regs

The event will fail to open if the register is requested but not
available so only add it to the mask if the kernel supports sve and also
if it supports that specific register.

Signed-off-by: James Clark <james.clark@arm.com>
---
 tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++
 tools/perf/util/perf_regs.c            |  2 ++
 2 files changed, 36 insertions(+)

diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64/util/perf_regs.c
index 476b037eea1c..c0a921512a90 100644
--- a/tools/perf/arch/arm64/util/perf_regs.c
+++ b/tools/perf/arch/arm64/util/perf_regs.c
@@ -2,9 +2,11 @@
 #include <errno.h>
 #include <regex.h>
 #include <string.h>
+#include <sys/auxv.h>
 #include <linux/kernel.h>
 #include <linux/zalloc.h>
 
+#include "../../../perf-sys.h"
 #include "../../../util/debug.h"
 #include "../../../util/event.h"
 #include "../../../util/perf_regs.h"
@@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] = {
 	SMPL_REG(lr, PERF_REG_ARM64_LR),
 	SMPL_REG(sp, PERF_REG_ARM64_SP),
 	SMPL_REG(pc, PERF_REG_ARM64_PC),
+	SMPL_REG(vg, PERF_REG_ARM64_VG),
 	SMPL_REG_END
 };
 
@@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op)
 
 	return SDT_ARG_VALID;
 }
+
+uint64_t arch__user_reg_mask(void)
+{
+	struct perf_event_attr attr = {
+		.type                   = PERF_TYPE_HARDWARE,
+		.config                 = PERF_COUNT_HW_CPU_CYCLES,
+		.sample_type            = PERF_SAMPLE_REGS_USER,
+		.disabled               = 1,
+		.exclude_kernel         = 1,
+		.sample_period		= 1,
+		.sample_regs_user	= PERF_REGS_MASK
+	};
+	int fd;
+
+	if (getauxval(AT_HWCAP) & HWCAP_SVE)
+		attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
+
+	/*
+	 * Check if the pmu supports perf extended regs, before
+	 * returning the register mask to sample.
+	 */
+	if (attr.sample_regs_user != PERF_REGS_MASK) {
+		event_attr_init(&attr);
+		fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
+		if (fd != -1) {
+			close(fd);
+			return attr.sample_regs_user;
+		}
+	}
+	return PERF_REGS_MASK;
+}
diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
index a982e40ee5a9..872dd3d38782 100644
--- a/tools/perf/util/perf_regs.c
+++ b/tools/perf/util/perf_regs.c
@@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id)
 		return "lr";
 	case PERF_REG_ARM64_PC:
 		return "pc";
+	case PERF_REG_ARM64_VG:
+		return "vg";
 	default:
 		return NULL;
 	}
-- 
2.28.0

Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register

[Leo Yan]

On Tue, May 17, 2022 at 11:20:05AM +0100, James Clark wrote:
> Add the name of the VG register so it can be used in --user-regs
> 
> The event will fail to open if the register is requested but not
> available so only add it to the mask if the kernel supports sve and also
> if it supports that specific register.
> 
> Signed-off-by: James Clark <james.clark@arm.com>
> ---
>  tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++
>  tools/perf/util/perf_regs.c            |  2 ++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64/util/perf_regs.c
> index 476b037eea1c..c0a921512a90 100644
> --- a/tools/perf/arch/arm64/util/perf_regs.c
> +++ b/tools/perf/arch/arm64/util/perf_regs.c
> @@ -2,9 +2,11 @@
>  #include <errno.h>
>  #include <regex.h>
>  #include <string.h>
> +#include <sys/auxv.h>
>  #include <linux/kernel.h>
>  #include <linux/zalloc.h>
>  
> +#include "../../../perf-sys.h"
>  #include "../../../util/debug.h"
>  #include "../../../util/event.h"
>  #include "../../../util/perf_regs.h"
> @@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] = {
>  	SMPL_REG(lr, PERF_REG_ARM64_LR),
>  	SMPL_REG(sp, PERF_REG_ARM64_SP),
>  	SMPL_REG(pc, PERF_REG_ARM64_PC),
> +	SMPL_REG(vg, PERF_REG_ARM64_VG),
>  	SMPL_REG_END
>  };
>  
> @@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op)
>  
>  	return SDT_ARG_VALID;
>  }
> +
> +uint64_t arch__user_reg_mask(void)
> +{
> +	struct perf_event_attr attr = {
> +		.type                   = PERF_TYPE_HARDWARE,
> +		.config                 = PERF_COUNT_HW_CPU_CYCLES,
> +		.sample_type            = PERF_SAMPLE_REGS_USER,
> +		.disabled               = 1,
> +		.exclude_kernel         = 1,
> +		.sample_period		= 1,
> +		.sample_regs_user	= PERF_REGS_MASK
> +	};
> +	int fd;
> +
> +	if (getauxval(AT_HWCAP) & HWCAP_SVE)
> +		attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
> +
> +	/*
> +	 * Check if the pmu supports perf extended regs, before
> +	 * returning the register mask to sample.
> +	 */
> +	if (attr.sample_regs_user != PERF_REGS_MASK) {
> +		event_attr_init(&attr);
> +		fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
> +		if (fd != -1) {
> +			close(fd);
> +			return attr.sample_regs_user;
> +		}
> +	}

Just curious, since we can know SVE is supported from reading
auxiliary value, can we directly return the register mask as below?

  PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG);

Except this question, this patch looks good to me.

Thanks,
Leo

> +	return PERF_REGS_MASK;
> +}
> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
> index a982e40ee5a9..872dd3d38782 100644
> --- a/tools/perf/util/perf_regs.c
> +++ b/tools/perf/util/perf_regs.c
> @@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id)
>  		return "lr";
>  	case PERF_REG_ARM64_PC:
>  		return "pc";
> +	case PERF_REG_ARM64_VG:
> +		return "vg";
>  	default:
>  		return NULL;
>  	}
> -- 
> 2.28.0
> 

Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register

[Leo Yan]

On Tue, May 17, 2022 at 11:20:05AM +0100, James Clark wrote:
> Add the name of the VG register so it can be used in --user-regs
> 
> The event will fail to open if the register is requested but not
> available so only add it to the mask if the kernel supports sve and also
> if it supports that specific register.
> 
> Signed-off-by: James Clark <james.clark@arm.com>
> ---
>  tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++
>  tools/perf/util/perf_regs.c            |  2 ++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64/util/perf_regs.c
> index 476b037eea1c..c0a921512a90 100644
> --- a/tools/perf/arch/arm64/util/perf_regs.c
> +++ b/tools/perf/arch/arm64/util/perf_regs.c
> @@ -2,9 +2,11 @@
>  #include <errno.h>
>  #include <regex.h>
>  #include <string.h>
> +#include <sys/auxv.h>
>  #include <linux/kernel.h>
>  #include <linux/zalloc.h>
>  
> +#include "../../../perf-sys.h"
>  #include "../../../util/debug.h"
>  #include "../../../util/event.h"
>  #include "../../../util/perf_regs.h"
> @@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] = {
>  	SMPL_REG(lr, PERF_REG_ARM64_LR),
>  	SMPL_REG(sp, PERF_REG_ARM64_SP),
>  	SMPL_REG(pc, PERF_REG_ARM64_PC),
> +	SMPL_REG(vg, PERF_REG_ARM64_VG),
>  	SMPL_REG_END
>  };
>  
> @@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op)
>  
>  	return SDT_ARG_VALID;
>  }
> +
> +uint64_t arch__user_reg_mask(void)
> +{
> +	struct perf_event_attr attr = {
> +		.type                   = PERF_TYPE_HARDWARE,
> +		.config                 = PERF_COUNT_HW_CPU_CYCLES,
> +		.sample_type            = PERF_SAMPLE_REGS_USER,
> +		.disabled               = 1,
> +		.exclude_kernel         = 1,
> +		.sample_period		= 1,
> +		.sample_regs_user	= PERF_REGS_MASK
> +	};
> +	int fd;
> +
> +	if (getauxval(AT_HWCAP) & HWCAP_SVE)
> +		attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
> +
> +	/*
> +	 * Check if the pmu supports perf extended regs, before
> +	 * returning the register mask to sample.
> +	 */
> +	if (attr.sample_regs_user != PERF_REGS_MASK) {
> +		event_attr_init(&attr);
> +		fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
> +		if (fd != -1) {
> +			close(fd);
> +			return attr.sample_regs_user;
> +		}
> +	}

Just curious, since we can know SVE is supported from reading
auxiliary value, can we directly return the register mask as below?

  PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG);

Except this question, this patch looks good to me.

Thanks,
Leo

> +	return PERF_REGS_MASK;
> +}
> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
> index a982e40ee5a9..872dd3d38782 100644
> --- a/tools/perf/util/perf_regs.c
> +++ b/tools/perf/util/perf_regs.c
> @@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id)
>  		return "lr";
>  	case PERF_REG_ARM64_PC:
>  		return "pc";
> +	case PERF_REG_ARM64_VG:
> +		return "vg";
>  	default:
>  		return NULL;
>  	}
> -- 
> 2.28.0
> 

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Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register

[James Clark]

On 17/05/2022 14:19, Leo Yan wrote:
> On Tue, May 17, 2022 at 11:20:05AM +0100, James Clark wrote:
>> Add the name of the VG register so it can be used in --user-regs
>>
>> The event will fail to open if the register is requested but not
>> available so only add it to the mask if the kernel supports sve and also
>> if it supports that specific register.
>>
>> Signed-off-by: James Clark <james.clark@arm.com>
>> ---
>>  tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++
>>  tools/perf/util/perf_regs.c            |  2 ++
>>  2 files changed, 36 insertions(+)
>>
>> diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64/util/perf_regs.c
>> index 476b037eea1c..c0a921512a90 100644
>> --- a/tools/perf/arch/arm64/util/perf_regs.c
>> +++ b/tools/perf/arch/arm64/util/perf_regs.c
>> @@ -2,9 +2,11 @@
>>  #include <errno.h>
>>  #include <regex.h>
>>  #include <string.h>
>> +#include <sys/auxv.h>
>>  #include <linux/kernel.h>
>>  #include <linux/zalloc.h>
>>  
>> +#include "../../../perf-sys.h"
>>  #include "../../../util/debug.h"
>>  #include "../../../util/event.h"
>>  #include "../../../util/perf_regs.h"
>> @@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] = {
>>  	SMPL_REG(lr, PERF_REG_ARM64_LR),
>>  	SMPL_REG(sp, PERF_REG_ARM64_SP),
>>  	SMPL_REG(pc, PERF_REG_ARM64_PC),
>> +	SMPL_REG(vg, PERF_REG_ARM64_VG),
>>  	SMPL_REG_END
>>  };
>>  
>> @@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op)
>>  
>>  	return SDT_ARG_VALID;
>>  }
>> +
>> +uint64_t arch__user_reg_mask(void)
>> +{
>> +	struct perf_event_attr attr = {
>> +		.type                   = PERF_TYPE_HARDWARE,
>> +		.config                 = PERF_COUNT_HW_CPU_CYCLES,
>> +		.sample_type            = PERF_SAMPLE_REGS_USER,
>> +		.disabled               = 1,
>> +		.exclude_kernel         = 1,
>> +		.sample_period		= 1,
>> +		.sample_regs_user	= PERF_REGS_MASK
>> +	};
>> +	int fd;
>> +
>> +	if (getauxval(AT_HWCAP) & HWCAP_SVE)
>> +		attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
>> +
>> +	/*
>> +	 * Check if the pmu supports perf extended regs, before
>> +	 * returning the register mask to sample.
>> +	 */
>> +	if (attr.sample_regs_user != PERF_REGS_MASK) {
>> +		event_attr_init(&attr);
>> +		fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
>> +		if (fd != -1) {
>> +			close(fd);
>> +			return attr.sample_regs_user;
>> +		}
>> +	}
> 
> Just curious, since we can know SVE is supported from reading
> auxiliary value, can we directly return the register mask as below?
> 
>   PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG);

I was trying to cover the case where the system supports SVE, but
the kernel doesn't have my changes to add the VG register yet.

Technically I could just attempt to open the event without checking
for SVE first and see if it works or not. But I preferred to be
explicit so it's obvious why we're doing that.

James

> 
> Except this question, this patch looks good to me.
> 
> Thanks,
> Leo
> 
>> +	return PERF_REGS_MASK;
>> +}
>> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
>> index a982e40ee5a9..872dd3d38782 100644
>> --- a/tools/perf/util/perf_regs.c
>> +++ b/tools/perf/util/perf_regs.c
>> @@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id)
>>  		return "lr";
>>  	case PERF_REG_ARM64_PC:
>>  		return "pc";
>> +	case PERF_REG_ARM64_VG:
>> +		return "vg";
>>  	default:
>>  		return NULL;
>>  	}
>> -- 
>> 2.28.0
>>

Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register

[James Clark]

On 17/05/2022 14:19, Leo Yan wrote:
> On Tue, May 17, 2022 at 11:20:05AM +0100, James Clark wrote:
>> Add the name of the VG register so it can be used in --user-regs
>>
>> The event will fail to open if the register is requested but not
>> available so only add it to the mask if the kernel supports sve and also
>> if it supports that specific register.
>>
>> Signed-off-by: James Clark <james.clark@arm.com>
>> ---
>>  tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++
>>  tools/perf/util/perf_regs.c            |  2 ++
>>  2 files changed, 36 insertions(+)
>>
>> diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64/util/perf_regs.c
>> index 476b037eea1c..c0a921512a90 100644
>> --- a/tools/perf/arch/arm64/util/perf_regs.c
>> +++ b/tools/perf/arch/arm64/util/perf_regs.c
>> @@ -2,9 +2,11 @@
>>  #include <errno.h>
>>  #include <regex.h>
>>  #include <string.h>
>> +#include <sys/auxv.h>
>>  #include <linux/kernel.h>
>>  #include <linux/zalloc.h>
>>  
>> +#include "../../../perf-sys.h"
>>  #include "../../../util/debug.h"
>>  #include "../../../util/event.h"
>>  #include "../../../util/perf_regs.h"
>> @@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] = {
>>  	SMPL_REG(lr, PERF_REG_ARM64_LR),
>>  	SMPL_REG(sp, PERF_REG_ARM64_SP),
>>  	SMPL_REG(pc, PERF_REG_ARM64_PC),
>> +	SMPL_REG(vg, PERF_REG_ARM64_VG),
>>  	SMPL_REG_END
>>  };
>>  
>> @@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op)
>>  
>>  	return SDT_ARG_VALID;
>>  }
>> +
>> +uint64_t arch__user_reg_mask(void)
>> +{
>> +	struct perf_event_attr attr = {
>> +		.type                   = PERF_TYPE_HARDWARE,
>> +		.config                 = PERF_COUNT_HW_CPU_CYCLES,
>> +		.sample_type            = PERF_SAMPLE_REGS_USER,
>> +		.disabled               = 1,
>> +		.exclude_kernel         = 1,
>> +		.sample_period		= 1,
>> +		.sample_regs_user	= PERF_REGS_MASK
>> +	};
>> +	int fd;
>> +
>> +	if (getauxval(AT_HWCAP) & HWCAP_SVE)
>> +		attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
>> +
>> +	/*
>> +	 * Check if the pmu supports perf extended regs, before
>> +	 * returning the register mask to sample.
>> +	 */
>> +	if (attr.sample_regs_user != PERF_REGS_MASK) {
>> +		event_attr_init(&attr);
>> +		fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
>> +		if (fd != -1) {
>> +			close(fd);
>> +			return attr.sample_regs_user;
>> +		}
>> +	}
> 
> Just curious, since we can know SVE is supported from reading
> auxiliary value, can we directly return the register mask as below?
> 
>   PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG);

I was trying to cover the case where the system supports SVE, but
the kernel doesn't have my changes to add the VG register yet.

Technically I could just attempt to open the event without checking
for SVE first and see if it works or not. But I preferred to be
explicit so it's obvious why we're doing that.

James

> 
> Except this question, this patch looks good to me.
> 
> Thanks,
> Leo
> 
>> +	return PERF_REGS_MASK;
>> +}
>> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
>> index a982e40ee5a9..872dd3d38782 100644
>> --- a/tools/perf/util/perf_regs.c
>> +++ b/tools/perf/util/perf_regs.c
>> @@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id)
>>  		return "lr";
>>  	case PERF_REG_ARM64_PC:
>>  		return "pc";
>> +	case PERF_REG_ARM64_VG:
>> +		return "vg";
>>  	default:
>>  		return NULL;
>>  	}
>> -- 
>> 2.28.0
>>

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Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register

[Leo Yan]

On Wed, May 18, 2022 at 10:44:57AM +0100, James Clark wrote:

[...]

> >> +	if (getauxval(AT_HWCAP) & HWCAP_SVE)
> >> +		attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
> >> +
> >> +	/*
> >> +	 * Check if the pmu supports perf extended regs, before
> >> +	 * returning the register mask to sample.
> >> +	 */
> >> +	if (attr.sample_regs_user != PERF_REGS_MASK) {
> >> +		event_attr_init(&attr);
> >> +		fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
> >> +		if (fd != -1) {
> >> +			close(fd);
> >> +			return attr.sample_regs_user;
> >> +		}
> >> +	}
> > 
> > Just curious, since we can know SVE is supported from reading
> > auxiliary value, can we directly return the register mask as below?
> > 
> >   PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG);
> 
> I was trying to cover the case where the system supports SVE, but
> the kernel doesn't have my changes to add the VG register yet.
> 
> Technically I could just attempt to open the event without checking
> for SVE first and see if it works or not. But I preferred to be
> explicit so it's obvious why we're doing that.

Understand; LGTM.

Reviewed-by: Leo Yan <leo.yan@linaro.org>

Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register

[Leo Yan]

On Wed, May 18, 2022 at 10:44:57AM +0100, James Clark wrote:

[...]

> >> +	if (getauxval(AT_HWCAP) & HWCAP_SVE)
> >> +		attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
> >> +
> >> +	/*
> >> +	 * Check if the pmu supports perf extended regs, before
> >> +	 * returning the register mask to sample.
> >> +	 */
> >> +	if (attr.sample_regs_user != PERF_REGS_MASK) {
> >> +		event_attr_init(&attr);
> >> +		fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
> >> +		if (fd != -1) {
> >> +			close(fd);
> >> +			return attr.sample_regs_user;
> >> +		}
> >> +	}
> > 
> > Just curious, since we can know SVE is supported from reading
> > auxiliary value, can we directly return the register mask as below?
> > 
> >   PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG);
> 
> I was trying to cover the case where the system supports SVE, but
> the kernel doesn't have my changes to add the VG register yet.
> 
> Technically I could just attempt to open the event without checking
> for SVE first and see if it works or not. But I preferred to be
> explicit so it's obvious why we're doing that.

Understand; LGTM.

Reviewed-by: Leo Yan <leo.yan@linaro.org>

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Re: [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[Arnaldo Carvalho de Melo]

Em Tue, May 17, 2022 at 11:20:01AM +0100, James Clark escreveu:
> Changes since v1:
> 
>   * Split patchset into kernel side and Perf tool changes

Thanks, now I'll wait for the kernel side to be merged.

- Arnaldo
 
> When SVE registers are pushed onto the stack the VG register is required to
> unwind because the stack offsets would vary by the SVE register width at the
> time when the sample was taken.
> 
> The patches ("[PATCH v2 0/2] perf: arm64: Kernel support for Dwarf unwinding
> through SVE functions") add support for sampling the VG register to the kernel
> and the docs. This is the patchset to add support to userspace perf.
> 
> A small change is also required to libunwind or libdw depending on which
> unwinder is used, and these will be published later. Without these changes Perf
> continues to work with both libraries, although the VG register is still not
> used for unwinding. 
> 
> Thanks
> James
> 
> James Clark (4):
>   perf tools: arm64: Copy perf_regs.h from the kernel
>   perf tools: Use dynamic register set for Dwarf unwind
>   perf tools: arm64: Decouple Libunwind register names from Perf
>   perf tools: arm64: Add support for VG register
> 
>  tools/arch/arm64/include/uapi/asm/perf_regs.h |  7 +-
>  tools/perf/arch/arm64/util/perf_regs.c        | 34 +++++++++
>  tools/perf/arch/arm64/util/unwind-libunwind.c | 73 +------------------
>  tools/perf/util/evsel.c                       |  2 +-
>  tools/perf/util/perf_regs.c                   |  2 +
>  5 files changed, 45 insertions(+), 73 deletions(-)
> 
> -- 
> 2.28.0

-- 

- Arnaldo

Re: [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[Arnaldo Carvalho de Melo]

Em Tue, May 17, 2022 at 11:20:01AM +0100, James Clark escreveu:
> Changes since v1:
> 
>   * Split patchset into kernel side and Perf tool changes

Thanks, now I'll wait for the kernel side to be merged.

- Arnaldo
 
> When SVE registers are pushed onto the stack the VG register is required to
> unwind because the stack offsets would vary by the SVE register width at the
> time when the sample was taken.
> 
> The patches ("[PATCH v2 0/2] perf: arm64: Kernel support for Dwarf unwinding
> through SVE functions") add support for sampling the VG register to the kernel
> and the docs. This is the patchset to add support to userspace perf.
> 
> A small change is also required to libunwind or libdw depending on which
> unwinder is used, and these will be published later. Without these changes Perf
> continues to work with both libraries, although the VG register is still not
> used for unwinding. 
> 
> Thanks
> James
> 
> James Clark (4):
>   perf tools: arm64: Copy perf_regs.h from the kernel
>   perf tools: Use dynamic register set for Dwarf unwind
>   perf tools: arm64: Decouple Libunwind register names from Perf
>   perf tools: arm64: Add support for VG register
> 
>  tools/arch/arm64/include/uapi/asm/perf_regs.h |  7 +-
>  tools/perf/arch/arm64/util/perf_regs.c        | 34 +++++++++
>  tools/perf/arch/arm64/util/unwind-libunwind.c | 73 +------------------
>  tools/perf/util/evsel.c                       |  2 +-
>  tools/perf/util/perf_regs.c                   |  2 +
>  5 files changed, 45 insertions(+), 73 deletions(-)
> 
> -- 
> 2.28.0

-- 

- Arnaldo

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Re: [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[German Gomez]

On 17/05/2022 15:58, Arnaldo Carvalho de Melo wrote:
> Em Tue, May 17, 2022 at 11:20:01AM +0100, James Clark escreveu:
>> Changes since v1:
>>
>>   * Split patchset into kernel side and Perf tool changes
> Thanks, now I'll wait for the kernel side to be merged.
>
> - Arnaldo
>  

Hi,

I think we also need to fix the below import (it's trying to import the
perf_regs.h from the kernel, not the tools/ dir).

diff --git a/tools/perf/util/libunwind/arm64.c b/tools/perf/util/libunwind/arm64.c
index 15f60fd09424..014d82159656 100644
--- a/tools/perf/util/libunwind/arm64.c
+++ b/tools/perf/util/libunwind/arm64.c
@@ -24,7 +24,7 @@
 #include "unwind.h"
 #include "libunwind-aarch64.h"
 #define perf_event_arm_regs perf_event_arm64_regs
-#include <../../../../arch/arm64/include/uapi/asm/perf_regs.h>
+#include <../../../arch/arm64/include/uapi/asm/perf_regs.h>
 #undef perf_event_arm_regs
 #include "../../arch/arm64/util/unwind-libunwind.c"

Re: [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[German Gomez]

On 17/05/2022 15:58, Arnaldo Carvalho de Melo wrote:
> Em Tue, May 17, 2022 at 11:20:01AM +0100, James Clark escreveu:
>> Changes since v1:
>>
>>   * Split patchset into kernel side and Perf tool changes
> Thanks, now I'll wait for the kernel side to be merged.
>
> - Arnaldo
>  

Hi,

I think we also need to fix the below import (it's trying to import the
perf_regs.h from the kernel, not the tools/ dir).

diff --git a/tools/perf/util/libunwind/arm64.c b/tools/perf/util/libunwind/arm64.c
index 15f60fd09424..014d82159656 100644
--- a/tools/perf/util/libunwind/arm64.c
+++ b/tools/perf/util/libunwind/arm64.c
@@ -24,7 +24,7 @@
 #include "unwind.h"
 #include "libunwind-aarch64.h"
 #define perf_event_arm_regs perf_event_arm64_regs
-#include <../../../../arch/arm64/include/uapi/asm/perf_regs.h>
+#include <../../../arch/arm64/include/uapi/asm/perf_regs.h>
 #undef perf_event_arm_regs
 #include "../../arch/arm64/util/unwind-libunwind.c"



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Re: [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[Arnaldo Carvalho de Melo]

Em Fri, May 20, 2022 at 12:46:24PM +0100, German Gomez escreveu:
> 
> On 17/05/2022 15:58, Arnaldo Carvalho de Melo wrote:
> > Em Tue, May 17, 2022 at 11:20:01AM +0100, James Clark escreveu:
> >> Changes since v1:
> >>
> >>   * Split patchset into kernel side and Perf tool changes
> > Thanks, now I'll wait for the kernel side to be merged.
> >
> > - Arnaldo
> >  
> 
> Hi,
> 
> I think we also need to fix the below import (it's trying to import the
> perf_regs.h from the kernel, not the tools/ dir).

Sure, that is why it is important to do a:

make -C tools/perf build-test

before posting patches, as it will do, among other tests, a detached tarball test using:

⬢[acme@toolbox perf-urgent]$ make help | grep perf
  perf-tar-src-pkg    - Build perf-5.18.0-rc7.tar source tarball
  perf-targz-src-pkg  - Build perf-5.18.0-rc7.tar.gz source tarball
  perf-tarbz2-src-pkg - Build perf-5.18.0-rc7.tar.bz2 source tarball
  perf-tarxz-src-pkg  - Build perf-5.18.0-rc7.tar.xz source tarball
  perf-tarzst-src-pkg - Build perf-5.18.0-rc7.tar.zst source tarball
⬢[acme@toolbox perf-urgent]$

That will pick just what is in tools/perf/MANIFEST and that doesn´t
include the kernel headers, just what is in tools/ then building with
this patchkit would fail.

To recap:

⬢[acme@toolbox perf-urgent]$ make perf-tarxz-src-pkg
  TAR
  PERF_VERSION = 5.18.rc7.gc645054ef517
⬢[acme@toolbox perf-urgent]$ ls -la perf-5.18.0-rc7.tar.xz
-rw-r--r--. 1 acme acme 2364832 May 20 09:32 perf-5.18.0-rc7.tar.xz
⬢[acme@toolbox perf-urgent]$ tar tvf perf-5.18.0-rc7.tar.xz | tail
-rw-rw-r-- root/root      7364 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/vdso.c
-rw-rw-r-- root/root       639 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/vdso.h
-rw-rw-r-- root/root      1793 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/zlib.c
-rw-rw-r-- root/root      2672 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/zstd.c
drwxrwxr-x root/root         0 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/
-rw-rw-r-- root/root      1091 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/Makefile.arch
-rw-rw-r-- root/root      5905 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/Makefile.include
-rw-rw-r-- root/root      5288 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/utilities.mak
-rw-r--r-- acme/acme        41 2022-05-20 09:32 perf-5.18.0-rc7/HEAD
-rw-r--r-- acme/acme        46 2022-05-20 09:32 perf-5.18.0-rc7/PERF-VERSION-FILE
⬢[acme@toolbox perf-urgent]$

- Arnaldo
 
> diff --git a/tools/perf/util/libunwind/arm64.c b/tools/perf/util/libunwind/arm64.c
> index 15f60fd09424..014d82159656 100644
> --- a/tools/perf/util/libunwind/arm64.c
> +++ b/tools/perf/util/libunwind/arm64.c
> @@ -24,7 +24,7 @@
>  #include "unwind.h"
>  #include "libunwind-aarch64.h"
>  #define perf_event_arm_regs perf_event_arm64_regs
> -#include <../../../../arch/arm64/include/uapi/asm/perf_regs.h>
> +#include <../../../arch/arm64/include/uapi/asm/perf_regs.h>
>  #undef perf_event_arm_regs
>  #include "../../arch/arm64/util/unwind-libunwind.c"
> 

-- 

- Arnaldo

Re: [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[Arnaldo Carvalho de Melo]

Em Fri, May 20, 2022 at 12:46:24PM +0100, German Gomez escreveu:
> 
> On 17/05/2022 15:58, Arnaldo Carvalho de Melo wrote:
> > Em Tue, May 17, 2022 at 11:20:01AM +0100, James Clark escreveu:
> >> Changes since v1:
> >>
> >>   * Split patchset into kernel side and Perf tool changes
> > Thanks, now I'll wait for the kernel side to be merged.
> >
> > - Arnaldo
> >  
> 
> Hi,
> 
> I think we also need to fix the below import (it's trying to import the
> perf_regs.h from the kernel, not the tools/ dir).

Sure, that is why it is important to do a:

make -C tools/perf build-test

before posting patches, as it will do, among other tests, a detached tarball test using:

⬢[acme@toolbox perf-urgent]$ make help | grep perf
  perf-tar-src-pkg    - Build perf-5.18.0-rc7.tar source tarball
  perf-targz-src-pkg  - Build perf-5.18.0-rc7.tar.gz source tarball
  perf-tarbz2-src-pkg - Build perf-5.18.0-rc7.tar.bz2 source tarball
  perf-tarxz-src-pkg  - Build perf-5.18.0-rc7.tar.xz source tarball
  perf-tarzst-src-pkg - Build perf-5.18.0-rc7.tar.zst source tarball
⬢[acme@toolbox perf-urgent]$

That will pick just what is in tools/perf/MANIFEST and that doesn´t
include the kernel headers, just what is in tools/ then building with
this patchkit would fail.

To recap:

⬢[acme@toolbox perf-urgent]$ make perf-tarxz-src-pkg
  TAR
  PERF_VERSION = 5.18.rc7.gc645054ef517
⬢[acme@toolbox perf-urgent]$ ls -la perf-5.18.0-rc7.tar.xz
-rw-r--r--. 1 acme acme 2364832 May 20 09:32 perf-5.18.0-rc7.tar.xz
⬢[acme@toolbox perf-urgent]$ tar tvf perf-5.18.0-rc7.tar.xz | tail
-rw-rw-r-- root/root      7364 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/vdso.c
-rw-rw-r-- root/root       639 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/vdso.h
-rw-rw-r-- root/root      1793 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/zlib.c
-rw-rw-r-- root/root      2672 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/zstd.c
drwxrwxr-x root/root         0 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/
-rw-rw-r-- root/root      1091 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/Makefile.arch
-rw-rw-r-- root/root      5905 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/Makefile.include
-rw-rw-r-- root/root      5288 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/utilities.mak
-rw-r--r-- acme/acme        41 2022-05-20 09:32 perf-5.18.0-rc7/HEAD
-rw-r--r-- acme/acme        46 2022-05-20 09:32 perf-5.18.0-rc7/PERF-VERSION-FILE
⬢[acme@toolbox perf-urgent]$

- Arnaldo
 
> diff --git a/tools/perf/util/libunwind/arm64.c b/tools/perf/util/libunwind/arm64.c
> index 15f60fd09424..014d82159656 100644
> --- a/tools/perf/util/libunwind/arm64.c
> +++ b/tools/perf/util/libunwind/arm64.c
> @@ -24,7 +24,7 @@
>  #include "unwind.h"
>  #include "libunwind-aarch64.h"
>  #define perf_event_arm_regs perf_event_arm64_regs
> -#include <../../../../arch/arm64/include/uapi/asm/perf_regs.h>
> +#include <../../../arch/arm64/include/uapi/asm/perf_regs.h>
>  #undef perf_event_arm_regs
>  #include "../../arch/arm64/util/unwind-libunwind.c"
> 

-- 

- Arnaldo

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Re: [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[James Clark]

On 20/05/2022 13:32, Arnaldo Carvalho de Melo wrote:
> Em Fri, May 20, 2022 at 12:46:24PM +0100, German Gomez escreveu:
>>
>> On 17/05/2022 15:58, Arnaldo Carvalho de Melo wrote:
>>> Em Tue, May 17, 2022 at 11:20:01AM +0100, James Clark escreveu:
>>>> Changes since v1:
>>>>
>>>>   * Split patchset into kernel side and Perf tool changes
>>> Thanks, now I'll wait for the kernel side to be merged.
>>>
>>> - Arnaldo
>>>  
>>
>> Hi,
>>
>> I think we also need to fix the below import (it's trying to import the
>> perf_regs.h from the kernel, not the tools/ dir).
> 
> Sure, that is why it is important to do a:
> 
> make -C tools/perf build-test
> 

Oops thanks, I will submit another version with a fix for this included.

James

> before posting patches, as it will do, among other tests, a detached tarball test using:
> 
> ⬢[acme@toolbox perf-urgent]$ make help | grep perf
>   perf-tar-src-pkg    - Build perf-5.18.0-rc7.tar source tarball
>   perf-targz-src-pkg  - Build perf-5.18.0-rc7.tar.gz source tarball
>   perf-tarbz2-src-pkg - Build perf-5.18.0-rc7.tar.bz2 source tarball
>   perf-tarxz-src-pkg  - Build perf-5.18.0-rc7.tar.xz source tarball
>   perf-tarzst-src-pkg - Build perf-5.18.0-rc7.tar.zst source tarball
> ⬢[acme@toolbox perf-urgent]$
> 
> That will pick just what is in tools/perf/MANIFEST and that doesn´t
> include the kernel headers, just what is in tools/ then building with
> this patchkit would fail.
> 
> To recap:
> 
> ⬢[acme@toolbox perf-urgent]$ make perf-tarxz-src-pkg
>   TAR
>   PERF_VERSION = 5.18.rc7.gc645054ef517
> ⬢[acme@toolbox perf-urgent]$ ls -la perf-5.18.0-rc7.tar.xz
> -rw-r--r--. 1 acme acme 2364832 May 20 09:32 perf-5.18.0-rc7.tar.xz
> ⬢[acme@toolbox perf-urgent]$ tar tvf perf-5.18.0-rc7.tar.xz | tail
> -rw-rw-r-- root/root      7364 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/vdso.c
> -rw-rw-r-- root/root       639 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/vdso.h
> -rw-rw-r-- root/root      1793 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/zlib.c
> -rw-rw-r-- root/root      2672 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/zstd.c
> drwxrwxr-x root/root         0 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/
> -rw-rw-r-- root/root      1091 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/Makefile.arch
> -rw-rw-r-- root/root      5905 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/Makefile.include
> -rw-rw-r-- root/root      5288 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/utilities.mak
> -rw-r--r-- acme/acme        41 2022-05-20 09:32 perf-5.18.0-rc7/HEAD
> -rw-r--r-- acme/acme        46 2022-05-20 09:32 perf-5.18.0-rc7/PERF-VERSION-FILE
> ⬢[acme@toolbox perf-urgent]$
> 
> - Arnaldo
>  
>> diff --git a/tools/perf/util/libunwind/arm64.c b/tools/perf/util/libunwind/arm64.c
>> index 15f60fd09424..014d82159656 100644
>> --- a/tools/perf/util/libunwind/arm64.c
>> +++ b/tools/perf/util/libunwind/arm64.c
>> @@ -24,7 +24,7 @@
>>  #include "unwind.h"
>>  #include "libunwind-aarch64.h"
>>  #define perf_event_arm_regs perf_event_arm64_regs
>> -#include <../../../../arch/arm64/include/uapi/asm/perf_regs.h>
>> +#include <../../../arch/arm64/include/uapi/asm/perf_regs.h>
>>  #undef perf_event_arm_regs
>>  #include "../../arch/arm64/util/unwind-libunwind.c"
>>
> 

Re: [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions

[James Clark]

On 20/05/2022 13:32, Arnaldo Carvalho de Melo wrote:
> Em Fri, May 20, 2022 at 12:46:24PM +0100, German Gomez escreveu:
>>
>> On 17/05/2022 15:58, Arnaldo Carvalho de Melo wrote:
>>> Em Tue, May 17, 2022 at 11:20:01AM +0100, James Clark escreveu:
>>>> Changes since v1:
>>>>
>>>>   * Split patchset into kernel side and Perf tool changes
>>> Thanks, now I'll wait for the kernel side to be merged.
>>>
>>> - Arnaldo
>>>  
>>
>> Hi,
>>
>> I think we also need to fix the below import (it's trying to import the
>> perf_regs.h from the kernel, not the tools/ dir).
> 
> Sure, that is why it is important to do a:
> 
> make -C tools/perf build-test
> 

Oops thanks, I will submit another version with a fix for this included.

James

> before posting patches, as it will do, among other tests, a detached tarball test using:
> 
> ⬢[acme@toolbox perf-urgent]$ make help | grep perf
>   perf-tar-src-pkg    - Build perf-5.18.0-rc7.tar source tarball
>   perf-targz-src-pkg  - Build perf-5.18.0-rc7.tar.gz source tarball
>   perf-tarbz2-src-pkg - Build perf-5.18.0-rc7.tar.bz2 source tarball
>   perf-tarxz-src-pkg  - Build perf-5.18.0-rc7.tar.xz source tarball
>   perf-tarzst-src-pkg - Build perf-5.18.0-rc7.tar.zst source tarball
> ⬢[acme@toolbox perf-urgent]$
> 
> That will pick just what is in tools/perf/MANIFEST and that doesn´t
> include the kernel headers, just what is in tools/ then building with
> this patchkit would fail.
> 
> To recap:
> 
> ⬢[acme@toolbox perf-urgent]$ make perf-tarxz-src-pkg
>   TAR
>   PERF_VERSION = 5.18.rc7.gc645054ef517
> ⬢[acme@toolbox perf-urgent]$ ls -la perf-5.18.0-rc7.tar.xz
> -rw-r--r--. 1 acme acme 2364832 May 20 09:32 perf-5.18.0-rc7.tar.xz
> ⬢[acme@toolbox perf-urgent]$ tar tvf perf-5.18.0-rc7.tar.xz | tail
> -rw-rw-r-- root/root      7364 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/vdso.c
> -rw-rw-r-- root/root       639 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/vdso.h
> -rw-rw-r-- root/root      1793 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/zlib.c
> -rw-rw-r-- root/root      2672 2022-05-20 09:32 perf-5.18.0-rc7/tools/perf/util/zstd.c
> drwxrwxr-x root/root         0 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/
> -rw-rw-r-- root/root      1091 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/Makefile.arch
> -rw-rw-r-- root/root      5905 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/Makefile.include
> -rw-rw-r-- root/root      5288 2022-05-20 09:32 perf-5.18.0-rc7/tools/scripts/utilities.mak
> -rw-r--r-- acme/acme        41 2022-05-20 09:32 perf-5.18.0-rc7/HEAD
> -rw-r--r-- acme/acme        46 2022-05-20 09:32 perf-5.18.0-rc7/PERF-VERSION-FILE
> ⬢[acme@toolbox perf-urgent]$
> 
> - Arnaldo
>  
>> diff --git a/tools/perf/util/libunwind/arm64.c b/tools/perf/util/libunwind/arm64.c
>> index 15f60fd09424..014d82159656 100644
>> --- a/tools/perf/util/libunwind/arm64.c
>> +++ b/tools/perf/util/libunwind/arm64.c
>> @@ -24,7 +24,7 @@
>>  #include "unwind.h"
>>  #include "libunwind-aarch64.h"
>>  #define perf_event_arm_regs perf_event_arm64_regs
>> -#include <../../../../arch/arm64/include/uapi/asm/perf_regs.h>
>> +#include <../../../arch/arm64/include/uapi/asm/perf_regs.h>
>>  #undef perf_event_arm_regs
>>  #include "../../arch/arm64/util/unwind-libunwind.c"
>>
> 

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