From: Marc Kleine-Budde <mkl@pengutronix.de>
To: Pankaj Bansal <pankaj.bansal@nxp.com>,
wg@grandegger.com, linux-can@vger.kernel.org
Cc: V.Sethi@nxp.com, poonam.aggrwal@nxp.com,
Bhupesh Sharma <bhupesh.sharma@freescale.com>,
Sakar Arora <Sakar.Arora@freescale.com>
Subject: Re: [PATCH 1/2] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers.
Date: Fri, 10 Nov 2017 11:06:41 +0100 [thread overview]
Message-ID: <a08c34d0-5870-b4b3-f68d-3db33ba3e950@pengutronix.de> (raw)
In-Reply-To: <1510307990-15418-1-git-send-email-pankaj.bansal@nxp.com>
[-- Attachment #1.1: Type: text/plain, Size: 22173 bytes --]
On 11/10/2017 10:59 AM, Pankaj Bansal wrote:
> The FlexCAN driver assumed that FlexCAN controller is big endian for
> powerpc architecture and little endian for other architectures.
>
> But this may not be the case. FlexCAN controller can be little or
> big endian on any architecture. For e.g. NXP LS1021A ARM based SOC
> has big endian FlexCAN controller.
>
> Therefore, the driver has been modified to add a provision for both
> types of controllers using an additional device tree property. Big
> Endian controllers should have "big-endian" set in the device tree.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
> Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
> ---
> Tested on Arm32 based NXP LS1021A-TWR board (linux-can-next/master branch)
> Tested on PowerPC based NXP P1010RDB board (after back porting to Freescale SDK 1.4 linux)
>
> drivers/net/can/flexcan.c | 212 ++++++++++++++++++++----------------
> 1 file changed, 116 insertions(+), 96 deletions(-)
>
> diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
> index a13a489..d4ce2df 100644
> --- a/drivers/net/can/flexcan.c
> +++ b/drivers/net/can/flexcan.c
> @@ -279,6 +279,10 @@ struct flexcan_priv {
> struct clk *clk_per;
> const struct flexcan_devtype_data *devtype_data;
> struct regulator *reg_xceiver;
> +
> + /* Read and Write APIs */
> + u32 (*read)(void __iomem *addr);
> + void (*write)(u32 val, void __iomem *addr);
> };
>
> static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
> @@ -312,39 +316,45 @@ static const struct can_bittiming_const flexcan_bittiming_const = {
> .brp_inc = 1,
> };
>
> -/* Abstract off the read/write for arm versus ppc. This
> - * assumes that PPC uses big-endian registers and everything
> - * else uses little-endian registers, independent of CPU
> - * endianness.
> +/* FlexCAN module is essentially modelled as a little-endian IP in most
> + * SoCs, i.e the registers as well as the message buffer areas are
> + * implemented in a little-endian fashion.
> + *
> + * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
> + * module in a big-endian fashion (i.e the registers as well as the
> + * message buffer areas are implemented in a big-endian way).
> + *
> + * In addition, the FlexCAN module can be found on SoCs having ARM or
> + * PPC cores. So, we need to abstract off the register read/write
> + * functions, ensuring that these cater to all the combinations of module
> + * endianness and underlying CPU endianness.
> */
> -#if defined(CONFIG_PPC)
> -static inline u32 flexcan_read(void __iomem *addr)
> +static inline u32 flexcan_read_le(void __iomem *addr)
> {
> - return in_be32(addr);
> + return ioread32(addr);
> }
>
> -static inline void flexcan_write(u32 val, void __iomem *addr)
> +static inline void flexcan_write_le(u32 val, void __iomem *addr)
> {
> - out_be32(addr, val);
> + iowrite32(val, addr);
> }
Please make this the be variants, followed by the le below. Should make
the patch easier to read.
> -#else
> -static inline u32 flexcan_read(void __iomem *addr)
> +
> +static inline u32 flexcan_read_be(void __iomem *addr)
> {
> - return readl(addr);
> + return ioread32be(addr);
> }
>
> -static inline void flexcan_write(u32 val, void __iomem *addr)
> +static inline void flexcan_write_be(u32 val, void __iomem *addr)
> {
> - writel(val, addr);
> + iowrite32be(val, addr);
> }
> -#endif
>
> static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
> {
> struct flexcan_regs __iomem *regs = priv->regs;
> u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
>
> - flexcan_write(reg_ctrl, ®s->ctrl);
> + priv->write(reg_ctrl, ®s->ctrl);
> }
>
> static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
> @@ -352,7 +362,7 @@ static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
> struct flexcan_regs __iomem *regs = priv->regs;
> u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
>
> - flexcan_write(reg_ctrl, ®s->ctrl);
> + priv->write(reg_ctrl, ®s->ctrl);
> }
>
> static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
> @@ -377,14 +387,14 @@ static int flexcan_chip_enable(struct flexcan_priv *priv)
> unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
> u32 reg;
>
> - reg = flexcan_read(®s->mcr);
> + reg = priv->read(®s->mcr);
> reg &= ~FLEXCAN_MCR_MDIS;
> - flexcan_write(reg, ®s->mcr);
> + priv->write(reg, ®s->mcr);
>
> - while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
> + while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
> udelay(10);
>
> - if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
> + if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
> return -ETIMEDOUT;
>
> return 0;
> @@ -396,14 +406,14 @@ static int flexcan_chip_disable(struct flexcan_priv *priv)
> unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
> u32 reg;
>
> - reg = flexcan_read(®s->mcr);
> + reg = priv->read(®s->mcr);
> reg |= FLEXCAN_MCR_MDIS;
> - flexcan_write(reg, ®s->mcr);
> + priv->write(reg, ®s->mcr);
>
> - while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
> + while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
> udelay(10);
>
> - if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
> + if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
> return -ETIMEDOUT;
>
> return 0;
> @@ -415,14 +425,14 @@ static int flexcan_chip_freeze(struct flexcan_priv *priv)
> unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
> u32 reg;
>
> - reg = flexcan_read(®s->mcr);
> + reg = priv->read(®s->mcr);
> reg |= FLEXCAN_MCR_HALT;
> - flexcan_write(reg, ®s->mcr);
> + priv->write(reg, ®s->mcr);
>
> - while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
> + while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
> udelay(100);
>
> - if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
> + if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
> return -ETIMEDOUT;
>
> return 0;
> @@ -434,14 +444,14 @@ static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
> unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
> u32 reg;
>
> - reg = flexcan_read(®s->mcr);
> + reg = priv->read(®s->mcr);
> reg &= ~FLEXCAN_MCR_HALT;
> - flexcan_write(reg, ®s->mcr);
> + priv->write(reg, ®s->mcr);
>
> - while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
> + while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
> udelay(10);
>
> - if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
> + if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
> return -ETIMEDOUT;
>
> return 0;
> @@ -452,11 +462,11 @@ static int flexcan_chip_softreset(struct flexcan_priv *priv)
> struct flexcan_regs __iomem *regs = priv->regs;
> unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
>
> - flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
> - while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
> + priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
> + while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
> udelay(10);
>
> - if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
> + if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
> return -ETIMEDOUT;
>
> return 0;
> @@ -467,7 +477,7 @@ static int __flexcan_get_berr_counter(const struct net_device *dev,
> {
> const struct flexcan_priv *priv = netdev_priv(dev);
> struct flexcan_regs __iomem *regs = priv->regs;
> - u32 reg = flexcan_read(®s->ecr);
> + u32 reg = priv->read(®s->ecr);
>
> bec->txerr = (reg >> 0) & 0xff;
> bec->rxerr = (reg >> 8) & 0xff;
> @@ -523,24 +533,24 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
>
> if (cf->can_dlc > 0) {
> data = be32_to_cpup((__be32 *)&cf->data[0]);
> - flexcan_write(data, &priv->tx_mb->data[0]);
> + priv->write(data, &priv->tx_mb->data[0]);
> }
> if (cf->can_dlc > 3) {
> data = be32_to_cpup((__be32 *)&cf->data[4]);
> - flexcan_write(data, &priv->tx_mb->data[1]);
> + priv->write(data, &priv->tx_mb->data[1]);
> }
>
> can_put_echo_skb(skb, dev, 0);
>
> - flexcan_write(can_id, &priv->tx_mb->can_id);
> - flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
> + priv->write(can_id, &priv->tx_mb->can_id);
> + priv->write(ctrl, &priv->tx_mb->can_ctrl);
>
> /* Errata ERR005829 step8:
> * Write twice INACTIVE(0x8) code to first MB.
> */
> - flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
> + priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
> &priv->tx_mb_reserved->can_ctrl);
> - flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
> + priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
> &priv->tx_mb_reserved->can_ctrl);
>
> return NETDEV_TX_OK;
> @@ -659,7 +669,7 @@ static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
> u32 code;
>
> do {
> - reg_ctrl = flexcan_read(&mb->can_ctrl);
> + reg_ctrl = priv->read(&mb->can_ctrl);
> } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
>
> /* is this MB empty? */
> @@ -674,17 +684,17 @@ static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
> offload->dev->stats.rx_errors++;
> }
> } else {
> - reg_iflag1 = flexcan_read(®s->iflag1);
> + reg_iflag1 = priv->read(®s->iflag1);
> if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
> return 0;
>
> - reg_ctrl = flexcan_read(&mb->can_ctrl);
> + reg_ctrl = priv->read(&mb->can_ctrl);
> }
>
> /* increase timstamp to full 32 bit */
> *timestamp = reg_ctrl << 16;
>
> - reg_id = flexcan_read(&mb->can_id);
> + reg_id = priv->read(&mb->can_id);
> if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
> cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
> else
> @@ -694,19 +704,19 @@ static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
> cf->can_id |= CAN_RTR_FLAG;
> cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
>
> - *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
> - *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
> + *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
> + *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
>
> /* mark as read */
> if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
> /* Clear IRQ */
> if (n < 32)
> - flexcan_write(BIT(n), ®s->iflag1);
> + priv->write(BIT(n), ®s->iflag1);
> else
> - flexcan_write(BIT(n - 32), ®s->iflag2);
> + priv->write(BIT(n - 32), ®s->iflag2);
> } else {
> - flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
> - flexcan_read(®s->timer);
> + priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
> + priv->read(®s->timer);
> }
>
> return 1;
> @@ -718,8 +728,8 @@ static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
> struct flexcan_regs __iomem *regs = priv->regs;
> u32 iflag1, iflag2;
>
> - iflag2 = flexcan_read(®s->iflag2) & priv->reg_imask2_default;
> - iflag1 = flexcan_read(®s->iflag1) & priv->reg_imask1_default &
> + iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default;
> + iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default &
> ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
>
> return (u64)iflag2 << 32 | iflag1;
> @@ -735,7 +745,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
> u32 reg_iflag1, reg_esr;
> enum can_state last_state = priv->can.state;
>
> - reg_iflag1 = flexcan_read(®s->iflag1);
> + reg_iflag1 = priv->read(®s->iflag1);
>
> /* reception interrupt */
> if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
> @@ -758,7 +768,8 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
> /* FIFO overflow interrupt */
> if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
> handled = IRQ_HANDLED;
> - flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
> + priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
> + ®s->iflag1);
> dev->stats.rx_over_errors++;
> dev->stats.rx_errors++;
> }
> @@ -772,18 +783,18 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
> can_led_event(dev, CAN_LED_EVENT_TX);
>
> /* after sending a RTR frame MB is in RX mode */
> - flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
> + priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
> &priv->tx_mb->can_ctrl);
> - flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
> + priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
> netif_wake_queue(dev);
> }
>
> - reg_esr = flexcan_read(®s->esr);
> + reg_esr = priv->read(®s->esr);
>
> /* ACK all bus error and state change IRQ sources */
> if (reg_esr & FLEXCAN_ESR_ALL_INT) {
> handled = IRQ_HANDLED;
> - flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
> + priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
> }
>
> /* state change interrupt or broken error state quirk fix is enabled */
> @@ -845,7 +856,7 @@ static void flexcan_set_bittiming(struct net_device *dev)
> struct flexcan_regs __iomem *regs = priv->regs;
> u32 reg;
>
> - reg = flexcan_read(®s->ctrl);
> + reg = priv->read(®s->ctrl);
> reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
> FLEXCAN_CTRL_RJW(0x3) |
> FLEXCAN_CTRL_PSEG1(0x7) |
> @@ -869,11 +880,11 @@ static void flexcan_set_bittiming(struct net_device *dev)
> reg |= FLEXCAN_CTRL_SMP;
>
> netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
> - flexcan_write(reg, ®s->ctrl);
> + priv->write(reg, ®s->ctrl);
>
> /* print chip status */
> netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
> - flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
> + priv->read(®s->mcr), priv->read(®s->ctrl));
> }
>
> /* flexcan_chip_start
> @@ -912,7 +923,7 @@ static int flexcan_chip_start(struct net_device *dev)
> * choose format C
> * set max mailbox number
> */
> - reg_mcr = flexcan_read(®s->mcr);
> + reg_mcr = priv->read(®s->mcr);
> reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
> reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
> FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
> @@ -926,7 +937,7 @@ static int flexcan_chip_start(struct net_device *dev)
> FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
> }
> netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
> - flexcan_write(reg_mcr, ®s->mcr);
> + priv->write(reg_mcr, ®s->mcr);
>
> /* CTRL
> *
> @@ -939,7 +950,7 @@ static int flexcan_chip_start(struct net_device *dev)
> * enable bus off interrupt
> * (== FLEXCAN_CTRL_ERR_STATE)
> */
> - reg_ctrl = flexcan_read(®s->ctrl);
> + reg_ctrl = priv->read(®s->ctrl);
> reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
> reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
> FLEXCAN_CTRL_ERR_STATE;
> @@ -959,45 +970,45 @@ static int flexcan_chip_start(struct net_device *dev)
> /* leave interrupts disabled for now */
> reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
> netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
> - flexcan_write(reg_ctrl, ®s->ctrl);
> + priv->write(reg_ctrl, ®s->ctrl);
>
> if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
> - reg_ctrl2 = flexcan_read(®s->ctrl2);
> + reg_ctrl2 = priv->read(®s->ctrl2);
> reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
> - flexcan_write(reg_ctrl2, ®s->ctrl2);
> + priv->write(reg_ctrl2, ®s->ctrl2);
> }
>
> /* clear and invalidate all mailboxes first */
> for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
> - flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
> + priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
> ®s->mb[i].can_ctrl);
> }
>
> if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
> for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
> - flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
> + priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
> ®s->mb[i].can_ctrl);
> }
>
> /* Errata ERR005829: mark first TX mailbox as INACTIVE */
> - flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
> + priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
> &priv->tx_mb_reserved->can_ctrl);
>
> /* mark TX mailbox as INACTIVE */
> - flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
> + priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
> &priv->tx_mb->can_ctrl);
>
> /* acceptance mask/acceptance code (accept everything) */
> - flexcan_write(0x0, ®s->rxgmask);
> - flexcan_write(0x0, ®s->rx14mask);
> - flexcan_write(0x0, ®s->rx15mask);
> + priv->write(0x0, ®s->rxgmask);
> + priv->write(0x0, ®s->rx14mask);
> + priv->write(0x0, ®s->rx15mask);
>
> if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
> - flexcan_write(0x0, ®s->rxfgmask);
> + priv->write(0x0, ®s->rxfgmask);
>
> /* clear acceptance filters */
> for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
> - flexcan_write(0, ®s->rximr[i]);
> + priv->write(0, ®s->rximr[i]);
>
> /* On Vybrid, disable memory error detection interrupts
> * and freeze mode.
> @@ -1010,16 +1021,16 @@ static int flexcan_chip_start(struct net_device *dev)
> * and Correction of Memory Errors" to write to
> * MECR register
> */
> - reg_ctrl2 = flexcan_read(®s->ctrl2);
> + reg_ctrl2 = priv->read(®s->ctrl2);
> reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
> - flexcan_write(reg_ctrl2, ®s->ctrl2);
> + priv->write(reg_ctrl2, ®s->ctrl2);
>
> - reg_mecr = flexcan_read(®s->mecr);
> + reg_mecr = priv->read(®s->mecr);
> reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
> - flexcan_write(reg_mecr, ®s->mecr);
> + priv->write(reg_mecr, ®s->mecr);
> reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
> FLEXCAN_MECR_FANCEI_MSK);
> - flexcan_write(reg_mecr, ®s->mecr);
> + priv->write(reg_mecr, ®s->mecr);
> }
>
> err = flexcan_transceiver_enable(priv);
> @@ -1035,14 +1046,14 @@ static int flexcan_chip_start(struct net_device *dev)
>
> /* enable interrupts atomically */
> disable_irq(dev->irq);
> - flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
> - flexcan_write(priv->reg_imask1_default, ®s->imask1);
> - flexcan_write(priv->reg_imask2_default, ®s->imask2);
> + priv->write(priv->reg_ctrl_default, ®s->ctrl);
> + priv->write(priv->reg_imask1_default, ®s->imask1);
> + priv->write(priv->reg_imask2_default, ®s->imask2);
> enable_irq(dev->irq);
>
> /* print chip status */
> netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
> - flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
> + priv->read(®s->mcr), priv->read(®s->ctrl));
>
> return 0;
>
> @@ -1067,9 +1078,9 @@ static void flexcan_chip_stop(struct net_device *dev)
> flexcan_chip_disable(priv);
>
> /* Disable all interrupts */
> - flexcan_write(0, ®s->imask2);
> - flexcan_write(0, ®s->imask1);
> - flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
> + priv->write(0, ®s->imask2);
> + priv->write(0, ®s->imask1);
> + priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
> ®s->ctrl);
>
> flexcan_transceiver_disable(priv);
> @@ -1185,26 +1196,26 @@ static int register_flexcandev(struct net_device *dev)
> err = flexcan_chip_disable(priv);
> if (err)
> goto out_disable_per;
> - reg = flexcan_read(®s->ctrl);
> + reg = priv->read(®s->ctrl);
> reg |= FLEXCAN_CTRL_CLK_SRC;
> - flexcan_write(reg, ®s->ctrl);
> + priv->write(reg, ®s->ctrl);
>
> err = flexcan_chip_enable(priv);
> if (err)
> goto out_chip_disable;
>
> /* set freeze, halt and activate FIFO, restrict register access */
> - reg = flexcan_read(®s->mcr);
> + reg = priv->read(®s->mcr);
> reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
> FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
> - flexcan_write(reg, ®s->mcr);
> + priv->write(reg, ®s->mcr);
>
> /* Currently we only support newer versions of this core
> * featuring a RX hardware FIFO (although this driver doesn't
> * make use of it on some cores). Older cores, found on some
> * Coldfire derivates are not tested.
> */
> - reg = flexcan_read(®s->mcr);
> + reg = priv->read(®s->mcr);
> if (!(reg & FLEXCAN_MCR_FEN)) {
> netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
> err = -ENODEV;
> @@ -1313,6 +1324,15 @@ static int flexcan_probe(struct platform_device *pdev)
> dev->flags |= IFF_ECHO;
>
> priv = netdev_priv(dev);
> +
> + if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
Don't do this. This is not backwards compatible with the existing PPC
boards. Please add all needed information to the devtype_data.
> + priv->read = flexcan_read_be;
> + priv->write = flexcan_write_be;
> + } else {
> + priv->read = flexcan_read_le;
> + priv->write = flexcan_write_le;
> + }
> +
> priv->can.clock.freq = clock_freq;
> priv->can.bittiming_const = &flexcan_bittiming_const;
> priv->can.do_set_mode = flexcan_set_mode;
>
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
next prev parent reply other threads:[~2017-11-10 10:46 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-10 9:59 [PATCH 1/2] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers Pankaj Bansal
2017-11-10 9:59 ` [PATCH 2/2] can: flexcan: adding platform specific details for LS1021A Pankaj Bansal
2017-11-10 10:06 ` Marc Kleine-Budde [this message]
2017-11-10 11:06 ` [PATCH 1/2] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers Pankaj Bansal
2017-11-10 11:09 ` Marc Kleine-Budde
2017-11-10 12:35 ` Pankaj Bansal
[not found] ` <AM0PR0402MB394051B0FAADBC45AF71439CF1540-mYCQpYF9suc3mfjNbz3WnI3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2017-11-10 12:49 ` Marc Kleine-Budde
2017-11-10 16:32 ` Pankaj Bansal
[not found] ` <AM0PR0402MB3940DE05B2BA456D0FF54498F1540-mYCQpYF9suc3mfjNbz3WnI3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2017-11-13 15:50 ` Marc Kleine-Budde
2017-11-10 10:48 ` Marc Kleine-Budde
2017-11-14 11:56 ` [PATCH v2 " Pankaj Bansal
2017-11-14 11:56 ` [PATCH v2 2/2] can: flexcan: adding platform specific details for LS1021A Pankaj Bansal
2017-11-14 12:59 ` Marc Kleine-Budde
2017-11-16 5:34 ` Pankaj Bansal
2017-11-16 7:05 ` Wolfgang Grandegger
2017-11-16 7:23 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-11-20 11:11 ` Pankaj Bansal
2017-11-21 2:13 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-11-21 2:37 ` Pankaj Bansal
2017-11-21 3:31 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-11-21 10:01 ` Pankaj Bansal
2017-11-23 7:23 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-11-21 12:43 ` Marc Kleine-Budde
2017-11-22 2:56 ` ZHU Yi (ST-FIR/ENG1-Zhu)
2017-11-22 6:27 ` Pankaj Bansal
2017-11-22 13:56 ` Marc Kleine-Budde
2017-11-22 11:59 ` Marc Kleine-Budde
2017-11-23 1:26 ` ZHU Yi (ST-FIR/ENG1-Zhu)
[not found] ` <CALw8SCUGuCmq+S_9-o-ZDYJuASveuj71WH97jYsEvNZX2N5ZXA@mail.gmail.com>
2017-11-23 20:17 ` Mirza Krak
2017-11-23 21:05 ` Wolfgang Grandegger
2017-11-24 16:02 ` Mirza Krak
2017-11-24 19:19 ` Wolfgang Grandegger
2017-11-26 21:11 ` Mirza Krak
2017-11-27 14:00 ` Marc Kleine-Budde
[not found] ` <CALw8SCVNqN0SM1e=bxXZFMVL0VN0iy0LgFj9Hv4BeRwAbb9Y6A@mail.gmail.com>
2017-11-28 22:11 ` Mirza Krak
2017-12-01 10:12 ` Mirza Krak
2017-12-01 10:32 ` Marc Kleine-Budde
2017-11-27 16:34 ` Stefan Agner
2017-11-14 15:24 ` [PATCH v2 1/2] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers Marc Kleine-Budde
2017-11-16 5:24 ` Pankaj Bansal
2017-11-16 12:04 ` Marc Kleine-Budde
2017-11-21 12:18 ` Pankaj Bansal
2017-11-21 12:38 ` Marc Kleine-Budde
2017-11-23 9:09 ` [PATCH v3 " Pankaj Bansal
2017-11-23 9:09 ` [PATCH v3 2/2] can: flexcan: adding platform specific details for LS1021A Pankaj Bansal
2017-11-23 9:16 ` Marc Kleine-Budde
2017-11-23 10:01 ` Pankaj Bansal
2017-11-23 10:07 ` Marc Kleine-Budde
2017-11-23 12:01 ` Pankaj Bansal
2017-11-23 12:33 ` Marc Kleine-Budde
2017-11-23 9:18 ` [PATCH v3 1/2] can: flexcan: Remodel FlexCAN register r/w APIs for big endian FlexCAN controllers Marc Kleine-Budde
2017-11-23 9:55 ` Pankaj Bansal
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