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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH 2/4] x86/P2M: relax guarding of MMIO entries
Date: Mon, 6 Sep 2021 20:53:38 +0100	[thread overview]
Message-ID: <bf091ebc-95e7-b357-9f84-4ec3a6346fac@citrix.com> (raw)
In-Reply-To: <818cc08e-8372-35c4-935f-86a87cceec75@suse.com>

On 01/09/2021 14:08, Jan Beulich wrote:
>>>> Restricting execute permissions is something unique to virt.  It doesn't
>>>> exist in a non-virtualised system, as I and D side reads are
>>>> indistinguishable outside of the core.
>>>>
>>>> Furthermore, it is inexpressible on some systems/configurations.
>>>>
>>>> Introspection is the only technology which should be restricting execute
>>>> permissions in the p2m, and only when it takes responsibility for
>>>> dealing with the fallout.
>>> IOW are you saying that the calls to set_identity_p2m_entry()
>>> (pre-dating XSA-378) were wrong to use p2m_access_rw?
>> Yes.
>>
>>>  Because that's
>>> what's getting the way here.
>> On a real machine, you really can write some executable code into an
>> E820 reserved region and jump to it.  You can also execute code from
>> real BARs is you happen to know that they are prefetchable (or you're a
>> glutton for UC reads...)
>>
>> And there is the WPBT ACPI table which exists specifically to let
>> firmware inject drivers/applications into a windows environment, and may
>> come out of the SPI ROM in the first place.
>>
>>
>> Is it sensible to execute an E820 reserved region, or unmarked BAR? 
>> Probably not.
>>
>> Should it work, because that's how real hardware behaves?  Absolutely.
>>
>> Any restrictions beyond that want handling by some kind of introspection
>> agent which has a policy of what to do with legal-but-dodgy-looking actions.
> IOW you suggest we remove p2m_access_t parameters from various functions,
> going with just default access?

p2m_access_t was very obviously a bodge when introduced, and I doubt it
would pass today's review standards.

It is definitely a mis-design, given its ill-specified and overlapping
semantics with respect to the p2m type.

>  Of course, as pointed out in another
> reply, we'll need to split p2m_mmio_direct into multiple types then, at
> the very least to honor the potential r/o restriction of AMD IOMMU unity
> mapped regions. (FAOD all of this isn't a short term plan anyway, at least
> afaic.)

I don't think that will be necessary.

IVMDs are almost non-existent, and given how many other areas of the AMD
IOMMU spec are totally unused, I wouldn't be surprised if r/o unity
mappings were in that category too.  There's no obvious usecase for r/o,
as anything critical enough in the platform to have an IVMD in the first
place will also be non-trivial enough to require bidirectional
communication somehow.

The unity mapping only says "this device requires read-only access".  It
doesn't say "this must be mapped read-only", and it is legitimate to map
a r/o unity mapping as r/w.

If such a case actually exists, there's clearly one agent in the system
with r/w access into the r/o range, and mapping it r/w is equivalent to
the "IOMMU not enabled in the first place" case which is the default
case for most software for the past decade-and-a-bit.

In other words, I don't think the r/o unit maps on their own are a good
enough reasons to split the type.  If we gain other reasons then fine,
but this seems like chunk of complexity with no real users.

~Andrew



  reply	other threads:[~2021-09-06 19:54 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-30 13:01 [PATCH 0/4] x86/PVH: Dom0 building adjustments Jan Beulich
2021-08-30 13:02 ` [PATCH 1/4] x86/PVH: de-duplicate mappings for first Mb of Dom0 memory Jan Beulich
2021-08-31 13:02   ` Andrew Cooper
2021-08-31 13:14     ` Jan Beulich
2021-08-31 13:19       ` Jan Beulich
2021-08-31 13:27         ` Andrew Cooper
2021-08-31 13:36           ` Jan Beulich
2021-09-01 11:49             ` Andrew Cooper
2021-09-01  8:41       ` Roger Pau Monné
2021-08-30 13:02 ` [PATCH 2/4] x86/P2M: relax guarding of MMIO entries Jan Beulich
2021-08-31 13:16   ` Jan Beulich
2021-08-31 13:16   ` Andrew Cooper
2021-08-31 13:26     ` Jan Beulich
2021-08-31 15:25       ` Andrew Cooper
2021-08-31 15:38         ` Jan Beulich
2021-09-01  8:08           ` Jan Beulich
2021-09-01  8:50           ` Roger Pau Monné
2021-09-01  9:53             ` Jan Beulich
2021-09-01 13:48               ` Roger Pau Monné
2021-09-01 14:05                 ` Jan Beulich
2021-09-01 12:47           ` Andrew Cooper
2021-09-01 13:08             ` Jan Beulich
2021-09-06 19:53               ` Andrew Cooper [this message]
2021-09-07  6:27                 ` Jan Beulich
2021-08-30 13:03 ` [PATCH 3/4] x86/PVH: improve Dom0 memory size calculation Jan Beulich
2021-08-31 14:07   ` Andrew Cooper
2021-08-31 15:30     ` Jan Beulich
2021-08-30 13:03 ` [PATCH 4/4] x86/PV: properly set shadow allocation for Dom0 Jan Beulich
2021-08-31 13:47   ` Andrew Cooper
2021-08-31 14:25     ` Jan Beulich
2021-08-31 21:08   ` Tim Deegan
2021-08-31  8:53 ` [PATCH 0/4] x86/PVH: Dom0 building adjustments Jan Beulich
2021-09-01 13:56   ` Roger Pau Monné
2021-09-01 14:19     ` Jan Beulich
2021-09-01 14:25       ` Jan Beulich
2021-09-01 16:13       ` Roger Pau Monné
2021-09-02  6:30         ` Jan Beulich
2021-09-01 15:06 ` Jan Beulich
2021-09-01 15:24   ` Juergen Gross
2021-09-01 15:51     ` Jan Beulich

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