* [PATCH 01/66] drm/amdgpu: move headless sku check into harvest function
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 02/66] drm/amdgpu: add debugfs access to the IP discovery table Alex Deucher
` (65 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Consolidate harvesting information.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 7 +++++++
drivers/gpu/drm/amd/amdgpu/nv.c | 14 --------------
2 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index ada7bc19118a..f55613611a02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -413,6 +413,13 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
}
+ if ((adev->pdev->device == 0x731E &&
+ (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) ||
+ (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9) ||
+ (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) {
+ adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
+ adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
+ }
}
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index ff80786e3918..726975caf4be 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -608,16 +608,6 @@ static const struct amdgpu_ip_block_version nv_common_ip_block =
.funcs = &nv_common_ip_funcs,
};
-static bool nv_is_headless_sku(struct pci_dev *pdev)
-{
- if ((pdev->device == 0x731E &&
- (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
- (pdev->device == 0x7340 && pdev->revision == 0xC9) ||
- (pdev->device == 0x7360 && pdev->revision == 0xC7))
- return true;
- return false;
-}
-
static int nv_reg_base_init(struct amdgpu_device *adev)
{
int r;
@@ -631,10 +621,6 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
}
amdgpu_discovery_harvest_ip(adev);
- if (nv_is_headless_sku(adev->pdev)) {
- adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
- adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
- }
return 0;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 02/66] drm/amdgpu: add debugfs access to the IP discovery table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
2021-09-21 18:06 ` [PATCH 01/66] drm/amdgpu: move headless sku check into harvest function Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 03/66] drm/amdgpu: store HW IP versions in the driver structure Alex Deucher
` (64 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Useful for debugging and new asic validation.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d356e329e6f8..cdb963b9bea0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -830,6 +830,7 @@ struct amdgpu_device {
struct notifier_block acpi_nb;
struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
struct debugfs_blob_wrapper debugfs_vbios_blob;
+ struct debugfs_blob_wrapper debugfs_discovery_blob;
struct mutex srbm_mutex;
/* GRBM index mutex. Protects concurrent access to GRBM index */
struct mutex grbm_idx_mutex;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 074ffcf0dac2..31e16a42d4e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1757,6 +1757,11 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
debugfs_create_blob("amdgpu_vbios", 0444, root,
&adev->debugfs_vbios_blob);
+ adev->debugfs_discovery_blob.data = adev->mman.discovery_bin;
+ adev->debugfs_discovery_blob.size = adev->mman.discovery_tmr_size;
+ debugfs_create_blob("amdgpu_discovery", 0444, root,
+ &adev->debugfs_discovery_blob);
+
return 0;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 03/66] drm/amdgpu: store HW IP versions in the driver structure
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
2021-09-21 18:06 ` [PATCH 01/66] drm/amdgpu: move headless sku check into harvest function Alex Deucher
2021-09-21 18:06 ` [PATCH 02/66] drm/amdgpu: add debugfs access to the IP discovery table Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table Alex Deucher
` (63 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
So we can check the IP versions directly rather than using
asic type.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++++
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 -
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index cdb963b9bea0..61ef0d81a957 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -760,6 +760,9 @@ enum amd_hw_ip_block_type {
#define HWIP_MAX_INSTANCE 10
+#define HW_ID_MAX 300
+#define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
+
struct amd_powerplay {
void *pp_handle;
const struct amd_pm_funcs *pp_funcs;
@@ -1090,6 +1093,7 @@ struct amdgpu_device {
struct pci_saved_state *pci_state;
struct amdgpu_reset_control *reset_cntl;
+ uint32_t ip_versions[HW_ID_MAX];
};
static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index f55613611a02..67e7a46f5020 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -30,7 +30,6 @@
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
#define mmMM_DATA 0x1
-#define HW_ID_MAX 300
static const char *hw_id_names[HW_ID_MAX] = {
[MP1_HWID] = "MP1",
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (2 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 03/66] drm/amdgpu: store HW IP versions in the driver structure Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-22 16:58 ` Felix Kuehling
2021-09-21 18:06 ` [PATCH 05/66] drm/amdgpu: add XGMI HWIP Alex Deucher
` (62 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Prerequisite for using IP versions in the driver rather
than asic type.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 67e7a46f5020..ff52fcce1f93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -244,6 +244,11 @@ void amdgpu_discovery_fini(struct amdgpu_device *adev)
adev->mman.discovery_bin = NULL;
}
+static u32 amdgpu_discovery_convert_version(u32 major, u32 minor, u32 revision)
+{
+ return (major << 16) | (minor << 8) | revision;
+}
+
int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
{
struct binary_header *bhdr;
@@ -316,8 +321,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
hw_id_names[le16_to_cpu(ip->hw_id)]);
adev->reg_offset[hw_ip][ip->number_instance] =
ip->base_address;
+ adev->ip_versions[hw_ip] =
+ amdgpu_discovery_convert_version(ip->major, ip->minor, ip->revision);
}
-
}
ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table
2021-09-21 18:06 ` [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table Alex Deucher
@ 2021-09-22 16:58 ` Felix Kuehling
2021-09-22 20:43 ` Deucher, Alexander
0 siblings, 1 reply; 106+ messages in thread
From: Felix Kuehling @ 2021-09-22 16:58 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
Am 2021-09-21 um 2:06 p.m. schrieb Alex Deucher:
> Prerequisite for using IP versions in the driver rather
> than asic type.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 67e7a46f5020..ff52fcce1f93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -244,6 +244,11 @@ void amdgpu_discovery_fini(struct amdgpu_device *adev)
> adev->mman.discovery_bin = NULL;
> }
>
> +static u32 amdgpu_discovery_convert_version(u32 major, u32 minor, u32 revision)
> +{
> + return (major << 16) | (minor << 8) | revision;
This does the same as the IP_VERSION macro defined in the previous
patch. Do you need this function at all?
Regards,
Felix
> +}
> +
> int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> {
> struct binary_header *bhdr;
> @@ -316,8 +321,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> hw_id_names[le16_to_cpu(ip->hw_id)]);
> adev->reg_offset[hw_ip][ip->number_instance] =
> ip->base_address;
> + adev->ip_versions[hw_ip] =
> + amdgpu_discovery_convert_version(ip->major, ip->minor, ip->revision);
> }
> -
> }
>
> ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table
2021-09-22 16:58 ` Felix Kuehling
@ 2021-09-22 20:43 ` Deucher, Alexander
0 siblings, 0 replies; 106+ messages in thread
From: Deucher, Alexander @ 2021-09-22 20:43 UTC (permalink / raw)
To: Kuehling, Felix, amd-gfx
[-- Attachment #1: Type: text/plain, Size: 2188 bytes --]
[AMD Official Use Only]
Fixed locally. Thanks!
Alex
________________________________
From: Kuehling, Felix <Felix.Kuehling@amd.com>
Sent: Wednesday, September 22, 2021 12:58 PM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table
Am 2021-09-21 um 2:06 p.m. schrieb Alex Deucher:
> Prerequisite for using IP versions in the driver rather
> than asic type.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 67e7a46f5020..ff52fcce1f93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -244,6 +244,11 @@ void amdgpu_discovery_fini(struct amdgpu_device *adev)
> adev->mman.discovery_bin = NULL;
> }
>
> +static u32 amdgpu_discovery_convert_version(u32 major, u32 minor, u32 revision)
> +{
> + return (major << 16) | (minor << 8) | revision;
This does the same as the IP_VERSION macro defined in the previous
patch. Do you need this function at all?
Regards,
Felix
> +}
> +
> int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> {
> struct binary_header *bhdr;
> @@ -316,8 +321,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> hw_id_names[le16_to_cpu(ip->hw_id)]);
> adev->reg_offset[hw_ip][ip->number_instance] =
> ip->base_address;
> + adev->ip_versions[hw_ip] =
> + amdgpu_discovery_convert_version(ip->major, ip->minor, ip->revision);
> }
> -
> }
>
> ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
[-- Attachment #2: Type: text/html, Size: 5317 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 05/66] drm/amdgpu: add XGMI HWIP
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (3 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 06/66] drm/amdgpu/nv: export common IP functions Alex Deucher
` (61 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
So we can track grab the appropriate XGMI info out of the
IP discovery table.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 61ef0d81a957..8df4be702870 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -755,6 +755,7 @@ enum amd_hw_ip_block_type {
CLK_HWIP,
UMC_HWIP,
RSMU_HWIP,
+ XGMI_HWIP,
MAX_HWIP
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index ff52fcce1f93..13d143c668a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -128,6 +128,7 @@ static int hw_id_map[MAX_HWIP] = {
[THM_HWIP] = THM_HWID,
[CLK_HWIP] = CLKA_HWID,
[UMC_HWIP] = UMC_HWID,
+ [XGMI_HWIP] = XGMI_HWID,
};
static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 06/66] drm/amdgpu/nv: export common IP functions
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (4 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 05/66] drm/amdgpu: add XGMI HWIP Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 07/66] drm/amdgpu: add initial IP enumeration via IP discovery table Alex Deucher
` (60 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
So they can be driven by IP dicovery table.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/nv.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 726975caf4be..0dc390a7509f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -599,7 +599,7 @@ static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
}
-static const struct amdgpu_ip_block_version nv_common_ip_block =
+const struct amdgpu_ip_block_version nv_common_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 1,
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index 1f40ba3b0460..7df2f85bbcd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -26,6 +26,8 @@
#include "nbio_v2_3.h"
+extern const struct amdgpu_ip_block_version nv_common_ip_block;
+
void nv_grbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
void nv_set_virt_ops(struct amdgpu_device *adev);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 07/66] drm/amdgpu: add initial IP enumeration via IP discovery table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (5 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 06/66] drm/amdgpu/nv: export common IP functions Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 08/66] drm/amdgpu/sdma5.0: convert to IP version checking Alex Deucher
` (59 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Add initial support for all navi based parts.
v2: rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 333 ++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 1 +
2 files changed, 334 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 13d143c668a0..048a08d7f480 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -26,6 +26,26 @@
#include "soc15_hw_ip.h"
#include "discovery.h"
+#include "gmc_v10_0.h"
+#include "gfxhub_v2_0.h"
+#include "mmhub_v2_0.h"
+#include "nbio_v2_3.h"
+#include "nbio_v7_2.h"
+#include "hdp_v5_0.h"
+#include "nv.h"
+#include "navi10_ih.h"
+#include "gfx_v10_0.h"
+#include "sdma_v5_0.h"
+#include "sdma_v5_2.h"
+#include "vcn_v2_0.h"
+#include "jpeg_v2_0.h"
+#include "vcn_v3_0.h"
+#include "jpeg_v3_0.h"
+#include "amdgpu_vkms.h"
+#include "mes_v10_1.h"
+#include "smuio_v11_0.h"
+#include "smuio_v11_0_6.h"
+
#define mmRCC_CONFIG_MEMSIZE 0xde3
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
@@ -463,3 +483,316 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
return 0;
}
+
+
+int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
+{
+ int r;
+
+ r = amdgpu_discovery_reg_base_init(adev);
+ if (r)
+ return -EINVAL;
+
+ amdgpu_discovery_harvest_ip(adev);
+
+ if (!adev->mman.discovery_bin) {
+ DRM_ERROR("ip discovery uninitialized\n");
+ return -EINVAL;
+ }
+
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ adev->family = AMDGPU_FAMILY_NV;
+ break;
+ case IP_VERSION(10, 3, 1):
+ adev->family = AMDGPU_FAMILY_VGH;
+ break;
+ case IP_VERSION(10, 3, 3):
+ adev->family = AMDGPU_FAMILY_YC;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (adev->ip_versions[XGMI_HWIP] == IP_VERSION(4, 8, 0))
+ adev->gmc.xgmi.supported = true;
+
+ /* set NBIO version */
+ switch (adev->ip_versions[NBIO_HWIP]) {
+ case IP_VERSION(7, 2, 0):
+ case IP_VERSION(7, 2, 1):
+ case IP_VERSION(7, 5, 0):
+ adev->nbio.funcs = &nbio_v7_2_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
+ break;
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 3, 0):
+ case IP_VERSION(2, 3, 1):
+ case IP_VERSION(2, 3, 2):
+ case IP_VERSION(3, 3, 0):
+ case IP_VERSION(3, 3, 1):
+ case IP_VERSION(3, 3, 2):
+ case IP_VERSION(3, 3, 3):
+ adev->nbio.funcs = &nbio_v2_3_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ break;
+ default:
+ break;
+ }
+
+ switch (adev->ip_versions[HDP_HWIP]) {
+ case IP_VERSION(5, 0, 0):
+ case IP_VERSION(5, 0, 1):
+ case IP_VERSION(5, 0, 2):
+ case IP_VERSION(5, 0, 3):
+ case IP_VERSION(5, 0, 4):
+ case IP_VERSION(5, 2, 0):
+ adev->hdp.funcs = &hdp_v5_0_funcs;
+ break;
+ default:
+ break;
+ }
+
+ switch (adev->ip_versions[SMUIO_HWIP]) {
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 4):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 8):
+ adev->smuio.funcs = &smuio_v11_0_funcs;
+ break;
+ case IP_VERSION(11, 0, 6):
+ case IP_VERSION(11, 0, 10):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 5, 0):
+ case IP_VERSION(13, 0, 1):
+ adev->smuio.funcs = &smuio_v11_0_6_funcs;
+ break;
+ default:
+ break;
+ }
+
+ /* what IP to use for this? */
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* use GC or MMHUB IP version */
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (adev->ip_versions[OSSSYS_HWIP]) {
+ case IP_VERSION(5, 0, 0):
+ case IP_VERSION(5, 0, 1):
+ case IP_VERSION(5, 0, 2):
+ case IP_VERSION(5, 0, 3):
+ case IP_VERSION(5, 2, 0):
+ case IP_VERSION(5, 2, 1):
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ switch (adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 5):
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
+ case IP_VERSION(11, 5, 0):
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ break;
+ case IP_VERSION(11, 0, 8):
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
+ break;
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
+ amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 8):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
+ case IP_VERSION(11, 5, 0):
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ break;
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
+ amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
+ amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+ } else {
+ switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 3):
+ case IP_VERSION(3, 0, 1):
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ break;
+ case IP_VERSION(2, 0, 3):
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ }
+#endif
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
+ amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(5, 0, 0):
+ case IP_VERSION(5, 0, 1):
+ case IP_VERSION(5, 0, 2):
+ case IP_VERSION(5, 0, 5):
+ amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
+ break;
+ case IP_VERSION(5, 2, 0):
+ case IP_VERSION(5, 2, 2):
+ case IP_VERSION(5, 2, 4):
+ case IP_VERSION(5, 2, 5):
+ case IP_VERSION(5, 2, 3):
+ case IP_VERSION(5, 2, 1):
+ amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 8):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
+ case IP_VERSION(11, 5, 0):
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ break;
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
+ amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ switch (adev->ip_versions[UVD_HWIP]) {
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 0, 2):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ break;
+ case IP_VERSION(2, 0, 3):
+ break;
+ case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 16):
+ case IP_VERSION(3, 1, 1):
+ case IP_VERSION(3, 0, 2):
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
+ break;
+ case IP_VERSION(3, 0, 33):
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (adev->enable_mes) {
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
+ break;
+ default:
+ break;;
+ }
+ }
+
+ return 0;
+}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
index 48e6b88cfdfe..0ea029e3b850 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
@@ -36,5 +36,6 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int n
int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
int *major, int *minor, int *revision);
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
+int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev);
#endif /* __AMDGPU_DISCOVERY__ */
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 08/66] drm/amdgpu/sdma5.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (6 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 07/66] drm/amdgpu: add initial IP enumeration via IP discovery table Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 09/66] drm/amdgpu/sdma5.2: " Alex Deucher
` (58 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
v2: rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 30 +++++++++++++-------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 50bf3b71bc93..2ab670c58520 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -187,8 +187,8 @@ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_NAVI10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(5, 0, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma_5,
(const u32)ARRAY_SIZE(golden_settings_sdma_5));
@@ -196,7 +196,7 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_nv10,
(const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
break;
- case CHIP_NAVI14:
+ case IP_VERSION(5, 0, 2):
soc15_program_register_sequence(adev,
golden_settings_sdma_5,
(const u32)ARRAY_SIZE(golden_settings_sdma_5));
@@ -204,7 +204,7 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_nv14,
(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
break;
- case CHIP_NAVI12:
+ case IP_VERSION(5, 0, 5):
if (amdgpu_sriov_vf(adev))
soc15_program_register_sequence(adev,
golden_settings_sdma_5_sriov,
@@ -217,7 +217,7 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_nv12,
(const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(5, 0, 1):
soc15_program_register_sequence(adev,
golden_settings_sdma_cyan_skillfish,
(const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
@@ -248,22 +248,22 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
const struct common_firmware_header *header = NULL;
const struct sdma_firmware_header_v1_0 *hdr;
- if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12))
+ if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 0, 5)))
return 0;
DRM_DEBUG("\n");
- switch (adev->asic_type) {
- case CHIP_NAVI10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(5, 0, 0):
chip_name = "navi10";
break;
- case CHIP_NAVI14:
+ case IP_VERSION(5, 0, 2):
chip_name = "navi14";
break;
- case CHIP_NAVI12:
+ case IP_VERSION(5, 0, 5):
chip_name = "navi12";
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(5, 0, 1):
if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
chip_name = "cyan_skillfish2";
else
@@ -1636,10 +1636,10 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(5, 0, 0):
+ case IP_VERSION(5, 0, 2):
+ case IP_VERSION(5, 0, 5):
sdma_v5_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v5_0_update_medium_grain_light_sleep(adev,
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 09/66] drm/amdgpu/sdma5.2: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (7 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 08/66] drm/amdgpu/sdma5.0: convert to IP version checking Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-22 5:55 ` Lazar, Lijo
2021-09-21 18:06 ` [PATCH 10/66] drm/amdgpu/gfx10: " Alex Deucher
` (57 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 48 +++++++++++++-------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index e4a96e7e386d..c5252f12eee9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -136,23 +136,23 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(5, 2, 0):
chip_name = "sienna_cichlid";
break;
- case CHIP_NAVY_FLOUNDER:
+ case IP_VERSION(5, 2, 2):
chip_name = "navy_flounder";
break;
- case CHIP_VANGOGH:
+ case IP_VERSION(5, 2, 1):
chip_name = "vangogh";
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(5, 2, 4):
chip_name = "dimgrey_cavefish";
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(5, 2, 5):
chip_name = "beige_goby";
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(5, 2, 3):
chip_name = "yellow_carp";
break;
default:
@@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
(void *)&adev->sdma.instance[0],
sizeof(struct amdgpu_sdma_instance));
- if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
+ if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 0)))
return 0;
DRM_DEBUG("psp_load == '%s'\n",
@@ -1209,17 +1209,17 @@ static int sdma_v5_2_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(5, 2, 0):
adev->sdma.num_instances = 4;
break;
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(5, 2, 2):
+ case IP_VERSION(5, 2, 4):
adev->sdma.num_instances = 2;
break;
- case CHIP_VANGOGH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(5, 2, 1):
+ case IP_VERSION(5, 2, 5):
+ case IP_VERSION(5, 2, 3):
adev->sdma.num_instances = 1;
break;
default:
@@ -1547,7 +1547,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
+ if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
@@ -1584,7 +1584,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
+ if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
@@ -1613,13 +1613,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(5, 2, 0):
+ case IP_VERSION(5, 2, 2):
+ case IP_VERSION(5, 2, 1):
+ case IP_VERSION(5, 2, 4):
+ case IP_VERSION(5, 2, 5):
+ case IP_VERSION(5, 2, 3):
sdma_v5_2_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v5_2_update_medium_grain_light_sleep(adev,
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 09/66] drm/amdgpu/sdma5.2: convert to IP version checking
2021-09-21 18:06 ` [PATCH 09/66] drm/amdgpu/sdma5.2: " Alex Deucher
@ 2021-09-22 5:55 ` Lazar, Lijo
2021-09-22 6:08 ` Chen, Guchun
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 5:55 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 48 +++++++++++++-------------
> 1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index e4a96e7e386d..c5252f12eee9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -136,23 +136,23 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
>
> DRM_DEBUG("\n");
>
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> + switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(5, 2, 0):
> chip_name = "sienna_cichlid";
> break;
> - case CHIP_NAVY_FLOUNDER:
> + case IP_VERSION(5, 2, 2):
> chip_name = "navy_flounder";
> break;
> - case CHIP_VANGOGH:
> + case IP_VERSION(5, 2, 1):
> chip_name = "vangogh";
> break;
> - case CHIP_DIMGREY_CAVEFISH:
> + case IP_VERSION(5, 2, 4):
> chip_name = "dimgrey_cavefish";
> break;
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(5, 2, 5):
> chip_name = "beige_goby";
> break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(5, 2, 3):
> chip_name = "yellow_carp";
> break;
> default:
> @@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
> (void *)&adev->sdma.instance[0],
> sizeof(struct amdgpu_sdma_instance));
>
> - if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 0)))
> return 0;
>
> DRM_DEBUG("psp_load == '%s'\n",
> @@ -1209,17 +1209,17 @@ static int sdma_v5_2_early_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> + switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(5, 2, 0):
> adev->sdma.num_instances = 4;
> break;
Isn't the instance count also expected from discovery table?
Thanks,
Lijo
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> + case IP_VERSION(5, 2, 2):
> + case IP_VERSION(5, 2, 4):
> adev->sdma.num_instances = 2;
> break;
> - case CHIP_VANGOGH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(5, 2, 1):
> + case IP_VERSION(5, 2, 5):
> + case IP_VERSION(5, 2, 3):
> adev->sdma.num_instances = 1;
> break;
> default:
> @@ -1547,7 +1547,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
>
> - if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
> + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
> @@ -1584,7 +1584,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
>
> - if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
> + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
> @@ -1613,13 +1613,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> + switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(5, 2, 0):
> + case IP_VERSION(5, 2, 2):
> + case IP_VERSION(5, 2, 1):
> + case IP_VERSION(5, 2, 4):
> + case IP_VERSION(5, 2, 5):
> + case IP_VERSION(5, 2, 3):
> sdma_v5_2_update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> sdma_v5_2_update_medium_grain_light_sleep(adev,
>
^ permalink raw reply [flat|nested] 106+ messages in thread* RE: [PATCH 09/66] drm/amdgpu/sdma5.2: convert to IP version checking
2021-09-22 5:55 ` Lazar, Lijo
@ 2021-09-22 6:08 ` Chen, Guchun
2021-09-22 9:18 ` Lazar, Lijo
0 siblings, 1 reply; 106+ messages in thread
From: Chen, Guchun @ 2021-09-22 6:08 UTC (permalink / raw)
To: Lazar, Lijo, Deucher, Alexander, amd-gfx
[Public]
> + switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(5, 2, 0):
> adev->sdma.num_instances = 4;
> break;
Isn't the instance count also expected from discovery table?
This will be addressed in patch 54 of the series.
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Lazar, Lijo
Sent: Wednesday, September 22, 2021 1:56 PM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 09/66] drm/amdgpu/sdma5.2: convert to IP version checking
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate IP version
> specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 48 +++++++++++++-------------
> 1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index e4a96e7e386d..c5252f12eee9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -136,23 +136,23 @@ static int sdma_v5_2_init_microcode(struct
> amdgpu_device *adev)
>
> DRM_DEBUG("\n");
>
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> + switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(5, 2, 0):
> chip_name = "sienna_cichlid";
> break;
> - case CHIP_NAVY_FLOUNDER:
> + case IP_VERSION(5, 2, 2):
> chip_name = "navy_flounder";
> break;
> - case CHIP_VANGOGH:
> + case IP_VERSION(5, 2, 1):
> chip_name = "vangogh";
> break;
> - case CHIP_DIMGREY_CAVEFISH:
> + case IP_VERSION(5, 2, 4):
> chip_name = "dimgrey_cavefish";
> break;
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(5, 2, 5):
> chip_name = "beige_goby";
> break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(5, 2, 3):
> chip_name = "yellow_carp";
> break;
> default:
> @@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
> (void *)&adev->sdma.instance[0],
> sizeof(struct amdgpu_sdma_instance));
>
> - if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] ==
> +IP_VERSION(5, 2, 0)))
> return 0;
>
> DRM_DEBUG("psp_load == '%s'\n",
> @@ -1209,17 +1209,17 @@ static int sdma_v5_2_early_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> + switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(5, 2, 0):
> adev->sdma.num_instances = 4;
> break;
Isn't the instance count also expected from discovery table?
Thanks,
Lijo
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> + case IP_VERSION(5, 2, 2):
> + case IP_VERSION(5, 2, 4):
> adev->sdma.num_instances = 2;
> break;
> - case CHIP_VANGOGH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(5, 2, 1):
> + case IP_VERSION(5, 2, 5):
> + case IP_VERSION(5, 2, 3):
> adev->sdma.num_instances = 1;
> break;
> default:
> @@ -1547,7 +1547,7 @@ static void
> sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
>
> - if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
> + if (adev->sdma.instance[i].fw_version < 70 &&
> +adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { @@
> -1584,7 +1584,7 @@ static void
> sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
>
> - if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
> + if (adev->sdma.instance[i].fw_version < 70 &&
> +adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { @@
> -1613,13 +1613,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> + switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(5, 2, 0):
> + case IP_VERSION(5, 2, 2):
> + case IP_VERSION(5, 2, 1):
> + case IP_VERSION(5, 2, 4):
> + case IP_VERSION(5, 2, 5):
> + case IP_VERSION(5, 2, 3):
> sdma_v5_2_update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> sdma_v5_2_update_medium_grain_light_sleep(adev,
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 09/66] drm/amdgpu/sdma5.2: convert to IP version checking
2021-09-22 6:08 ` Chen, Guchun
@ 2021-09-22 9:18 ` Lazar, Lijo
0 siblings, 0 replies; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 9:18 UTC (permalink / raw)
To: Chen, Guchun, Deucher, Alexander, amd-gfx
On 9/22/2021 11:38 AM, Chen, Guchun wrote:
> [Public]
>
>> + switch (adev->ip_versions[SDMA0_HWIP]) {
>> + case IP_VERSION(5, 2, 0):
>> adev->sdma.num_instances = 4;
>> break;
> Isn't the instance count also expected from discovery table?
>
> This will be addressed in patch 54 of the series.
>
Thanks Guchun! Saw that after a while :)
Alex,
Please ignore the comment. Apart from a few comments here and there, the
patch series in general looks good to me.
Thanks,
Lijo
> Regards,
> Guchun
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Lazar, Lijo
> Sent: Wednesday, September 22, 2021 1:56 PM
> To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 09/66] drm/amdgpu/sdma5.2: convert to IP version checking
>
>
>
> On 9/21/2021 11:36 PM, Alex Deucher wrote:
>> Use IP versions rather than asic_type to differentiate IP version
>> specific features.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 48 +++++++++++++-------------
>> 1 file changed, 24 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> index e4a96e7e386d..c5252f12eee9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> @@ -136,23 +136,23 @@ static int sdma_v5_2_init_microcode(struct
>> amdgpu_device *adev)
>>
>> DRM_DEBUG("\n");
>>
>> - switch (adev->asic_type) {
>> - case CHIP_SIENNA_CICHLID:
>> + switch (adev->ip_versions[SDMA0_HWIP]) {
>> + case IP_VERSION(5, 2, 0):
>> chip_name = "sienna_cichlid";
>> break;
>> - case CHIP_NAVY_FLOUNDER:
>> + case IP_VERSION(5, 2, 2):
>> chip_name = "navy_flounder";
>> break;
>> - case CHIP_VANGOGH:
>> + case IP_VERSION(5, 2, 1):
>> chip_name = "vangogh";
>> break;
>> - case CHIP_DIMGREY_CAVEFISH:
>> + case IP_VERSION(5, 2, 4):
>> chip_name = "dimgrey_cavefish";
>> break;
>> - case CHIP_BEIGE_GOBY:
>> + case IP_VERSION(5, 2, 5):
>> chip_name = "beige_goby";
>> break;
>> - case CHIP_YELLOW_CARP:
>> + case IP_VERSION(5, 2, 3):
>> chip_name = "yellow_carp";
>> break;
>> default:
>> @@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
>> (void *)&adev->sdma.instance[0],
>> sizeof(struct amdgpu_sdma_instance));
>>
>> - if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
>> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] ==
>> +IP_VERSION(5, 2, 0)))
>> return 0;
>>
>> DRM_DEBUG("psp_load == '%s'\n",
>> @@ -1209,17 +1209,17 @@ static int sdma_v5_2_early_init(void *handle)
>> {
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> - switch (adev->asic_type) {
>> - case CHIP_SIENNA_CICHLID:
>> + switch (adev->ip_versions[SDMA0_HWIP]) {
>> + case IP_VERSION(5, 2, 0):
>> adev->sdma.num_instances = 4;
>> break;
> Isn't the instance count also expected from discovery table?
>
> Thanks,
> Lijo
>
>> - case CHIP_NAVY_FLOUNDER:
>> - case CHIP_DIMGREY_CAVEFISH:
>> + case IP_VERSION(5, 2, 2):
>> + case IP_VERSION(5, 2, 4):
>> adev->sdma.num_instances = 2;
>> break;
>> - case CHIP_VANGOGH:
>> - case CHIP_BEIGE_GOBY:
>> - case CHIP_YELLOW_CARP:
>> + case IP_VERSION(5, 2, 1):
>> + case IP_VERSION(5, 2, 5):
>> + case IP_VERSION(5, 2, 3):
>> adev->sdma.num_instances = 1;
>> break;
>> default:
>> @@ -1547,7 +1547,7 @@ static void
>> sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
>>
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>>
>> - if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
>> + if (adev->sdma.instance[i].fw_version < 70 &&
>> +adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
>> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
>>
>> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { @@
>> -1584,7 +1584,7 @@ static void
>> sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>>
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>>
>> - if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
>> + if (adev->sdma.instance[i].fw_version < 70 &&
>> +adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
>> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
>>
>> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { @@
>> -1613,13 +1613,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>>
>> - switch (adev->asic_type) {
>> - case CHIP_SIENNA_CICHLID:
>> - case CHIP_NAVY_FLOUNDER:
>> - case CHIP_VANGOGH:
>> - case CHIP_DIMGREY_CAVEFISH:
>> - case CHIP_BEIGE_GOBY:
>> - case CHIP_YELLOW_CARP:
>> + switch (adev->ip_versions[SDMA0_HWIP]) {
>> + case IP_VERSION(5, 2, 0):
>> + case IP_VERSION(5, 2, 2):
>> + case IP_VERSION(5, 2, 1):
>> + case IP_VERSION(5, 2, 4):
>> + case IP_VERSION(5, 2, 5):
>> + case IP_VERSION(5, 2, 3):
>> sdma_v5_2_update_medium_grain_clock_gating(adev,
>> state == AMD_CG_STATE_GATE);
>> sdma_v5_2_update_medium_grain_light_sleep(adev,
>>
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 10/66] drm/amdgpu/gfx10: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (8 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 09/66] drm/amdgpu/sdma5.2: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs Alex Deucher
` (56 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
v2: rebase, squash in navi10 fixes (Alex)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 380 ++++++++++++-------------
1 file changed, 190 insertions(+), 190 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 16dbe593cba2..4c632306ed70 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1537,7 +1537,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
scratch_reg3 = adev->rmmio +
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
- if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
+ if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
spare_int = adev->rmmio +
(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
+ mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
@@ -3727,18 +3727,18 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_NAVI10:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
soc15_program_register_sequence(adev,
golden_settings_gc_rlc_spm_10_0_nv10,
(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
break;
- case CHIP_NAVI14:
+ case IP_VERSION(10, 1, 1):
soc15_program_register_sequence(adev,
golden_settings_gc_rlc_spm_10_1_nv14,
(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
break;
- case CHIP_NAVI12:
+ case IP_VERSION(10, 1, 2):
soc15_program_register_sequence(adev,
golden_settings_gc_rlc_spm_10_1_2_nv12,
(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
@@ -3750,8 +3750,8 @@ static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_NAVI10:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
soc15_program_register_sequence(adev,
golden_settings_gc_10_1,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
@@ -3759,7 +3759,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_10_0_nv10,
(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
break;
- case CHIP_NAVI14:
+ case IP_VERSION(10, 1, 1):
soc15_program_register_sequence(adev,
golden_settings_gc_10_1_1,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
@@ -3767,7 +3767,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_10_1_nv14,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
break;
- case CHIP_NAVI12:
+ case IP_VERSION(10, 1, 2):
soc15_program_register_sequence(adev,
golden_settings_gc_10_1_2,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
@@ -3775,7 +3775,7 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_10_1_2_nv12,
(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
break;
- case CHIP_SIENNA_CICHLID:
+ case IP_VERSION(10, 3, 0):
soc15_program_register_sequence(adev,
golden_settings_gc_10_3,
(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
@@ -3783,32 +3783,32 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_10_3_sienna_cichlid,
(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
break;
- case CHIP_NAVY_FLOUNDER:
+ case IP_VERSION(10, 3, 2):
soc15_program_register_sequence(adev,
golden_settings_gc_10_3_2,
(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
break;
- case CHIP_VANGOGH:
+ case IP_VERSION(10, 3, 1):
soc15_program_register_sequence(adev,
golden_settings_gc_10_3_vangogh,
(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 3):
soc15_program_register_sequence(adev,
golden_settings_gc_10_3_3,
(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(10, 3, 4):
soc15_program_register_sequence(adev,
golden_settings_gc_10_3_4,
(const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(10, 3, 5):
soc15_program_register_sequence(adev,
golden_settings_gc_10_3_5,
(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(10, 1, 3):
soc15_program_register_sequence(adev,
golden_settings_gc_10_0,
(const u32)ARRAY_SIZE(golden_settings_gc_10_0));
@@ -3985,11 +3985,11 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
{
adev->gfx.cp_fw_write_wait = false;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_NAVI14:
- case CHIP_CYAN_SKILLFISH:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 3):
if ((adev->gfx.me_fw_version >= 0x00000046) &&
(adev->gfx.me_feature_version >= 27) &&
(adev->gfx.pfp_fw_version >= 0x00000068) &&
@@ -3998,12 +3998,12 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
(adev->gfx.mec_feature_version >= 27))
adev->gfx.cp_fw_write_wait = true;
break;
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
adev->gfx.cp_fw_write_wait = true;
break;
default:
@@ -4066,8 +4066,8 @@ static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_NAVI10:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
@@ -4093,38 +4093,38 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->asic_type) {
- case CHIP_NAVI10:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
chip_name = "navi10";
break;
- case CHIP_NAVI14:
+ case IP_VERSION(10, 1, 1):
chip_name = "navi14";
if (!(adev->pdev->device == 0x7340 &&
adev->pdev->revision != 0x00))
wks = "_wks";
break;
- case CHIP_NAVI12:
+ case IP_VERSION(10, 1, 2):
chip_name = "navi12";
break;
- case CHIP_SIENNA_CICHLID:
+ case IP_VERSION(10, 3, 0):
chip_name = "sienna_cichlid";
break;
- case CHIP_NAVY_FLOUNDER:
+ case IP_VERSION(10, 3, 2):
chip_name = "navy_flounder";
break;
- case CHIP_VANGOGH:
+ case IP_VERSION(10, 3, 1):
chip_name = "vangogh";
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(10, 3, 4):
chip_name = "dimgrey_cavefish";
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(10, 3, 5):
chip_name = "beige_goby";
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 3):
chip_name = "yellow_carp";
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(10, 1, 3):
if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
chip_name = "cyan_skillfish2";
else
@@ -4684,10 +4684,10 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4695,12 +4695,12 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
break;
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4710,7 +4710,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.gb_addr_config_fields.num_pkrs =
1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(10, 1, 3):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4818,11 +4818,11 @@ static int gfx_v10_0_sw_init(void *handle)
struct amdgpu_kiq *kiq;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_CYAN_SKILLFISH:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
@@ -4830,12 +4830,12 @@ static int gfx_v10_0_sw_init(void *handle)
adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 8;
break;
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
@@ -5068,8 +5068,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
bitmap = i * adev->gfx.config.max_sh_per_se + j;
- if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
- (adev->asic_type == CHIP_YELLOW_CARP)) &&
+ if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
+ (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
continue;
gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -5096,7 +5096,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
/* for ASICs that integrates GFX v10.3
* pa_sc_tile_steering_override should be set to 0 */
- if (adev->asic_type >= CHIP_SIENNA_CICHLID)
+ if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
return 0;
/* init num_sc */
@@ -5249,7 +5249,7 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
/* TCCs are global (not instanced). */
uint32_t tcc_disable;
- if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
+ if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
} else {
@@ -5326,7 +5326,7 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
/* csib */
- if (adev->asic_type == CHIP_NAVI12) {
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
adev->gfx.rlc.clear_state_gpu_addr >> 32);
WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
@@ -5948,7 +5948,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
- if (adev->asic_type == CHIP_NAVI12) {
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
} else {
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
@@ -6337,13 +6337,13 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
}
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
}
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -6474,13 +6474,13 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
{
if (enable) {
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
break;
default:
@@ -6488,13 +6488,13 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
break;
}
} else {
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
(CP_MEC_CNTL__MEC_ME1_HALT_MASK |
CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6586,13 +6586,13 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
struct amdgpu_device *adev = ring->adev;
/* tell RLC which is KIQ queue */
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
tmp &= 0xffffff00;
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -7303,11 +7303,11 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
/* check if mmVGT_ESGS_RING_SIZE_UMD
* has been remapped to mmVGT_ESGS_RING_SIZE */
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
@@ -7320,8 +7320,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
return false;
}
break;
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 3):
return true;
default:
data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
@@ -7350,13 +7350,13 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
* index will auto-inc after each data writting */
WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -7520,19 +7520,19 @@ static int gfx_v10_0_hw_init(void *handle)
* init golden registers and rlc resume may override some registers,
* reconfig them here
*/
- if (adev->asic_type == CHIP_NAVI10 ||
- adev->asic_type == CHIP_NAVI14 ||
- adev->asic_type == CHIP_NAVI12)
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 10) ||
+ adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 1) ||
+ adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2))
gfx_v10_0_tcp_harvest(adev);
r = gfx_v10_0_cp_resume(adev);
if (r)
return r;
- if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
gfx_v10_3_program_pbb_mode(adev);
- if (adev->asic_type >= CHIP_SIENNA_CICHLID)
+ if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
gfx_v10_3_set_power_brake_sequence(adev);
return r;
@@ -7584,7 +7584,7 @@ static int gfx_v10_0_hw_fini(void *handle)
if (amdgpu_sriov_vf(adev)) {
gfx_v10_0_cp_gfx_enable(adev, false);
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
- if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
+ if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
tmp &= 0xffffff00;
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
@@ -7670,13 +7670,13 @@ static int gfx_v10_0_soft_reset(void *handle)
/* GRBM_STATUS2 */
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
GRBM_SOFT_RESET,
@@ -7726,9 +7726,9 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
{
uint64_t clock, clock_lo, clock_hi, hi_check;
- switch (adev->asic_type) {
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 3):
clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
break;
@@ -7784,19 +7784,19 @@ static int gfx_v10_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_CYAN_SKILLFISH:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
break;
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
break;
default:
@@ -7848,13 +7848,13 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
data = RLC_SAFE_MODE__CMD_MASK;
data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
/* wait for RLC_SAFE_MODE */
@@ -7884,13 +7884,13 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
uint32_t data;
data = RLC_SAFE_MODE__CMD_MASK;
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
break;
default:
@@ -8193,7 +8193,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d
mmCGTS_SA1_QUAD1_SM_CTRL_REG
};
- if (adev->asic_type == CHIP_NAVI12) {
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
tcp_ctrl_regs_nv12[i];
@@ -8238,8 +8238,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
/* === CGCG + CGLS === */
gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
- if ((adev->asic_type >= CHIP_NAVI10) &&
- (adev->asic_type <= CHIP_NAVI12))
+ if ((adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 1, 10)) &&
+ (adev->ip_versions[GC_HWIP] <= IP_VERSION(10, 1, 2)))
gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
} else {
/* CGCG/CGLS should be disabled before MGCG/MGLS
@@ -8335,12 +8335,12 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
* Power/performance team will optimize it and might give a new value later.
*/
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
- switch (adev->asic_type) {
- case CHIP_VANGOGH:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 1):
data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 3):
data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
break;
@@ -8399,18 +8399,18 @@ static int gfx_v10_0_set_powergating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
amdgpu_gfx_off_ctrl(adev, enable);
break;
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 3):
gfx_v10_cntl_pg(adev, enable);
amdgpu_gfx_off_ctrl(adev, enable);
break;
@@ -8428,16 +8428,16 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
gfx_v10_0_update_gfx_clock_gating(adev,
state == AMD_CG_STATE_GATE);
break;
@@ -9541,19 +9541,19 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
break;
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 3, 0):
adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
break;
default:
@@ -9641,8 +9641,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
bitmap = i * adev->gfx.config.max_sh_per_se + j;
- if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
- (adev->asic_type == CHIP_YELLOW_CARP)) &&
+ if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
+ (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
continue;
mask = 1;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (9 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 10/66] drm/amdgpu/gfx10: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-22 4:41 ` Lazar, Lijo
2021-09-22 16:16 ` Felix Kuehling
2021-09-21 18:06 ` [PATCH 12/66] drm/amdgpu: bind to any 0x1002 PCI diplay class device Alex Deucher
` (55 subsequent siblings)
66 siblings, 2 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Once we claim all 0x1002 PCI display class devices, we will
need to filter out devices owned by radeon.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 561 +++++++++++++++++++++++-
1 file changed, 560 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b6ce53fa9b03..3ab7099a1b16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -891,6 +891,559 @@ MODULE_PARM_DESC(smu_pptable_id,
"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
+static const u16 radeon_pciidlist[] = {
+ 0x3150,
+ 0x3151,
+ 0x3152,
+ 0x3154,
+ 0x3155,
+ 0x3E50,
+ 0x3E54,
+ 0x4136,
+ 0x4137,
+ 0x4144,
+ 0x4145,
+ 0x4146,
+ 0x4147,
+ 0x4148,
+ 0x4149,
+ 0x414A,
+ 0x414B,
+ 0x4150,
+ 0x4151,
+ 0x4152,
+ 0x4153,
+ 0x4154,
+ 0x4155,
+ 0x4156,
+ 0x4237,
+ 0x4242,
+ 0x4336,
+ 0x4337,
+ 0x4437,
+ 0x4966,
+ 0x4967,
+ 0x4A48,
+ 0x4A49,
+ 0x4A4A,
+ 0x4A4B,
+ 0x4A4C,
+ 0x4A4D,
+ 0x4A4E,
+ 0x4A4F,
+ 0x4A50,
+ 0x4A54,
+ 0x4B48,
+ 0x4B49,
+ 0x4B4A,
+ 0x4B4B,
+ 0x4B4C,
+ 0x4C57,
+ 0x4C58,
+ 0x4C59,
+ 0x4C5A,
+ 0x4C64,
+ 0x4C66,
+ 0x4C67,
+ 0x4E44,
+ 0x4E45,
+ 0x4E46,
+ 0x4E47,
+ 0x4E48,
+ 0x4E49,
+ 0x4E4A,
+ 0x4E4B,
+ 0x4E50,
+ 0x4E51,
+ 0x4E52,
+ 0x4E53,
+ 0x4E54,
+ 0x4E56,
+ 0x5144,
+ 0x5145,
+ 0x5146,
+ 0x5147,
+ 0x5148,
+ 0x514C,
+ 0x514D,
+ 0x5157,
+ 0x5158,
+ 0x5159,
+ 0x515A,
+ 0x515E,
+ 0x5460,
+ 0x5462,
+ 0x5464,
+ 0x5548,
+ 0x5549,
+ 0x554A,
+ 0x554B,
+ 0x554C,
+ 0x554D,
+ 0x554E,
+ 0x554F,
+ 0x5550,
+ 0x5551,
+ 0x5552,
+ 0x5554,
+ 0x564A,
+ 0x564B,
+ 0x564F,
+ 0x5652,
+ 0x5653,
+ 0x5657,
+ 0x5834,
+ 0x5835,
+ 0x5954,
+ 0x5955,
+ 0x5974,
+ 0x5975,
+ 0x5960,
+ 0x5961,
+ 0x5962,
+ 0x5964,
+ 0x5965,
+ 0x5969,
+ 0x5a41,
+ 0x5a42,
+ 0x5a61,
+ 0x5a62,
+ 0x5b60,
+ 0x5b62,
+ 0x5b63,
+ 0x5b64,
+ 0x5b65,
+ 0x5c61,
+ 0x5c63,
+ 0x5d48,
+ 0x5d49,
+ 0x5d4a,
+ 0x5d4c,
+ 0x5d4d,
+ 0x5d4e,
+ 0x5d4f,
+ 0x5d50,
+ 0x5d52,
+ 0x5d57,
+ 0x5e48,
+ 0x5e4a,
+ 0x5e4b,
+ 0x5e4c,
+ 0x5e4d,
+ 0x5e4f,
+ 0x6700,
+ 0x6701,
+ 0x6702,
+ 0x6703,
+ 0x6704,
+ 0x6705,
+ 0x6706,
+ 0x6707,
+ 0x6708,
+ 0x6709,
+ 0x6718,
+ 0x6719,
+ 0x671c,
+ 0x671d,
+ 0x671f,
+ 0x6720,
+ 0x6721,
+ 0x6722,
+ 0x6723,
+ 0x6724,
+ 0x6725,
+ 0x6726,
+ 0x6727,
+ 0x6728,
+ 0x6729,
+ 0x6738,
+ 0x6739,
+ 0x673e,
+ 0x6740,
+ 0x6741,
+ 0x6742,
+ 0x6743,
+ 0x6744,
+ 0x6745,
+ 0x6746,
+ 0x6747,
+ 0x6748,
+ 0x6749,
+ 0x674A,
+ 0x6750,
+ 0x6751,
+ 0x6758,
+ 0x6759,
+ 0x675B,
+ 0x675D,
+ 0x675F,
+ 0x6760,
+ 0x6761,
+ 0x6762,
+ 0x6763,
+ 0x6764,
+ 0x6765,
+ 0x6766,
+ 0x6767,
+ 0x6768,
+ 0x6770,
+ 0x6771,
+ 0x6772,
+ 0x6778,
+ 0x6779,
+ 0x677B,
+ 0x6840,
+ 0x6841,
+ 0x6842,
+ 0x6843,
+ 0x6849,
+ 0x684C,
+ 0x6850,
+ 0x6858,
+ 0x6859,
+ 0x6880,
+ 0x6888,
+ 0x6889,
+ 0x688A,
+ 0x688C,
+ 0x688D,
+ 0x6898,
+ 0x6899,
+ 0x689b,
+ 0x689c,
+ 0x689d,
+ 0x689e,
+ 0x68a0,
+ 0x68a1,
+ 0x68a8,
+ 0x68a9,
+ 0x68b0,
+ 0x68b8,
+ 0x68b9,
+ 0x68ba,
+ 0x68be,
+ 0x68bf,
+ 0x68c0,
+ 0x68c1,
+ 0x68c7,
+ 0x68c8,
+ 0x68c9,
+ 0x68d8,
+ 0x68d9,
+ 0x68da,
+ 0x68de,
+ 0x68e0,
+ 0x68e1,
+ 0x68e4,
+ 0x68e5,
+ 0x68e8,
+ 0x68e9,
+ 0x68f1,
+ 0x68f2,
+ 0x68f8,
+ 0x68f9,
+ 0x68fa,
+ 0x68fe,
+ 0x7100,
+ 0x7101,
+ 0x7102,
+ 0x7103,
+ 0x7104,
+ 0x7105,
+ 0x7106,
+ 0x7108,
+ 0x7109,
+ 0x710A,
+ 0x710B,
+ 0x710C,
+ 0x710E,
+ 0x710F,
+ 0x7140,
+ 0x7141,
+ 0x7142,
+ 0x7143,
+ 0x7144,
+ 0x7145,
+ 0x7146,
+ 0x7147,
+ 0x7149,
+ 0x714A,
+ 0x714B,
+ 0x714C,
+ 0x714D,
+ 0x714E,
+ 0x714F,
+ 0x7151,
+ 0x7152,
+ 0x7153,
+ 0x715E,
+ 0x715F,
+ 0x7180,
+ 0x7181,
+ 0x7183,
+ 0x7186,
+ 0x7187,
+ 0x7188,
+ 0x718A,
+ 0x718B,
+ 0x718C,
+ 0x718D,
+ 0x718F,
+ 0x7193,
+ 0x7196,
+ 0x719B,
+ 0x719F,
+ 0x71C0,
+ 0x71C1,
+ 0x71C2,
+ 0x71C3,
+ 0x71C4,
+ 0x71C5,
+ 0x71C6,
+ 0x71C7,
+ 0x71CD,
+ 0x71CE,
+ 0x71D2,
+ 0x71D4,
+ 0x71D5,
+ 0x71D6,
+ 0x71DA,
+ 0x71DE,
+ 0x7200,
+ 0x7210,
+ 0x7211,
+ 0x7240,
+ 0x7243,
+ 0x7244,
+ 0x7245,
+ 0x7246,
+ 0x7247,
+ 0x7248,
+ 0x7249,
+ 0x724A,
+ 0x724B,
+ 0x724C,
+ 0x724D,
+ 0x724E,
+ 0x724F,
+ 0x7280,
+ 0x7281,
+ 0x7283,
+ 0x7284,
+ 0x7287,
+ 0x7288,
+ 0x7289,
+ 0x728B,
+ 0x728C,
+ 0x7290,
+ 0x7291,
+ 0x7293,
+ 0x7297,
+ 0x7834,
+ 0x7835,
+ 0x791e,
+ 0x791f,
+ 0x793f,
+ 0x7941,
+ 0x7942,
+ 0x796c,
+ 0x796d,
+ 0x796e,
+ 0x796f,
+ 0x9400,
+ 0x9401,
+ 0x9402,
+ 0x9403,
+ 0x9405,
+ 0x940A,
+ 0x940B,
+ 0x940F,
+ 0x94A0,
+ 0x94A1,
+ 0x94A3,
+ 0x94B1,
+ 0x94B3,
+ 0x94B4,
+ 0x94B5,
+ 0x94B9,
+ 0x9440,
+ 0x9441,
+ 0x9442,
+ 0x9443,
+ 0x9444,
+ 0x9446,
+ 0x944A,
+ 0x944B,
+ 0x944C,
+ 0x944E,
+ 0x9450,
+ 0x9452,
+ 0x9456,
+ 0x945A,
+ 0x945B,
+ 0x945E,
+ 0x9460,
+ 0x9462,
+ 0x946A,
+ 0x946B,
+ 0x947A,
+ 0x947B,
+ 0x9480,
+ 0x9487,
+ 0x9488,
+ 0x9489,
+ 0x948A,
+ 0x948F,
+ 0x9490,
+ 0x9491,
+ 0x9495,
+ 0x9498,
+ 0x949C,
+ 0x949E,
+ 0x949F,
+ 0x94C0,
+ 0x94C1,
+ 0x94C3,
+ 0x94C4,
+ 0x94C5,
+ 0x94C6,
+ 0x94C7,
+ 0x94C8,
+ 0x94C9,
+ 0x94CB,
+ 0x94CC,
+ 0x94CD,
+ 0x9500,
+ 0x9501,
+ 0x9504,
+ 0x9505,
+ 0x9506,
+ 0x9507,
+ 0x9508,
+ 0x9509,
+ 0x950F,
+ 0x9511,
+ 0x9515,
+ 0x9517,
+ 0x9519,
+ 0x9540,
+ 0x9541,
+ 0x9542,
+ 0x954E,
+ 0x954F,
+ 0x9552,
+ 0x9553,
+ 0x9555,
+ 0x9557,
+ 0x955f,
+ 0x9580,
+ 0x9581,
+ 0x9583,
+ 0x9586,
+ 0x9587,
+ 0x9588,
+ 0x9589,
+ 0x958A,
+ 0x958B,
+ 0x958C,
+ 0x958D,
+ 0x958E,
+ 0x958F,
+ 0x9590,
+ 0x9591,
+ 0x9593,
+ 0x9595,
+ 0x9596,
+ 0x9597,
+ 0x9598,
+ 0x9599,
+ 0x959B,
+ 0x95C0,
+ 0x95C2,
+ 0x95C4,
+ 0x95C5,
+ 0x95C6,
+ 0x95C7,
+ 0x95C9,
+ 0x95CC,
+ 0x95CD,
+ 0x95CE,
+ 0x95CF,
+ 0x9610,
+ 0x9611,
+ 0x9612,
+ 0x9613,
+ 0x9614,
+ 0x9615,
+ 0x9616,
+ 0x9640,
+ 0x9641,
+ 0x9642,
+ 0x9643,
+ 0x9644,
+ 0x9645,
+ 0x9647,
+ 0x9648,
+ 0x9649,
+ 0x964a,
+ 0x964b,
+ 0x964c,
+ 0x964e,
+ 0x964f,
+ 0x9710,
+ 0x9711,
+ 0x9712,
+ 0x9713,
+ 0x9714,
+ 0x9715,
+ 0x9802,
+ 0x9803,
+ 0x9804,
+ 0x9805,
+ 0x9806,
+ 0x9807,
+ 0x9808,
+ 0x9809,
+ 0x980A,
+ 0x9900,
+ 0x9901,
+ 0x9903,
+ 0x9904,
+ 0x9905,
+ 0x9906,
+ 0x9907,
+ 0x9908,
+ 0x9909,
+ 0x990A,
+ 0x990B,
+ 0x990C,
+ 0x990D,
+ 0x990E,
+ 0x990F,
+ 0x9910,
+ 0x9913,
+ 0x9917,
+ 0x9918,
+ 0x9919,
+ 0x9990,
+ 0x9991,
+ 0x9992,
+ 0x9993,
+ 0x9994,
+ 0x9995,
+ 0x9996,
+ 0x9997,
+ 0x9998,
+ 0x9999,
+ 0x999A,
+ 0x999B,
+ 0x999C,
+ 0x999D,
+ 0x99A0,
+ 0x99A2,
+ 0x99A4,
+};
+
static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
@@ -1253,9 +1806,15 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
struct drm_device *ddev;
struct amdgpu_device *adev;
unsigned long flags = ent->driver_data;
- int ret, retry = 0;
+ int ret, retry = 0, i;
bool supports_atomic = false;
+ /* skip devices which are owned by radeon */
+ for (i = 0; i < ARRAY_SIZE(radeon_pciidlist); i++) {
+ if (radeon_pciidlist[i] == pdev->device)
+ return -ENODEV;
+ }
+
if (amdgpu_virtual_display ||
amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
supports_atomic = true;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs
2021-09-21 18:06 ` [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs Alex Deucher
@ 2021-09-22 4:41 ` Lazar, Lijo
2021-09-22 15:19 ` Deucher, Alexander
2021-09-22 16:16 ` Felix Kuehling
1 sibling, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 4:41 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Once we claim all 0x1002 PCI display class devices, we will
> need to filter out devices owned by radeon.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 561 +++++++++++++++++++++++-
> 1 file changed, 560 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index b6ce53fa9b03..3ab7099a1b16 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -891,6 +891,559 @@ MODULE_PARM_DESC(smu_pptable_id,
> "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
> module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
>
> +static const u16 radeon_pciidlist[] = {
Instead of associating to only radeon, maybe rename to something more
generic such that all device ids in the list will be skipped.
Thanks,
Lijo
> + 0x3150,
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> + 0x99A2,
> + 0x99A4,
> +};
> +
> static const struct pci_device_id pciidlist[] = {
> #ifdef CONFIG_DRM_AMDGPU_SI
> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
> @@ -1253,9 +1806,15 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
> struct drm_device *ddev;
> struct amdgpu_device *adev;
> unsigned long flags = ent->driver_data;
> - int ret, retry = 0;
> + int ret, retry = 0, i;
> bool supports_atomic = false;
>
> + /* skip devices which are owned by radeon */
> + for (i = 0; i < ARRAY_SIZE(radeon_pciidlist); i++) {
> + if (radeon_pciidlist[i] == pdev->device)
> + return -ENODEV;
> + }
> +
> if (amdgpu_virtual_display ||
> amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
> supports_atomic = true;
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs
2021-09-22 4:41 ` Lazar, Lijo
@ 2021-09-22 15:19 ` Deucher, Alexander
0 siblings, 0 replies; 106+ messages in thread
From: Deucher, Alexander @ 2021-09-22 15:19 UTC (permalink / raw)
To: Lazar, Lijo, amd-gfx
[-- Attachment #1: Type: text/plain, Size: 11631 bytes --]
[AMD Official Use Only]
Fixed locally. Thanks!
________________________________
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Wednesday, September 22, 2021 12:41 AM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Once we claim all 0x1002 PCI display class devices, we will
> need to filter out devices owned by radeon.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 561 +++++++++++++++++++++++-
> 1 file changed, 560 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index b6ce53fa9b03..3ab7099a1b16 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -891,6 +891,559 @@ MODULE_PARM_DESC(smu_pptable_id,
> "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
> module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
>
> +static const u16 radeon_pciidlist[] = {
Instead of associating to only radeon, maybe rename to something more
generic such that all device ids in the list will be skipped.
Thanks,
Lijo
> + 0x3150,
> + 0x3151,
> + 0x3152,
> + 0x3154,
> + 0x3155,
> + 0x3E50,
> + 0x3E54,
> + 0x4136,
> + 0x4137,
> + 0x4144,
> + 0x4145,
> + 0x4146,
> + 0x4147,
> + 0x4148,
> + 0x4149,
> + 0x414A,
> + 0x414B,
> + 0x4150,
> + 0x4151,
> + 0x4152,
> + 0x4153,
> + 0x4154,
> + 0x4155,
> + 0x4156,
> + 0x4237,
> + 0x4242,
> + 0x4336,
> + 0x4337,
> + 0x4437,
> + 0x4966,
> + 0x4967,
> + 0x4A48,
> + 0x4A49,
> + 0x4A4A,
> + 0x4A4B,
> + 0x4A4C,
> + 0x4A4D,
> + 0x4A4E,
> + 0x4A4F,
> + 0x4A50,
> + 0x4A54,
> + 0x4B48,
> + 0x4B49,
> + 0x4B4A,
> + 0x4B4B,
> + 0x4B4C,
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> + 0x4C64,
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> + 0x4E44,
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> + 0x4E56,
> + 0x5144,
> + 0x5145,
> + 0x5146,
> + 0x5147,
> + 0x5148,
> + 0x514C,
> + 0x514D,
> + 0x5157,
> + 0x5158,
> + 0x5159,
> + 0x515A,
> + 0x515E,
> + 0x5460,
> + 0x5462,
> + 0x5464,
> + 0x5548,
> + 0x5549,
> + 0x554A,
> + 0x554B,
> + 0x554C,
> + 0x554D,
> + 0x554E,
> + 0x554F,
> + 0x5550,
> + 0x5551,
> + 0x5552,
> + 0x5554,
> + 0x564A,
> + 0x564B,
> + 0x564F,
> + 0x5652,
> + 0x5653,
> + 0x5657,
> + 0x5834,
> + 0x5835,
> + 0x5954,
> + 0x5955,
> + 0x5974,
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> +};
> +
> static const struct pci_device_id pciidlist[] = {
> #ifdef CONFIG_DRM_AMDGPU_SI
> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
> @@ -1253,9 +1806,15 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
> struct drm_device *ddev;
> struct amdgpu_device *adev;
> unsigned long flags = ent->driver_data;
> - int ret, retry = 0;
> + int ret, retry = 0, i;
> bool supports_atomic = false;
>
> + /* skip devices which are owned by radeon */
> + for (i = 0; i < ARRAY_SIZE(radeon_pciidlist); i++) {
> + if (radeon_pciidlist[i] == pdev->device)
> + return -ENODEV;
> + }
> +
> if (amdgpu_virtual_display ||
> amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
> supports_atomic = true;
>
[-- Attachment #2: Type: text/html, Size: 28390 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs
2021-09-21 18:06 ` [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs Alex Deucher
2021-09-22 4:41 ` Lazar, Lijo
@ 2021-09-22 16:16 ` Felix Kuehling
2021-09-22 17:07 ` Alex Deucher
1 sibling, 1 reply; 106+ messages in thread
From: Felix Kuehling @ 2021-09-22 16:16 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
Am 2021-09-21 um 2:06 p.m. schrieb Alex Deucher:
> Once we claim all 0x1002 PCI display class devices, we will
> need to filter out devices owned by radeon.
Could this list be built from radeon_PCI_IDS and r128_PCI_IDs in
drm/drm_pciids.h to avoid duplication? It also looks like your list is
missing the r128 IDs at the moment.
Regards,
Felix
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 561 +++++++++++++++++++++++-
> 1 file changed, 560 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index b6ce53fa9b03..3ab7099a1b16 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -891,6 +891,559 @@ MODULE_PARM_DESC(smu_pptable_id,
> "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
> module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
>
> +static const u16 radeon_pciidlist[] = {
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> + 0x999C,
> + 0x999D,
> + 0x99A0,
> + 0x99A2,
> + 0x99A4,
> +};
> +
> static const struct pci_device_id pciidlist[] = {
> #ifdef CONFIG_DRM_AMDGPU_SI
> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
> @@ -1253,9 +1806,15 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
> struct drm_device *ddev;
> struct amdgpu_device *adev;
> unsigned long flags = ent->driver_data;
> - int ret, retry = 0;
> + int ret, retry = 0, i;
> bool supports_atomic = false;
>
> + /* skip devices which are owned by radeon */
> + for (i = 0; i < ARRAY_SIZE(radeon_pciidlist); i++) {
> + if (radeon_pciidlist[i] == pdev->device)
> + return -ENODEV;
> + }
> +
> if (amdgpu_virtual_display ||
> amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
> supports_atomic = true;
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs
2021-09-22 16:16 ` Felix Kuehling
@ 2021-09-22 17:07 ` Alex Deucher
0 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-22 17:07 UTC (permalink / raw)
To: Felix Kuehling; +Cc: Alex Deucher, amd-gfx list
On Wed, Sep 22, 2021 at 12:16 PM Felix Kuehling <felix.kuehling@amd.com> wrote:
>
>
> Am 2021-09-21 um 2:06 p.m. schrieb Alex Deucher:
> > Once we claim all 0x1002 PCI display class devices, we will
> > need to filter out devices owned by radeon.
> Could this list be built from radeon_PCI_IDS and r128_PCI_IDs in
> drm/drm_pciids.h to avoid duplication? It also looks like your list is
> missing the r128 IDs at the moment.
I added the r128 and mach64 ids locally as well. I took a look at
using radeon_PCI_IDS and r128_PCI_IDs, but it made the array much
bigger because of all of the additional information in them and it
complicated the handling of SI/CIK support between radeon and amdgpu.
Alex
>
> Regards,
> Felix
>
>
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 561 +++++++++++++++++++++++-
> > 1 file changed, 560 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index b6ce53fa9b03..3ab7099a1b16 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -891,6 +891,559 @@ MODULE_PARM_DESC(smu_pptable_id,
> > "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
> > module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
> >
> > +static const u16 radeon_pciidlist[] = {
> > + 0x3150,
> > + 0x3151,
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> > + 0x9641,
> > + 0x9642,
> > + 0x9643,
> > + 0x9644,
> > + 0x9645,
> > + 0x9647,
> > + 0x9648,
> > + 0x9649,
> > + 0x964a,
> > + 0x964b,
> > + 0x964c,
> > + 0x964e,
> > + 0x964f,
> > + 0x9710,
> > + 0x9711,
> > + 0x9712,
> > + 0x9713,
> > + 0x9714,
> > + 0x9715,
> > + 0x9802,
> > + 0x9803,
> > + 0x9804,
> > + 0x9805,
> > + 0x9806,
> > + 0x9807,
> > + 0x9808,
> > + 0x9809,
> > + 0x980A,
> > + 0x9900,
> > + 0x9901,
> > + 0x9903,
> > + 0x9904,
> > + 0x9905,
> > + 0x9906,
> > + 0x9907,
> > + 0x9908,
> > + 0x9909,
> > + 0x990A,
> > + 0x990B,
> > + 0x990C,
> > + 0x990D,
> > + 0x990E,
> > + 0x990F,
> > + 0x9910,
> > + 0x9913,
> > + 0x9917,
> > + 0x9918,
> > + 0x9919,
> > + 0x9990,
> > + 0x9991,
> > + 0x9992,
> > + 0x9993,
> > + 0x9994,
> > + 0x9995,
> > + 0x9996,
> > + 0x9997,
> > + 0x9998,
> > + 0x9999,
> > + 0x999A,
> > + 0x999B,
> > + 0x999C,
> > + 0x999D,
> > + 0x99A0,
> > + 0x99A2,
> > + 0x99A4,
> > +};
> > +
> > static const struct pci_device_id pciidlist[] = {
> > #ifdef CONFIG_DRM_AMDGPU_SI
> > {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
> > @@ -1253,9 +1806,15 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
> > struct drm_device *ddev;
> > struct amdgpu_device *adev;
> > unsigned long flags = ent->driver_data;
> > - int ret, retry = 0;
> > + int ret, retry = 0, i;
> > bool supports_atomic = false;
> >
> > + /* skip devices which are owned by radeon */
> > + for (i = 0; i < ARRAY_SIZE(radeon_pciidlist); i++) {
> > + if (radeon_pciidlist[i] == pdev->device)
> > + return -ENODEV;
> > + }
> > +
> > if (amdgpu_virtual_display ||
> > amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
> > supports_atomic = true;
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 12/66] drm/amdgpu: bind to any 0x1002 PCI diplay class device
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (10 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 13/66] drm/amdgpu/gmc10.0: convert to IP version checking Alex Deucher
` (54 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Bind to all 0x1002 GPU devices.
For now we explicitly return -ENODEV for generic bindings.
Remove this check once IP discovery based checking is in place.
v2: rebase (Alex)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3ab7099a1b16..c21eac6216a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1793,6 +1793,16 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
{0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
+ { PCI_DEVICE(0x1002, PCI_ANY_ID),
+ .class = PCI_CLASS_DISPLAY_VGA << 8,
+ .class_mask = 0xffffff,
+ .driver_data = 0 },
+
+ { PCI_DEVICE(0x1002, PCI_ANY_ID),
+ .class = PCI_CLASS_DISPLAY_OTHER << 8,
+ .class_mask = 0xffffff,
+ .driver_data = 0 },
+
{0, 0, 0}
};
@@ -1815,6 +1825,11 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
return -ENODEV;
}
+ if (flags == 0) {
+ DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n");
+ return -ENODEV;
+ }
+
if (amdgpu_virtual_display ||
amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
supports_atomic = true;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 13/66] drm/amdgpu/gmc10.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (11 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 12/66] drm/amdgpu: bind to any 0x1002 PCI diplay class device Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 14/66] drm/amdgpu: Use IP discovery to drive setting IP blocks by default Alex Deucher
` (53 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
v2: squash in gmc fixes
v3: rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 91 +++++++++-----------------
1 file changed, 30 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 41c3a0d70b7c..b488257ff201 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -133,7 +133,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
* the new fast GRBM interface.
*/
if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
- (adev->asic_type < CHIP_SIENNA_CICHLID))
+ (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
RREG32(hub->vm_l2_pro_fault_status);
status = RREG32(hub->vm_l2_pro_fault_status);
@@ -268,7 +268,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
* to avoid a false ACK due to the new fast GRBM interface.
*/
if ((vmhub == AMDGPU_GFXHUB_0) &&
- (adev->asic_type < CHIP_SIENNA_CICHLID))
+ (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
hub->eng_distance * eng, hub_ip);
@@ -657,8 +657,8 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
+ switch (adev->ip_versions[UMC_HWIP]) {
+ case IP_VERSION(8, 7, 0):
adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
@@ -674,9 +674,9 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 3, 0):
+ case IP_VERSION(2, 4, 0):
adev->mmhub.funcs = &mmhub_v2_3_funcs;
break;
default:
@@ -687,13 +687,13 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
break;
default:
@@ -800,23 +800,9 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
/* set the gart size */
- if (amdgpu_gart_size == -1) {
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
- default:
- adev->gmc.gart_size = 512ULL << 20;
- break;
- }
- } else
+ if (amdgpu_gart_size == -1)
+ adev->gmc.gart_size = 512ULL << 20;
+ else
adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
@@ -871,17 +857,17 @@ static int gmc_v10_0_sw_init(void *handle)
adev->gmc.vram_vendor = vram_vendor;
}
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
adev->num_vmhubs = 2;
/*
* To fulfill 4-level page support,
@@ -989,21 +975,6 @@ static int gmc_v10_0_sw_fini(void *handle)
static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
- break;
- default:
- break;
- }
}
/**
@@ -1161,8 +1132,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
if (r)
return r;
- if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
- adev->asic_type <= CHIP_YELLOW_CARP)
+ if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
return athub_v2_1_set_clockgating(adev, state);
else
return athub_v2_0_set_clockgating(adev, state);
@@ -1174,8 +1144,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
adev->mmhub.funcs->get_clockgating(adev, flags);
- if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
- adev->asic_type <= CHIP_YELLOW_CARP)
+ if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
athub_v2_1_get_clockgating(adev, flags);
else
athub_v2_0_get_clockgating(adev, flags);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 14/66] drm/amdgpu: Use IP discovery to drive setting IP blocks by default
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (12 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 13/66] drm/amdgpu/gmc10.0: convert to IP version checking Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 15/66] drm/amdgpu: drive nav10 from the IP discovery table Alex Deucher
` (52 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Drive the asic setup from the IP discovery table rather than
hardcoded settings based on asic type.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 38d3a7e6474a..782ebd5d2239 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2164,8 +2164,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
return r;
break;
default:
- /* FIXME: not supported yet */
- return -EINVAL;
+ r = amdgpu_discovery_set_ip_blocks(adev);
+ if (r)
+ return r;
+ break;
}
amdgpu_amdkfd_device_probe(adev);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 15/66] drm/amdgpu: drive nav10 from the IP discovery table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (13 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 14/66] drm/amdgpu: Use IP discovery to drive setting IP blocks by default Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 16/66] drm/amdgpu/gfxhub2.1: convert to IP version checking Alex Deucher
` (51 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Rather than hardcoding based on asic_type, use the IP
discovery table to configure the driver.
Only tested on Navi10 so far.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 782ebd5d2239..a4503e006fb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2142,7 +2142,6 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
if (r)
return r;
break;
- case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 16/66] drm/amdgpu/gfxhub2.1: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (14 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 15/66] drm/amdgpu: drive nav10 from the IP discovery table Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 17/66] drm/amdgpu/mmhub2.0: " Alex Deucher
` (50 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 1a374ec0514a..149f3843e0e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -506,8 +506,8 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
u32 max_num_physical_nodes = 0;
u32 max_physical_node_id = 0;
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
+ switch (adev->ip_versions[XGMI_HWIP]) {
+ case IP_VERSION(4, 8, 0):
max_num_physical_nodes = 4;
max_physical_node_id = 3;
break;
@@ -544,7 +544,7 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
adev->gfx.config.max_sh_per_se *
adev->gfx.config.max_shader_engines);
- if (adev->asic_type == CHIP_YELLOW_CARP) {
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3)) {
/* Get SA disabled bitmap from eFuse setting */
efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 17/66] drm/amdgpu/mmhub2.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (15 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 16/66] drm/amdgpu/gfxhub2.1: convert to IP version checking Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 18/66] drm/amdgpu/mmhub2.1: " Alex Deucher
` (49 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 73 +++++++++++--------------
1 file changed, 32 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 7ded6b2f058e..e0cb919b4814 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -153,18 +153,16 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
dev_err(adev->dev,
"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
status);
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_NAVI14:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 0, 2):
mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
break;
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(2, 1, 2):
mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];
break;
default:
@@ -571,11 +569,10 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
return;
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 1, 2):
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
break;
@@ -606,11 +603,10 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
}
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 1, 2):
if (def != data)
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
if (def1 != data1)
@@ -633,11 +629,10 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
return;
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 1, 2):
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
break;
default:
@@ -651,11 +646,10 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
if (def != data) {
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 1, 2):
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
break;
default:
@@ -671,14 +665,12 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 1, 2):
mmhub_v2_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
mmhub_v2_0_update_medium_grain_light_sleep(adev,
@@ -698,11 +690,10 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
if (amdgpu_sriov_vf(adev))
*flags = 0;
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 1, 2):
data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
break;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 18/66] drm/amdgpu/mmhub2.1: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (16 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 17/66] drm/amdgpu/mmhub2.0: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 19/66] drm/amdgpu/vcn3.0: " Alex Deucher
` (48 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index 88e457a150e0..4cf5d0595bbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -90,9 +90,9 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
dev_err(adev->dev,
"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
status);
- switch (adev->asic_type) {
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[MMHUB_HWIP]) {
+ case IP_VERSION(2, 3, 0):
+ case IP_VERSION(2, 4, 0):
mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
break;
default:
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 19/66] drm/amdgpu/vcn3.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (17 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 18/66] drm/amdgpu/mmhub2.1: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 20/66] drm/amdgpu/athub2.0: " Alex Deucher
` (47 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index b1af70d49c6e..ef36ee0f3a5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -95,7 +95,7 @@ static int vcn_v3_0_early_init(void *handle)
adev->vcn.num_enc_rings = 1;
} else {
- if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+ if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
u32 harvest;
adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
@@ -112,7 +112,7 @@ static int vcn_v3_0_early_init(void *handle)
} else
adev->vcn.num_vcn_inst = 1;
- if (adev->asic_type == CHIP_BEIGE_GOBY)
+ if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
adev->vcn.num_enc_rings = 0;
else
adev->vcn.num_enc_rings = 2;
@@ -1272,7 +1272,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
fw_shared->rb.wptr = lower_32_bits(ring->wptr);
fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
- if (adev->asic_type != CHIP_BEIGE_GOBY) {
+ if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
ring = &adev->vcn.inst[i].ring_enc[0];
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
@@ -1644,7 +1644,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
- if (adev->asic_type != CHIP_BEIGE_GOBY) {
+ if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
/* Restore */
fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 20/66] drm/amdgpu/athub2.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (18 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 19/66] drm/amdgpu/vcn3.0: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 21/66] drm/amdgpu/athub2.1: " Alex Deucher
` (46 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
index 3ac505d954c4..d3f634eb40fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
@@ -77,10 +77,9 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
+ switch (adev->ip_versions[ATHUB_HWIP]) {
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 0, 2):
athub_v2_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
athub_v2_0_update_medium_grain_light_sleep(adev,
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 21/66] drm/amdgpu/athub2.1: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (19 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 20/66] drm/amdgpu/athub2.0: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 22/66] drm/amdgpu/navi10_ih: " Alex Deucher
` (45 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
index c12c2900732b..0fbeaf05204e 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
@@ -70,11 +70,10 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[ATHUB_HWIP]) {
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 1, 2):
athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE);
athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE);
break;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 22/66] drm/amdgpu/navi10_ih: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (20 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 21/66] drm/amdgpu/athub2.1: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 23/66] drm/amdgpu/amdgpu_smu: " Alex Deucher
` (44 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 530011622801..c3f968d9cfcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -107,7 +107,7 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
{
u32 ih_cntl, ih_rb_cntl;
- if (adev->asic_type < CHIP_SIENNA_CICHLID)
+ if (adev->ip_versions[OSSSYS_HWIP] < IP_VERSION(5, 0, 3))
return;
ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
@@ -332,13 +332,10 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
if (ih[0]->use_bus_addr) {
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[OSSSYS_HWIP]) {
+ case IP_VERSION(5, 0, 3):
+ case IP_VERSION(5, 2, 0):
+ case IP_VERSION(5, 2, 1):
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 23/66] drm/amdgpu/amdgpu_smu: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (21 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 22/66] drm/amdgpu/navi10_ih: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-22 7:32 ` Lazar, Lijo
2021-09-21 18:06 ` [PATCH 24/66] drm/amdgpu/smu11.0: " Alex Deucher
` (43 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
v2: rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 94 +++++++++++++----------
1 file changed, 55 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 04863a797115..5f372d353d9d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -455,7 +455,8 @@ static int smu_get_power_num_states(void *handle,
bool is_support_sw_smu(struct amdgpu_device *adev)
{
- if (adev->asic_type >= CHIP_ARCTURUS)
+ if ((adev->asic_type >= CHIP_ARCTURUS) ||
+ (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0)))
return true;
return false;
@@ -575,43 +576,47 @@ static int smu_set_funcs(struct amdgpu_device *adev)
if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
smu->od_enabled = true;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 5):
+ case IP_VERSION(11, 0, 9):
navi10_set_ppt_funcs(smu);
break;
- case CHIP_ARCTURUS:
- adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
- arcturus_set_ppt_funcs(smu);
- /* OD is not supported on Arcturus */
- smu->od_enabled =false;
- break;
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
sienna_cichlid_set_ppt_funcs(smu);
break;
- case CHIP_ALDEBARAN:
- aldebaran_set_ppt_funcs(smu);
- /* Enable pp_od_clk_voltage node */
- smu->od_enabled = true;
- break;
- case CHIP_RENOIR:
+ case IP_VERSION(12, 0, 0):
renoir_set_ppt_funcs(smu);
break;
- case CHIP_VANGOGH:
+ case IP_VERSION(11, 5, 0):
vangogh_set_ppt_funcs(smu);
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(13, 0, 1):
yellow_carp_set_ppt_funcs(smu);
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(11, 0, 8):
cyan_skillfish_set_ppt_funcs(smu);
break;
default:
- return -EINVAL;
+ switch (adev->asic_type) {
+ case CHIP_ARCTURUS:
+ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ arcturus_set_ppt_funcs(smu);
+ /* OD is not supported on Arcturus */
+ smu->od_enabled =false;
+ break;
+ case CHIP_ALDEBARAN:
+ aldebaran_set_ppt_funcs(smu);
+ /* Enable pp_od_clk_voltage node */
+ smu->od_enabled = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
}
return 0;
@@ -694,7 +699,7 @@ static int smu_late_init(void *handle)
return ret;
}
- if (adev->asic_type == CHIP_YELLOW_CARP)
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
return 0;
if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
@@ -1140,8 +1145,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
if (adev->in_suspend && smu_is_dpm_running(smu)) {
dev_info(adev->dev, "dpm has been enabled\n");
/* this is needed specifically */
- if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
- (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
+ if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)))
ret = smu_system_features_control(smu, true);
return ret;
}
@@ -1284,7 +1291,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
int ret = 0;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- if (adev->asic_type < CHIP_NAVI10) {
+ if (adev->ip_versions[MP1_HWIP] < IP_VERSION(11, 0, 0)) {
if (smu->ppt_funcs->load_microcode) {
ret = smu->ppt_funcs->load_microcode(smu);
if (ret)
@@ -1403,8 +1410,14 @@ static int smu_disable_dpms(struct smu_context *smu)
* properly.
*/
if (smu->uploading_custom_pp_table &&
- (adev->asic_type >= CHIP_NAVI10) &&
- (adev->asic_type <= CHIP_BEIGE_GOBY))
+ ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))))
return smu_disable_all_features_with_exception(smu,
true,
SMU_FEATURE_COUNT);
@@ -1413,9 +1426,11 @@ static int smu_disable_dpms(struct smu_context *smu)
* For Sienna_Cichlid, PMFW will handle the features disablement properly
* on BACO in. Driver involvement is unnecessary.
*/
- if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
- ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) &&
- use_baco)
+ if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))) &&
+ use_baco)
return smu_disable_all_features_with_exception(smu,
true,
SMU_FEATURE_BACO_BIT);
@@ -1436,7 +1451,7 @@ static int smu_disable_dpms(struct smu_context *smu)
dev_err(adev->dev, "Failed to disable smu features.\n");
}
- if (adev->asic_type >= CHIP_NAVI10 &&
+ if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0) &&
adev->gfx.rlc.funcs->stop)
adev->gfx.rlc.funcs->stop(adev);
@@ -2229,6 +2244,7 @@ int smu_get_power_limit(void *handle,
enum pp_power_type pp_power_type)
{
struct smu_context *smu = handle;
+ struct amdgpu_device *adev = smu->adev;
enum smu_ppt_limit_level limit_level;
uint32_t limit_type;
int ret = 0;
@@ -2273,10 +2289,10 @@ int smu_get_power_limit(void *handle,
switch (limit_level) {
case SMU_PPT_LIMIT_CURRENT:
if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
- (smu->adev->asic_type == CHIP_SIENNA_CICHLID) ||
- (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) ||
- (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) ||
- (smu->adev->asic_type == CHIP_BEIGE_GOBY))
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
ret = smu_get_asic_power_limits(smu,
&smu->current_power_limit,
NULL,
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 23/66] drm/amdgpu/amdgpu_smu: convert to IP version checking
2021-09-21 18:06 ` [PATCH 23/66] drm/amdgpu/amdgpu_smu: " Alex Deucher
@ 2021-09-22 7:32 ` Lazar, Lijo
2021-09-22 15:40 ` Deucher, Alexander
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 7:32 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> v2: rebase
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 94 +++++++++++++----------
> 1 file changed, 55 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 04863a797115..5f372d353d9d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -455,7 +455,8 @@ static int smu_get_power_num_states(void *handle,
>
> bool is_support_sw_smu(struct amdgpu_device *adev)
> {
> - if (adev->asic_type >= CHIP_ARCTURUS)
> + if ((adev->asic_type >= CHIP_ARCTURUS) ||
> + (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0)))
> return true;
>
> return false;
> @@ -575,43 +576,47 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
> smu->od_enabled = true;
>
> - switch (adev->asic_type) {
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_NAVI12:
> + switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(11, 0, 0):
> + case IP_VERSION(11, 0, 5):
> + case IP_VERSION(11, 0, 9):
> navi10_set_ppt_funcs(smu);
> break;
> - case CHIP_ARCTURUS:
> - adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> - arcturus_set_ppt_funcs(smu);
> - /* OD is not supported on Arcturus */
> - smu->od_enabled =false;
> - break;
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(11, 0, 7):
> + case IP_VERSION(11, 0, 11):
> + case IP_VERSION(11, 0, 12):
> + case IP_VERSION(11, 0, 13):
> sienna_cichlid_set_ppt_funcs(smu);
> break;
> - case CHIP_ALDEBARAN:
> - aldebaran_set_ppt_funcs(smu);
> - /* Enable pp_od_clk_voltage node */
> - smu->od_enabled = true;
> - break;
> - case CHIP_RENOIR:
> + case IP_VERSION(12, 0, 0):
> renoir_set_ppt_funcs(smu);
> break;
> - case CHIP_VANGOGH:
> + case IP_VERSION(11, 5, 0):
> vangogh_set_ppt_funcs(smu);
> break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(13, 0, 1):
> yellow_carp_set_ppt_funcs(smu);
> break;
> - case CHIP_CYAN_SKILLFISH:
> + case IP_VERSION(11, 0, 8):
> cyan_skillfish_set_ppt_funcs(smu);
> break;
> default:
> - return -EINVAL;
> + switch (adev->asic_type) {
> + case CHIP_ARCTURUS:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> + arcturus_set_ppt_funcs(smu);
> + /* OD is not supported on Arcturus */
> + smu->od_enabled =false;
> + break;
> + case CHIP_ALDEBARAN:
> + aldebaran_set_ppt_funcs(smu);
> + /* Enable pp_od_clk_voltage node */
> + smu->od_enabled = true;
> + break;
> + default:
> + return -EINVAL;
> + }
> + break;
> }
>
> return 0;
> @@ -694,7 +699,7 @@ static int smu_late_init(void *handle)
> return ret;
> }
>
> - if (adev->asic_type == CHIP_YELLOW_CARP)
> + if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
> return 0;
>
> if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
> @@ -1140,8 +1145,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
> if (adev->in_suspend && smu_is_dpm_running(smu)) {
> dev_info(adev->dev, "dpm has been enabled\n");
> /* this is needed specifically */
> - if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
> - (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> + if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)))
switch...case looks better here
> ret = smu_system_features_control(smu, true);
> return ret;
> }
> @@ -1284,7 +1291,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
> int ret = 0;
>
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> - if (adev->asic_type < CHIP_NAVI10) {
> + if (adev->ip_versions[MP1_HWIP] < IP_VERSION(11, 0, 0)) {
> if (smu->ppt_funcs->load_microcode) {
> ret = smu->ppt_funcs->load_microcode(smu);
> if (ret)
> @@ -1403,8 +1410,14 @@ static int smu_disable_dpms(struct smu_context *smu)
> * properly.
> */
> if (smu->uploading_custom_pp_table &&
> - (adev->asic_type >= CHIP_NAVI10) &&
> - (adev->asic_type <= CHIP_BEIGE_GOBY))
> + ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))))
Same - switch...case
> return smu_disable_all_features_with_exception(smu,
> true,
> SMU_FEATURE_COUNT);
> @@ -1413,9 +1426,11 @@ static int smu_disable_dpms(struct smu_context *smu)
> * For Sienna_Cichlid, PMFW will handle the features disablement properly
> * on BACO in. Driver involvement is unnecessary.
> */
> - if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
> - ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) &&
> - use_baco)
> + if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))) &&
> + use_baco)
Here as well.
Thanks,
Lijo
> return smu_disable_all_features_with_exception(smu,
> true,
> SMU_FEATURE_BACO_BIT);
> @@ -1436,7 +1451,7 @@ static int smu_disable_dpms(struct smu_context *smu)
> dev_err(adev->dev, "Failed to disable smu features.\n");
> }
>
> - if (adev->asic_type >= CHIP_NAVI10 &&
> + if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0) &&
> adev->gfx.rlc.funcs->stop)
> adev->gfx.rlc.funcs->stop(adev);
>
> @@ -2229,6 +2244,7 @@ int smu_get_power_limit(void *handle,
> enum pp_power_type pp_power_type)
> {
> struct smu_context *smu = handle;
> + struct amdgpu_device *adev = smu->adev;
> enum smu_ppt_limit_level limit_level;
> uint32_t limit_type;
> int ret = 0;
> @@ -2273,10 +2289,10 @@ int smu_get_power_limit(void *handle,
> switch (limit_level) {
> case SMU_PPT_LIMIT_CURRENT:
> if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
> - (smu->adev->asic_type == CHIP_SIENNA_CICHLID) ||
> - (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) ||
> - (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) ||
> - (smu->adev->asic_type == CHIP_BEIGE_GOBY))
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
> ret = smu_get_asic_power_limits(smu,
> &smu->current_power_limit,
> NULL,
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 23/66] drm/amdgpu/amdgpu_smu: convert to IP version checking
2021-09-22 7:32 ` Lazar, Lijo
@ 2021-09-22 15:40 ` Deucher, Alexander
0 siblings, 0 replies; 106+ messages in thread
From: Deucher, Alexander @ 2021-09-22 15:40 UTC (permalink / raw)
To: Lazar, Lijo, amd-gfx
[-- Attachment #1: Type: text/plain, Size: 9545 bytes --]
[Public]
Fixed locally. Thanks!
________________________________
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Wednesday, September 22, 2021 3:32 AM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 23/66] drm/amdgpu/amdgpu_smu: convert to IP version checking
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> v2: rebase
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 94 +++++++++++++----------
> 1 file changed, 55 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 04863a797115..5f372d353d9d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -455,7 +455,8 @@ static int smu_get_power_num_states(void *handle,
>
> bool is_support_sw_smu(struct amdgpu_device *adev)
> {
> - if (adev->asic_type >= CHIP_ARCTURUS)
> + if ((adev->asic_type >= CHIP_ARCTURUS) ||
> + (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0)))
> return true;
>
> return false;
> @@ -575,43 +576,47 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
> smu->od_enabled = true;
>
> - switch (adev->asic_type) {
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_NAVI12:
> + switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(11, 0, 0):
> + case IP_VERSION(11, 0, 5):
> + case IP_VERSION(11, 0, 9):
> navi10_set_ppt_funcs(smu);
> break;
> - case CHIP_ARCTURUS:
> - adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> - arcturus_set_ppt_funcs(smu);
> - /* OD is not supported on Arcturus */
> - smu->od_enabled =false;
> - break;
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(11, 0, 7):
> + case IP_VERSION(11, 0, 11):
> + case IP_VERSION(11, 0, 12):
> + case IP_VERSION(11, 0, 13):
> sienna_cichlid_set_ppt_funcs(smu);
> break;
> - case CHIP_ALDEBARAN:
> - aldebaran_set_ppt_funcs(smu);
> - /* Enable pp_od_clk_voltage node */
> - smu->od_enabled = true;
> - break;
> - case CHIP_RENOIR:
> + case IP_VERSION(12, 0, 0):
> renoir_set_ppt_funcs(smu);
> break;
> - case CHIP_VANGOGH:
> + case IP_VERSION(11, 5, 0):
> vangogh_set_ppt_funcs(smu);
> break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(13, 0, 1):
> yellow_carp_set_ppt_funcs(smu);
> break;
> - case CHIP_CYAN_SKILLFISH:
> + case IP_VERSION(11, 0, 8):
> cyan_skillfish_set_ppt_funcs(smu);
> break;
> default:
> - return -EINVAL;
> + switch (adev->asic_type) {
> + case CHIP_ARCTURUS:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> + arcturus_set_ppt_funcs(smu);
> + /* OD is not supported on Arcturus */
> + smu->od_enabled =false;
> + break;
> + case CHIP_ALDEBARAN:
> + aldebaran_set_ppt_funcs(smu);
> + /* Enable pp_od_clk_voltage node */
> + smu->od_enabled = true;
> + break;
> + default:
> + return -EINVAL;
> + }
> + break;
> }
>
> return 0;
> @@ -694,7 +699,7 @@ static int smu_late_init(void *handle)
> return ret;
> }
>
> - if (adev->asic_type == CHIP_YELLOW_CARP)
> + if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
> return 0;
>
> if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
> @@ -1140,8 +1145,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
> if (adev->in_suspend && smu_is_dpm_running(smu)) {
> dev_info(adev->dev, "dpm has been enabled\n");
> /* this is needed specifically */
> - if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
> - (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> + if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)))
switch...case looks better here
> ret = smu_system_features_control(smu, true);
> return ret;
> }
> @@ -1284,7 +1291,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
> int ret = 0;
>
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> - if (adev->asic_type < CHIP_NAVI10) {
> + if (adev->ip_versions[MP1_HWIP] < IP_VERSION(11, 0, 0)) {
> if (smu->ppt_funcs->load_microcode) {
> ret = smu->ppt_funcs->load_microcode(smu);
> if (ret)
> @@ -1403,8 +1410,14 @@ static int smu_disable_dpms(struct smu_context *smu)
> * properly.
> */
> if (smu->uploading_custom_pp_table &&
> - (adev->asic_type >= CHIP_NAVI10) &&
> - (adev->asic_type <= CHIP_BEIGE_GOBY))
> + ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))))
Same - switch...case
> return smu_disable_all_features_with_exception(smu,
> true,
> SMU_FEATURE_COUNT);
> @@ -1413,9 +1426,11 @@ static int smu_disable_dpms(struct smu_context *smu)
> * For Sienna_Cichlid, PMFW will handle the features disablement properly
> * on BACO in. Driver involvement is unnecessary.
> */
> - if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
> - ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) &&
> - use_baco)
> + if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))) &&
> + use_baco)
Here as well.
Thanks,
Lijo
> return smu_disable_all_features_with_exception(smu,
> true,
> SMU_FEATURE_BACO_BIT);
> @@ -1436,7 +1451,7 @@ static int smu_disable_dpms(struct smu_context *smu)
> dev_err(adev->dev, "Failed to disable smu features.\n");
> }
>
> - if (adev->asic_type >= CHIP_NAVI10 &&
> + if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0) &&
> adev->gfx.rlc.funcs->stop)
> adev->gfx.rlc.funcs->stop(adev);
>
> @@ -2229,6 +2244,7 @@ int smu_get_power_limit(void *handle,
> enum pp_power_type pp_power_type)
> {
> struct smu_context *smu = handle;
> + struct amdgpu_device *adev = smu->adev;
> enum smu_ppt_limit_level limit_level;
> uint32_t limit_type;
> int ret = 0;
> @@ -2273,10 +2289,10 @@ int smu_get_power_limit(void *handle,
> switch (limit_level) {
> case SMU_PPT_LIMIT_CURRENT:
> if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
> - (smu->adev->asic_type == CHIP_SIENNA_CICHLID) ||
> - (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) ||
> - (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) ||
> - (smu->adev->asic_type == CHIP_BEIGE_GOBY))
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
> ret = smu_get_asic_power_limits(smu,
> &smu->current_power_limit,
> NULL,
>
[-- Attachment #2: Type: text/html, Size: 22870 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 24/66] drm/amdgpu/smu11.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (22 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 23/66] drm/amdgpu/amdgpu_smu: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 25/66] drm/amdgpu/navi10_ppt: " Alex Deucher
` (42 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
v2: rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 88 ++++++++++---------
1 file changed, 46 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 87b055466a33..5af7c8b7806f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -90,36 +90,37 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
struct amdgpu_firmware_info *ucode = NULL;
if (amdgpu_sriov_vf(adev) &&
- ((adev->asic_type == CHIP_NAVI12) ||
- (adev->asic_type == CHIP_SIENNA_CICHLID)))
+ ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7))))
return 0;
- switch (adev->asic_type) {
- case CHIP_ARCTURUS:
- chip_name = "arcturus";
- break;
- case CHIP_NAVI10:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 0):
chip_name = "navi10";
break;
- case CHIP_NAVI14:
+ case IP_VERSION(11, 0, 5):
chip_name = "navi14";
break;
- case CHIP_NAVI12:
+ case IP_VERSION(11, 0, 9):
chip_name = "navi12";
break;
- case CHIP_SIENNA_CICHLID:
+ case IP_VERSION(11, 0, 7):
chip_name = "sienna_cichlid";
break;
- case CHIP_NAVY_FLOUNDER:
+ case IP_VERSION(11, 0, 11):
chip_name = "navy_flounder";
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(11, 0, 12):
chip_name = "dimgrey_cavefish";
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(11, 0, 13):
chip_name = "beige_goby";
break;
default:
+ if (adev->asic_type == CHIP_ARCTURUS) {
+ chip_name = "arcturus";
+ break;
+ }
dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
return -EINVAL;
}
@@ -238,38 +239,39 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
if (smu->is_apu)
adev->pm.fw_version = smu_version;
- switch (smu->adev->asic_type) {
- case CHIP_ARCTURUS:
- smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
- break;
- case CHIP_NAVI10:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 0):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
break;
- case CHIP_NAVI12:
+ case IP_VERSION(11, 0, 9):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
break;
- case CHIP_NAVI14:
+ case IP_VERSION(11, 0, 5):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
break;
- case CHIP_SIENNA_CICHLID:
+ case IP_VERSION(11, 0, 7):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
break;
- case CHIP_NAVY_FLOUNDER:
+ case IP_VERSION(11, 0, 11):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
break;
case CHIP_VANGOGH:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(11, 0, 12):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(11, 0, 13):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(11, 0, 8):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
break;
default:
+ if (adev->asic_type == CHIP_ARCTURUS) {
+ smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
+ break;
+ }
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
break;
@@ -492,8 +494,9 @@ int smu_v11_0_fini_smc_tables(struct smu_context *smu)
int smu_v11_0_init_power(struct smu_context *smu)
{
+ struct amdgpu_device *adev = smu->adev;
struct smu_power_context *smu_power = &smu->smu_power;
- size_t size = smu->adev->asic_type == CHIP_VANGOGH ?
+ size_t size = adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ?
sizeof(struct smu_11_5_power_context) :
sizeof(struct smu_11_0_power_context);
@@ -750,8 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
/* Navy_Flounder/Dimgrey_Cavefish do not support to change
* display num currently
*/
- if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
- adev->asic_type <= CHIP_BEIGE_GOBY)
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11) ||
+ adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ||
+ adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
return 0;
return smu_cmn_send_smc_msg_with_param(smu,
@@ -1136,15 +1140,15 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
int ret = 0;
struct amdgpu_device *adev = smu->adev;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_VANGOGH:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 5):
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
+ case IP_VERSION(11, 5, 0):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
if (enable)
@@ -1630,11 +1634,11 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
mutex_lock(&smu_baco->mutex);
if (state == SMU_BACO_STATE_ENTER) {
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
if (amdgpu_runtime_pm == 2)
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_EnterBaco,
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 25/66] drm/amdgpu/navi10_ppt: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (23 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 24/66] drm/amdgpu/smu11.0: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 26/66] drm/amdgpu/sienna_cichlid_ppt: " Alex Deucher
` (41 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 50 +++++++++----------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index ae11f5ed7a97..d96f904a765b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -345,7 +345,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
/* DPM UCLK enablement should be skipped for navi10 A0 secure board */
if (!(is_asic_secure(smu) &&
- (adev->asic_type == CHIP_NAVI10) &&
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
(adev->rev_id == 0)) &&
(adev->pm.pp_feature & PP_MCLK_DPM_MASK))
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
@@ -354,7 +354,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
/* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
if (is_asic_secure(smu) &&
- (adev->asic_type == CHIP_NAVI10) &&
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
(adev->rev_id == 0))
*(uint64_t *)feature_mask &=
~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
@@ -925,18 +925,18 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
return ret;
}
- switch (adev->asic_type) {
- case CHIP_NAVI12:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 9):
if (smu_version > 0x00341C00)
ret = navi12_get_smu_metrics_data(smu, member, value);
else
ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
break;
- case CHIP_NAVI10:
- case CHIP_NAVI14:
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 5):
default:
- if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
- ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
+ if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
+ ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
ret = navi10_get_smu_metrics_data(smu, member, value);
else
ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
@@ -1509,8 +1509,8 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
uint32_t sclk_freq;
pstate_table->gfxclk_pstate.min = gfx_table->min;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 0):
switch (adev->pdev->revision) {
case 0xf0: /* XTX */
case 0xc0:
@@ -1525,7 +1525,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
break;
}
break;
- case CHIP_NAVI14:
+ case IP_VERSION(11, 0, 5):
switch (adev->pdev->revision) {
case 0xc7: /* XT */
case 0xf4:
@@ -1548,7 +1548,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
break;
}
break;
- case CHIP_NAVI12:
+ case IP_VERSION(11, 0, 9):
sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
break;
default:
@@ -2562,8 +2562,8 @@ static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
return false;
- if (adev->asic_type == CHIP_NAVI10 ||
- adev->asic_type == CHIP_NAVI14)
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0) ||
+ adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5))
return true;
return false;
@@ -2671,8 +2671,8 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
* - PPSMC_MSG_SetDriverDummyTableDramAddrLow
* - PPSMC_MSG_GetUMCFWWA
*/
- if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) ||
- ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) {
+ if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
+ ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GET_UMC_FW_WA,
0,
@@ -2691,13 +2691,13 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
return 0;
if (umc_fw_disable_cdr) {
- if (adev->asic_type == CHIP_NAVI10)
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
return navi10_umc_hybrid_cdr_workaround(smu);
} else {
return navi10_set_dummy_pstates_table_location(smu);
}
} else {
- if (adev->asic_type == CHIP_NAVI10)
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
return navi10_umc_hybrid_cdr_workaround(smu);
}
@@ -3151,18 +3151,18 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
return ret;
}
- switch (adev->asic_type) {
- case CHIP_NAVI12:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 0, 9):
if (smu_version > 0x00341C00)
ret = navi12_get_gpu_metrics(smu, table);
else
ret = navi12_get_legacy_gpu_metrics(smu, table);
break;
- case CHIP_NAVI10:
- case CHIP_NAVI14:
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 5):
default:
- if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
- ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
+ if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
+ ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
ret = navi10_get_gpu_metrics(smu, table);
else
ret =navi10_get_legacy_gpu_metrics(smu, table);
@@ -3180,7 +3180,7 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
uint32_t param = 0;
/* Navi12 does not support this */
- if (adev->asic_type == CHIP_NAVI12)
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))
return 0;
/*
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 26/66] drm/amdgpu/sienna_cichlid_ppt: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (24 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 25/66] drm/amdgpu/navi10_ppt: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 27/66] drm/amdgpu: drive all navi asics from the IP discovery table Alex Deucher
` (40 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index ca57221e3962..6a0fed5e33d9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -74,7 +74,7 @@
#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
#define GET_PPTABLE_MEMBER(field, member) do {\
- if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
+ if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))\
(*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
else\
(*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
@@ -82,7 +82,7 @@
static int get_table_size(struct smu_context *smu)
{
- if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
+ if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
return sizeof(PPTable_beige_goby_t);
else
return sizeof(PPTable_t);
@@ -298,7 +298,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
}
if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
- (adev->asic_type > CHIP_SIENNA_CICHLID) &&
+ (adev->ip_versions[MP1_HWIP] > IP_VERSION(11, 0, 7)) &&
!(adev->flags & AMD_IS_APU))
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
@@ -496,7 +496,7 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s
uint32_t throttler_status = 0;
int i;
- if ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
+ if ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
(smu->smc_fw_version >= 0x3A4300)) {
for (i = 0; i < THROTTLER_COUNT; i++)
throttler_status |=
@@ -517,7 +517,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
&(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
SmuMetrics_V2_t *metrics_v2 =
&(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
- bool use_metrics_v2 = ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
+ bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
(smu->smc_fw_version >= 0x3A4300)) ? true : false;
uint16_t average_gfx_activity;
int ret = 0;
@@ -1170,7 +1170,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
* and onwards SMU firmwares.
*/
smu_cmn_get_smc_version(smu, NULL, &smu_version);
- if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+ if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
(smu_version < 0x003a2900))
break;
@@ -1937,7 +1937,7 @@ static void sienna_cichlid_dump_od_table(struct smu_context *smu,
od_table->UclkFmax);
smu_cmn_get_smc_version(smu, NULL, &smu_version);
- if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+ if (!((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
(smu_version < 0x003a2900)))
dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
}
@@ -2161,7 +2161,7 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
* and onwards SMU firmwares.
*/
smu_cmn_get_smc_version(smu, NULL, &smu_version);
- if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+ if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
(smu_version < 0x003a2900)) {
dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
"only by 58.41.0 and onwards SMU firmwares!\n");
@@ -2865,7 +2865,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
PPTable_t *pptable = table_context->driver_pptable;
int i;
- if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
+ if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)) {
beige_goby_dump_pptable(smu);
return;
}
@@ -3625,7 +3625,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
SmuMetrics_V2_t *metrics_v2 =
&(metrics_external.SmuMetrics_V2);
struct amdgpu_device *adev = smu->adev;
- bool use_metrics_v2 = ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+ bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
(smu->smc_fw_version >= 0x3A4300)) ? true : false;
uint16_t average_gfx_activity;
int ret = 0;
@@ -3706,8 +3706,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
- if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu->smc_fw_version > 0x003A1E00) ||
- ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu->smc_fw_version > 0x00410400)) {
+ if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
+ ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
} else {
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 27/66] drm/amdgpu: drive all navi asics from the IP discovery table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (25 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 26/66] drm/amdgpu/sienna_cichlid_ppt: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 28/66] drm/amdgpu/nv: convert to IP version checking Alex Deucher
` (39 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Rather than hardcoding based on asic_type, use the IP
discovery table to configure the driver.
v2: rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a4503e006fb3..2bf18bc30f69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2142,26 +2142,6 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
if (r)
return r;
break;
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
- if (adev->asic_type == CHIP_VANGOGH)
- adev->family = AMDGPU_FAMILY_VGH;
- else if (adev->asic_type == CHIP_YELLOW_CARP)
- adev->family = AMDGPU_FAMILY_YC;
- else
- adev->family = AMDGPU_FAMILY_NV;
-
- r = nv_set_ip_blocks(adev);
- if (r)
- return r;
- break;
default:
r = amdgpu_discovery_set_ip_blocks(adev);
if (r)
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 28/66] drm/amdgpu/nv: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (26 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 27/66] drm/amdgpu: drive all navi asics from the IP discovery table Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-22 7:31 ` Lazar, Lijo
2021-09-21 18:06 ` [PATCH 29/66] drm/amdgpu/display/dm: " Alex Deucher
` (38 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 75 +++++++++++++++++----------------
1 file changed, 38 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 0dc390a7509f..57be517d70bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -180,8 +180,8 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
const struct amdgpu_video_codecs **codecs)
{
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
+ switch (adev->ip_versions[UVD_HWIP]) {
+ case IP_VERSION(3, 0, 0):
if (amdgpu_sriov_vf(adev)) {
if (encode)
*codecs = &sriov_sc_video_codecs_encode;
@@ -194,29 +194,27 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
*codecs = &sc_video_codecs_decode;
}
return 0;
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_VANGOGH:
+ case IP_VERSION(3, 0, 16):
+ case IP_VERSION(3, 0, 2):
if (encode)
*codecs = &nv_video_codecs_encode;
else
*codecs = &sc_video_codecs_decode;
return 0;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(3, 1, 1):
if (encode)
*codecs = &nv_video_codecs_encode;
else
*codecs = &yc_video_codecs_decode;
return 0;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(3, 0, 33):
if (encode)
*codecs = &bg_video_codecs_encode;
else
*codecs = &bg_video_codecs_decode;
return 0;
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 0, 2):
if (encode)
*codecs = &nv_video_codecs_encode;
else
@@ -511,14 +509,15 @@ nv_asic_reset_method(struct amdgpu_device *adev)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
amdgpu_reset_method);
- switch (adev->asic_type) {
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(11, 5, 0):
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
return AMD_RESET_METHOD_MODE2;
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
return AMD_RESET_METHOD_MODE1;
default:
if (amdgpu_dpm_is_baco_supported(adev))
@@ -1042,8 +1041,11 @@ static int nv_common_early_init(void *handle)
adev->rev_id = nv_get_rev_id(adev);
adev->external_rev_id = 0xff;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
+ /* TODO: split the GC and PG flags based on the relevant IP version for which
+ * they are relevant.
+ */
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(10, 1, 10):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_IH_CG |
@@ -1065,7 +1067,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_ATHUB;
adev->external_rev_id = adev->rev_id + 0x1;
break;
- case CHIP_NAVI14:
+ case IP_VERSION(10, 1, 1):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_IH_CG |
@@ -1086,7 +1088,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_VCN_DPG;
adev->external_rev_id = adev->rev_id + 20;
break;
- case CHIP_NAVI12:
+ case IP_VERSION(10, 1, 2):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CGCG |
@@ -1115,7 +1117,7 @@ static int nv_common_early_init(void *handle)
adev->rev_id = 0;
adev->external_rev_id = adev->rev_id + 0xa;
break;
- case CHIP_SIENNA_CICHLID:
+ case IP_VERSION(10, 3, 0):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
@@ -1139,7 +1141,7 @@ static int nv_common_early_init(void *handle)
}
adev->external_rev_id = adev->rev_id + 0x28;
break;
- case CHIP_NAVY_FLOUNDER:
+ case IP_VERSION(10, 3, 2):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
@@ -1158,8 +1160,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x32;
break;
-
- case CHIP_VANGOGH:
+ case IP_VERSION(10, 3, 1):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CP_LS |
@@ -1182,7 +1183,7 @@ static int nv_common_early_init(void *handle)
if (adev->apu_flags & AMD_APU_IS_VANGOGH)
adev->external_rev_id = adev->rev_id + 0x01;
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(10, 3, 4):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
@@ -1201,7 +1202,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x3c;
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(10, 3, 5):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
@@ -1218,7 +1219,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x46;
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(10, 3, 3):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CGCG |
@@ -1247,7 +1248,7 @@ static int nv_common_early_init(void *handle)
else
adev->external_rev_id = adev->rev_id + 0x01;
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(10, 1, 3):
adev->cg_flags = 0;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x82;
@@ -1374,14 +1375,14 @@ static int nv_common_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ switch (adev->ip_versions[NBIO_HWIP]) {
+ case IP_VERSION(2, 3, 0):
+ case IP_VERSION(2, 3, 1):
+ case IP_VERSION(2, 3, 2):
+ case IP_VERSION(3, 3, 0):
+ case IP_VERSION(3, 3, 1):
+ case IP_VERSION(3, 3, 2):
+ case IP_VERSION(3, 3, 3):
adev->nbio.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
adev->nbio.funcs->update_medium_grain_light_sleep(adev,
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 28/66] drm/amdgpu/nv: convert to IP version checking
2021-09-21 18:06 ` [PATCH 28/66] drm/amdgpu/nv: convert to IP version checking Alex Deucher
@ 2021-09-22 7:31 ` Lazar, Lijo
2021-09-22 15:21 ` Alex Deucher
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 7:31 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 75 +++++++++++++++++----------------
> 1 file changed, 38 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 0dc390a7509f..57be517d70bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -180,8 +180,8 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
> static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
> const struct amdgpu_video_codecs **codecs)
> {
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> + switch (adev->ip_versions[UVD_HWIP]) {
> + case IP_VERSION(3, 0, 0):
> if (amdgpu_sriov_vf(adev)) {
> if (encode)
> *codecs = &sriov_sc_video_codecs_encode;
> @@ -194,29 +194,27 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
> *codecs = &sc_video_codecs_decode;
> }
> return 0;
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_VANGOGH:
> + case IP_VERSION(3, 0, 16):
> + case IP_VERSION(3, 0, 2):
> if (encode)
> *codecs = &nv_video_codecs_encode;
> else
> *codecs = &sc_video_codecs_decode;
> return 0;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(3, 1, 1):
> if (encode)
> *codecs = &nv_video_codecs_encode;
> else
> *codecs = &yc_video_codecs_decode;
> return 0;
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(3, 0, 33):
> if (encode)
> *codecs = &bg_video_codecs_encode;
> else
> *codecs = &bg_video_codecs_decode;
> return 0;
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_NAVI12:
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 0, 2):
> if (encode)
> *codecs = &nv_video_codecs_encode;
> else
> @@ -511,14 +509,15 @@ nv_asic_reset_method(struct amdgpu_device *adev)
> dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
> amdgpu_reset_method);
>
> - switch (adev->asic_type) {
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
> + switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(11, 5, 0):
> + case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 3):
Odd. Two cases replaced by 3 - are there two versions for YC?
Thanks,
Lijo
> return AMD_RESET_METHOD_MODE2;
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(11, 0, 7):
> + case IP_VERSION(11, 0, 11):
> + case IP_VERSION(11, 0, 12):
> + case IP_VERSION(11, 0, 13):
> return AMD_RESET_METHOD_MODE1;
> default:
> if (amdgpu_dpm_is_baco_supported(adev))
> @@ -1042,8 +1041,11 @@ static int nv_common_early_init(void *handle)
>
> adev->rev_id = nv_get_rev_id(adev);
> adev->external_rev_id = 0xff;
> - switch (adev->asic_type) {
> - case CHIP_NAVI10:
> + /* TODO: split the GC and PG flags based on the relevant IP version for which
> + * they are relevant.
> + */
> + switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(10, 1, 10):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_CGCG |
> AMD_CG_SUPPORT_IH_CG |
> @@ -1065,7 +1067,7 @@ static int nv_common_early_init(void *handle)
> AMD_PG_SUPPORT_ATHUB;
> adev->external_rev_id = adev->rev_id + 0x1;
> break;
> - case CHIP_NAVI14:
> + case IP_VERSION(10, 1, 1):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_CGCG |
> AMD_CG_SUPPORT_IH_CG |
> @@ -1086,7 +1088,7 @@ static int nv_common_early_init(void *handle)
> AMD_PG_SUPPORT_VCN_DPG;
> adev->external_rev_id = adev->rev_id + 20;
> break;
> - case CHIP_NAVI12:
> + case IP_VERSION(10, 1, 2):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_MGLS |
> AMD_CG_SUPPORT_GFX_CGCG |
> @@ -1115,7 +1117,7 @@ static int nv_common_early_init(void *handle)
> adev->rev_id = 0;
> adev->external_rev_id = adev->rev_id + 0xa;
> break;
> - case CHIP_SIENNA_CICHLID:
> + case IP_VERSION(10, 3, 0):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_CGCG |
> AMD_CG_SUPPORT_GFX_CGLS |
> @@ -1139,7 +1141,7 @@ static int nv_common_early_init(void *handle)
> }
> adev->external_rev_id = adev->rev_id + 0x28;
> break;
> - case CHIP_NAVY_FLOUNDER:
> + case IP_VERSION(10, 3, 2):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_CGCG |
> AMD_CG_SUPPORT_GFX_CGLS |
> @@ -1158,8 +1160,7 @@ static int nv_common_early_init(void *handle)
> AMD_PG_SUPPORT_MMHUB;
> adev->external_rev_id = adev->rev_id + 0x32;
> break;
> -
> - case CHIP_VANGOGH:
> + case IP_VERSION(10, 3, 1):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_MGLS |
> AMD_CG_SUPPORT_GFX_CP_LS |
> @@ -1182,7 +1183,7 @@ static int nv_common_early_init(void *handle)
> if (adev->apu_flags & AMD_APU_IS_VANGOGH)
> adev->external_rev_id = adev->rev_id + 0x01;
> break;
> - case CHIP_DIMGREY_CAVEFISH:
> + case IP_VERSION(10, 3, 4):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_CGCG |
> AMD_CG_SUPPORT_GFX_CGLS |
> @@ -1201,7 +1202,7 @@ static int nv_common_early_init(void *handle)
> AMD_PG_SUPPORT_MMHUB;
> adev->external_rev_id = adev->rev_id + 0x3c;
> break;
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(10, 3, 5):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_CGCG |
> AMD_CG_SUPPORT_GFX_CGLS |
> @@ -1218,7 +1219,7 @@ static int nv_common_early_init(void *handle)
> AMD_PG_SUPPORT_MMHUB;
> adev->external_rev_id = adev->rev_id + 0x46;
> break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(10, 3, 3):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_MGLS |
> AMD_CG_SUPPORT_GFX_CGCG |
> @@ -1247,7 +1248,7 @@ static int nv_common_early_init(void *handle)
> else
> adev->external_rev_id = adev->rev_id + 0x01;
> break;
> - case CHIP_CYAN_SKILLFISH:
> + case IP_VERSION(10, 1, 3):
> adev->cg_flags = 0;
> adev->pg_flags = 0;
> adev->external_rev_id = adev->rev_id + 0x82;
> @@ -1374,14 +1375,14 @@ static int nv_common_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->asic_type) {
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_NAVI12:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> + switch (adev->ip_versions[NBIO_HWIP]) {
> + case IP_VERSION(2, 3, 0):
> + case IP_VERSION(2, 3, 1):
> + case IP_VERSION(2, 3, 2):
> + case IP_VERSION(3, 3, 0):
> + case IP_VERSION(3, 3, 1):
> + case IP_VERSION(3, 3, 2):
> + case IP_VERSION(3, 3, 3):
> adev->nbio.funcs->update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> adev->nbio.funcs->update_medium_grain_light_sleep(adev,
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 28/66] drm/amdgpu/nv: convert to IP version checking
2021-09-22 7:31 ` Lazar, Lijo
@ 2021-09-22 15:21 ` Alex Deucher
0 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-22 15:21 UTC (permalink / raw)
To: Lazar, Lijo; +Cc: Alex Deucher, amd-gfx list
On Wed, Sep 22, 2021 at 3:32 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 9/21/2021 11:36 PM, Alex Deucher wrote:
> > Use IP versions rather than asic_type to differentiate
> > IP version specific features.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/nv.c | 75 +++++++++++++++++----------------
> > 1 file changed, 38 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> > index 0dc390a7509f..57be517d70bf 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -180,8 +180,8 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
> > static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
> > const struct amdgpu_video_codecs **codecs)
> > {
> > - switch (adev->asic_type) {
> > - case CHIP_SIENNA_CICHLID:
> > + switch (adev->ip_versions[UVD_HWIP]) {
> > + case IP_VERSION(3, 0, 0):
> > if (amdgpu_sriov_vf(adev)) {
> > if (encode)
> > *codecs = &sriov_sc_video_codecs_encode;
> > @@ -194,29 +194,27 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
> > *codecs = &sc_video_codecs_decode;
> > }
> > return 0;
> > - case CHIP_NAVY_FLOUNDER:
> > - case CHIP_DIMGREY_CAVEFISH:
> > - case CHIP_VANGOGH:
> > + case IP_VERSION(3, 0, 16):
> > + case IP_VERSION(3, 0, 2):
> > if (encode)
> > *codecs = &nv_video_codecs_encode;
> > else
> > *codecs = &sc_video_codecs_decode;
> > return 0;
> > - case CHIP_YELLOW_CARP:
> > + case IP_VERSION(3, 1, 1):
> > if (encode)
> > *codecs = &nv_video_codecs_encode;
> > else
> > *codecs = &yc_video_codecs_decode;
> > return 0;
> > - case CHIP_BEIGE_GOBY:
> > + case IP_VERSION(3, 0, 33):
> > if (encode)
> > *codecs = &bg_video_codecs_encode;
> > else
> > *codecs = &bg_video_codecs_decode;
> > return 0;
> > - case CHIP_NAVI10:
> > - case CHIP_NAVI14:
> > - case CHIP_NAVI12:
> > + case IP_VERSION(2, 0, 0):
> > + case IP_VERSION(2, 0, 2):
> > if (encode)
> > *codecs = &nv_video_codecs_encode;
> > else
> > @@ -511,14 +509,15 @@ nv_asic_reset_method(struct amdgpu_device *adev)
> > dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
> > amdgpu_reset_method);
> >
> > - switch (adev->asic_type) {
> > - case CHIP_VANGOGH:
> > - case CHIP_YELLOW_CARP:
> > + switch (adev->ip_versions[MP1_HWIP]) {
> > + case IP_VERSION(11, 5, 0):
> > + case IP_VERSION(13, 0, 1):
> > + case IP_VERSION(13, 0, 3):
>
> Odd. Two cases replaced by 3 - are there two versions for YC?
The versions of some IPs changed with newer silicon spins.
Alex
>
> Thanks,
> Lijo
>
> > return AMD_RESET_METHOD_MODE2;
> > - case CHIP_SIENNA_CICHLID:
> > - case CHIP_NAVY_FLOUNDER:
> > - case CHIP_DIMGREY_CAVEFISH:
> > - case CHIP_BEIGE_GOBY:
> > + case IP_VERSION(11, 0, 7):
> > + case IP_VERSION(11, 0, 11):
> > + case IP_VERSION(11, 0, 12):
> > + case IP_VERSION(11, 0, 13):
> > return AMD_RESET_METHOD_MODE1;
> > default:
> > if (amdgpu_dpm_is_baco_supported(adev))
> > @@ -1042,8 +1041,11 @@ static int nv_common_early_init(void *handle)
> >
> > adev->rev_id = nv_get_rev_id(adev);
> > adev->external_rev_id = 0xff;
> > - switch (adev->asic_type) {
> > - case CHIP_NAVI10:
> > + /* TODO: split the GC and PG flags based on the relevant IP version for which
> > + * they are relevant.
> > + */
> > + switch (adev->ip_versions[GC_HWIP]) {
> > + case IP_VERSION(10, 1, 10):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > AMD_CG_SUPPORT_IH_CG |
> > @@ -1065,7 +1067,7 @@ static int nv_common_early_init(void *handle)
> > AMD_PG_SUPPORT_ATHUB;
> > adev->external_rev_id = adev->rev_id + 0x1;
> > break;
> > - case CHIP_NAVI14:
> > + case IP_VERSION(10, 1, 1):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > AMD_CG_SUPPORT_IH_CG |
> > @@ -1086,7 +1088,7 @@ static int nv_common_early_init(void *handle)
> > AMD_PG_SUPPORT_VCN_DPG;
> > adev->external_rev_id = adev->rev_id + 20;
> > break;
> > - case CHIP_NAVI12:
> > + case IP_VERSION(10, 1, 2):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_MGLS |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > @@ -1115,7 +1117,7 @@ static int nv_common_early_init(void *handle)
> > adev->rev_id = 0;
> > adev->external_rev_id = adev->rev_id + 0xa;
> > break;
> > - case CHIP_SIENNA_CICHLID:
> > + case IP_VERSION(10, 3, 0):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > AMD_CG_SUPPORT_GFX_CGLS |
> > @@ -1139,7 +1141,7 @@ static int nv_common_early_init(void *handle)
> > }
> > adev->external_rev_id = adev->rev_id + 0x28;
> > break;
> > - case CHIP_NAVY_FLOUNDER:
> > + case IP_VERSION(10, 3, 2):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > AMD_CG_SUPPORT_GFX_CGLS |
> > @@ -1158,8 +1160,7 @@ static int nv_common_early_init(void *handle)
> > AMD_PG_SUPPORT_MMHUB;
> > adev->external_rev_id = adev->rev_id + 0x32;
> > break;
> > -
> > - case CHIP_VANGOGH:
> > + case IP_VERSION(10, 3, 1):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_MGLS |
> > AMD_CG_SUPPORT_GFX_CP_LS |
> > @@ -1182,7 +1183,7 @@ static int nv_common_early_init(void *handle)
> > if (adev->apu_flags & AMD_APU_IS_VANGOGH)
> > adev->external_rev_id = adev->rev_id + 0x01;
> > break;
> > - case CHIP_DIMGREY_CAVEFISH:
> > + case IP_VERSION(10, 3, 4):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > AMD_CG_SUPPORT_GFX_CGLS |
> > @@ -1201,7 +1202,7 @@ static int nv_common_early_init(void *handle)
> > AMD_PG_SUPPORT_MMHUB;
> > adev->external_rev_id = adev->rev_id + 0x3c;
> > break;
> > - case CHIP_BEIGE_GOBY:
> > + case IP_VERSION(10, 3, 5):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > AMD_CG_SUPPORT_GFX_CGLS |
> > @@ -1218,7 +1219,7 @@ static int nv_common_early_init(void *handle)
> > AMD_PG_SUPPORT_MMHUB;
> > adev->external_rev_id = adev->rev_id + 0x46;
> > break;
> > - case CHIP_YELLOW_CARP:
> > + case IP_VERSION(10, 3, 3):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_MGLS |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > @@ -1247,7 +1248,7 @@ static int nv_common_early_init(void *handle)
> > else
> > adev->external_rev_id = adev->rev_id + 0x01;
> > break;
> > - case CHIP_CYAN_SKILLFISH:
> > + case IP_VERSION(10, 1, 3):
> > adev->cg_flags = 0;
> > adev->pg_flags = 0;
> > adev->external_rev_id = adev->rev_id + 0x82;
> > @@ -1374,14 +1375,14 @@ static int nv_common_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->asic_type) {
> > - case CHIP_NAVI10:
> > - case CHIP_NAVI14:
> > - case CHIP_NAVI12:
> > - case CHIP_SIENNA_CICHLID:
> > - case CHIP_NAVY_FLOUNDER:
> > - case CHIP_DIMGREY_CAVEFISH:
> > - case CHIP_BEIGE_GOBY:
> > + switch (adev->ip_versions[NBIO_HWIP]) {
> > + case IP_VERSION(2, 3, 0):
> > + case IP_VERSION(2, 3, 1):
> > + case IP_VERSION(2, 3, 2):
> > + case IP_VERSION(3, 3, 0):
> > + case IP_VERSION(3, 3, 1):
> > + case IP_VERSION(3, 3, 2):
> > + case IP_VERSION(3, 3, 3):
> > adev->nbio.funcs->update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > adev->nbio.funcs->update_medium_grain_light_sleep(adev,
> >
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 29/66] drm/amdgpu/display/dm: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (27 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 28/66] drm/amdgpu/nv: convert to IP version checking Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-22 7:37 ` Lazar, Lijo
2021-09-21 18:06 ` [PATCH 30/66] drm/amdgpu: add DCI HWIP Alex Deucher
` (37 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 194 ++++++++++--------
1 file changed, 109 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 07adac1a8c42..e189d72f08e9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1342,16 +1342,23 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_RAVEN:
- case CHIP_RENOIR:
- init_data.flags.gpu_vm_support = true;
- if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
- init_data.flags.disable_dmcu = true;
- break;
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
init_data.flags.gpu_vm_support = true;
break;
default:
+ switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(2, 1, 0):
+ init_data.flags.gpu_vm_support = true;
+ if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
+ init_data.flags.disable_dmcu = true;
+ break;
+ case IP_VERSION(3, 0, 1):
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ init_data.flags.gpu_vm_support = true;
+ break;
+ default:
+ break;
+ }
break;
}
@@ -1442,7 +1449,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
#endif
#ifdef CONFIG_DRM_AMD_DC_HDCP
- if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
+ if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
if (!adev->dm.hdcp_workqueue)
@@ -1637,15 +1644,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_RENOIR:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
return 0;
case CHIP_NAVI12:
fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1659,6 +1657,20 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
return 0;
break;
default:
+ switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 3):
+ case IP_VERSION(3, 0, 1):
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ return 0;
+ default:
+ break;
+ }
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
return -EINVAL;
}
@@ -1737,34 +1749,36 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
enum dmub_status status;
int r;
- switch (adev->asic_type) {
- case CHIP_RENOIR:
+ switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(2, 1, 0):
dmub_asic = DMUB_ASIC_DCN21;
fw_name_dmub = FIRMWARE_RENOIR_DMUB;
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
break;
- case CHIP_SIENNA_CICHLID:
- dmub_asic = DMUB_ASIC_DCN30;
- fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
- break;
- case CHIP_NAVY_FLOUNDER:
- dmub_asic = DMUB_ASIC_DCN30;
- fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
+ case IP_VERSION(3, 0, 0):
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
+ dmub_asic = DMUB_ASIC_DCN30;
+ fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
+ } else {
+ dmub_asic = DMUB_ASIC_DCN30;
+ fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
+ }
break;
- case CHIP_VANGOGH:
+ case IP_VERSION(3, 0, 1):
dmub_asic = DMUB_ASIC_DCN301;
fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(3, 0, 2):
dmub_asic = DMUB_ASIC_DCN302;
fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(3, 0, 3):
dmub_asic = DMUB_ASIC_DCN303;
fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
dmub_asic = DMUB_ASIC_DCN31;
fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
break;
@@ -2063,10 +2077,9 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
* therefore, this function apply to navi10/12/14 but not Renoir
* *
*/
- switch(adev->asic_type) {
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
+ switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 0, 0):
break;
default:
return 0;
@@ -3287,7 +3300,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
int i;
unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
- if (adev->asic_type >= CHIP_VEGA10)
+ if (adev->family >= AMDGPU_FAMILY_AI)
client_id = SOC15_IH_CLIENTID_DCE;
int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -4072,18 +4085,19 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Use Outbox interrupt */
- switch (adev->asic_type) {
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_YELLOW_CARP:
- case CHIP_RENOIR:
+ switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ case IP_VERSION(2, 1, 0):
if (register_outbox_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
}
break;
default:
- DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", adev->asic_type);
+ DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
+ adev->ip_versions[DCE_HWIP]);
}
#endif
@@ -4171,16 +4185,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break;
#if defined(CONFIG_DRM_AMD_DC_DCN)
case CHIP_RAVEN:
- case CHIP_NAVI12:
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_RENOIR:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_VANGOGH:
- case CHIP_YELLOW_CARP:
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
@@ -4188,6 +4192,26 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break;
#endif
default:
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 3):
+ case IP_VERSION(3, 0, 1):
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ if (dcn10_register_irq_handlers(dm->adev)) {
+ DRM_ERROR("DM: Failed to initialize IRQ\n");
+ goto fail;
+ }
+ break;
+ default:
+ break;
+ }
+#endif
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
goto fail;
}
@@ -4338,38 +4362,43 @@ static int dm_early_init(void *handle)
break;
#if defined(CONFIG_DRM_AMD_DC_DCN)
case CHIP_RAVEN:
- case CHIP_RENOIR:
- case CHIP_VANGOGH:
- adev->mode_info.num_crtc = 4;
- adev->mode_info.num_hpd = 4;
- adev->mode_info.num_dig = 4;
- break;
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- adev->mode_info.num_crtc = 6;
- adev->mode_info.num_hpd = 6;
- adev->mode_info.num_dig = 6;
- break;
- case CHIP_YELLOW_CARP:
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
break;
- case CHIP_NAVI14:
- case CHIP_DIMGREY_CAVEFISH:
- adev->mode_info.num_crtc = 5;
- adev->mode_info.num_hpd = 5;
- adev->mode_info.num_dig = 5;
- break;
- case CHIP_BEIGE_GOBY:
- adev->mode_info.num_crtc = 2;
- adev->mode_info.num_hpd = 2;
- adev->mode_info.num_dig = 2;
- break;
#endif
default:
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(3, 0, 0):
+ adev->mode_info.num_crtc = 6;
+ adev->mode_info.num_hpd = 6;
+ adev->mode_info.num_dig = 6;
+ break;
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(3, 0, 2):
+ adev->mode_info.num_crtc = 5;
+ adev->mode_info.num_hpd = 5;
+ adev->mode_info.num_dig = 5;
+ break;
+ case IP_VERSION(3, 0, 3):
+ adev->mode_info.num_crtc = 2;
+ adev->mode_info.num_hpd = 2;
+ adev->mode_info.num_dig = 2;
+ break;
+ case IP_VERSION(3, 0, 1):
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ adev->mode_info.num_crtc = 4;
+ adev->mode_info.num_hpd = 4;
+ adev->mode_info.num_dig = 4;
+ break;
+ default:
+ break;
+ }
+#endif
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
return -EINVAL;
}
@@ -4590,12 +4619,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
tiling_info->gfx9.num_rb_per_se =
adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
tiling_info->gfx9.shaderEnable = 1;
- if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER ||
- adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
- adev->asic_type == CHIP_BEIGE_GOBY ||
- adev->asic_type == CHIP_YELLOW_CARP ||
- adev->asic_type == CHIP_VANGOGH)
+ if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
}
@@ -5036,7 +5060,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
case AMDGPU_FAMILY_NV:
case AMDGPU_FAMILY_VGH:
case AMDGPU_FAMILY_YC:
- if (adev->asic_type >= CHIP_SIENNA_CICHLID)
+ if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
add_gfx10_3_modifiers(adev, mods, &size, &capacity);
else
add_gfx10_1_modifiers(adev, mods, &size, &capacity);
@@ -7647,7 +7671,7 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
- if (dm->adev->asic_type >= CHIP_BONAIRE &&
+ if (dm->adev->family >= AMDGPU_FAMILY_CI &&
plane->type != DRM_PLANE_TYPE_CURSOR)
drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
supported_rotations);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 29/66] drm/amdgpu/display/dm: convert to IP version checking
2021-09-21 18:06 ` [PATCH 29/66] drm/amdgpu/display/dm: " Alex Deucher
@ 2021-09-22 7:37 ` Lazar, Lijo
2021-09-22 15:53 ` Deucher, Alexander
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 7:37 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 194 ++++++++++--------
> 1 file changed, 109 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 07adac1a8c42..e189d72f08e9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1342,16 +1342,23 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> case CHIP_CARRIZO:
> case CHIP_STONEY:
> case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - init_data.flags.gpu_vm_support = true;
> - if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> - init_data.flags.disable_dmcu = true;
> - break;
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
> init_data.flags.gpu_vm_support = true;
> break;
> default:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 1, 0):
> + init_data.flags.gpu_vm_support = true;
> + if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> + init_data.flags.disable_dmcu = true;
> + break;
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + init_data.flags.gpu_vm_support = true;
> + break;
> + default:
> + break;
> + }
> break;
> }
>
> @@ -1442,7 +1449,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> #endif
>
> #ifdef CONFIG_DRM_AMD_DC_HDCP
> - if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
> + if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
> adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
>
> if (!adev->dm.hdcp_workqueue)
> @@ -1637,15 +1644,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
> case CHIP_VEGA10:
> case CHIP_VEGA12:
> case CHIP_VEGA20:
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_RENOIR:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
> return 0;
> case CHIP_NAVI12:
> fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
> @@ -1659,6 +1657,20 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
> return 0;
> break;
> default:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 0, 2):
> + case IP_VERSION(3, 0, 3):
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + return 0;
> + default:
> + break;
> + }
> DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
> return -EINVAL;
> }
> @@ -1737,34 +1749,36 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
> enum dmub_status status;
> int r;
>
> - switch (adev->asic_type) {
> - case CHIP_RENOIR:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 1, 0):
> dmub_asic = DMUB_ASIC_DCN21;
> fw_name_dmub = FIRMWARE_RENOIR_DMUB;
> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
> break;
> - case CHIP_SIENNA_CICHLID:
> - dmub_asic = DMUB_ASIC_DCN30;
> - fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
> - break;
> - case CHIP_NAVY_FLOUNDER:
> - dmub_asic = DMUB_ASIC_DCN30;
> - fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
> + case IP_VERSION(3, 0, 0):
> + if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
> + dmub_asic = DMUB_ASIC_DCN30;
> + fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
> + } else {
> + dmub_asic = DMUB_ASIC_DCN30;
> + fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
> + }
> break;
> - case CHIP_VANGOGH:
> + case IP_VERSION(3, 0, 1):
> dmub_asic = DMUB_ASIC_DCN301;
> fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
> break;
> - case CHIP_DIMGREY_CAVEFISH:
> + case IP_VERSION(3, 0, 2):
> dmub_asic = DMUB_ASIC_DCN302;
> fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
> break;
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(3, 0, 3):
> dmub_asic = DMUB_ASIC_DCN303;
> fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
> break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> dmub_asic = DMUB_ASIC_DCN31;
> fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
> break;
> @@ -2063,10 +2077,9 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
> * therefore, this function apply to navi10/12/14 but not Renoir
> * *
> */
> - switch(adev->asic_type) {
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_NAVI12:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 0, 0):
> break;
> default:
> return 0;
> @@ -3287,7 +3300,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
> int i;
> unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
>
> - if (adev->asic_type >= CHIP_VEGA10)
> + if (adev->family >= AMDGPU_FAMILY_AI)
> client_id = SOC15_IH_CLIENTID_DCE;
>
> int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
> @@ -4072,18 +4085,19 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> /* Use Outbox interrupt */
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_YELLOW_CARP:
> - case CHIP_RENOIR:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + case IP_VERSION(2, 1, 0):
> if (register_outbox_irq_handlers(dm->adev)) {
> DRM_ERROR("DM: Failed to initialize IRQ\n");
> goto fail;
> }
> break;
> default:
> - DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", adev->asic_type);
> + DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
> + adev->ip_versions[DCE_HWIP]);
> }
> #endif
>
> @@ -4171,16 +4185,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> break;
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> case CHIP_RAVEN:
> - case CHIP_NAVI12:
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_RENOIR:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
> if (dcn10_register_irq_handlers(dm->adev)) {
> DRM_ERROR("DM: Failed to initialize IRQ\n");
> goto fail;
> @@ -4188,6 +4192,26 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> break;
> #endif
> default:
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 0, 2):
> + case IP_VERSION(3, 0, 3):
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + if (dcn10_register_irq_handlers(dm->adev)) {
> + DRM_ERROR("DM: Failed to initialize IRQ\n");
> + goto fail;
> + }
> + break;
> + default:
> + break;
> + }
> +#endif
> DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
> goto fail;
> }
> @@ -4338,38 +4362,43 @@ static int dm_early_init(void *handle)
> break;
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_VANGOGH:
> - adev->mode_info.num_crtc = 4;
> - adev->mode_info.num_hpd = 4;
> - adev->mode_info.num_dig = 4;
> - break;
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - adev->mode_info.num_crtc = 6;
> - adev->mode_info.num_hpd = 6;
> - adev->mode_info.num_dig = 6;
> - break;
> - case CHIP_YELLOW_CARP:
> adev->mode_info.num_crtc = 4;
> adev->mode_info.num_hpd = 4;
> adev->mode_info.num_dig = 4;
> break;
> - case CHIP_NAVI14:
> - case CHIP_DIMGREY_CAVEFISH:
> - adev->mode_info.num_crtc = 5;
> - adev->mode_info.num_hpd = 5;
> - adev->mode_info.num_dig = 5;
> - break;
> - case CHIP_BEIGE_GOBY:
> - adev->mode_info.num_crtc = 2;
> - adev->mode_info.num_hpd = 2;
> - adev->mode_info.num_dig = 2;
> - break;
> #endif
> default:
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(3, 0, 0):
> + adev->mode_info.num_crtc = 6;
> + adev->mode_info.num_hpd = 6;
> + adev->mode_info.num_dig = 6;
> + break;
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(3, 0, 2):
> + adev->mode_info.num_crtc = 5;
> + adev->mode_info.num_hpd = 5;
> + adev->mode_info.num_dig = 5;
> + break;
> + case IP_VERSION(3, 0, 3):
> + adev->mode_info.num_crtc = 2;
> + adev->mode_info.num_hpd = 2;
> + adev->mode_info.num_dig = 2;
> + break;
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + adev->mode_info.num_crtc = 4;
> + adev->mode_info.num_hpd = 4;
> + adev->mode_info.num_dig = 4;
> + break;
> + default:
> + break;
> + }
> +#endif
> DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
> return -EINVAL;
> }
> @@ -4590,12 +4619,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
> tiling_info->gfx9.num_rb_per_se =
> adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
> tiling_info->gfx9.shaderEnable = 1;
> - if (adev->asic_type == CHIP_SIENNA_CICHLID ||
> - adev->asic_type == CHIP_NAVY_FLOUNDER ||
> - adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
> - adev->asic_type == CHIP_BEIGE_GOBY ||
> - adev->asic_type == CHIP_YELLOW_CARP ||
> - adev->asic_type == CHIP_VANGOGH)
> + if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
> }
>
> @@ -5036,7 +5060,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
> case AMDGPU_FAMILY_NV:
> case AMDGPU_FAMILY_VGH:
> case AMDGPU_FAMILY_YC:
> - if (adev->asic_type >= CHIP_SIENNA_CICHLID)
> + if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> add_gfx10_3_modifiers(adev, mods, &size, &capacity);
> else
> add_gfx10_1_modifiers(adev, mods, &size, &capacity);
> @@ -7647,7 +7671,7 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
> DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
> DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
>
> - if (dm->adev->asic_type >= CHIP_BONAIRE &&
> + if (dm->adev->family >= AMDGPU_FAMILY_CI &&
This doesn't look related.
Thanks,
Lijo
> plane->type != DRM_PLANE_TYPE_CURSOR)
> drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
> supported_rotations);
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 29/66] drm/amdgpu/display/dm: convert to IP version checking
2021-09-22 7:37 ` Lazar, Lijo
@ 2021-09-22 15:53 ` Deucher, Alexander
0 siblings, 0 replies; 106+ messages in thread
From: Deucher, Alexander @ 2021-09-22 15:53 UTC (permalink / raw)
To: Lazar, Lijo, amd-gfx
[-- Attachment #1: Type: text/plain, Size: 14521 bytes --]
[AMD Official Use Only]
Fixed locally.
Alex
________________________________
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Wednesday, September 22, 2021 3:37 AM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 29/66] drm/amdgpu/display/dm: convert to IP version checking
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 194 ++++++++++--------
> 1 file changed, 109 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 07adac1a8c42..e189d72f08e9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1342,16 +1342,23 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> case CHIP_CARRIZO:
> case CHIP_STONEY:
> case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - init_data.flags.gpu_vm_support = true;
> - if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> - init_data.flags.disable_dmcu = true;
> - break;
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
> init_data.flags.gpu_vm_support = true;
> break;
> default:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 1, 0):
> + init_data.flags.gpu_vm_support = true;
> + if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> + init_data.flags.disable_dmcu = true;
> + break;
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + init_data.flags.gpu_vm_support = true;
> + break;
> + default:
> + break;
> + }
> break;
> }
>
> @@ -1442,7 +1449,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> #endif
>
> #ifdef CONFIG_DRM_AMD_DC_HDCP
> - if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
> + if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
> adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
>
> if (!adev->dm.hdcp_workqueue)
> @@ -1637,15 +1644,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
> case CHIP_VEGA10:
> case CHIP_VEGA12:
> case CHIP_VEGA20:
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_RENOIR:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
> return 0;
> case CHIP_NAVI12:
> fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
> @@ -1659,6 +1657,20 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
> return 0;
> break;
> default:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 0, 2):
> + case IP_VERSION(3, 0, 3):
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + return 0;
> + default:
> + break;
> + }
> DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
> return -EINVAL;
> }
> @@ -1737,34 +1749,36 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
> enum dmub_status status;
> int r;
>
> - switch (adev->asic_type) {
> - case CHIP_RENOIR:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 1, 0):
> dmub_asic = DMUB_ASIC_DCN21;
> fw_name_dmub = FIRMWARE_RENOIR_DMUB;
> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
> break;
> - case CHIP_SIENNA_CICHLID:
> - dmub_asic = DMUB_ASIC_DCN30;
> - fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
> - break;
> - case CHIP_NAVY_FLOUNDER:
> - dmub_asic = DMUB_ASIC_DCN30;
> - fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
> + case IP_VERSION(3, 0, 0):
> + if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
> + dmub_asic = DMUB_ASIC_DCN30;
> + fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
> + } else {
> + dmub_asic = DMUB_ASIC_DCN30;
> + fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
> + }
> break;
> - case CHIP_VANGOGH:
> + case IP_VERSION(3, 0, 1):
> dmub_asic = DMUB_ASIC_DCN301;
> fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
> break;
> - case CHIP_DIMGREY_CAVEFISH:
> + case IP_VERSION(3, 0, 2):
> dmub_asic = DMUB_ASIC_DCN302;
> fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
> break;
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(3, 0, 3):
> dmub_asic = DMUB_ASIC_DCN303;
> fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
> break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> dmub_asic = DMUB_ASIC_DCN31;
> fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
> break;
> @@ -2063,10 +2077,9 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
> * therefore, this function apply to navi10/12/14 but not Renoir
> * *
> */
> - switch(adev->asic_type) {
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_NAVI12:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 0, 0):
> break;
> default:
> return 0;
> @@ -3287,7 +3300,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
> int i;
> unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
>
> - if (adev->asic_type >= CHIP_VEGA10)
> + if (adev->family >= AMDGPU_FAMILY_AI)
> client_id = SOC15_IH_CLIENTID_DCE;
>
> int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
> @@ -4072,18 +4085,19 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> /* Use Outbox interrupt */
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_YELLOW_CARP:
> - case CHIP_RENOIR:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + case IP_VERSION(2, 1, 0):
> if (register_outbox_irq_handlers(dm->adev)) {
> DRM_ERROR("DM: Failed to initialize IRQ\n");
> goto fail;
> }
> break;
> default:
> - DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", adev->asic_type);
> + DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
> + adev->ip_versions[DCE_HWIP]);
> }
> #endif
>
> @@ -4171,16 +4185,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> break;
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> case CHIP_RAVEN:
> - case CHIP_NAVI12:
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_RENOIR:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
> if (dcn10_register_irq_handlers(dm->adev)) {
> DRM_ERROR("DM: Failed to initialize IRQ\n");
> goto fail;
> @@ -4188,6 +4192,26 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> break;
> #endif
> default:
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 0, 2):
> + case IP_VERSION(3, 0, 3):
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + if (dcn10_register_irq_handlers(dm->adev)) {
> + DRM_ERROR("DM: Failed to initialize IRQ\n");
> + goto fail;
> + }
> + break;
> + default:
> + break;
> + }
> +#endif
> DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
> goto fail;
> }
> @@ -4338,38 +4362,43 @@ static int dm_early_init(void *handle)
> break;
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_VANGOGH:
> - adev->mode_info.num_crtc = 4;
> - adev->mode_info.num_hpd = 4;
> - adev->mode_info.num_dig = 4;
> - break;
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - adev->mode_info.num_crtc = 6;
> - adev->mode_info.num_hpd = 6;
> - adev->mode_info.num_dig = 6;
> - break;
> - case CHIP_YELLOW_CARP:
> adev->mode_info.num_crtc = 4;
> adev->mode_info.num_hpd = 4;
> adev->mode_info.num_dig = 4;
> break;
> - case CHIP_NAVI14:
> - case CHIP_DIMGREY_CAVEFISH:
> - adev->mode_info.num_crtc = 5;
> - adev->mode_info.num_hpd = 5;
> - adev->mode_info.num_dig = 5;
> - break;
> - case CHIP_BEIGE_GOBY:
> - adev->mode_info.num_crtc = 2;
> - adev->mode_info.num_hpd = 2;
> - adev->mode_info.num_dig = 2;
> - break;
> #endif
> default:
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(3, 0, 0):
> + adev->mode_info.num_crtc = 6;
> + adev->mode_info.num_hpd = 6;
> + adev->mode_info.num_dig = 6;
> + break;
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(3, 0, 2):
> + adev->mode_info.num_crtc = 5;
> + adev->mode_info.num_hpd = 5;
> + adev->mode_info.num_dig = 5;
> + break;
> + case IP_VERSION(3, 0, 3):
> + adev->mode_info.num_crtc = 2;
> + adev->mode_info.num_hpd = 2;
> + adev->mode_info.num_dig = 2;
> + break;
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + adev->mode_info.num_crtc = 4;
> + adev->mode_info.num_hpd = 4;
> + adev->mode_info.num_dig = 4;
> + break;
> + default:
> + break;
> + }
> +#endif
> DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
> return -EINVAL;
> }
> @@ -4590,12 +4619,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
> tiling_info->gfx9.num_rb_per_se =
> adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
> tiling_info->gfx9.shaderEnable = 1;
> - if (adev->asic_type == CHIP_SIENNA_CICHLID ||
> - adev->asic_type == CHIP_NAVY_FLOUNDER ||
> - adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
> - adev->asic_type == CHIP_BEIGE_GOBY ||
> - adev->asic_type == CHIP_YELLOW_CARP ||
> - adev->asic_type == CHIP_VANGOGH)
> + if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
> }
>
> @@ -5036,7 +5060,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
> case AMDGPU_FAMILY_NV:
> case AMDGPU_FAMILY_VGH:
> case AMDGPU_FAMILY_YC:
> - if (adev->asic_type >= CHIP_SIENNA_CICHLID)
> + if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> add_gfx10_3_modifiers(adev, mods, &size, &capacity);
> else
> add_gfx10_1_modifiers(adev, mods, &size, &capacity);
> @@ -7647,7 +7671,7 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
> DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
> DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
>
> - if (dm->adev->asic_type >= CHIP_BONAIRE &&
> + if (dm->adev->family >= AMDGPU_FAMILY_CI &&
This doesn't look related.
Thanks,
Lijo
> plane->type != DRM_PLANE_TYPE_CURSOR)
> drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
> supported_rotations);
>
[-- Attachment #2: Type: text/html, Size: 35029 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 30/66] drm/amdgpu: add DCI HWIP
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (28 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 29/66] drm/amdgpu/display/dm: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-23 15:43 ` Harry Wentland
2021-09-21 18:06 ` [PATCH 31/66] drm/amdgpu: make soc15_common_ip_funcs static Alex Deucher
` (36 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
So we can track grab the appropriate DCE info out of the
IP discovery table. This is a separare IP from DCN.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8df4be702870..815db33190ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -756,6 +756,7 @@ enum amd_hw_ip_block_type {
UMC_HWIP,
RSMU_HWIP,
XGMI_HWIP,
+ DCI_HWIP,
MAX_HWIP
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 048a08d7f480..6a993043badc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -149,6 +149,7 @@ static int hw_id_map[MAX_HWIP] = {
[CLK_HWIP] = CLKA_HWID,
[UMC_HWIP] = UMC_HWID,
[XGMI_HWIP] = XGMI_HWID,
+ [DCI_HWIP] = DCI_HWID,
};
static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 30/66] drm/amdgpu: add DCI HWIP
2021-09-21 18:06 ` [PATCH 30/66] drm/amdgpu: add DCI HWIP Alex Deucher
@ 2021-09-23 15:43 ` Harry Wentland
2021-09-24 19:58 ` Alex Deucher
0 siblings, 1 reply; 106+ messages in thread
From: Harry Wentland @ 2021-09-23 15:43 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 2021-09-21 14:06, Alex Deucher wrote:
> So we can track grab the appropriate DCE info out of the
> IP discovery table. This is a separare IP from DCN.
>
I've never looked at the HWID stuff before. Do I understand it correctly
that DCI_HWID is for DCE IP and DMU_HWID for DCN IP?
In that case it might be good to rename DCE_HWIP to DCN_HWIP to avoid
confusion. Ideally as a prep patch so as to avoid excessive renames
later.
Harry
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 8df4be702870..815db33190ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -756,6 +756,7 @@ enum amd_hw_ip_block_type {
> UMC_HWIP,
> RSMU_HWIP,
> XGMI_HWIP,
> + DCI_HWIP,
> MAX_HWIP
> };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 048a08d7f480..6a993043badc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -149,6 +149,7 @@ static int hw_id_map[MAX_HWIP] = {
> [CLK_HWIP] = CLKA_HWID,
> [UMC_HWIP] = UMC_HWID,
> [XGMI_HWIP] = XGMI_HWID,
> + [DCI_HWIP] = DCI_HWID,
> };
>
> static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 30/66] drm/amdgpu: add DCI HWIP
2021-09-23 15:43 ` Harry Wentland
@ 2021-09-24 19:58 ` Alex Deucher
2021-09-24 20:40 ` Harry Wentland
0 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-24 19:58 UTC (permalink / raw)
To: Harry Wentland; +Cc: Alex Deucher, amd-gfx list
On Thu, Sep 23, 2021 at 11:43 AM Harry Wentland <harry.wentland@amd.com> wrote:
>
> On 2021-09-21 14:06, Alex Deucher wrote:
> > So we can track grab the appropriate DCE info out of the
> > IP discovery table. This is a separare IP from DCN.
> >
>
> I've never looked at the HWID stuff before. Do I understand it correctly
> that DCI_HWID is for DCE IP and DMU_HWID for DCN IP?
yes.
>
> In that case it might be good to rename DCE_HWIP to DCN_HWIP to avoid
> confusion. Ideally as a prep patch so as to avoid excessive renames
> later.
The names align with what we use internally in the IP discovery
documentation. I'd prefer to keep them aligned, but I guess it's not
a big deal.
Alex
>
> Harry
>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 8df4be702870..815db33190ca 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -756,6 +756,7 @@ enum amd_hw_ip_block_type {
> > UMC_HWIP,
> > RSMU_HWIP,
> > XGMI_HWIP,
> > + DCI_HWIP,
> > MAX_HWIP
> > };
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > index 048a08d7f480..6a993043badc 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > @@ -149,6 +149,7 @@ static int hw_id_map[MAX_HWIP] = {
> > [CLK_HWIP] = CLKA_HWID,
> > [UMC_HWIP] = UMC_HWID,
> > [XGMI_HWIP] = XGMI_HWID,
> > + [DCI_HWIP] = DCI_HWID,
> > };
> >
> > static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
> >
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 30/66] drm/amdgpu: add DCI HWIP
2021-09-24 19:58 ` Alex Deucher
@ 2021-09-24 20:40 ` Harry Wentland
0 siblings, 0 replies; 106+ messages in thread
From: Harry Wentland @ 2021-09-24 20:40 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, amd-gfx list
On 2021-09-24 15:58, Alex Deucher wrote:
> On Thu, Sep 23, 2021 at 11:43 AM Harry Wentland <harry.wentland@amd.com> wrote:
>>
>> On 2021-09-21 14:06, Alex Deucher wrote:
>>> So we can track grab the appropriate DCE info out of the
>>> IP discovery table. This is a separare IP from DCN.
>>>
>>
>> I've never looked at the HWID stuff before. Do I understand it correctly
>> that DCI_HWID is for DCE IP and DMU_HWID for DCN IP?
>
> yes.
>
Thanks.
>>
>> In that case it might be good to rename DCE_HWIP to DCN_HWIP to avoid
>> confusion. Ideally as a prep patch so as to avoid excessive renames
>> later.
>
> The names align with what we use internally in the IP discovery
> documentation. I'd prefer to keep them aligned, but I guess it's not
> a big deal.
>
In that case it's fine.
Patch is Acked-by: Harry Wentland <harry.wentland@amd.com>
Harry
> Alex
>
>
>>
>> Harry
>>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
>>> 2 files changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 8df4be702870..815db33190ca 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -756,6 +756,7 @@ enum amd_hw_ip_block_type {
>>> UMC_HWIP,
>>> RSMU_HWIP,
>>> XGMI_HWIP,
>>> + DCI_HWIP,
>>> MAX_HWIP
>>> };
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>>> index 048a08d7f480..6a993043badc 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>>> @@ -149,6 +149,7 @@ static int hw_id_map[MAX_HWIP] = {
>>> [CLK_HWIP] = CLKA_HWID,
>>> [UMC_HWIP] = UMC_HWID,
>>> [XGMI_HWIP] = XGMI_HWID,
>>> + [DCI_HWIP] = DCI_HWID,
>>> };
>>>
>>> static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
>>>
>>
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 31/66] drm/amdgpu: make soc15_common_ip_funcs static
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (29 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 30/66] drm/amdgpu: add DCI HWIP Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 32/66] drm/amdgpu/soc15: export common IP functions Alex Deucher
` (35 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
It's not used outside of soc15.c
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/soc15.h | 2 --
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f75130cad98e..1b1e9bfd20f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -85,6 +85,8 @@
#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
+static const struct amd_ip_funcs soc15_common_ip_funcs;
+
/* Vega, Raven, Arcturus */
static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
{
@@ -1646,7 +1648,7 @@ static int soc15_common_set_powergating_state(void *handle,
return 0;
}
-const struct amd_ip_funcs soc15_common_ip_funcs = {
+static const struct amd_ip_funcs soc15_common_ip_funcs = {
.name = "soc15_common",
.early_init = soc15_common_early_init,
.late_init = soc15_common_late_init,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 034cfdfc4dbe..a025339ac5e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -31,8 +31,6 @@
#define SOC15_FLUSH_GPU_TLB_NUM_WREG 6
#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3
-extern const struct amd_ip_funcs soc15_common_ip_funcs;
-
struct soc15_reg_golden {
u32 hwip;
u32 instance;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 32/66] drm/amdgpu/soc15: export common IP functions
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (30 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 31/66] drm/amdgpu: make soc15_common_ip_funcs static Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts Alex Deucher
` (34 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
So they can be driven by IP discovery table.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
drivers/gpu/drm/amd/amdgpu/soc15.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 1b1e9bfd20f1..dffe7d7ff9e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -706,7 +706,7 @@ static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
}
-static const struct amdgpu_ip_block_version vega10_common_ip_block =
+const struct amdgpu_ip_block_version vega10_common_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_COMMON,
.major = 2,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index a025339ac5e9..f9359003385d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -28,6 +28,8 @@
#include "nbio_v7_0.h"
#include "nbio_v7_4.h"
+extern const struct amdgpu_ip_block_version vega10_common_ip_block;
+
#define SOC15_FLUSH_GPU_TLB_NUM_WREG 6
#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (31 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 32/66] drm/amdgpu/soc15: export common IP functions Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-22 7:48 ` Lazar, Lijo
2021-09-22 7:54 ` Lazar, Lijo
2021-09-21 18:06 ` [PATCH 34/66] drm/amdgpu/soc15: get rev_id in soc15_common_early_init Alex Deucher
` (33 subsequent siblings)
66 siblings, 2 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Hardcode the IP versions for asics without IP discovery tables
and then enumerate the asics based on the IP versions.
TODO: fix SR-IOV support
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 417 ++++++++++++++++--
1 file changed, 387 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 6a993043badc..e3b4578872f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -26,6 +26,26 @@
#include "soc15_hw_ip.h"
#include "discovery.h"
+#include "soc15.h"
+#include "gfx_v9_0.h"
+#include "gmc_v9_0.h"
+#include "df_v1_7.h"
+#include "df_v3_6.h"
+#include "nbio_v6_1.h"
+#include "nbio_v7_0.h"
+#include "nbio_v7_4.h"
+#include "hdp_v4_0.h"
+#include "vega10_ih.h"
+#include "vega20_ih.h"
+#include "sdma_v4_0.h"
+#include "uvd_v7_0.h"
+#include "vce_v4_0.h"
+#include "vcn_v1_0.h"
+#include "vcn_v2_0.h"
+#include "jpeg_v2_0.h"
+#include "vcn_v2_5.h"
+#include "jpeg_v2_5.h"
+#include "smuio_v9_0.h"
#include "gmc_v10_0.h"
#include "gfxhub_v2_0.h"
#include "mmhub_v2_0.h"
@@ -45,6 +65,7 @@
#include "mes_v10_1.h"
#include "smuio_v11_0.h"
#include "smuio_v11_0_6.h"
+#include "smuio_v13_0.h"
#define mmRCC_CONFIG_MEMSIZE 0xde3
#define mmMM_INDEX 0x0
@@ -485,23 +506,166 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
return 0;
}
-
int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
{
int r;
- r = amdgpu_discovery_reg_base_init(adev);
- if (r)
- return -EINVAL;
+ switch (adev->asic_type) {
+ case CHIP_VEGA10:
+ vega10_reg_base_init(adev);
+ adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
+ adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
+ adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
+ adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
+ break;
+ case CHIP_VEGA12:
+ vega10_reg_base_init(adev);
+ adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
+ adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
+ adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
+ adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
+ adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
+ adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
+ adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
+ break;
+ case CHIP_RAVEN:
+ vega10_reg_base_init(adev);
+ if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
+ adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
+ adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
+ adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
+ adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
+ adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
+ adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
+ adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
+ adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
+ adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
+ } else {
+ adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
+ adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
+ adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
+ }
+ break;
+ case CHIP_VEGA20:
+ vega20_reg_base_init(adev);
+ adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
+ adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
+ adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
+ adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
+ adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
+ break;
+ case CHIP_ARCTURUS:
+ arct_reg_base_init(adev);
+ adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
+ adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
+ adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
+ adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
+ adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
+ adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
+ adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
+ adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
+ adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
+ adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
+ break;
+ case CHIP_ALDEBARAN:
+ aldebaran_reg_base_init(adev);
+ adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
+ adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
+ adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
+ adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
+ adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
+ break;
+ default:
+ r = amdgpu_discovery_reg_base_init(adev);
+ if (r)
+ return -EINVAL;
- amdgpu_discovery_harvest_ip(adev);
+ amdgpu_discovery_harvest_ip(adev);
- if (!adev->mman.discovery_bin) {
- DRM_ERROR("ip discovery uninitialized\n");
- return -EINVAL;
+ if (!adev->mman.discovery_bin) {
+ DRM_ERROR("ip discovery uninitialized\n");
+ return -EINVAL;
+ }
+ break;
}
switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ adev->family = AMDGPU_FAMILY_AI;
+ break;
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ adev->family = AMDGPU_FAMILY_RV;
+ break;
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -527,6 +691,23 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
/* set NBIO version */
switch (adev->ip_versions[NBIO_HWIP]) {
+ case IP_VERSION(6, 1, 0):
+ case IP_VERSION(6, 2, 0):
+ adev->nbio.funcs = &nbio_v6_1_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
+ break;
+ case IP_VERSION(7, 0, 0):
+ case IP_VERSION(7, 0, 1):
+ case IP_VERSION(2, 5, 0):
+ adev->nbio.funcs = &nbio_v7_0_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
+ break;
+ case IP_VERSION(7, 4, 0):
+ case IP_VERSION(7, 4, 1):
+ case IP_VERSION(7, 4, 4):
+ adev->nbio.funcs = &nbio_v7_4_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
+ break;
case IP_VERSION(7, 2, 0):
case IP_VERSION(7, 2, 1):
case IP_VERSION(7, 5, 0):
@@ -549,6 +730,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
switch (adev->ip_versions[HDP_HWIP]) {
+ case IP_VERSION(4, 0, 0):
+ case IP_VERSION(4, 0, 1):
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 2, 0):
+ case IP_VERSION(4, 2, 1):
+ case IP_VERSION(4, 4, 0):
+ adev->hdp.funcs = &hdp_v4_0_funcs;
+ break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
@@ -561,8 +751,34 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
}
+ switch (adev->ip_versions[DF_HWIP]) {
+ case IP_VERSION(3, 6, 0):
+ case IP_VERSION(3, 6, 1):
+ case IP_VERSION(3, 6, 2):
+ adev->df.funcs = &df_v3_6_funcs;
+ break;
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 5, 0):
+ case IP_VERSION(3, 5, 1):
+ case IP_VERSION(3, 5, 2):
+ adev->df.funcs = &df_v1_7_funcs;
+ break;
+ default:
+ break;
+ }
+
switch (adev->ip_versions[SMUIO_HWIP]) {
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ case IP_VERSION(10, 0, 2):
+ adev->smuio.funcs = &smuio_v9_0_funcs;
+ break;
case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 2):
+ case IP_VERSION(11, 0, 3):
case IP_VERSION(11, 0, 4):
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 8):
@@ -575,12 +791,25 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 1):
adev->smuio.funcs = &smuio_v11_0_6_funcs;
break;
+ case IP_VERSION(13, 0, 2):
+ adev->smuio.funcs = &smuio_v13_0_funcs;
+ break;
default:
break;
}
/* what IP to use for this? */
switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+ break;
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -599,6 +828,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
/* use GC or MMHUB IP version */
switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+ break;
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -616,6 +855,18 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
switch (adev->ip_versions[OSSSYS_HWIP]) {
+ case IP_VERSION(4, 0, 0):
+ case IP_VERSION(4, 0, 1):
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 3, 0):
+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+ break;
+ case IP_VERSION(4, 2, 0):
+ case IP_VERSION(4, 2, 1):
+ case IP_VERSION(4, 4, 0):
+ amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
+ break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
@@ -630,7 +881,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
switch (adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(9, 0, 0):
+ amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+ break;
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
+ break;
case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 2):
+ case IP_VERSION(11, 0, 4):
case IP_VERSION(11, 0, 5):
case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 7):
@@ -643,7 +903,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 8):
amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
break;
+ case IP_VERSION(11, 0, 3):
+ case IP_VERSION(12, 0, 1):
+ amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
+ break;
case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
break;
@@ -654,6 +919,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ case IP_VERSION(11, 0, 2):
+ if (adev->asic_type == CHIP_ARCTURUS)
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ else
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
+ break;
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 7):
@@ -664,7 +938,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 0):
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
break;
+ case IP_VERSION(12, 0, 0):
+ case IP_VERSION(12, 0, 1):
+ amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
+ break;
case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
break;
@@ -676,10 +955,13 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
- } else {
+ } else if (adev->ip_versions[DCE_HWIP]) {
switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
case IP_VERSION(2, 0, 2):
case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 0, 0):
case IP_VERSION(3, 0, 2):
case IP_VERSION(3, 0, 3):
@@ -693,10 +975,29 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
default:
return -EINVAL;
}
-
+ } else if (adev->ip_versions[DCI_HWIP]) {
+ switch (adev->ip_versions[DCI_HWIP]) {
+ case IP_VERSION(12, 0, 0):
+ case IP_VERSION(12, 0, 1):
+ case IP_VERSION(12, 1, 0):
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
}
#endif
switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ break;
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 1):
@@ -714,6 +1015,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
+ case IP_VERSION(4, 0, 1):
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 1, 2):
+ case IP_VERSION(4, 2, 0):
+ case IP_VERSION(4, 2, 2):
+ case IP_VERSION(4, 4, 0):
+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
@@ -734,6 +1045,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ case IP_VERSION(11, 0, 2):
+ if (adev->asic_type == CHIP_ARCTURUS)
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ else
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
+ break;
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 7):
@@ -744,7 +1064,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 0):
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
break;
+ case IP_VERSION(12, 0, 0):
+ case IP_VERSION(12, 0, 1):
+ amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
+ break;
case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
break;
@@ -753,26 +1078,58 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
}
- switch (adev->ip_versions[UVD_HWIP]) {
- case IP_VERSION(2, 0, 0):
- case IP_VERSION(2, 0, 2):
- amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
- break;
- case IP_VERSION(2, 0, 3):
- break;
- case IP_VERSION(3, 0, 0):
- case IP_VERSION(3, 0, 16):
- case IP_VERSION(3, 1, 1):
- case IP_VERSION(3, 0, 2):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
- break;
- case IP_VERSION(3, 0, 33):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
- break;
- default:
- return -EINVAL;
+ if (adev->ip_versions[VCE_HWIP]) {
+ switch (adev->ip_versions[UVD_HWIP]) {
+ case IP_VERSION(7, 0, 0):
+ case IP_VERSION(7, 2, 0):
+ amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+ switch (adev->ip_versions[VCE_HWIP]) {
+ case IP_VERSION(4, 0, 0):
+ case IP_VERSION(4, 1, 0):
+ amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else {
+ switch (adev->ip_versions[UVD_HWIP]) {
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
+ amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
+ break;
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 2, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ break;
+ case IP_VERSION(2, 0, 3):
+ break;
+ case IP_VERSION(2, 5, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
+ break;
+ case IP_VERSION(2, 6, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
+ break;
+ case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 16):
+ case IP_VERSION(3, 1, 1):
+ case IP_VERSION(3, 0, 2):
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
+ break;
+ case IP_VERSION(3, 0, 33):
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
}
if (adev->enable_mes) {
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts
2021-09-21 18:06 ` [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts Alex Deucher
@ 2021-09-22 7:48 ` Lazar, Lijo
2021-09-22 7:54 ` Lazar, Lijo
1 sibling, 0 replies; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 7:48 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Hardcode the IP versions for asics without IP discovery tables
> and then enumerate the asics based on the IP versions.
>
> TODO: fix SR-IOV support
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 417 ++++++++++++++++--
> 1 file changed, 387 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 6a993043badc..e3b4578872f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -26,6 +26,26 @@
> #include "soc15_hw_ip.h"
> #include "discovery.h"
>
> +#include "soc15.h"
> +#include "gfx_v9_0.h"
> +#include "gmc_v9_0.h"
> +#include "df_v1_7.h"
> +#include "df_v3_6.h"
> +#include "nbio_v6_1.h"
> +#include "nbio_v7_0.h"
> +#include "nbio_v7_4.h"
> +#include "hdp_v4_0.h"
> +#include "vega10_ih.h"
> +#include "vega20_ih.h"
> +#include "sdma_v4_0.h"
> +#include "uvd_v7_0.h"
> +#include "vce_v4_0.h"
> +#include "vcn_v1_0.h"
> +#include "vcn_v2_0.h"
> +#include "jpeg_v2_0.h"
> +#include "vcn_v2_5.h"
> +#include "jpeg_v2_5.h"
> +#include "smuio_v9_0.h"
> #include "gmc_v10_0.h"
> #include "gfxhub_v2_0.h"
> #include "mmhub_v2_0.h"
> @@ -45,6 +65,7 @@
> #include "mes_v10_1.h"
> #include "smuio_v11_0.h"
> #include "smuio_v11_0_6.h"
> +#include "smuio_v13_0.h"
>
> #define mmRCC_CONFIG_MEMSIZE 0xde3
> #define mmMM_INDEX 0x0
> @@ -485,23 +506,166 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
> return 0;
> }
>
> -
> int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> {
> int r;
>
> - r = amdgpu_discovery_reg_base_init(adev);
> - if (r)
> - return -EINVAL;
> + switch (adev->asic_type) {
> + case CHIP_VEGA10:
> + vega10_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
> + break;
> + case CHIP_VEGA12:
> + vega10_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
> + break;
> + case CHIP_RAVEN:
> + vega10_reg_base_init(adev);
> + if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
> + adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
> + } else {
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
> + adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
> + }
> + break;
> + case CHIP_VEGA20:
> + vega20_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
> + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
> + break;
> + case CHIP_ARCTURUS:
> + arct_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
> + break;
> + case CHIP_ALDEBARAN:
> + aldebaran_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
> + adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
> + break;
> + default:
> + r = amdgpu_discovery_reg_base_init(adev);
> + if (r)
> + return -EINVAL;
>
> - amdgpu_discovery_harvest_ip(adev);
> + amdgpu_discovery_harvest_ip(adev);
>
> - if (!adev->mman.discovery_bin) {
> - DRM_ERROR("ip discovery uninitialized\n");
> - return -EINVAL;
> + if (!adev->mman.discovery_bin) {
> + DRM_ERROR("ip discovery uninitialized\n");
> + return -EINVAL;
> + }
> + break;
> }
>
> switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + adev->family = AMDGPU_FAMILY_AI;
> + break;
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + adev->family = AMDGPU_FAMILY_RV;
> + break;
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -527,6 +691,23 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> /* set NBIO version */
> switch (adev->ip_versions[NBIO_HWIP]) {
> + case IP_VERSION(6, 1, 0):
> + case IP_VERSION(6, 2, 0):
> + adev->nbio.funcs = &nbio_v6_1_funcs;
> + adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
> + break;
> + case IP_VERSION(7, 0, 0):
> + case IP_VERSION(7, 0, 1):
> + case IP_VERSION(2, 5, 0):
> + adev->nbio.funcs = &nbio_v7_0_funcs;
> + adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
> + break;
> + case IP_VERSION(7, 4, 0):
> + case IP_VERSION(7, 4, 1):
> + case IP_VERSION(7, 4, 4):
> + adev->nbio.funcs = &nbio_v7_4_funcs;
> + adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
> + break;
> case IP_VERSION(7, 2, 0):
> case IP_VERSION(7, 2, 1):
> case IP_VERSION(7, 5, 0):
> @@ -549,6 +730,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> switch (adev->ip_versions[HDP_HWIP]) {
> + case IP_VERSION(4, 0, 0):
> + case IP_VERSION(4, 0, 1):
> + case IP_VERSION(4, 1, 0):
> + case IP_VERSION(4, 1, 1):
> + case IP_VERSION(4, 2, 0):
> + case IP_VERSION(4, 2, 1):
> + case IP_VERSION(4, 4, 0):
> + adev->hdp.funcs = &hdp_v4_0_funcs;
> + break;
> case IP_VERSION(5, 0, 0):
> case IP_VERSION(5, 0, 1):
> case IP_VERSION(5, 0, 2):
> @@ -561,8 +751,34 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> break;
> }
>
> + switch (adev->ip_versions[DF_HWIP]) {
> + case IP_VERSION(3, 6, 0):
> + case IP_VERSION(3, 6, 1):
> + case IP_VERSION(3, 6, 2):
> + adev->df.funcs = &df_v3_6_funcs;
> + break;
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(2, 1, 1):
> + case IP_VERSION(2, 5, 0):
> + case IP_VERSION(3, 5, 1):
> + case IP_VERSION(3, 5, 2):
> + adev->df.funcs = &df_v1_7_funcs;
> + break;
> + default:
> + break;
> + }
> +
> switch (adev->ip_versions[SMUIO_HWIP]) {
> + case IP_VERSION(9, 0, 0):
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(10, 0, 0):
> + case IP_VERSION(10, 0, 1):
> + case IP_VERSION(10, 0, 2):
> + adev->smuio.funcs = &smuio_v9_0_funcs;
> + break;
> case IP_VERSION(11, 0, 0):
> + case IP_VERSION(11, 0, 2):
> + case IP_VERSION(11, 0, 3):
> case IP_VERSION(11, 0, 4):
> case IP_VERSION(11, 0, 7):
> case IP_VERSION(11, 0, 8):
> @@ -575,12 +791,25 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(13, 0, 1):
> adev->smuio.funcs = &smuio_v11_0_6_funcs;
> break;
> + case IP_VERSION(13, 0, 2):
> + adev->smuio.funcs = &smuio_v13_0_funcs;
> + break;
> default:
> break;
> }
>
> /* what IP to use for this? */
> switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
> + break;
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -599,6 +828,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> /* use GC or MMHUB IP version */
> switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
> + break;
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -616,6 +855,18 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> switch (adev->ip_versions[OSSSYS_HWIP]) {
> + case IP_VERSION(4, 0, 0):
> + case IP_VERSION(4, 0, 1):
> + case IP_VERSION(4, 1, 0):
> + case IP_VERSION(4, 1, 1):
> + case IP_VERSION(4, 3, 0):
> + amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
> + break;
> + case IP_VERSION(4, 2, 0):
> + case IP_VERSION(4, 2, 1):
> + case IP_VERSION(4, 4, 0):
> + amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
> + break;
> case IP_VERSION(5, 0, 0):
> case IP_VERSION(5, 0, 1):
> case IP_VERSION(5, 0, 2):
> @@ -630,7 +881,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> switch (adev->ip_versions[MP0_HWIP]) {
> + case IP_VERSION(9, 0, 0):
> + amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
> + break;
> + case IP_VERSION(10, 0, 0):
> + case IP_VERSION(10, 0, 1):
> + amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
> + break;
> case IP_VERSION(11, 0, 0):
> + case IP_VERSION(11, 0, 2):
> + case IP_VERSION(11, 0, 4):
> case IP_VERSION(11, 0, 5):
> case IP_VERSION(11, 0, 9):
> case IP_VERSION(11, 0, 7):
> @@ -643,7 +903,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(11, 0, 8):
> amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
> break;
> + case IP_VERSION(11, 0, 3):
> + case IP_VERSION(12, 0, 1):
> + amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
> + break;
> case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 2):
> case IP_VERSION(13, 0, 3):
> amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
> break;
> @@ -654,6 +919,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(9, 0, 0):
> + case IP_VERSION(10, 0, 0):
> + case IP_VERSION(10, 0, 1):
> + case IP_VERSION(11, 0, 2):
> + if (adev->asic_type == CHIP_ARCTURUS)
> + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
Better to split to two separate cases - 11.0.2 supports swsmu block, for
others pp_smu block.
> + else
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> + break;
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 9):
> case IP_VERSION(11, 0, 7):
> @@ -664,7 +938,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(11, 5, 0):
> amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> break;
> + case IP_VERSION(12, 0, 0):
> + case IP_VERSION(12, 0, 1):
> + amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
> + break;
> case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 2):
> case IP_VERSION(13, 0, 3):
> amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
> break;
> @@ -676,10 +955,13 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
> amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> - } else {
> + } else if (adev->ip_versions[DCE_HWIP]) {
> switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(1, 0, 0):
> + case IP_VERSION(1, 0, 1):
> case IP_VERSION(2, 0, 2):
> case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 1, 0):
> case IP_VERSION(3, 0, 0):
> case IP_VERSION(3, 0, 2):
> case IP_VERSION(3, 0, 3):
> @@ -693,10 +975,29 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> default:
> return -EINVAL;
> }
> -
> + } else if (adev->ip_versions[DCI_HWIP]) {
> + switch (adev->ip_versions[DCI_HWIP]) {
> + case IP_VERSION(12, 0, 0):
> + case IP_VERSION(12, 0, 1):
> + case IP_VERSION(12, 1, 0):
> + amdgpu_device_ip_block_add(adev, &dm_ip_block);
> + break;
> + default:
> + return -EINVAL;
> + }
> }
> #endif
> switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
> + break;
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 2):
> case IP_VERSION(10, 1, 1):
> @@ -714,6 +1015,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(4, 0, 0):
> + case IP_VERSION(4, 0, 1):
> + case IP_VERSION(4, 1, 0):
> + case IP_VERSION(4, 1, 1):
> + case IP_VERSION(4, 1, 2):
> + case IP_VERSION(4, 2, 0):
> + case IP_VERSION(4, 2, 2):
> + case IP_VERSION(4, 4, 0):
> + amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
> + break;
> case IP_VERSION(5, 0, 0):
> case IP_VERSION(5, 0, 1):
> case IP_VERSION(5, 0, 2):
> @@ -734,6 +1045,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(9, 0, 0):
> + case IP_VERSION(10, 0, 0):
> + case IP_VERSION(10, 0, 1):
> + case IP_VERSION(11, 0, 2):
> + if (adev->asic_type == CHIP_ARCTURUS)
> + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
Same comment as earlier.
Thanks,
Lijo
> + else
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> + break;
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 9):
> case IP_VERSION(11, 0, 7):
> @@ -744,7 +1064,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(11, 5, 0):
> amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> break;
> + case IP_VERSION(12, 0, 0):
> + case IP_VERSION(12, 0, 1):
> + amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
> + break;
> case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 2):
> case IP_VERSION(13, 0, 3):
> amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
> break;
> @@ -753,26 +1078,58 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
> }
>
> - switch (adev->ip_versions[UVD_HWIP]) {
> - case IP_VERSION(2, 0, 0):
> - case IP_VERSION(2, 0, 2):
> - amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
> - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> - break;
> - case IP_VERSION(2, 0, 3):
> - break;
> - case IP_VERSION(3, 0, 0):
> - case IP_VERSION(3, 0, 16):
> - case IP_VERSION(3, 1, 1):
> - case IP_VERSION(3, 0, 2):
> - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
> - break;
> - case IP_VERSION(3, 0, 33):
> - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> - break;
> - default:
> - return -EINVAL;
> + if (adev->ip_versions[VCE_HWIP]) {
> + switch (adev->ip_versions[UVD_HWIP]) {
> + case IP_VERSION(7, 0, 0):
> + case IP_VERSION(7, 2, 0):
> + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
> + break;
> + default:
> + return -EINVAL;
> + }
> + switch (adev->ip_versions[VCE_HWIP]) {
> + case IP_VERSION(4, 0, 0):
> + case IP_VERSION(4, 1, 0):
> + amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
> + break;
> + default:
> + return -EINVAL;
> + }
> + } else {
> + switch (adev->ip_versions[UVD_HWIP]) {
> + case IP_VERSION(1, 0, 0):
> + case IP_VERSION(1, 0, 1):
> + amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
> + break;
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 2, 0):
> + amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
> + amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> + break;
> + case IP_VERSION(2, 0, 3):
> + break;
> + case IP_VERSION(2, 5, 0):
> + amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
> + amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
> + break;
> + case IP_VERSION(2, 6, 0):
> + amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
> + amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
> + break;
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 0, 16):
> + case IP_VERSION(3, 1, 1):
> + case IP_VERSION(3, 0, 2):
> + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> + amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
> + break;
> + case IP_VERSION(3, 0, 33):
> + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> + break;
> + default:
> + return -EINVAL;
> + }
> }
>
> if (adev->enable_mes) {
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts
2021-09-21 18:06 ` [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts Alex Deucher
2021-09-22 7:48 ` Lazar, Lijo
@ 2021-09-22 7:54 ` Lazar, Lijo
2021-09-22 15:58 ` Alex Deucher
1 sibling, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 7:54 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Hardcode the IP versions for asics without IP discovery tables
> and then enumerate the asics based on the IP versions.
>
> TODO: fix SR-IOV support
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 417 ++++++++++++++++--
> 1 file changed, 387 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 6a993043badc..e3b4578872f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -26,6 +26,26 @@
> #include "soc15_hw_ip.h"
> #include "discovery.h"
>
> +#include "soc15.h"
> +#include "gfx_v9_0.h"
> +#include "gmc_v9_0.h"
> +#include "df_v1_7.h"
> +#include "df_v3_6.h"
> +#include "nbio_v6_1.h"
> +#include "nbio_v7_0.h"
> +#include "nbio_v7_4.h"
> +#include "hdp_v4_0.h"
> +#include "vega10_ih.h"
> +#include "vega20_ih.h"
> +#include "sdma_v4_0.h"
> +#include "uvd_v7_0.h"
> +#include "vce_v4_0.h"
> +#include "vcn_v1_0.h"
> +#include "vcn_v2_0.h"
> +#include "jpeg_v2_0.h"
> +#include "vcn_v2_5.h"
> +#include "jpeg_v2_5.h"
> +#include "smuio_v9_0.h"
> #include "gmc_v10_0.h"
> #include "gfxhub_v2_0.h"
> #include "mmhub_v2_0.h"
> @@ -45,6 +65,7 @@
> #include "mes_v10_1.h"
> #include "smuio_v11_0.h"
> #include "smuio_v11_0_6.h"
> +#include "smuio_v13_0.h"
>
> #define mmRCC_CONFIG_MEMSIZE 0xde3
> #define mmMM_INDEX 0x0
> @@ -485,23 +506,166 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
> return 0;
> }
>
> -
> int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> {
> int r;
>
> - r = amdgpu_discovery_reg_base_init(adev);
> - if (r)
> - return -EINVAL;
> + switch (adev->asic_type) {
> + case CHIP_VEGA10:
> + vega10_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
> + break;
> + case CHIP_VEGA12:
> + vega10_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
> + break;
> + case CHIP_RAVEN:
> + vega10_reg_base_init(adev);
> + if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
> + adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
> + } else {
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
> + adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
> + }
> + break;
> + case CHIP_VEGA20:
> + vega20_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
> + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
> + break;
> + case CHIP_ARCTURUS:
> + arct_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
Just found that this version is shared with VG20. Since it's a soft IP
version table anyway, any problem in changing to say 11.0.3 and avoid
ASIC checks?
Thanks,
Lijo
> + adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
> + break;
> + case CHIP_ALDEBARAN:
> + aldebaran_reg_base_init(adev);
> + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
> + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
> + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
> + adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
> + adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
> + break;
> + default:
> + r = amdgpu_discovery_reg_base_init(adev);
> + if (r)
> + return -EINVAL;
>
> - amdgpu_discovery_harvest_ip(adev);
> + amdgpu_discovery_harvest_ip(adev);
>
> - if (!adev->mman.discovery_bin) {
> - DRM_ERROR("ip discovery uninitialized\n");
> - return -EINVAL;
> + if (!adev->mman.discovery_bin) {
> + DRM_ERROR("ip discovery uninitialized\n");
> + return -EINVAL;
> + }
> + break;
> }
>
> switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + adev->family = AMDGPU_FAMILY_AI;
> + break;
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + adev->family = AMDGPU_FAMILY_RV;
> + break;
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -527,6 +691,23 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> /* set NBIO version */
> switch (adev->ip_versions[NBIO_HWIP]) {
> + case IP_VERSION(6, 1, 0):
> + case IP_VERSION(6, 2, 0):
> + adev->nbio.funcs = &nbio_v6_1_funcs;
> + adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
> + break;
> + case IP_VERSION(7, 0, 0):
> + case IP_VERSION(7, 0, 1):
> + case IP_VERSION(2, 5, 0):
> + adev->nbio.funcs = &nbio_v7_0_funcs;
> + adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
> + break;
> + case IP_VERSION(7, 4, 0):
> + case IP_VERSION(7, 4, 1):
> + case IP_VERSION(7, 4, 4):
> + adev->nbio.funcs = &nbio_v7_4_funcs;
> + adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
> + break;
> case IP_VERSION(7, 2, 0):
> case IP_VERSION(7, 2, 1):
> case IP_VERSION(7, 5, 0):
> @@ -549,6 +730,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> switch (adev->ip_versions[HDP_HWIP]) {
> + case IP_VERSION(4, 0, 0):
> + case IP_VERSION(4, 0, 1):
> + case IP_VERSION(4, 1, 0):
> + case IP_VERSION(4, 1, 1):
> + case IP_VERSION(4, 2, 0):
> + case IP_VERSION(4, 2, 1):
> + case IP_VERSION(4, 4, 0):
> + adev->hdp.funcs = &hdp_v4_0_funcs;
> + break;
> case IP_VERSION(5, 0, 0):
> case IP_VERSION(5, 0, 1):
> case IP_VERSION(5, 0, 2):
> @@ -561,8 +751,34 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> break;
> }
>
> + switch (adev->ip_versions[DF_HWIP]) {
> + case IP_VERSION(3, 6, 0):
> + case IP_VERSION(3, 6, 1):
> + case IP_VERSION(3, 6, 2):
> + adev->df.funcs = &df_v3_6_funcs;
> + break;
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(2, 1, 1):
> + case IP_VERSION(2, 5, 0):
> + case IP_VERSION(3, 5, 1):
> + case IP_VERSION(3, 5, 2):
> + adev->df.funcs = &df_v1_7_funcs;
> + break;
> + default:
> + break;
> + }
> +
> switch (adev->ip_versions[SMUIO_HWIP]) {
> + case IP_VERSION(9, 0, 0):
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(10, 0, 0):
> + case IP_VERSION(10, 0, 1):
> + case IP_VERSION(10, 0, 2):
> + adev->smuio.funcs = &smuio_v9_0_funcs;
> + break;
> case IP_VERSION(11, 0, 0):
> + case IP_VERSION(11, 0, 2):
> + case IP_VERSION(11, 0, 3):
> case IP_VERSION(11, 0, 4):
> case IP_VERSION(11, 0, 7):
> case IP_VERSION(11, 0, 8):
> @@ -575,12 +791,25 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(13, 0, 1):
> adev->smuio.funcs = &smuio_v11_0_6_funcs;
> break;
> + case IP_VERSION(13, 0, 2):
> + adev->smuio.funcs = &smuio_v13_0_funcs;
> + break;
> default:
> break;
> }
>
> /* what IP to use for this? */
> switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
> + break;
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -599,6 +828,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> /* use GC or MMHUB IP version */
> switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
> + break;
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -616,6 +855,18 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> switch (adev->ip_versions[OSSSYS_HWIP]) {
> + case IP_VERSION(4, 0, 0):
> + case IP_VERSION(4, 0, 1):
> + case IP_VERSION(4, 1, 0):
> + case IP_VERSION(4, 1, 1):
> + case IP_VERSION(4, 3, 0):
> + amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
> + break;
> + case IP_VERSION(4, 2, 0):
> + case IP_VERSION(4, 2, 1):
> + case IP_VERSION(4, 4, 0):
> + amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
> + break;
> case IP_VERSION(5, 0, 0):
> case IP_VERSION(5, 0, 1):
> case IP_VERSION(5, 0, 2):
> @@ -630,7 +881,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> switch (adev->ip_versions[MP0_HWIP]) {
> + case IP_VERSION(9, 0, 0):
> + amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
> + break;
> + case IP_VERSION(10, 0, 0):
> + case IP_VERSION(10, 0, 1):
> + amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
> + break;
> case IP_VERSION(11, 0, 0):
> + case IP_VERSION(11, 0, 2):
> + case IP_VERSION(11, 0, 4):
> case IP_VERSION(11, 0, 5):
> case IP_VERSION(11, 0, 9):
> case IP_VERSION(11, 0, 7):
> @@ -643,7 +903,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(11, 0, 8):
> amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
> break;
> + case IP_VERSION(11, 0, 3):
> + case IP_VERSION(12, 0, 1):
> + amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
> + break;
> case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 2):
> case IP_VERSION(13, 0, 3):
> amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
> break;
> @@ -654,6 +919,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(9, 0, 0):
> + case IP_VERSION(10, 0, 0):
> + case IP_VERSION(10, 0, 1):
> + case IP_VERSION(11, 0, 2):
> + if (adev->asic_type == CHIP_ARCTURUS)
> + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> + else
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> + break;
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 9):
> case IP_VERSION(11, 0, 7):
> @@ -664,7 +938,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(11, 5, 0):
> amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> break;
> + case IP_VERSION(12, 0, 0):
> + case IP_VERSION(12, 0, 1):
> + amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
> + break;
> case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 2):
> case IP_VERSION(13, 0, 3):
> amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
> break;
> @@ -676,10 +955,13 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
> amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> - } else {
> + } else if (adev->ip_versions[DCE_HWIP]) {
> switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(1, 0, 0):
> + case IP_VERSION(1, 0, 1):
> case IP_VERSION(2, 0, 2):
> case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 1, 0):
> case IP_VERSION(3, 0, 0):
> case IP_VERSION(3, 0, 2):
> case IP_VERSION(3, 0, 3):
> @@ -693,10 +975,29 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> default:
> return -EINVAL;
> }
> -
> + } else if (adev->ip_versions[DCI_HWIP]) {
> + switch (adev->ip_versions[DCI_HWIP]) {
> + case IP_VERSION(12, 0, 0):
> + case IP_VERSION(12, 0, 1):
> + case IP_VERSION(12, 1, 0):
> + amdgpu_device_ip_block_add(adev, &dm_ip_block);
> + break;
> + default:
> + return -EINVAL;
> + }
> }
> #endif
> switch (adev->ip_versions[GC_HWIP]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
> + break;
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 2):
> case IP_VERSION(10, 1, 1):
> @@ -714,6 +1015,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(4, 0, 0):
> + case IP_VERSION(4, 0, 1):
> + case IP_VERSION(4, 1, 0):
> + case IP_VERSION(4, 1, 1):
> + case IP_VERSION(4, 1, 2):
> + case IP_VERSION(4, 2, 0):
> + case IP_VERSION(4, 2, 2):
> + case IP_VERSION(4, 4, 0):
> + amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
> + break;
> case IP_VERSION(5, 0, 0):
> case IP_VERSION(5, 0, 1):
> case IP_VERSION(5, 0, 2):
> @@ -734,6 +1045,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(9, 0, 0):
> + case IP_VERSION(10, 0, 0):
> + case IP_VERSION(10, 0, 1):
> + case IP_VERSION(11, 0, 2):
> + if (adev->asic_type == CHIP_ARCTURUS)
> + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> + else
> + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> + break;
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 9):
> case IP_VERSION(11, 0, 7):
> @@ -744,7 +1064,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case IP_VERSION(11, 5, 0):
> amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> break;
> + case IP_VERSION(12, 0, 0):
> + case IP_VERSION(12, 0, 1):
> + amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
> + break;
> case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 2):
> case IP_VERSION(13, 0, 3):
> amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
> break;
> @@ -753,26 +1078,58 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
> }
>
> - switch (adev->ip_versions[UVD_HWIP]) {
> - case IP_VERSION(2, 0, 0):
> - case IP_VERSION(2, 0, 2):
> - amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
> - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> - break;
> - case IP_VERSION(2, 0, 3):
> - break;
> - case IP_VERSION(3, 0, 0):
> - case IP_VERSION(3, 0, 16):
> - case IP_VERSION(3, 1, 1):
> - case IP_VERSION(3, 0, 2):
> - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
> - break;
> - case IP_VERSION(3, 0, 33):
> - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> - break;
> - default:
> - return -EINVAL;
> + if (adev->ip_versions[VCE_HWIP]) {
> + switch (adev->ip_versions[UVD_HWIP]) {
> + case IP_VERSION(7, 0, 0):
> + case IP_VERSION(7, 2, 0):
> + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
> + break;
> + default:
> + return -EINVAL;
> + }
> + switch (adev->ip_versions[VCE_HWIP]) {
> + case IP_VERSION(4, 0, 0):
> + case IP_VERSION(4, 1, 0):
> + amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
> + break;
> + default:
> + return -EINVAL;
> + }
> + } else {
> + switch (adev->ip_versions[UVD_HWIP]) {
> + case IP_VERSION(1, 0, 0):
> + case IP_VERSION(1, 0, 1):
> + amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
> + break;
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 2, 0):
> + amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
> + amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> + break;
> + case IP_VERSION(2, 0, 3):
> + break;
> + case IP_VERSION(2, 5, 0):
> + amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
> + amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
> + break;
> + case IP_VERSION(2, 6, 0):
> + amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
> + amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
> + break;
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 0, 16):
> + case IP_VERSION(3, 1, 1):
> + case IP_VERSION(3, 0, 2):
> + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> + amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
> + break;
> + case IP_VERSION(3, 0, 33):
> + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> + break;
> + default:
> + return -EINVAL;
> + }
> }
>
> if (adev->enable_mes) {
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts
2021-09-22 7:54 ` Lazar, Lijo
@ 2021-09-22 15:58 ` Alex Deucher
0 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-22 15:58 UTC (permalink / raw)
To: Lazar, Lijo; +Cc: Alex Deucher, amd-gfx list
On Wed, Sep 22, 2021 at 3:54 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 9/21/2021 11:36 PM, Alex Deucher wrote:
> > Hardcode the IP versions for asics without IP discovery tables
> > and then enumerate the asics based on the IP versions.
> >
> > TODO: fix SR-IOV support
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 417 ++++++++++++++++--
> > 1 file changed, 387 insertions(+), 30 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > index 6a993043badc..e3b4578872f1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > @@ -26,6 +26,26 @@
> > #include "soc15_hw_ip.h"
> > #include "discovery.h"
> >
> > +#include "soc15.h"
> > +#include "gfx_v9_0.h"
> > +#include "gmc_v9_0.h"
> > +#include "df_v1_7.h"
> > +#include "df_v3_6.h"
> > +#include "nbio_v6_1.h"
> > +#include "nbio_v7_0.h"
> > +#include "nbio_v7_4.h"
> > +#include "hdp_v4_0.h"
> > +#include "vega10_ih.h"
> > +#include "vega20_ih.h"
> > +#include "sdma_v4_0.h"
> > +#include "uvd_v7_0.h"
> > +#include "vce_v4_0.h"
> > +#include "vcn_v1_0.h"
> > +#include "vcn_v2_0.h"
> > +#include "jpeg_v2_0.h"
> > +#include "vcn_v2_5.h"
> > +#include "jpeg_v2_5.h"
> > +#include "smuio_v9_0.h"
> > #include "gmc_v10_0.h"
> > #include "gfxhub_v2_0.h"
> > #include "mmhub_v2_0.h"
> > @@ -45,6 +65,7 @@
> > #include "mes_v10_1.h"
> > #include "smuio_v11_0.h"
> > #include "smuio_v11_0_6.h"
> > +#include "smuio_v13_0.h"
> >
> > #define mmRCC_CONFIG_MEMSIZE 0xde3
> > #define mmMM_INDEX 0x0
> > @@ -485,23 +506,166 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
> > return 0;
> > }
> >
> > -
> > int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > {
> > int r;
> >
> > - r = amdgpu_discovery_reg_base_init(adev);
> > - if (r)
> > - return -EINVAL;
> > + switch (adev->asic_type) {
> > + case CHIP_VEGA10:
> > + vega10_reg_base_init(adev);
> > + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> > + adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
> > + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
> > + adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
> > + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> > + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
> > + break;
> > + case CHIP_VEGA12:
> > + vega10_reg_base_init(adev);
> > + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
> > + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
> > + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
> > + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
> > + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
> > + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
> > + adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
> > + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
> > + adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
> > + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
> > + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> > + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
> > + break;
> > + case CHIP_RAVEN:
> > + vega10_reg_base_init(adev);
> > + if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
> > + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
> > + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
> > + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
> > + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
> > + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
> > + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
> > + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
> > + adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
> > + adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
> > + adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
> > + adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
> > + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
> > + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
> > + adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
> > + adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
> > + } else {
> > + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
> > + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
> > + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
> > + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
> > + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
> > + adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> > + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
> > + adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
> > + adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
> > + adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
> > + adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
> > + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
> > + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
> > + adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
> > + adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
> > + }
> > + break;
> > + case CHIP_VEGA20:
> > + vega20_reg_base_init(adev);
> > + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
> > + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
> > + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
> > + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
> > + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
> > + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
> > + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
> > + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
> > + adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
> > + adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
> > + adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
> > + adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
> > + break;
> > + case CHIP_ARCTURUS:
> > + arct_reg_base_init(adev);
> > + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
> > + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
> > + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
> > + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
> > + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
> > + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
> > + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
> > + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
> > + adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
> > + adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
>
> Just found that this version is shared with VG20. Since it's a soft IP
> version table anyway, any problem in changing to say 11.0.3 and avoid
> ASIC checks?
I thought about that, but wanted to stay consistent with the hw
versions documented internally.
Alex
>
> Thanks,
> Lijo
>
> > + adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
> > + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
> > + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
> > + adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
> > + break;
> > + case CHIP_ALDEBARAN:
> > + aldebaran_reg_base_init(adev);
> > + adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
> > + adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
> > + adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
> > + adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
> > + adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
> > + adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
> > + adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
> > + adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
> > + adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
> > + adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
> > + adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
> > + adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
> > + adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
> > + adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
> > + adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
> > + break;
> > + default:
> > + r = amdgpu_discovery_reg_base_init(adev);
> > + if (r)
> > + return -EINVAL;
> >
> > - amdgpu_discovery_harvest_ip(adev);
> > + amdgpu_discovery_harvest_ip(adev);
> >
> > - if (!adev->mman.discovery_bin) {
> > - DRM_ERROR("ip discovery uninitialized\n");
> > - return -EINVAL;
> > + if (!adev->mman.discovery_bin) {
> > + DRM_ERROR("ip discovery uninitialized\n");
> > + return -EINVAL;
> > + }
> > + break;
> > }
> >
> > switch (adev->ip_versions[GC_HWIP]) {
> > + case IP_VERSION(9, 0, 1):
> > + case IP_VERSION(9, 2, 1):
> > + case IP_VERSION(9, 4, 0):
> > + case IP_VERSION(9, 4, 1):
> > + case IP_VERSION(9, 4, 2):
> > + adev->family = AMDGPU_FAMILY_AI;
> > + break;
> > + case IP_VERSION(9, 1, 0):
> > + case IP_VERSION(9, 2, 2):
> > + case IP_VERSION(9, 3, 0):
> > + adev->family = AMDGPU_FAMILY_RV;
> > + break;
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -527,6 +691,23 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >
> > /* set NBIO version */
> > switch (adev->ip_versions[NBIO_HWIP]) {
> > + case IP_VERSION(6, 1, 0):
> > + case IP_VERSION(6, 2, 0):
> > + adev->nbio.funcs = &nbio_v6_1_funcs;
> > + adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
> > + break;
> > + case IP_VERSION(7, 0, 0):
> > + case IP_VERSION(7, 0, 1):
> > + case IP_VERSION(2, 5, 0):
> > + adev->nbio.funcs = &nbio_v7_0_funcs;
> > + adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
> > + break;
> > + case IP_VERSION(7, 4, 0):
> > + case IP_VERSION(7, 4, 1):
> > + case IP_VERSION(7, 4, 4):
> > + adev->nbio.funcs = &nbio_v7_4_funcs;
> > + adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
> > + break;
> > case IP_VERSION(7, 2, 0):
> > case IP_VERSION(7, 2, 1):
> > case IP_VERSION(7, 5, 0):
> > @@ -549,6 +730,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > switch (adev->ip_versions[HDP_HWIP]) {
> > + case IP_VERSION(4, 0, 0):
> > + case IP_VERSION(4, 0, 1):
> > + case IP_VERSION(4, 1, 0):
> > + case IP_VERSION(4, 1, 1):
> > + case IP_VERSION(4, 2, 0):
> > + case IP_VERSION(4, 2, 1):
> > + case IP_VERSION(4, 4, 0):
> > + adev->hdp.funcs = &hdp_v4_0_funcs;
> > + break;
> > case IP_VERSION(5, 0, 0):
> > case IP_VERSION(5, 0, 1):
> > case IP_VERSION(5, 0, 2):
> > @@ -561,8 +751,34 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > break;
> > }
> >
> > + switch (adev->ip_versions[DF_HWIP]) {
> > + case IP_VERSION(3, 6, 0):
> > + case IP_VERSION(3, 6, 1):
> > + case IP_VERSION(3, 6, 2):
> > + adev->df.funcs = &df_v3_6_funcs;
> > + break;
> > + case IP_VERSION(2, 1, 0):
> > + case IP_VERSION(2, 1, 1):
> > + case IP_VERSION(2, 5, 0):
> > + case IP_VERSION(3, 5, 1):
> > + case IP_VERSION(3, 5, 2):
> > + adev->df.funcs = &df_v1_7_funcs;
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > switch (adev->ip_versions[SMUIO_HWIP]) {
> > + case IP_VERSION(9, 0, 0):
> > + case IP_VERSION(9, 0, 1):
> > + case IP_VERSION(10, 0, 0):
> > + case IP_VERSION(10, 0, 1):
> > + case IP_VERSION(10, 0, 2):
> > + adev->smuio.funcs = &smuio_v9_0_funcs;
> > + break;
> > case IP_VERSION(11, 0, 0):
> > + case IP_VERSION(11, 0, 2):
> > + case IP_VERSION(11, 0, 3):
> > case IP_VERSION(11, 0, 4):
> > case IP_VERSION(11, 0, 7):
> > case IP_VERSION(11, 0, 8):
> > @@ -575,12 +791,25 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > case IP_VERSION(13, 0, 1):
> > adev->smuio.funcs = &smuio_v11_0_6_funcs;
> > break;
> > + case IP_VERSION(13, 0, 2):
> > + adev->smuio.funcs = &smuio_v13_0_funcs;
> > + break;
> > default:
> > break;
> > }
> >
> > /* what IP to use for this? */
> > switch (adev->ip_versions[GC_HWIP]) {
> > + case IP_VERSION(9, 0, 1):
> > + case IP_VERSION(9, 1, 0):
> > + case IP_VERSION(9, 2, 1):
> > + case IP_VERSION(9, 2, 2):
> > + case IP_VERSION(9, 3, 0):
> > + case IP_VERSION(9, 4, 0):
> > + case IP_VERSION(9, 4, 1):
> > + case IP_VERSION(9, 4, 2):
> > + amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
> > + break;
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -599,6 +828,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >
> > /* use GC or MMHUB IP version */
> > switch (adev->ip_versions[GC_HWIP]) {
> > + case IP_VERSION(9, 0, 1):
> > + case IP_VERSION(9, 1, 0):
> > + case IP_VERSION(9, 2, 1):
> > + case IP_VERSION(9, 2, 2):
> > + case IP_VERSION(9, 3, 0):
> > + case IP_VERSION(9, 4, 0):
> > + case IP_VERSION(9, 4, 1):
> > + case IP_VERSION(9, 4, 2):
> > + amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
> > + break;
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -616,6 +855,18 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > switch (adev->ip_versions[OSSSYS_HWIP]) {
> > + case IP_VERSION(4, 0, 0):
> > + case IP_VERSION(4, 0, 1):
> > + case IP_VERSION(4, 1, 0):
> > + case IP_VERSION(4, 1, 1):
> > + case IP_VERSION(4, 3, 0):
> > + amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
> > + break;
> > + case IP_VERSION(4, 2, 0):
> > + case IP_VERSION(4, 2, 1):
> > + case IP_VERSION(4, 4, 0):
> > + amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
> > + break;
> > case IP_VERSION(5, 0, 0):
> > case IP_VERSION(5, 0, 1):
> > case IP_VERSION(5, 0, 2):
> > @@ -630,7 +881,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >
> > if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> > switch (adev->ip_versions[MP0_HWIP]) {
> > + case IP_VERSION(9, 0, 0):
> > + amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
> > + break;
> > + case IP_VERSION(10, 0, 0):
> > + case IP_VERSION(10, 0, 1):
> > + amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
> > + break;
> > case IP_VERSION(11, 0, 0):
> > + case IP_VERSION(11, 0, 2):
> > + case IP_VERSION(11, 0, 4):
> > case IP_VERSION(11, 0, 5):
> > case IP_VERSION(11, 0, 9):
> > case IP_VERSION(11, 0, 7):
> > @@ -643,7 +903,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > case IP_VERSION(11, 0, 8):
> > amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
> > break;
> > + case IP_VERSION(11, 0, 3):
> > + case IP_VERSION(12, 0, 1):
> > + amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
> > + break;
> > case IP_VERSION(13, 0, 1):
> > + case IP_VERSION(13, 0, 2):
> > case IP_VERSION(13, 0, 3):
> > amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
> > break;
> > @@ -654,6 +919,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >
> > if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> > switch (adev->ip_versions[MP1_HWIP]) {
> > + case IP_VERSION(9, 0, 0):
> > + case IP_VERSION(10, 0, 0):
> > + case IP_VERSION(10, 0, 1):
> > + case IP_VERSION(11, 0, 2):
> > + if (adev->asic_type == CHIP_ARCTURUS)
> > + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> > + else
> > + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> > + break;
> > case IP_VERSION(11, 0, 0):
> > case IP_VERSION(11, 0, 9):
> > case IP_VERSION(11, 0, 7):
> > @@ -664,7 +938,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > case IP_VERSION(11, 5, 0):
> > amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> > break;
> > + case IP_VERSION(12, 0, 0):
> > + case IP_VERSION(12, 0, 1):
> > + amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
> > + break;
> > case IP_VERSION(13, 0, 1):
> > + case IP_VERSION(13, 0, 2):
> > case IP_VERSION(13, 0, 3):
> > amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
> > break;
> > @@ -676,10 +955,13 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
> > amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
> > #if defined(CONFIG_DRM_AMD_DC)
> > - } else {
> > + } else if (adev->ip_versions[DCE_HWIP]) {
> > switch (adev->ip_versions[DCE_HWIP]) {
> > + case IP_VERSION(1, 0, 0):
> > + case IP_VERSION(1, 0, 1):
> > case IP_VERSION(2, 0, 2):
> > case IP_VERSION(2, 0, 0):
> > + case IP_VERSION(2, 1, 0):
> > case IP_VERSION(3, 0, 0):
> > case IP_VERSION(3, 0, 2):
> > case IP_VERSION(3, 0, 3):
> > @@ -693,10 +975,29 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > default:
> > return -EINVAL;
> > }
> > -
> > + } else if (adev->ip_versions[DCI_HWIP]) {
> > + switch (adev->ip_versions[DCI_HWIP]) {
> > + case IP_VERSION(12, 0, 0):
> > + case IP_VERSION(12, 0, 1):
> > + case IP_VERSION(12, 1, 0):
> > + amdgpu_device_ip_block_add(adev, &dm_ip_block);
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > }
> > #endif
> > switch (adev->ip_versions[GC_HWIP]) {
> > + case IP_VERSION(9, 0, 1):
> > + case IP_VERSION(9, 1, 0):
> > + case IP_VERSION(9, 2, 1):
> > + case IP_VERSION(9, 2, 2):
> > + case IP_VERSION(9, 3, 0):
> > + case IP_VERSION(9, 4, 0):
> > + case IP_VERSION(9, 4, 1):
> > + case IP_VERSION(9, 4, 2):
> > + amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
> > + break;
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 2):
> > case IP_VERSION(10, 1, 1):
> > @@ -714,6 +1015,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > switch (adev->ip_versions[SDMA0_HWIP]) {
> > + case IP_VERSION(4, 0, 0):
> > + case IP_VERSION(4, 0, 1):
> > + case IP_VERSION(4, 1, 0):
> > + case IP_VERSION(4, 1, 1):
> > + case IP_VERSION(4, 1, 2):
> > + case IP_VERSION(4, 2, 0):
> > + case IP_VERSION(4, 2, 2):
> > + case IP_VERSION(4, 4, 0):
> > + amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
> > + break;
> > case IP_VERSION(5, 0, 0):
> > case IP_VERSION(5, 0, 1):
> > case IP_VERSION(5, 0, 2):
> > @@ -734,6 +1045,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >
> > if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> > switch (adev->ip_versions[MP1_HWIP]) {
> > + case IP_VERSION(9, 0, 0):
> > + case IP_VERSION(10, 0, 0):
> > + case IP_VERSION(10, 0, 1):
> > + case IP_VERSION(11, 0, 2):
> > + if (adev->asic_type == CHIP_ARCTURUS)
> > + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> > + else
> > + amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
> > + break;
> > case IP_VERSION(11, 0, 0):
> > case IP_VERSION(11, 0, 9):
> > case IP_VERSION(11, 0, 7):
> > @@ -744,7 +1064,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > case IP_VERSION(11, 5, 0):
> > amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> > break;
> > + case IP_VERSION(12, 0, 0):
> > + case IP_VERSION(12, 0, 1):
> > + amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
> > + break;
> > case IP_VERSION(13, 0, 1):
> > + case IP_VERSION(13, 0, 2):
> > case IP_VERSION(13, 0, 3):
> > amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
> > break;
> > @@ -753,26 +1078,58 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> > }
> >
> > - switch (adev->ip_versions[UVD_HWIP]) {
> > - case IP_VERSION(2, 0, 0):
> > - case IP_VERSION(2, 0, 2):
> > - amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
> > - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> > - break;
> > - case IP_VERSION(2, 0, 3):
> > - break;
> > - case IP_VERSION(3, 0, 0):
> > - case IP_VERSION(3, 0, 16):
> > - case IP_VERSION(3, 1, 1):
> > - case IP_VERSION(3, 0, 2):
> > - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> > - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
> > - break;
> > - case IP_VERSION(3, 0, 33):
> > - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> > - break;
> > - default:
> > - return -EINVAL;
> > + if (adev->ip_versions[VCE_HWIP]) {
> > + switch (adev->ip_versions[UVD_HWIP]) {
> > + case IP_VERSION(7, 0, 0):
> > + case IP_VERSION(7, 2, 0):
> > + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > + switch (adev->ip_versions[VCE_HWIP]) {
> > + case IP_VERSION(4, 0, 0):
> > + case IP_VERSION(4, 1, 0):
> > + amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > + } else {
> > + switch (adev->ip_versions[UVD_HWIP]) {
> > + case IP_VERSION(1, 0, 0):
> > + case IP_VERSION(1, 0, 1):
> > + amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
> > + break;
> > + case IP_VERSION(2, 0, 0):
> > + case IP_VERSION(2, 0, 2):
> > + case IP_VERSION(2, 2, 0):
> > + amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
> > + amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> > + break;
> > + case IP_VERSION(2, 0, 3):
> > + break;
> > + case IP_VERSION(2, 5, 0):
> > + amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
> > + amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
> > + break;
> > + case IP_VERSION(2, 6, 0):
> > + amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
> > + amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
> > + break;
> > + case IP_VERSION(3, 0, 0):
> > + case IP_VERSION(3, 0, 16):
> > + case IP_VERSION(3, 1, 1):
> > + case IP_VERSION(3, 0, 2):
> > + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> > + amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
> > + break;
> > + case IP_VERSION(3, 0, 33):
> > + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > if (adev->enable_mes) {
> >
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 34/66] drm/amdgpu/soc15: get rev_id in soc15_common_early_init
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (32 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 35/66] drm/amdgpu: drive all vega asics from the IP discovery table Alex Deucher
` (32 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
for consistency with other SoCs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index dffe7d7ff9e2..f26d33faa0cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1155,7 +1155,7 @@ static int soc15_common_early_init(void *handle)
adev->se_cac_rreg = &soc15_se_cac_rreg;
adev->se_cac_wreg = &soc15_se_cac_wreg;
-
+ adev->rev_id = soc15_get_rev_id(adev);
adev->external_rev_id = 0xFF;
switch (adev->asic_type) {
case CHIP_VEGA10:
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 35/66] drm/amdgpu: drive all vega asics from the IP discovery table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (33 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 34/66] drm/amdgpu/soc15: get rev_id in soc15_common_early_init Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 36/66] drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support Alex Deucher
` (31 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Rather than hardcoding based on asic_type, use the IP
discovery table to configure the driver.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2bf18bc30f69..d64e5a209cf4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2126,22 +2126,6 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
if (r)
return r;
break;
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
- if (adev->flags & AMD_IS_APU)
- adev->family = AMDGPU_FAMILY_RV;
- else
- adev->family = AMDGPU_FAMILY_AI;
-
- r = soc15_set_ip_blocks(adev);
- if (r)
- return r;
- break;
default:
r = amdgpu_discovery_set_ip_blocks(adev);
if (r)
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 36/66] drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (34 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 35/66] drm/amdgpu: drive all vega asics from the IP discovery table Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-23 15:58 ` Harry Wentland
2021-09-21 18:06 ` [PATCH 37/66] drm/amdgpu/display/dm: convert RAVEN to IP version checking Alex Deucher
` (30 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
We are not going to support any new chips with the old
non-DC code so make it the default.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d64e5a209cf4..3f2686296f5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3212,13 +3212,15 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
case CHIP_VANGOGH:
case CHIP_YELLOW_CARP:
#endif
+ default:
return amdgpu_dc != 0;
-#endif
+#else
default:
if (amdgpu_dc > 0)
DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
"but isn't supported by ASIC, ignoring\n");
return false;
+#endif
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 36/66] drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support
2021-09-21 18:06 ` [PATCH 36/66] drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support Alex Deucher
@ 2021-09-23 15:58 ` Harry Wentland
0 siblings, 0 replies; 106+ messages in thread
From: Harry Wentland @ 2021-09-23 15:58 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 2021-09-21 14:06, Alex Deucher wrote:
> We are not going to support any new chips with the old
> non-DC code so make it the default.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index d64e5a209cf4..3f2686296f5b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3212,13 +3212,15 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
> case CHIP_VANGOGH:
> case CHIP_YELLOW_CARP:
> #endif
> + default:
> return amdgpu_dc != 0;
> -#endif
> +#else
> default:
> if (amdgpu_dc > 0)
> DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
> "but isn't supported by ASIC, ignoring\n");
> return false;
> +#endif
> }
> }
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 37/66] drm/amdgpu/display/dm: convert RAVEN to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (35 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 36/66] drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 38/66] drm/amdgpu/sdma4.0: convert " Alex Deucher
` (29 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 +++++--------------
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e189d72f08e9..519930fe79a2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1341,7 +1341,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_CARRIZO:
case CHIP_STONEY:
- case CHIP_RAVEN:
init_data.flags.gpu_vm_support = true;
break;
default:
@@ -1351,6 +1350,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
init_data.flags.disable_dmcu = true;
break;
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
@@ -4183,17 +4184,11 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
goto fail;
}
break;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- case CHIP_RAVEN:
- if (dcn10_register_irq_handlers(dm->adev)) {
- DRM_ERROR("DM: Failed to initialize IRQ\n");
- goto fail;
- }
- break;
-#endif
default:
#if defined(CONFIG_DRM_AMD_DC_DCN)
switch (adev->ip_versions[DCE_HWIP]) {
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
case IP_VERSION(2, 0, 2):
case IP_VERSION(2, 0, 0):
case IP_VERSION(2, 1, 0):
@@ -4360,13 +4355,6 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- case CHIP_RAVEN:
- adev->mode_info.num_crtc = 4;
- adev->mode_info.num_hpd = 4;
- adev->mode_info.num_dig = 4;
- break;
-#endif
default:
#if defined(CONFIG_DRM_AMD_DC_DCN)
switch (adev->ip_versions[DCE_HWIP]) {
@@ -4387,6 +4375,8 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 2;
adev->mode_info.num_dig = 2;
break;
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
case IP_VERSION(3, 0, 1):
case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 1, 2):
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 38/66] drm/amdgpu/sdma4.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (36 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 37/66] drm/amdgpu/display/dm: convert RAVEN to IP version checking Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 39/66] drm/amdgpu/hdp4.0: " Alex Deucher
` (28 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 107 ++++++++++++++-----------
1 file changed, 60 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 8931000dcd41..3219dca3e44f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -469,8 +469,8 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma_4,
ARRAY_SIZE(golden_settings_sdma_4));
@@ -478,7 +478,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_vg10,
ARRAY_SIZE(golden_settings_sdma_vg10));
break;
- case CHIP_VEGA12:
+ case IP_VERSION(4, 0, 1):
soc15_program_register_sequence(adev,
golden_settings_sdma_4,
ARRAY_SIZE(golden_settings_sdma_4));
@@ -486,7 +486,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_vg12,
ARRAY_SIZE(golden_settings_sdma_vg12));
break;
- case CHIP_VEGA20:
+ case IP_VERSION(4, 2, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma0_4_2_init,
ARRAY_SIZE(golden_settings_sdma0_4_2_init));
@@ -497,17 +497,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma1_4_2,
ARRAY_SIZE(golden_settings_sdma1_4_2));
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(4, 2, 2):
soc15_program_register_sequence(adev,
golden_settings_sdma_arct,
ARRAY_SIZE(golden_settings_sdma_arct));
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(4, 4, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma_aldebaran,
ARRAY_SIZE(golden_settings_sdma_aldebaran));
break;
- case CHIP_RAVEN:
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
soc15_program_register_sequence(adev,
golden_settings_sdma_4_1,
ARRAY_SIZE(golden_settings_sdma_4_1));
@@ -520,7 +521,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_rv1,
ARRAY_SIZE(golden_settings_sdma_rv1));
break;
- case CHIP_RENOIR:
+ case IP_VERSION(4, 1, 2):
soc15_program_register_sequence(adev,
golden_settings_sdma_4_3,
ARRAY_SIZE(golden_settings_sdma_4_3));
@@ -538,12 +539,12 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
* The only chips with SDMAv4 and ULV are VG10 and VG20.
* Server SKUs take a different hysteresis setting from other SKUs.
*/
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
if (adev->pdev->device == 0x6860)
break;
return;
- case CHIP_VEGA20:
+ case IP_VERSION(4, 2, 0):
if (adev->pdev->device == 0x66a1)
break;
return;
@@ -589,8 +590,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
/* arcturus shares the same FW memory across
all SDMA isntances */
- if (adev->asic_type == CHIP_ARCTURUS ||
- adev->asic_type == CHIP_ALDEBARAN)
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
+ adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0))
break;
}
@@ -620,17 +621,18 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
chip_name = "vega10";
break;
- case CHIP_VEGA12:
+ case IP_VERSION(4, 0, 1):
chip_name = "vega12";
break;
- case CHIP_VEGA20:
+ case IP_VERSION(4, 2, 0):
chip_name = "vega20";
break;
- case CHIP_RAVEN:
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
chip_name = "raven2";
else if (adev->apu_flags & AMD_APU_IS_PICASSO)
@@ -638,16 +640,16 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
else
chip_name = "raven";
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(4, 2, 2):
chip_name = "arcturus";
break;
- case CHIP_RENOIR:
+ case IP_VERSION(4, 1, 2):
if (adev->apu_flags & AMD_APU_IS_RENOIR)
chip_name = "renoir";
else
chip_name = "green_sardine";
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(4, 4, 0):
chip_name = "aldebaran";
break;
default:
@@ -665,8 +667,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
goto out;
for (i = 1; i < adev->sdma.num_instances; i++) {
- if (adev->asic_type == CHIP_ARCTURUS ||
- adev->asic_type == CHIP_ALDEBARAN) {
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
+ adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0)) {
/* Acturus & Aldebaran will leverage the same FW memory
for every SDMA instance */
memcpy((void *)&adev->sdma.instance[i],
@@ -1106,7 +1108,7 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
* Arcturus for the moment and firmware version 14
* and above.
*/
- if (adev->asic_type == CHIP_ARCTURUS &&
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) &&
adev->sdma.instance[i].fw_version >= 14)
WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
/* Extend page fault timeout to avoid interrupt storm */
@@ -1393,9 +1395,10 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
return;
- switch (adev->asic_type) {
- case CHIP_RAVEN:
- case CHIP_RENOIR:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 1, 2):
sdma_v4_1_init_power_gating(adev);
sdma_v4_1_update_power_gating(adev, true);
break;
@@ -1835,13 +1838,13 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
{
uint fw_version = adev->sdma.instance[0].fw_version;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
return fw_version >= 430;
- case CHIP_VEGA12:
+ case IP_VERSION(4, 0, 1):
/*return fw_version >= 31;*/
return false;
- case CHIP_VEGA20:
+ case IP_VERSION(4, 2, 0):
return fw_version >= 123;
default:
return false;
@@ -1853,14 +1856,22 @@ static int sdma_v4_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
- if (adev->flags & AMD_IS_APU)
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 1, 2):
adev->sdma.num_instances = 1;
- else if (adev->asic_type == CHIP_ARCTURUS)
+ break;
+ case IP_VERSION(4, 2, 2):
adev->sdma.num_instances = 8;
- else if (adev->asic_type == CHIP_ALDEBARAN)
+ break;
+ case IP_VERSION(4, 4, 0):
adev->sdma.num_instances = 5;
- else
+ break;
+ default:
adev->sdma.num_instances = 2;
+ break;
+ }
r = sdma_v4_0_init_microcode(adev);
if (r) {
@@ -1869,7 +1880,8 @@ static int sdma_v4_0_early_init(void *handle)
}
/* TODO: Page queue breaks driver reload under SRIOV */
- if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
+ if ((adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 0, 0)) &&
+ amdgpu_sriov_vf((adev)))
adev->sdma.has_page_queue = false;
else if (sdma_v4_0_fw_support_paging_queue(adev))
adev->sdma.has_page_queue = true;
@@ -2141,14 +2153,14 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
amdgpu_fence_process(&adev->sdma.instance[instance].ring);
break;
case 1:
- if (adev->asic_type == CHIP_VEGA20)
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 0))
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
case 2:
/* XXX compute */
break;
case 3:
- if (adev->asic_type != CHIP_VEGA20)
+ if (adev->ip_versions[SDMA0_HWIP] != IP_VERSION(4, 2, 0))
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
}
@@ -2364,9 +2376,10 @@ static int sdma_v4_0_set_powergating_state(void *handle,
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->asic_type) {
- case CHIP_RAVEN:
- case CHIP_RENOIR:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 1, 2):
sdma_v4_1_update_power_gating(adev,
state == AMD_PG_STATE_GATE);
break;
@@ -2551,7 +2564,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
int i;
for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
adev->sdma.instance[i].ring.funcs =
&sdma_v4_0_ring_funcs_2nd_mmhub;
else
@@ -2559,7 +2572,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
&sdma_v4_0_ring_funcs;
adev->sdma.instance[i].ring.me = i;
if (adev->sdma.has_page_queue) {
- if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
adev->sdma.instance[i].page.funcs =
&sdma_v4_0_page_ring_funcs_2nd_mmhub;
else
@@ -2786,12 +2799,12 @@ static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_VEGA20:
- case CHIP_ARCTURUS:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 2, 0):
+ case IP_VERSION(4, 2, 2):
adev->sdma.funcs = &sdma_v4_0_ras_funcs;
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(4, 4, 0):
adev->sdma.funcs = &sdma_v4_4_ras_funcs;
break;
default:
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 39/66] drm/amdgpu/hdp4.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (37 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 38/66] drm/amdgpu/sdma4.0: convert " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 40/66] drm/amdgpu/gfx9.0: " Alex Deucher
` (27 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index 74b90cc2bf48..88938115557b 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -49,7 +49,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
struct amdgpu_ring *ring)
{
- if (adev->asic_type == CHIP_ALDEBARAN)
+ if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 4, 0))
return;
if (!ring || !ring->funcs->emit_wreg)
@@ -79,7 +79,7 @@ static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
return;
- if (adev->asic_type >= CHIP_ALDEBARAN)
+ if (adev->ip_versions[HDP_HWIP] >= IP_VERSION(4, 4, 0))
WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
else
/*read back hdp ras counter to reset it to 0 */
@@ -91,9 +91,10 @@ static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
{
uint32_t def, data;
- if (adev->asic_type == CHIP_VEGA10 ||
- adev->asic_type == CHIP_VEGA12 ||
- adev->asic_type == CHIP_RAVEN) {
+ if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 0) ||
+ adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 1) ||
+ adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 1) ||
+ adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 0)) {
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
@@ -135,8 +136,8 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_ARCTURUS:
+ switch (adev->ip_versions[HDP_HWIP]) {
+ case IP_VERSION(4, 2, 1):
WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
break;
default:
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 40/66] drm/amdgpu/gfx9.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (38 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 39/66] drm/amdgpu/hdp4.0: " Alex Deucher
@ 2021-09-21 18:06 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 41/66] drm/amdgpu/amdgpu_psp: " Alex Deucher
` (26 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:06 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 227 ++++++++++++++------------
1 file changed, 120 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d9be1b773085..3a160d78c98f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -953,8 +953,8 @@ static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
soc15_program_register_sequence(adev,
golden_settings_gc_9_0,
ARRAY_SIZE(golden_settings_gc_9_0));
@@ -962,7 +962,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_9_0_vg10,
ARRAY_SIZE(golden_settings_gc_9_0_vg10));
break;
- case CHIP_VEGA12:
+ case IP_VERSION(9, 2, 1):
soc15_program_register_sequence(adev,
golden_settings_gc_9_2_1,
ARRAY_SIZE(golden_settings_gc_9_2_1));
@@ -970,7 +970,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_9_2_1_vg12,
ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
break;
- case CHIP_VEGA20:
+ case IP_VERSION(9, 4, 0):
soc15_program_register_sequence(adev,
golden_settings_gc_9_0,
ARRAY_SIZE(golden_settings_gc_9_0));
@@ -978,12 +978,13 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_9_0_vg20,
ARRAY_SIZE(golden_settings_gc_9_0_vg20));
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(9, 4, 1):
soc15_program_register_sequence(adev,
golden_settings_gc_9_4_1_arct,
ARRAY_SIZE(golden_settings_gc_9_4_1_arct));
break;
- case CHIP_RAVEN:
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
soc15_program_register_sequence(adev, golden_settings_gc_9_1,
ARRAY_SIZE(golden_settings_gc_9_1));
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
@@ -995,12 +996,12 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_9_1_rv1,
ARRAY_SIZE(golden_settings_gc_9_1_rv1));
break;
- case CHIP_RENOIR:
+ case IP_VERSION(9, 3, 0):
soc15_program_register_sequence(adev,
golden_settings_gc_9_1_rn,
ARRAY_SIZE(golden_settings_gc_9_1_rn));
return; /* for renoir, don't need common goldensetting */
- case CHIP_ALDEBARAN:
+ case IP_VERSION(9, 4, 2):
gfx_v9_4_2_init_golden_registers(adev,
adev->smuio.funcs->get_die_id(adev));
break;
@@ -1008,8 +1009,8 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
break;
}
- if ((adev->asic_type != CHIP_ARCTURUS) &&
- (adev->asic_type != CHIP_ALDEBARAN))
+ if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
+ (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2)))
soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
}
@@ -1193,15 +1194,15 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
adev->gfx.me_fw_write_wait = false;
adev->gfx.mec_fw_write_wait = false;
- if ((adev->asic_type != CHIP_ARCTURUS) &&
+ if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
((adev->gfx.mec_fw_version < 0x000001a5) ||
(adev->gfx.mec_feature_version < 46) ||
(adev->gfx.pfp_fw_version < 0x000000b7) ||
(adev->gfx.pfp_feature_version < 46)))
DRM_WARN_ONCE("CP firmware version too old, please update!");
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
if ((adev->gfx.me_fw_version >= 0x0000009c) &&
(adev->gfx.me_feature_version >= 42) &&
(adev->gfx.pfp_fw_version >= 0x000000b1) &&
@@ -1212,7 +1213,7 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
(adev->gfx.mec_feature_version >= 42))
adev->gfx.mec_fw_write_wait = true;
break;
- case CHIP_VEGA12:
+ case IP_VERSION(9, 2, 1):
if ((adev->gfx.me_fw_version >= 0x0000009c) &&
(adev->gfx.me_feature_version >= 44) &&
(adev->gfx.pfp_fw_version >= 0x000000b2) &&
@@ -1223,7 +1224,7 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
(adev->gfx.mec_feature_version >= 44))
adev->gfx.mec_fw_write_wait = true;
break;
- case CHIP_VEGA20:
+ case IP_VERSION(9, 4, 0):
if ((adev->gfx.me_fw_version >= 0x0000009c) &&
(adev->gfx.me_feature_version >= 44) &&
(adev->gfx.pfp_fw_version >= 0x000000b2) &&
@@ -1234,7 +1235,8 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
(adev->gfx.mec_feature_version >= 44))
adev->gfx.mec_fw_write_wait = true;
break;
- case CHIP_RAVEN:
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
if ((adev->gfx.me_fw_version >= 0x0000009c) &&
(adev->gfx.me_feature_version >= 42) &&
(adev->gfx.pfp_fw_version >= 0x000000b1) &&
@@ -1299,7 +1301,7 @@ static bool is_raven_kicker(struct amdgpu_device *adev)
static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
{
- if ((adev->asic_type == CHIP_RENOIR) &&
+ if ((adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0)) &&
(adev->gfx.me_fw_version >= 0x000000a5) &&
(adev->gfx.me_feature_version >= 52))
return true;
@@ -1312,12 +1314,13 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
break;
- case CHIP_RAVEN:
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
(adev->apu_flags & AMD_APU_IS_PICASSO)) &&
((!is_raven_kicker(adev) &&
@@ -1331,7 +1334,7 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_RLC_SMU_HS;
break;
- case CHIP_RENOIR:
+ case IP_VERSION(9, 3, 0):
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_CP |
@@ -1555,9 +1558,9 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)
{
- if (adev->asic_type == CHIP_ALDEBARAN ||
- adev->asic_type == CHIP_ARCTURUS ||
- adev->asic_type == CHIP_RENOIR)
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2) ||
+ adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
+ adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0))
return false;
return true;
@@ -1665,17 +1668,18 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
chip_name = "vega10";
break;
- case CHIP_VEGA12:
+ case IP_VERSION(9, 2, 1):
chip_name = "vega12";
break;
- case CHIP_VEGA20:
+ case IP_VERSION(9, 4, 0):
chip_name = "vega20";
break;
- case CHIP_RAVEN:
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
chip_name = "raven2";
else if (adev->apu_flags & AMD_APU_IS_PICASSO)
@@ -1683,16 +1687,16 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
else
chip_name = "raven";
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(9, 4, 1):
chip_name = "arcturus";
break;
- case CHIP_RENOIR:
+ case IP_VERSION(9, 3, 0):
if (adev->apu_flags & AMD_APU_IS_RENOIR)
chip_name = "renoir";
else
chip_name = "green_sardine";
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(9, 4, 2):
chip_name = "aldebaran";
break;
default:
@@ -1796,7 +1800,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
if (adev->flags & AMD_IS_APU)
always_on_cu_num = 4;
- else if (adev->asic_type == CHIP_VEGA12)
+ else if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1))
always_on_cu_num = 8;
else
always_on_cu_num = 12;
@@ -1965,11 +1969,12 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
return r;
}
- switch (adev->asic_type) {
- case CHIP_RAVEN:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
gfx_v9_0_init_lbpw(adev);
break;
- case CHIP_VEGA20:
+ case IP_VERSION(9, 4, 0):
gfx_v9_4_init_lbpw(adev);
break;
default:
@@ -2144,8 +2149,8 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -2153,7 +2158,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
break;
- case CHIP_VEGA12:
+ case IP_VERSION(9, 2, 1):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -2162,7 +2167,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
DRM_INFO("fix gfx.config for vega12\n");
break;
- case CHIP_VEGA20:
+ case IP_VERSION(9, 4, 0):
adev->gfx.ras_funcs = &gfx_v9_0_ras_funcs;
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
@@ -2177,7 +2182,8 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
if (err)
return err;
break;
- case CHIP_RAVEN:
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -2188,7 +2194,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
else
gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(9, 4, 1):
adev->gfx.ras_funcs = &gfx_v9_4_ras_funcs;
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
@@ -2199,7 +2205,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
gb_addr_config &= ~0xf3e777ff;
gb_addr_config |= 0x22014042;
break;
- case CHIP_RENOIR:
+ case IP_VERSION(9, 3, 0):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -2209,7 +2215,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
gb_addr_config &= ~0xf3e777ff;
gb_addr_config |= 0x22010042;
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(9, 4, 2):
adev->gfx.ras_funcs = &gfx_v9_4_2_ras_funcs;
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
@@ -2307,14 +2313,15 @@ static int gfx_v9_0_sw_init(void *handle)
struct amdgpu_kiq *kiq;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 2):
adev->gfx.mec.num_mec = 2;
break;
default:
@@ -2598,8 +2605,8 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
{
uint32_t tmp;
- switch (adev->asic_type) {
- case CHIP_ARCTURUS:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 4, 1):
tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
DISABLE_BARRIER_WAITCNT, 1);
@@ -2934,7 +2941,7 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
/* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
- if (adev->asic_type != CHIP_RENOIR)
+ if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 3, 0))
pwr_10_0_gfxip_control_over_cgpg(adev, true);
}
}
@@ -3046,7 +3053,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
* And it's needed by gfxoff feature.
*/
if (adev->gfx.rlc.is_rlc_v2_1) {
- if (adev->asic_type == CHIP_VEGA12 ||
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1) ||
(adev->apu_flags & AMD_APU_IS_RAVEN2))
gfx_v9_1_init_rlc_save_restore_list(adev);
gfx_v9_0_enable_save_restore_machine(adev);
@@ -3159,14 +3166,15 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
return r;
}
- switch (adev->asic_type) {
- case CHIP_RAVEN:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
if (amdgpu_lbpw == 0)
gfx_v9_0_enable_lbpw(adev, false);
else
gfx_v9_0_enable_lbpw(adev, true);
break;
- case CHIP_VEGA20:
+ case IP_VERSION(9, 4, 0):
if (amdgpu_lbpw > 0)
gfx_v9_0_enable_lbpw(adev, true);
else
@@ -3961,8 +3969,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
{
u32 tmp;
- if (adev->asic_type != CHIP_ARCTURUS &&
- adev->asic_type != CHIP_ALDEBARAN)
+ if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1) &&
+ adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2))
return;
tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
@@ -4002,7 +4010,7 @@ static int gfx_v9_0_hw_init(void *handle)
if (r)
return r;
- if (adev->asic_type == CHIP_ALDEBARAN)
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
gfx_v9_4_2_set_power_brake_sequence(adev);
return r;
@@ -4234,7 +4242,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->gfx.gpu_clock_mutex);
- if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
clock = gfx_v9_0_kiq_read_clock(adev);
} else {
WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
@@ -4584,7 +4592,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
if (!ring->sched.ready)
return 0;
- if (adev->asic_type == CHIP_ARCTURUS) {
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1)) {
vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
@@ -4734,8 +4742,8 @@ static int gfx_v9_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->asic_type == CHIP_ARCTURUS ||
- adev->asic_type == CHIP_ALDEBARAN)
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
+ adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
adev->gfx.num_gfx_rings = 0;
else
adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
@@ -4769,7 +4777,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
}
/* requires IBs so do in late init after IB pool is initialized */
- if (adev->asic_type == CHIP_ALDEBARAN)
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
else
r = gfx_v9_0_do_edc_gpr_workarounds(adev);
@@ -4897,7 +4905,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
/* 1 - RLC_CGTT_MGCG_OVERRIDE */
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
- if (adev->asic_type != CHIP_VEGA12)
+ if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
@@ -4931,7 +4939,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
/* 1 - MGCG_OVERRIDE */
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
- if (adev->asic_type != CHIP_VEGA12)
+ if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
@@ -5037,7 +5045,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
/* enable cgcg FSM(0x0000363F) */
def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
- if (adev->asic_type == CHIP_ARCTURUS)
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1))
data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
else
@@ -5163,9 +5171,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_PG_STATE_GATE);
- switch (adev->asic_type) {
- case CHIP_RAVEN:
- case CHIP_RENOIR:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 3, 0):
if (!enable)
amdgpu_gfx_off_ctrl(adev, false);
@@ -5191,7 +5200,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
if (enable)
amdgpu_gfx_off_ctrl(adev, true);
break;
- case CHIP_VEGA12:
+ case IP_VERSION(9, 2, 1):
amdgpu_gfx_off_ctrl(adev, enable);
break;
default:
@@ -5209,14 +5218,15 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 2):
gfx_v9_0_update_gfx_clock_gating(adev,
state == AMD_CG_STATE_GATE);
break;
@@ -5258,7 +5268,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) {
/* AMD_CG_SUPPORT_GFX_3D_CGCG */
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
@@ -7029,14 +7039,15 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
- case CHIP_RENOIR:
- case CHIP_ALDEBARAN:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 2):
adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
break;
default:
@@ -7047,17 +7058,18 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
{
/* init asci gds info */
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
adev->gds.gds_size = 0x10000;
break;
- case CHIP_RAVEN:
- case CHIP_ARCTURUS:
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 4, 1):
adev->gds.gds_size = 0x1000;
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(9, 4, 2):
/* aldebaran removed all the GDS internal memory,
* only support GWS opcode in kernel, like barrier
* semaphore.etc */
@@ -7068,24 +7080,25 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
break;
}
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA20:
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 4, 0):
adev->gds.gds_compute_max_wave_id = 0x7ff;
break;
- case CHIP_VEGA12:
+ case IP_VERSION(9, 2, 1):
adev->gds.gds_compute_max_wave_id = 0x27f;
break;
- case CHIP_RAVEN:
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 1, 0):
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
else
adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(9, 4, 1):
adev->gds.gds_compute_max_wave_id = 0xfff;
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(9, 4, 2):
/* deprecated for Aldebaran, no usage at all */
adev->gds.gds_compute_max_wave_id = 0;
break;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 41/66] drm/amdgpu/amdgpu_psp: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (39 preceding siblings ...)
2021-09-21 18:06 ` [PATCH 40/66] drm/amdgpu/gfx9.0: " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 42/66] drm/amdgpu/psp_v11.0: " Alex Deucher
` (25 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 101 ++++++++++++++----------
1 file changed, 58 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7d09b28889af..c47d29689be4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -71,17 +71,25 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp
{
struct amdgpu_device *adev = psp->adev;
- psp->pmfw_centralized_cstate_management = false;
-
- if (amdgpu_sriov_vf(adev))
- return;
-
- if (adev->flags & AMD_IS_APU)
+ if (amdgpu_sriov_vf(adev)) {
+ psp->pmfw_centralized_cstate_management = false;
return;
+ }
- if ((adev->asic_type >= CHIP_ARCTURUS) ||
- (adev->asic_type >= CHIP_NAVI12))
+ switch (adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(11, 0, 4):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
+ case IP_VERSION(13, 0, 2):
psp->pmfw_centralized_cstate_management = true;
+ break;
+ default:
+ psp->pmfw_centralized_cstate_management = false;
+ break;
+ }
}
static int psp_early_init(void *handle)
@@ -89,43 +97,45 @@ static int psp_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
+ switch (adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(9, 0, 0):
psp_v3_1_set_psp_funcs(psp);
psp->autoload_supported = false;
break;
- case CHIP_RAVEN:
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
psp_v10_0_set_psp_funcs(psp);
psp->autoload_supported = false;
break;
- case CHIP_VEGA20:
- case CHIP_ARCTURUS:
+ case IP_VERSION(11, 0, 2):
+ case IP_VERSION(11, 0, 4):
psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = false;
break;
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 5):
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 5, 0):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
- case CHIP_RENOIR:
+ case IP_VERSION(11, 0, 3):
+ case IP_VERSION(12, 0, 1):
psp_v12_0_set_psp_funcs(psp);
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(13, 0, 2):
psp_v13_0_set_psp_funcs(psp);
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
- case CHIP_CYAN_SKILLFISH:
+ case IP_VERSION(11, 0, 8):
if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
psp_v11_0_8_set_psp_funcs(psp);
psp->autoload_supported = false;
@@ -268,7 +278,8 @@ static int psp_sw_init(void *handle)
DRM_ERROR("Failed to load psp firmware!\n");
return ret;
}
- } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) {
+ } else if (amdgpu_sriov_vf(adev) &&
+ adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2)) {
ret = psp_init_ta_microcode(psp, "aldebaran");
if (ret) {
DRM_ERROR("Failed to initialize ta microcode!\n");
@@ -311,7 +322,8 @@ static int psp_sw_init(void *handle)
}
}
- if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
+ if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
+ adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7)) {
ret= psp_sysfs_init(adev);
if (ret) {
return ret;
@@ -341,8 +353,8 @@ static int psp_sw_fini(void *handle)
psp->ta_fw = NULL;
}
- if (adev->asic_type == CHIP_NAVI10 ||
- adev->asic_type == CHIP_SIENNA_CICHLID)
+ if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
+ adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7))
psp_sysfs_fini(adev);
kfree(cmd);
@@ -601,10 +613,10 @@ static int psp_tmr_init(struct psp_context *psp)
static bool psp_skip_tmr(struct psp_context *psp)
{
- switch (psp->adev->asic_type) {
- case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
- case CHIP_ALDEBARAN:
+ switch (psp->adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(13, 0, 2):
return true;
default:
return false;
@@ -998,8 +1010,9 @@ int psp_xgmi_terminate(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev;
/* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
- if (adev->asic_type == CHIP_ARCTURUS ||
- (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
+ if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
+ (adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
+ adev->gmc.xgmi.connected_to_cpu))
return 0;
if (!psp->xgmi_context.context.initialized)
@@ -1100,8 +1113,8 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
{
- return psp->adev->asic_type == CHIP_ALDEBARAN &&
- psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;
+ return psp->adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
+ psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;
}
/*
@@ -2219,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp)
if ((amdgpu_in_reset(adev) &&
ras && adev->ras_enabled &&
- (adev->asic_type == CHIP_ARCTURUS ||
- adev->asic_type == CHIP_VEGA20))) {
+ (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
+ adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 2)))) {
ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
if (ret) {
DRM_WARN("Failed to set MP1 state prepare for reload\n");
@@ -2317,8 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
continue;
if (psp->autoload_supported &&
- (adev->asic_type >= CHIP_SIENNA_CICHLID &&
- adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
+ (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7) ||
+ adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 11) ||
+ adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 12)) &&
(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
@@ -2905,7 +2919,8 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
ucode_array_start_addr = (uint8_t *)sos_hdr +
le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
- if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) {
+ if (adev->gmc.xgmi.connected_to_cpu ||
+ (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2))) {
adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 42/66] drm/amdgpu/psp_v11.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (40 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 41/66] drm/amdgpu/amdgpu_psp: " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 43/66] drm/amdgpu/psp_v13.0: " Alex Deucher
` (24 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 44 +++++++++++++-------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 3c02e75fd366..13dace5d2855 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -93,35 +93,35 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
DRM_DEBUG("\n");
- switch (adev->asic_type) {
- case CHIP_VEGA20:
+ switch (adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(11, 0, 2):
chip_name = "vega20";
break;
- case CHIP_NAVI10:
+ case IP_VERSION(11, 0, 0):
chip_name = "navi10";
break;
- case CHIP_NAVI14:
+ case IP_VERSION(11, 0, 5):
chip_name = "navi14";
break;
- case CHIP_NAVI12:
+ case IP_VERSION(11, 0, 9):
chip_name = "navi12";
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(11, 0, 4):
chip_name = "arcturus";
break;
- case CHIP_SIENNA_CICHLID:
+ case IP_VERSION(11, 0, 7):
chip_name = "sienna_cichlid";
break;
- case CHIP_NAVY_FLOUNDER:
+ case IP_VERSION(11, 0, 11):
chip_name = "navy_flounder";
break;
- case CHIP_VANGOGH:
+ case IP_VERSION(11, 5, 0):
chip_name = "vangogh";
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(11, 0, 12):
chip_name = "dimgrey_cavefish";
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(11, 0, 13):
chip_name = "beige_goby";
break;
default:
@@ -129,9 +129,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
}
- switch (adev->asic_type) {
- case CHIP_VEGA20:
- case CHIP_ARCTURUS:
+ switch (adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(11, 0, 2):
+ case IP_VERSION(11, 0, 4):
err = psp_init_sos_microcode(psp, chip_name);
if (err)
return err;
@@ -168,9 +168,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
le32_to_cpu(ta_hdr->ras.offset_bytes);
}
break;
- case CHIP_NAVI10:
- case CHIP_NAVI14:
- case CHIP_NAVI12:
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 5):
+ case IP_VERSION(11, 0, 9):
err = psp_init_sos_microcode(psp, chip_name);
if (err)
return err;
@@ -213,9 +213,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
le32_to_cpu(ta_hdr->dtm.offset_bytes);
}
break;
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
err = psp_init_sos_microcode(psp, chip_name);
if (err)
return err;
@@ -223,7 +223,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
if (err)
return err;
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(11, 0, 13):
err = psp_init_sos_microcode(psp, chip_name);
if (err)
return err;
@@ -231,7 +231,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
if (err)
return err;
break;
- case CHIP_VANGOGH:
+ case IP_VERSION(11, 5, 0):
err = psp_init_asd_microcode(psp, chip_name);
if (err)
return err;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 43/66] drm/amdgpu/psp_v13.0: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (41 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 42/66] drm/amdgpu/psp_v11.0: " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 44/66] drm/amdgpu/pm/smu_v11.0: update " Alex Deucher
` (23 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 47a500f64db2..64b52c5ea981 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -47,18 +47,19 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
const char *chip_name;
int err = 0;
- switch (adev->asic_type) {
- case CHIP_ALDEBARAN:
+ switch (adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(13, 0, 2):
chip_name = "aldebaran";
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
chip_name = "yellow_carp";
break;
default:
BUG();
}
- switch (adev->asic_type) {
- case CHIP_ALDEBARAN:
+ switch (adev->ip_versions[MP0_HWIP]) {
+ case IP_VERSION(13, 0, 2):
err = psp_init_sos_microcode(psp, chip_name);
if (err)
return err;
@@ -66,7 +67,8 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
if (err)
return err;
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
err = psp_init_asd_microcode(psp, chip_name);
if (err)
return err;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 44/66] drm/amdgpu/pm/smu_v11.0: update IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (42 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 43/66] drm/amdgpu/psp_v13.0: " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 45/66] drm/amdgpu/pm/smu_v13.0: convert " Alex Deucher
` (22 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 24 +++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 5af7c8b7806f..1ae8b8dc3bd3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -116,12 +116,12 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
case IP_VERSION(11, 0, 13):
chip_name = "beige_goby";
break;
+ case IP_VERSION(11, 0, 2):
+ chip_name = "arcturus";
+ break;
default:
- if (adev->asic_type == CHIP_ARCTURUS) {
- chip_name = "arcturus";
- break;
- }
- dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
+ dev_err(adev->dev, "Unsupported IP version 0x%x\n",
+ adev->ip_versions[MP1_HWIP]);
return -EINVAL;
}
@@ -267,12 +267,12 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
case IP_VERSION(11, 0, 8):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
break;
+ case IP_VERSION(11, 0, 2):
+ smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
+ break;
default:
- if (adev->asic_type == CHIP_ARCTURUS) {
- smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
- break;
- }
- dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
+ dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
+ adev->ip_versions[MP1_HWIP]);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
break;
}
@@ -1653,7 +1653,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
default:
if (!ras || !adev->ras_enabled ||
adev->gmc.xgmi.pending_reset) {
- if (adev->asic_type == CHIP_ARCTURUS) {
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
data |= 0x80000000;
WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
@@ -1935,7 +1935,7 @@ int smu_v11_0_set_performance_level(struct smu_context *smu,
* Separate MCLK and SOCCLK soft min/max settings are not allowed
* on Arcturus.
*/
- if (adev->asic_type == CHIP_ARCTURUS) {
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
mclk_min = mclk_max = 0;
socclk_min = socclk_max = 0;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 45/66] drm/amdgpu/pm/smu_v13.0: convert IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (43 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 44/66] drm/amdgpu/pm/smu_v11.0: update " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-22 8:18 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more " Alex Deucher
` (21 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 22 +++++++++++--------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index a0e50f23b1dd..08f3cc809fc6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -89,12 +89,13 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_ALDEBARAN:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(13, 0, 2):
chip_name = "aldebaran";
break;
default:
- dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
+ dev_err(adev->dev, "Unsupported IP version 0x%x\n",
+ adev->ip_versions[MP1_HWIP]);
return -EINVAL;
}
@@ -210,15 +211,17 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
smu_minor = (smu_version >> 8) & 0xff;
smu_debug = (smu_version >> 0) & 0xff;
- switch (smu->adev->asic_type) {
- case CHIP_ALDEBARAN:
+ switch (smu->adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(13, 0, 2):
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
break;
default:
- dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
+ dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
+ smu->adev->ip_versions[MP1_HWIP]);
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
break;
}
@@ -740,8 +743,9 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
int ret = 0;
struct amdgpu_device *adev = smu->adev;
- switch (adev->asic_type) {
- case CHIP_YELLOW_CARP:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 3):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
if (enable)
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 45/66] drm/amdgpu/pm/smu_v13.0: convert IP version checking
2021-09-21 18:07 ` [PATCH 45/66] drm/amdgpu/pm/smu_v13.0: convert " Alex Deucher
@ 2021-09-22 8:18 ` Lazar, Lijo
0 siblings, 0 replies; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 8:18 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:37 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 22 +++++++++++--------
> 1 file changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index a0e50f23b1dd..08f3cc809fc6 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -89,12 +89,13 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->asic_type) {
> - case CHIP_ALDEBARAN:
> + switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(13, 0, 2):
> chip_name = "aldebaran";
> break;
> default:
> - dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
> + dev_err(adev->dev, "Unsupported IP version 0x%x\n",
> + adev->ip_versions[MP1_HWIP]);
> return -EINVAL;
> }
>
> @@ -210,15 +211,17 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
> smu_minor = (smu_version >> 8) & 0xff;
> smu_debug = (smu_version >> 0) & 0xff;
>
> - switch (smu->adev->asic_type) {
> - case CHIP_ALDEBARAN:
> + switch (smu->adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(13, 0, 2):
> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
> break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 3):
> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
> break;
Ah, there are two versions. Commented about something similar in another
patch. Please ignore.
Thanks,
Lijo
> default:
> - dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
> + dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
> + smu->adev->ip_versions[MP1_HWIP]);
> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
> break;
> }
> @@ -740,8 +743,9 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
> int ret = 0;
> struct amdgpu_device *adev = smu->adev;
>
> - switch (adev->asic_type) {
> - case CHIP_YELLOW_CARP:
> + switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(13, 0, 1):
> + case IP_VERSION(13, 0, 3):
> if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
> return 0;
> if (enable)
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (44 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 45/66] drm/amdgpu/pm/smu_v13.0: convert " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-22 8:16 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 47/66] drm/amdgpu/amdgpu_vcn: convert to " Alex Deucher
` (20 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 ++++++++++-------------
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5f372d353d9d..150cac4ea75c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -455,8 +455,7 @@ static int smu_get_power_num_states(void *handle,
bool is_support_sw_smu(struct amdgpu_device *adev)
{
- if ((adev->asic_type >= CHIP_ARCTURUS) ||
- (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0)))
+ if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
return true;
return false;
@@ -600,23 +599,19 @@ static int smu_set_funcs(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 8):
cyan_skillfish_set_ppt_funcs(smu);
break;
- default:
- switch (adev->asic_type) {
- case CHIP_ARCTURUS:
- adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
- arcturus_set_ppt_funcs(smu);
- /* OD is not supported on Arcturus */
- smu->od_enabled =false;
- break;
- case CHIP_ALDEBARAN:
- aldebaran_set_ppt_funcs(smu);
- /* Enable pp_od_clk_voltage node */
- smu->od_enabled = true;
- break;
- default:
- return -EINVAL;
- }
+ case IP_VERSION(11, 0, 2):
+ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ arcturus_set_ppt_funcs(smu);
+ /* OD is not supported on Arcturus */
+ smu->od_enabled =false;
+ break;
+ case IP_VERSION(13, 0, 2):
+ aldebaran_set_ppt_funcs(smu);
+ /* Enable pp_od_clk_voltage node */
+ smu->od_enabled = true;
break;
+ default:
+ return -EINVAL;
}
return 0;
@@ -2288,11 +2283,11 @@ int smu_get_power_limit(void *handle,
} else {
switch (limit_level) {
case SMU_PPT_LIMIT_CURRENT:
- if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
+ if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 2)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
+ (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
ret = smu_get_asic_power_limits(smu,
&smu->current_power_limit,
NULL,
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP version checking
2021-09-21 18:07 ` [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more " Alex Deucher
@ 2021-09-22 8:16 ` Lazar, Lijo
2021-09-22 16:06 ` Deucher, Alexander
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 8:16 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:37 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 ++++++++++-------------
> 1 file changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 5f372d353d9d..150cac4ea75c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -455,8 +455,7 @@ static int smu_get_power_num_states(void *handle,
>
> bool is_support_sw_smu(struct amdgpu_device *adev)
> {
> - if ((adev->asic_type >= CHIP_ARCTURUS) ||
> - (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0)))
> + if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
> return true;
>
> return false;
> @@ -600,23 +599,19 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> case IP_VERSION(11, 0, 8):
> cyan_skillfish_set_ppt_funcs(smu);
> break;
> - default:
> - switch (adev->asic_type) {
> - case CHIP_ARCTURUS:
> - adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> - arcturus_set_ppt_funcs(smu);
> - /* OD is not supported on Arcturus */
> - smu->od_enabled =false;
> - break;
> - case CHIP_ALDEBARAN:
> - aldebaran_set_ppt_funcs(smu);
> - /* Enable pp_od_clk_voltage node */
> - smu->od_enabled = true;
> - break;
> - default:
> - return -EINVAL;
> - }
> + case IP_VERSION(11, 0, 2):
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> + arcturus_set_ppt_funcs(smu);
> + /* OD is not supported on Arcturus */
> + smu->od_enabled =false;
> + break;
> + case IP_VERSION(13, 0, 2):
> + aldebaran_set_ppt_funcs(smu);
> + /* Enable pp_od_clk_voltage node */
> + smu->od_enabled = true;
> break;
> + default:
> + return -EINVAL;
> }
>
> return 0;
> @@ -2288,11 +2283,11 @@ int smu_get_power_limit(void *handle,
> } else {
> switch (limit_level) {
> case SMU_PPT_LIMIT_CURRENT:
> - if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
> + if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 2)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
Maybe seen/commented before, anyway switch...case
Thanks,
Lijo
> ret = smu_get_asic_power_limits(smu,
> &smu->current_power_limit,
> NULL,
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP version checking
2021-09-22 8:16 ` Lazar, Lijo
@ 2021-09-22 16:06 ` Deucher, Alexander
0 siblings, 0 replies; 106+ messages in thread
From: Deucher, Alexander @ 2021-09-22 16:06 UTC (permalink / raw)
To: Lazar, Lijo, amd-gfx
[-- Attachment #1: Type: text/plain, Size: 4080 bytes --]
[Public]
Fixed locally.
________________________________
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Wednesday, September 22, 2021 4:16 AM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP version checking
On 9/21/2021 11:37 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 ++++++++++-------------
> 1 file changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 5f372d353d9d..150cac4ea75c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -455,8 +455,7 @@ static int smu_get_power_num_states(void *handle,
>
> bool is_support_sw_smu(struct amdgpu_device *adev)
> {
> - if ((adev->asic_type >= CHIP_ARCTURUS) ||
> - (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0)))
> + if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
> return true;
>
> return false;
> @@ -600,23 +599,19 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> case IP_VERSION(11, 0, 8):
> cyan_skillfish_set_ppt_funcs(smu);
> break;
> - default:
> - switch (adev->asic_type) {
> - case CHIP_ARCTURUS:
> - adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> - arcturus_set_ppt_funcs(smu);
> - /* OD is not supported on Arcturus */
> - smu->od_enabled =false;
> - break;
> - case CHIP_ALDEBARAN:
> - aldebaran_set_ppt_funcs(smu);
> - /* Enable pp_od_clk_voltage node */
> - smu->od_enabled = true;
> - break;
> - default:
> - return -EINVAL;
> - }
> + case IP_VERSION(11, 0, 2):
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> + arcturus_set_ppt_funcs(smu);
> + /* OD is not supported on Arcturus */
> + smu->od_enabled =false;
> + break;
> + case IP_VERSION(13, 0, 2):
> + aldebaran_set_ppt_funcs(smu);
> + /* Enable pp_od_clk_voltage node */
> + smu->od_enabled = true;
> break;
> + default:
> + return -EINVAL;
> }
>
> return 0;
> @@ -2288,11 +2283,11 @@ int smu_get_power_limit(void *handle,
> } else {
> switch (limit_level) {
> case SMU_PPT_LIMIT_CURRENT:
> - if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
> + if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 2)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
Maybe seen/commented before, anyway switch...case
Thanks,
Lijo
> ret = smu_get_asic_power_limits(smu,
> &smu->current_power_limit,
> NULL,
>
[-- Attachment #2: Type: text/html, Size: 10246 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 47/66] drm/amdgpu/amdgpu_vcn: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (45 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 48/66] drm/amdgpu/vcn2.5: " Alex Deucher
` (19 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
v2: squash in fix for navy flounder and sienna cichlid
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 47 +++++++++++--------------
1 file changed, 21 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index b60b8fe5bf67..9724f5f5f702 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -86,8 +86,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_vcn_inst; i++)
atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
- switch (adev->asic_type) {
- case CHIP_RAVEN:
+ switch (adev->ip_versions[UVD_HWIP]) {
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
fw_name = FIRMWARE_RAVEN2;
else if (adev->apu_flags & AMD_APU_IS_PICASSO)
@@ -95,13 +96,13 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
else
fw_name = FIRMWARE_RAVEN;
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(2, 5, 0):
fw_name = FIRMWARE_ARCTURUS;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
- case CHIP_RENOIR:
+ case IP_VERSION(2, 2, 0):
if (adev->apu_flags & AMD_APU_IS_RENOIR)
fw_name = FIRMWARE_RENOIR;
else
@@ -111,58 +112,52 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(2, 6, 0):
fw_name = FIRMWARE_ALDEBARAN;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
- case CHIP_NAVI10:
+ case IP_VERSION(2, 0, 0):
fw_name = FIRMWARE_NAVI10;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
- case CHIP_NAVI14:
- fw_name = FIRMWARE_NAVI14;
- if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
- adev->vcn.indirect_sram = true;
- break;
- case CHIP_NAVI12:
- fw_name = FIRMWARE_NAVI12;
- if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
- adev->vcn.indirect_sram = true;
- break;
- case CHIP_SIENNA_CICHLID:
- fw_name = FIRMWARE_SIENNA_CICHLID;
+ case IP_VERSION(2, 0, 2):
+ if (adev->asic_type == CHIP_NAVI12)
+ fw_name = FIRMWARE_NAVI12;
+ else
+ fw_name = FIRMWARE_NAVI14;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
- case CHIP_NAVY_FLOUNDER:
- fw_name = FIRMWARE_NAVY_FLOUNDER;
+ case IP_VERSION(3, 0, 0):
+ if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
+ fw_name = FIRMWARE_SIENNA_CICHLID;
+ else
+ fw_name = FIRMWARE_NAVY_FLOUNDER;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
- case CHIP_VANGOGH:
+ case IP_VERSION(3, 0, 2):
fw_name = FIRMWARE_VANGOGH;
break;
- case CHIP_DIMGREY_CAVEFISH:
+ case IP_VERSION(3, 0, 16):
fw_name = FIRMWARE_DIMGREY_CAVEFISH;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
- case CHIP_BEIGE_GOBY:
+ case IP_VERSION(3, 0, 33):
fw_name = FIRMWARE_BEIGE_GOBY;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
- case CHIP_YELLOW_CARP:
+ case IP_VERSION(3, 1, 1):
fw_name = FIRMWARE_YELLOW_CARP;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 48/66] drm/amdgpu/vcn2.5: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (46 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 47/66] drm/amdgpu/amdgpu_vcn: convert to " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 49/66] drm/amdgpu/soc15: " Alex Deucher
` (18 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 1780ad1eacd6..b76d96559029 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1720,7 +1720,7 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
- if (adev->asic_type == CHIP_ARCTURUS)
+ if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
else /* CHIP_ALDEBARAN */
adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
@@ -1737,7 +1737,7 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
if (adev->vcn.harvest_config & (1 << j))
continue;
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- if (adev->asic_type == CHIP_ARCTURUS)
+ if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
else /* CHIP_ALDEBARAN */
adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 49/66] drm/amdgpu/soc15: convert to IP version checking
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (47 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 48/66] drm/amdgpu/vcn2.5: " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 50/66] drm/amd/display: fix error case handling Alex Deucher
` (17 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 159 ++++++++++++++++-------------
1 file changed, 88 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f26d33faa0cb..7f4cd1a4f6cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -156,31 +156,38 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
const struct amdgpu_video_codecs **codecs)
{
- switch (adev->asic_type) {
- case CHIP_VEGA20:
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- if (encode)
- *codecs = &vega_video_codecs_encode;
- else
- *codecs = &vega_video_codecs_decode;
- return 0;
- case CHIP_RAVEN:
- if (encode)
- *codecs = &vega_video_codecs_encode;
- else
- *codecs = &rv_video_codecs_decode;
- return 0;
- case CHIP_ARCTURUS:
- case CHIP_ALDEBARAN:
- case CHIP_RENOIR:
- if (encode)
- *codecs = &vega_video_codecs_encode;
- else
- *codecs = &rn_video_codecs_decode;
- return 0;
- default:
- return -EINVAL;
+ if (adev->ip_versions[VCE_HWIP]) {
+ switch (adev->ip_versions[VCE_HWIP]) {
+ case IP_VERSION(4, 0, 0):
+ case IP_VERSION(4, 1, 0):
+ if (encode)
+ *codecs = &vega_video_codecs_encode;
+ else
+ *codecs = &vega_video_codecs_decode;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+ } else {
+ switch (adev->ip_versions[UVD_HWIP]) {
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
+ if (encode)
+ *codecs = &vega_video_codecs_encode;
+ else
+ *codecs = &rv_video_codecs_decode;
+ return 0;
+ case IP_VERSION(2, 5, 0):
+ case IP_VERSION(2, 6, 0):
+ case IP_VERSION(2, 2, 0):
+ if (encode)
+ *codecs = &vega_video_codecs_encode;
+ else
+ *codecs = &rn_video_codecs_decode;
+ return 0;
+ default:
+ return -EINVAL;
+ }
}
}
@@ -334,9 +341,11 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
{
u32 reference_clock = adev->clock.spll.reference_freq;
- if (adev->asic_type == CHIP_RENOIR)
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
+ adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
return 10000;
- if (adev->asic_type == CHIP_RAVEN)
+ if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
+ adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
return reference_clock / 4;
return reference_clock;
@@ -567,28 +576,29 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
amdgpu_reset_method);
- switch (adev->asic_type) {
- case CHIP_RAVEN:
- case CHIP_RENOIR:
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ case IP_VERSION(12, 0, 0):
+ case IP_VERSION(12, 0, 1):
return AMD_RESET_METHOD_MODE2;
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_ARCTURUS:
- baco_reset = amdgpu_dpm_is_baco_supported(adev);
- break;
- case CHIP_VEGA20:
- if (adev->psp.sos.fw_version >= 0x80067)
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(11, 0, 2):
+ if (adev->asic_type == CHIP_VEGA20) {
+ if (adev->psp.sos.fw_version >= 0x80067)
+ baco_reset = amdgpu_dpm_is_baco_supported(adev);
+ /*
+ * 1. PMFW version > 0x284300: all cases use baco
+ * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
+ */
+ if (ras && adev->ras_enabled &&
+ adev->pm.fw_version <= 0x283400)
+ baco_reset = false;
+ } else {
baco_reset = amdgpu_dpm_is_baco_supported(adev);
-
- /*
- * 1. PMFW version > 0x284300: all cases use baco
- * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
- */
- if (ras && adev->ras_enabled &&
- adev->pm.fw_version <= 0x283400)
- baco_reset = false;
+ }
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(13, 0, 2):
/*
* 1.connected to cpu: driver issue mode2 reset
* 2.discret gpu: driver issue mode1 reset
@@ -631,15 +641,17 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
static bool soc15_supports_baco(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_ARCTURUS:
- return amdgpu_dpm_is_baco_supported(adev);
- case CHIP_VEGA20:
- if (adev->psp.sos.fw_version >= 0x80067)
+ switch (adev->ip_versions[MP1_HWIP]) {
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(11, 0, 2):
+ if (adev->asic_type == CHIP_VEGA20) {
+ if (adev->psp.sos.fw_version >= 0x80067)
+ return amdgpu_dpm_is_baco_supported(adev);
+ return false;
+ } else {
return amdgpu_dpm_is_baco_supported(adev);
- return false;
+ }
+ break;
default:
return false;
}
@@ -1157,8 +1169,11 @@ static int soc15_common_early_init(void *handle)
adev->rev_id = soc15_get_rev_id(adev);
adev->external_rev_id = 0xFF;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ /* TODO: split the GC and PG flags based on the relevant IP version for which
+ * they are relevant.
+ */
+ switch (adev->ip_versions[GC_HWIP]) {
+ case IP_VERSION(9, 0, 1):
adev->asic_funcs = &soc15_asic_funcs;
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
@@ -1182,7 +1197,7 @@ static int soc15_common_early_init(void *handle)
adev->pg_flags = 0;
adev->external_rev_id = 0x1;
break;
- case CHIP_VEGA12:
+ case IP_VERSION(9, 2, 1):
adev->asic_funcs = &soc15_asic_funcs;
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
@@ -1205,7 +1220,7 @@ static int soc15_common_early_init(void *handle)
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x14;
break;
- case CHIP_VEGA20:
+ case IP_VERSION(9, 4, 0):
adev->asic_funcs = &vega20_asic_funcs;
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
@@ -1228,7 +1243,8 @@ static int soc15_common_early_init(void *handle)
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x28;
break;
- case CHIP_RAVEN:
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
adev->asic_funcs = &soc15_asic_funcs;
if (adev->rev_id >= 0x8)
@@ -1302,7 +1318,7 @@ static int soc15_common_early_init(void *handle)
adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
}
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(9, 4, 1):
adev->asic_funcs = &vega20_asic_funcs;
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
@@ -1321,7 +1337,7 @@ static int soc15_common_early_init(void *handle)
adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
adev->external_rev_id = adev->rev_id + 0x32;
break;
- case CHIP_RENOIR:
+ case IP_VERSION(9, 3, 0):
adev->asic_funcs = &soc15_asic_funcs;
if (adev->apu_flags & AMD_APU_IS_RENOIR)
@@ -1352,7 +1368,7 @@ static int soc15_common_early_init(void *handle)
AMD_PG_SUPPORT_JPEG |
AMD_PG_SUPPORT_VCN_DPG;
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(9, 4, 2):
adev->asic_funcs = &vega20_asic_funcs;
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
@@ -1567,10 +1583,10 @@ static int soc15_common_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
+ switch (adev->ip_versions[NBIO_HWIP]) {
+ case IP_VERSION(6, 1, 0):
+ case IP_VERSION(6, 2, 0):
+ case IP_VERSION(7, 4, 0):
adev->nbio.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
adev->nbio.funcs->update_medium_grain_light_sleep(adev,
@@ -1586,8 +1602,9 @@ static int soc15_common_set_clockgating_state(void *handle,
adev->df.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
break;
- case CHIP_RAVEN:
- case CHIP_RENOIR:
+ case IP_VERSION(7, 0, 0):
+ case IP_VERSION(7, 0, 1):
+ case IP_VERSION(2, 5, 0):
adev->nbio.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
adev->nbio.funcs->update_medium_grain_light_sleep(adev,
@@ -1599,8 +1616,8 @@ static int soc15_common_set_clockgating_state(void *handle,
soc15_update_drm_light_sleep(adev,
state == AMD_CG_STATE_GATE);
break;
- case CHIP_ARCTURUS:
- case CHIP_ALDEBARAN:
+ case IP_VERSION(7, 4, 1):
+ case IP_VERSION(7, 4, 4):
adev->hdp.funcs->update_clock_gating(adev,
state == AMD_CG_STATE_GATE);
break;
@@ -1622,7 +1639,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
adev->hdp.funcs->get_clock_gating_state(adev, flags);
- if (adev->asic_type != CHIP_ALDEBARAN) {
+ if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
/* AMD_CG_SUPPORT_DRM_MGCG */
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 50/66] drm/amd/display: fix error case handling
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (48 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 49/66] drm/amdgpu/soc15: " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 51/66] drm/amdgpu: add VCN1 hardware IP Alex Deucher
` (16 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Guchun Chen, Alex Deucher
From: Guchun Chen <guchun.chen@amd.com>
Otherwise, we will run into error case path.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 519930fe79a2..fc8a30251fa4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4204,11 +4204,11 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
}
break;
default:
- break;
+ DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
+ adev->ip_versions[DCE_HWIP]);
+ goto fail;
}
#endif
- DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
- goto fail;
}
return 0;
@@ -4386,11 +4386,11 @@ static int dm_early_init(void *handle)
adev->mode_info.num_dig = 4;
break;
default:
- break;
+ DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
+ adev->ip_versions[DCE_HWIP]);
+ return -EINVAL;
}
#endif
- DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
- return -EINVAL;
}
amdgpu_dm_set_irq_funcs(adev);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 51/66] drm/amdgpu: add VCN1 hardware IP
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (49 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 50/66] drm/amd/display: fix error case handling Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 52/66] drm/amdgpu: store all instances of IPs in the IP version table Alex Deucher
` (15 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
So we can store the VCN IP revision for each instance of VCN.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 815db33190ca..b153c3740307 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -744,6 +744,7 @@ enum amd_hw_ip_block_type {
UVD_HWIP,
VCN_HWIP = UVD_HWIP,
JPEG_HWIP = VCN_HWIP,
+ VCN1_HWIP,
VCE_HWIP,
DF_HWIP,
DCE_HWIP,
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 52/66] drm/amdgpu: store all instances of IPs in the IP version table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (50 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 51/66] drm/amdgpu: add VCN1 hardware IP Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-22 8:36 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 53/66] drm/amdgpu: add HWID of SDMA instance 2 and 3 Alex Deucher
` (14 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use the instance to increment the entry in the table.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index e3b4578872f1..572a634f7a1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -364,8 +364,10 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
hw_id_names[le16_to_cpu(ip->hw_id)]);
adev->reg_offset[hw_ip][ip->number_instance] =
ip->base_address;
- adev->ip_versions[hw_ip] =
- amdgpu_discovery_convert_version(ip->major, ip->minor, ip->revision);
+ adev->ip_versions[hw_ip + ip->number_instance] =
+ amdgpu_discovery_convert_version(ip->major,
+ ip->minor,
+ ip->revision);
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 52/66] drm/amdgpu: store all instances of IPs in the IP version table
2021-09-21 18:07 ` [PATCH 52/66] drm/amdgpu: store all instances of IPs in the IP version table Alex Deucher
@ 2021-09-22 8:36 ` Lazar, Lijo
2021-09-22 8:45 ` Lazar, Lijo
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 8:36 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:37 PM, Alex Deucher wrote:
> Use the instance to increment the entry in the table.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index e3b4578872f1..572a634f7a1e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -364,8 +364,10 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> hw_id_names[le16_to_cpu(ip->hw_id)]);
> adev->reg_offset[hw_ip][ip->number_instance] =
> ip->base_address;
> - adev->ip_versions[hw_ip] =
> - amdgpu_discovery_convert_version(ip->major, ip->minor, ip->revision);
> + adev->ip_versions[hw_ip + ip->number_instance] =
> + amdgpu_discovery_convert_version(ip->major,
> + ip->minor,
> + ip->revision);
There could be multiple instances with the same hardware id, right? For
ex: SDMA in ARCT/ALDE. They don't have discovery table now, regardless
does this hold good in such cases?
Thanks,
Lijo
> }
> }
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 52/66] drm/amdgpu: store all instances of IPs in the IP version table
2021-09-22 8:36 ` Lazar, Lijo
@ 2021-09-22 8:45 ` Lazar, Lijo
0 siblings, 0 replies; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 8:45 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/22/2021 2:06 PM, Lazar, Lijo wrote:
>
>
> On 9/21/2021 11:37 PM, Alex Deucher wrote:
>> Use the instance to increment the entry in the table.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>> index e3b4578872f1..572a634f7a1e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>> @@ -364,8 +364,10 @@ int amdgpu_discovery_reg_base_init(struct
>> amdgpu_device *adev)
>> hw_id_names[le16_to_cpu(ip->hw_id)]);
>> adev->reg_offset[hw_ip][ip->number_instance] =
>> ip->base_address;
>> - adev->ip_versions[hw_ip] =
>> - amdgpu_discovery_convert_version(ip->major,
>> ip->minor, ip->revision);
>> + adev->ip_versions[hw_ip + ip->number_instance] =
>> + amdgpu_discovery_convert_version(ip->major,
>> + ip->minor,
>> + ip->revision);
>
> There could be multiple instances with the same hardware id, right? For
> ex: SDMA in ARCT/ALDE. They don't have discovery table now, regardless
> does this hold good in such cases?
>
> Thanks,
> Lijo
>
Never mind, found that HWIP used here is different from HW_ID.
Thanks,
Lijo
>> }
>> }
>>
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 53/66] drm/amdgpu: add HWID of SDMA instance 2 and 3
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (51 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 52/66] drm/amdgpu: store all instances of IPs in the IP version table Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 54/66] drm/amdgpu: get VCN and SDMA instances from IP discovery table Alex Deucher
` (13 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Guchun Chen, Alex Deucher
From: Guchun Chen <guchun.chen@amd.com>
They are missed.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/soc15_hw_ip.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/soc15_hw_ip.h b/drivers/gpu/drm/amd/include/soc15_hw_ip.h
index 45ca4c921a66..c1519d20596a 100644
--- a/drivers/gpu/drm/amd/include/soc15_hw_ip.h
+++ b/drivers/gpu/drm/amd/include/soc15_hw_ip.h
@@ -80,6 +80,8 @@
#define L1IMU15_HWID 65
#define WAFLC_HWID 66
#define FCH_USB_PD_HWID 67
+#define SDMA2_HWID 68
+#define SDMA3_HWID 69
#define PCIE_HWID 70
#define PCS_HWID 80
#define DDCL_HWID 89
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 54/66] drm/amdgpu: get VCN and SDMA instances from IP discovery table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (52 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 53/66] drm/amdgpu: add HWID of SDMA instance 2 and 3 Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 55/66] drm/amdgpu/sdma: remove manual instance setting Alex Deucher
` (12 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Rather than hardcoding it.
v2: squash in checks for SDMA3,4 (Guchun)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 572a634f7a1e..9e59fb792643 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -348,6 +348,11 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
if (le16_to_cpu(ip->hw_id) == VCN_HWID)
adev->vcn.num_vcn_inst++;
+ if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
+ le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
+ le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
+ le16_to_cpu(ip->hw_id) == SDMA3_HWID)
+ adev->sdma.num_instances++;
for (k = 0; k < num_base_address; k++) {
/*
@@ -515,6 +520,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_VEGA10:
vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
@@ -534,6 +540,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
case CHIP_VEGA12:
vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
@@ -553,6 +560,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
case CHIP_RAVEN:
vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 1;
+ adev->vcn.num_vcn_inst = 1;
if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
@@ -589,6 +598,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
case CHIP_VEGA20:
vega20_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
@@ -608,6 +618,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
case CHIP_ARCTURUS:
arct_reg_base_init(adev);
+ adev->sdma.num_instances = 8;
+ adev->vcn.num_vcn_inst = 2;
adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
@@ -625,6 +637,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
case CHIP_ALDEBARAN:
aldebaran_reg_base_init(adev);
+ adev->sdma.num_instances = 5;
+ adev->vcn.num_vcn_inst = 2;
adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 55/66] drm/amdgpu/sdma: remove manual instance setting
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (53 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 54/66] drm/amdgpu: get VCN and SDMA instances from IP discovery table Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 56/66] drm/amdgpu/vcn: " Alex Deucher
` (11 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Handled by IP discovery now.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 17 -----------------
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 --
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 17 -----------------
3 files changed, 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3219dca3e44f..cb74f8c35d0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1856,23 +1856,6 @@ static int sdma_v4_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
- switch (adev->ip_versions[SDMA0_HWIP]) {
- case IP_VERSION(4, 1, 0):
- case IP_VERSION(4, 1, 1):
- case IP_VERSION(4, 1, 2):
- adev->sdma.num_instances = 1;
- break;
- case IP_VERSION(4, 2, 2):
- adev->sdma.num_instances = 8;
- break;
- case IP_VERSION(4, 4, 0):
- adev->sdma.num_instances = 5;
- break;
- default:
- adev->sdma.num_instances = 2;
- break;
- }
-
r = sdma_v4_0_init_microcode(adev);
if (r) {
DRM_ERROR("Failed to load sdma firmware!\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 2ab670c58520..d3b01d2977c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1295,8 +1295,6 @@ static int sdma_v5_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->sdma.num_instances = 2;
-
sdma_v5_0_set_ring_funcs(adev);
sdma_v5_0_set_buffer_funcs(adev);
sdma_v5_0_set_vm_pte_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index c5252f12eee9..92f29beda3b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1209,23 +1209,6 @@ static int sdma_v5_2_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->ip_versions[SDMA0_HWIP]) {
- case IP_VERSION(5, 2, 0):
- adev->sdma.num_instances = 4;
- break;
- case IP_VERSION(5, 2, 2):
- case IP_VERSION(5, 2, 4):
- adev->sdma.num_instances = 2;
- break;
- case IP_VERSION(5, 2, 1):
- case IP_VERSION(5, 2, 5):
- case IP_VERSION(5, 2, 3):
- adev->sdma.num_instances = 1;
- break;
- default:
- break;
- }
-
sdma_v5_2_set_ring_funcs(adev);
sdma_v5_2_set_buffer_funcs(adev);
sdma_v5_2_set_vm_pte_funcs(adev);
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 56/66] drm/amdgpu/vcn: remove manual instance setting
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (54 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 55/66] drm/amdgpu/sdma: remove manual instance setting Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 57/66] drm/amdgpu: get VCN harvest information from IP discovery table Alex Deucher
` (10 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Handled by IP discovery now.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 +---
4 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 6c11739270c1..ad0d2564087c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -66,7 +66,6 @@ static int vcn_v1_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->vcn.num_vcn_inst = 1;
adev->vcn.num_enc_rings = 2;
vcn_v1_0_set_dec_ring_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index a03c0fc8338f..43f46ab07dda 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -69,7 +69,6 @@ static int vcn_v2_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->vcn.num_vcn_inst = 1;
if (amdgpu_sriov_vf(adev))
adev->vcn.num_enc_rings = 1;
else
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index b76d96559029..e9758969fbe6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -83,7 +83,7 @@ static int vcn_v2_5_early_init(void *handle)
} else {
u32 harvest;
int i;
- adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS;
+
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index ef36ee0f3a5e..a81d834ea0d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -98,7 +98,6 @@ static int vcn_v3_0_early_init(void *handle)
if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
u32 harvest;
- adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
@@ -109,8 +108,7 @@ static int vcn_v3_0_early_init(void *handle)
AMDGPU_VCN_HARVEST_VCN1))
/* both instances are harvested, disable the block */
return -ENOENT;
- } else
- adev->vcn.num_vcn_inst = 1;
+ }
if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
adev->vcn.num_enc_rings = 0;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 57/66] drm/amdgpu: get VCN harvest information from IP discovery table
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (55 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 56/66] drm/amdgpu/vcn: " Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 58/66] drm/amdgpu/ucode: add default behavior Alex Deucher
` (9 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use the table rather than asic specific harvest registers.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 9e59fb792643..9d8aea39f36a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -456,6 +456,10 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
case VCN_HWID:
vcn_harvest_count++;
+ if (harvest_info->list[i].number_instance == 0)
+ adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
+ else
+ adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
break;
case DMU_HWID:
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 58/66] drm/amdgpu/ucode: add default behavior
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (56 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 57/66] drm/amdgpu: get VCN harvest information from IP discovery table Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 59/66] drm/amdgpu: add new asic_type for IP discovery Alex Deucher
` (8 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Default to PSP ucode loading unless the user specifies
direct.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 527d67ded8a0..0c3127f37686 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -416,10 +416,11 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
else
return AMDGPU_FW_LOAD_PSP;
default:
- DRM_ERROR("Unknown firmware load type\n");
+ if (!load_type)
+ return AMDGPU_FW_LOAD_DIRECT;
+ else
+ return AMDGPU_FW_LOAD_PSP;
}
-
- return AMDGPU_FW_LOAD_DIRECT;
}
const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 59/66] drm/amdgpu: add new asic_type for IP discovery
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (57 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 58/66] drm/amdgpu/ucode: add default behavior Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 60/66] drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default Alex Deucher
` (7 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Add a new asic type for asics where we don't have an
explicit entry in the PCI ID list. We don't need
an asic type for these asics, other than something higher
than the existing ones, so just use this for all new
asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3f2686296f5b..0adb6e0f9f41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -125,6 +125,7 @@ const char *amdgpu_asic_name[] = {
"DIMGREY_CAVEFISH",
"BEIGE_GOBY",
"YELLOW_CARP",
+ "IP DISCOVERY",
"LAST",
};
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index 0f66a0d9f06d..90b69270f2fa 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -62,6 +62,7 @@ enum amd_asic_type {
CHIP_DIMGREY_CAVEFISH, /* 33 */
CHIP_BEIGE_GOBY, /* 34 */
CHIP_YELLOW_CARP, /* 35 */
+ CHIP_IP_DISCOVERY, /* 36 */
CHIP_LAST,
};
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 60/66] drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (58 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 59/66] drm/amdgpu: add new asic_type for IP discovery Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-23 6:47 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 61/66] drm/amdgpu: convert IP version array to include instances Alex Deucher
` (6 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
For new chips with no explicit entry in the PCI ID list.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c21eac6216a8..c7da1f7cc880 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1796,12 +1796,12 @@ static const struct pci_device_id pciidlist[] = {
{ PCI_DEVICE(0x1002, PCI_ANY_ID),
.class = PCI_CLASS_DISPLAY_VGA << 8,
.class_mask = 0xffffff,
- .driver_data = 0 },
+ .driver_data = CHIP_IP_DISCOVERY },
{ PCI_DEVICE(0x1002, PCI_ANY_ID),
.class = PCI_CLASS_DISPLAY_OTHER << 8,
.class_mask = 0xffffff,
- .driver_data = 0 },
+ .driver_data = CHIP_IP_DISCOVERY },
{0, 0, 0}
};
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 60/66] drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default
2021-09-21 18:07 ` [PATCH 60/66] drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default Alex Deucher
@ 2021-09-23 6:47 ` Lazar, Lijo
2021-09-23 21:46 ` Alex Deucher
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-23 6:47 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:37 PM, Alex Deucher wrote:
> For new chips with no explicit entry in the PCI ID list.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index c21eac6216a8..c7da1f7cc880 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1796,12 +1796,12 @@ static const struct pci_device_id pciidlist[] = {
> { PCI_DEVICE(0x1002, PCI_ANY_ID),
> .class = PCI_CLASS_DISPLAY_VGA << 8,
> .class_mask = 0xffffff,
> - .driver_data = 0 },
> + .driver_data = CHIP_IP_DISCOVERY },
>
> { PCI_DEVICE(0x1002, PCI_ANY_ID),
> .class = PCI_CLASS_DISPLAY_OTHER << 8,
> .class_mask = 0xffffff,
> - .driver_data = 0 },
> + .driver_data = CHIP_IP_DISCOVERY },
>
While listing the devices one by one, some of the below flags are also
used to indicate the device type/support. Since the patch is replacing
this method, I guess the series needs to address this one also
(especially AMD_IS_APU, it is used extensively).
enum amd_chip_flags {
AMD_ASIC_MASK = 0x0000ffffUL,
AMD_FLAGS_MASK = 0xffff0000UL,
AMD_IS_MOBILITY = 0x00010000UL,
AMD_IS_APU = 0x00020000UL,
AMD_IS_PX = 0x00040000UL,
AMD_EXP_HW_SUPPORT = 0x00080000UL,
};
Thanks,
Lijo
> {0, 0, 0}
> };
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 60/66] drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default
2021-09-23 6:47 ` Lazar, Lijo
@ 2021-09-23 21:46 ` Alex Deucher
0 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-23 21:46 UTC (permalink / raw)
To: Lazar, Lijo; +Cc: Alex Deucher, amd-gfx list
On Thu, Sep 23, 2021 at 2:47 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 9/21/2021 11:37 PM, Alex Deucher wrote:
> > For new chips with no explicit entry in the PCI ID list.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index c21eac6216a8..c7da1f7cc880 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -1796,12 +1796,12 @@ static const struct pci_device_id pciidlist[] = {
> > { PCI_DEVICE(0x1002, PCI_ANY_ID),
> > .class = PCI_CLASS_DISPLAY_VGA << 8,
> > .class_mask = 0xffffff,
> > - .driver_data = 0 },
> > + .driver_data = CHIP_IP_DISCOVERY },
> >
> > { PCI_DEVICE(0x1002, PCI_ANY_ID),
> > .class = PCI_CLASS_DISPLAY_OTHER << 8,
> > .class_mask = 0xffffff,
> > - .driver_data = 0 },
> > + .driver_data = CHIP_IP_DISCOVERY },
> >
>
> While listing the devices one by one, some of the below flags are also
> used to indicate the device type/support. Since the patch is replacing
> this method, I guess the series needs to address this one also
> (especially AMD_IS_APU, it is used extensively).
>
> enum amd_chip_flags {
> AMD_ASIC_MASK = 0x0000ffffUL,
> AMD_FLAGS_MASK = 0xffff0000UL,
> AMD_IS_MOBILITY = 0x00010000UL,
> AMD_IS_APU = 0x00020000UL,
> AMD_IS_PX = 0x00040000UL,
> AMD_EXP_HW_SUPPORT = 0x00080000UL,
> };
I think we could either deprecate the use of these or derive them from
the IP versions for the flags that are currently derived from DIDs.
E.g., if we introduce support for a new IP (say SDMA 7.1) and it's not
stable yet, we could add code to set the AMD_EXP_HW_SUPPORT flag if
that IP version is found.
Alex
>
> Thanks,
> Lijo
>
>
> > {0, 0, 0}
> > };
> >
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 61/66] drm/amdgpu: convert IP version array to include instances
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (59 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 60/66] drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-22 9:08 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 62/66] drm/amdgpu: clean up set IP function Alex Deucher
` (5 subsequent siblings)
66 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Allow us to query instances versions more cleanly.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 262 +++++++++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 +-
drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 80 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 72 ++---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 16 +-
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 14 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 14 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 8 +-
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 34 +--
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 24 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 52 ++--
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 32 +--
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 28 +-
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 +-
29 files changed, 394 insertions(+), 394 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b153c3740307..f4bceb2624fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1096,7 +1096,7 @@ struct amdgpu_device {
struct pci_saved_state *pci_state;
struct amdgpu_reset_control *reset_cntl;
- uint32_t ip_versions[HW_ID_MAX];
+ uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
};
static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 9d8aea39f36a..eff348dee9e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -369,7 +369,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
hw_id_names[le16_to_cpu(ip->hw_id)]);
adev->reg_offset[hw_ip][ip->number_instance] =
ip->base_address;
- adev->ip_versions[hw_ip + ip->number_instance] =
+ adev->ip_versions[hw_ip][ip->number_instance] =
amdgpu_discovery_convert_version(ip->major,
ip->minor,
ip->revision);
@@ -525,139 +525,139 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_VEGA10:
vega10_reg_base_init(adev);
adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
- adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
- adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
- adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
- adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
- adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
- adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
- adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
break;
case CHIP_VEGA12:
vega10_reg_base_init(adev);
adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
- adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
- adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
- adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
- adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
- adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
- adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
- adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
- adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
- adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
- adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
- adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
- adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
break;
case CHIP_RAVEN:
vega10_reg_base_init(adev);
adev->sdma.num_instances = 1;
adev->vcn.num_vcn_inst = 1;
if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
- adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
- adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
- adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
- adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
- adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
- adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
- adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
- adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
- adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
- adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
- adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
- adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
- adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
- adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
- adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
+ adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
} else {
- adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
- adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
- adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
- adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
- adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
- adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
- adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
- adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
- adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
- adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
- adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
- adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
- adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
- adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
- adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
+ adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
}
break;
case CHIP_VEGA20:
vega20_reg_base_init(adev);
adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
- adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
- adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
- adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
- adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
- adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
- adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
- adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
- adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
- adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
- adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
- adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
- adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
- adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
- adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
- adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
break;
case CHIP_ARCTURUS:
arct_reg_base_init(adev);
adev->sdma.num_instances = 8;
adev->vcn.num_vcn_inst = 2;
- adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
- adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
- adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
- adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
- adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
- adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
- adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
- adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
- adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
- adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
- adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
- adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
- adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
- adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
break;
case CHIP_ALDEBARAN:
aldebaran_reg_base_init(adev);
adev->sdma.num_instances = 5;
adev->vcn.num_vcn_inst = 2;
- adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
- adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
- adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
- adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
- adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
- adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
- adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
- adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
- adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
- adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
- adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
- adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
- adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
- adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
- adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
+ adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
break;
default:
r = amdgpu_discovery_reg_base_init(adev);
@@ -673,7 +673,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
}
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 2, 1):
case IP_VERSION(9, 4, 0):
@@ -706,11 +706,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
return -EINVAL;
}
- if (adev->ip_versions[XGMI_HWIP] == IP_VERSION(4, 8, 0))
+ if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
adev->gmc.xgmi.supported = true;
/* set NBIO version */
- switch (adev->ip_versions[NBIO_HWIP]) {
+ switch (adev->ip_versions[NBIO_HWIP][0]) {
case IP_VERSION(6, 1, 0):
case IP_VERSION(6, 2, 0):
adev->nbio.funcs = &nbio_v6_1_funcs;
@@ -749,7 +749,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
}
- switch (adev->ip_versions[HDP_HWIP]) {
+ switch (adev->ip_versions[HDP_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
@@ -771,7 +771,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
}
- switch (adev->ip_versions[DF_HWIP]) {
+ switch (adev->ip_versions[DF_HWIP][0]) {
case IP_VERSION(3, 6, 0):
case IP_VERSION(3, 6, 1):
case IP_VERSION(3, 6, 2):
@@ -788,7 +788,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
}
- switch (adev->ip_versions[SMUIO_HWIP]) {
+ switch (adev->ip_versions[SMUIO_HWIP][0]) {
case IP_VERSION(9, 0, 0):
case IP_VERSION(9, 0, 1):
case IP_VERSION(10, 0, 0):
@@ -819,7 +819,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
/* what IP to use for this? */
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 1, 0):
case IP_VERSION(9, 2, 1):
@@ -847,7 +847,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
/* use GC or MMHUB IP version */
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 1, 0):
case IP_VERSION(9, 2, 1):
@@ -874,7 +874,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
return -EINVAL;
}
- switch (adev->ip_versions[OSSSYS_HWIP]) {
+ switch (adev->ip_versions[OSSSYS_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
@@ -900,7 +900,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
- switch (adev->ip_versions[MP0_HWIP]) {
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(9, 0, 0):
amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
break;
@@ -938,7 +938,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(9, 0, 0):
case IP_VERSION(10, 0, 0):
case IP_VERSION(10, 0, 1):
@@ -975,8 +975,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
- } else if (adev->ip_versions[DCE_HWIP]) {
- switch (adev->ip_versions[DCE_HWIP]) {
+ } else if (adev->ip_versions[DCE_HWIP][0]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
case IP_VERSION(2, 0, 2):
@@ -995,8 +995,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
default:
return -EINVAL;
}
- } else if (adev->ip_versions[DCI_HWIP]) {
- switch (adev->ip_versions[DCI_HWIP]) {
+ } else if (adev->ip_versions[DCI_HWIP][0]) {
+ switch (adev->ip_versions[DCI_HWIP][0]) {
case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 0, 1):
case IP_VERSION(12, 1, 0):
@@ -1007,7 +1007,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
}
#endif
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 1, 0):
case IP_VERSION(9, 2, 1):
@@ -1034,7 +1034,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
return -EINVAL;
}
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
@@ -1064,7 +1064,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(9, 0, 0):
case IP_VERSION(10, 0, 0):
case IP_VERSION(10, 0, 1):
@@ -1098,8 +1098,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
}
- if (adev->ip_versions[VCE_HWIP]) {
- switch (adev->ip_versions[UVD_HWIP]) {
+ if (adev->ip_versions[VCE_HWIP][0]) {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(7, 0, 0):
case IP_VERSION(7, 2, 0):
amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
@@ -1107,7 +1107,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
default:
return -EINVAL;
}
- switch (adev->ip_versions[VCE_HWIP]) {
+ switch (adev->ip_versions[VCE_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 1, 0):
amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
@@ -1116,7 +1116,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
return -EINVAL;
}
} else {
- switch (adev->ip_versions[UVD_HWIP]) {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
@@ -1153,7 +1153,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
}
if (adev->enable_mes) {
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c47d29689be4..7d414f1606b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -76,7 +76,7 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp
return;
}
- switch (adev->ip_versions[MP0_HWIP]) {
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(11, 0, 4):
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 9):
@@ -97,7 +97,7 @@ static int psp_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
- switch (adev->ip_versions[MP0_HWIP]) {
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(9, 0, 0):
psp_v3_1_set_psp_funcs(psp);
psp->autoload_supported = false;
@@ -279,7 +279,7 @@ static int psp_sw_init(void *handle)
return ret;
}
} else if (amdgpu_sriov_vf(adev) &&
- adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2)) {
+ adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) {
ret = psp_init_ta_microcode(psp, "aldebaran");
if (ret) {
DRM_ERROR("Failed to initialize ta microcode!\n");
@@ -322,8 +322,8 @@ static int psp_sw_init(void *handle)
}
}
- if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
- adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7)) {
+ if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
+ adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
ret= psp_sysfs_init(adev);
if (ret) {
return ret;
@@ -353,8 +353,8 @@ static int psp_sw_fini(void *handle)
psp->ta_fw = NULL;
}
- if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
- adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7))
+ if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
+ adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
psp_sysfs_fini(adev);
kfree(cmd);
@@ -613,7 +613,7 @@ static int psp_tmr_init(struct psp_context *psp)
static bool psp_skip_tmr(struct psp_context *psp)
{
- switch (psp->adev->ip_versions[MP0_HWIP]) {
+ switch (psp->adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 7):
case IP_VERSION(13, 0, 2):
@@ -1010,8 +1010,8 @@ int psp_xgmi_terminate(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev;
/* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
- if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
- (adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
+ if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
+ (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
adev->gmc.xgmi.connected_to_cpu))
return 0;
@@ -1113,7 +1113,7 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
{
- return psp->adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
+ return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;
}
@@ -2232,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp)
if ((amdgpu_in_reset(adev) &&
ras && adev->ras_enabled &&
- (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
- adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 2)))) {
+ (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
+ adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
if (ret) {
DRM_WARN("Failed to set MP1 state prepare for reload\n");
@@ -2330,9 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
continue;
if (psp->autoload_supported &&
- (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7) ||
- adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 11) ||
- adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 12)) &&
+ (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
+ adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
+ adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
@@ -2920,7 +2920,7 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
if (adev->gmc.xgmi.connected_to_cpu ||
- (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2))) {
+ (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 9724f5f5f702..4d3f2386ef53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -86,7 +86,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_vcn_inst; i++)
atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
- switch (adev->ip_versions[UVD_HWIP]) {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
@@ -134,7 +134,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
adev->vcn.indirect_sram = true;
break;
case IP_VERSION(3, 0, 0):
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
fw_name = FIRMWARE_SIENNA_CICHLID;
else
fw_name = FIRMWARE_NAVY_FLOUNDER;
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
index d3f634eb40fb..ab6a07e5e8c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
@@ -77,7 +77,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[ATHUB_HWIP]) {
+ switch (adev->ip_versions[ATHUB_HWIP][0]) {
case IP_VERSION(2, 0, 0):
case IP_VERSION(2, 0, 2):
athub_v2_0_update_medium_grain_clock_gating(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
index 0fbeaf05204e..2edefd10e56c 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
@@ -70,7 +70,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[ATHUB_HWIP]) {
+ switch (adev->ip_versions[ATHUB_HWIP][0]) {
case IP_VERSION(2, 1, 0):
case IP_VERSION(2, 1, 1):
case IP_VERSION(2, 1, 2):
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 4c632306ed70..71bb3c0dc1da 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1537,7 +1537,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
scratch_reg3 = adev->rmmio +
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
- if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
+ if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
spare_int = adev->rmmio +
(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
+ mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
@@ -3727,7 +3727,7 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
soc15_program_register_sequence(adev,
golden_settings_gc_rlc_spm_10_0_nv10,
@@ -3750,7 +3750,7 @@ static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
soc15_program_register_sequence(adev,
golden_settings_gc_10_1,
@@ -3985,7 +3985,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
{
adev->gfx.cp_fw_write_wait = false;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 1):
@@ -4066,7 +4066,7 @@ static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
@@ -4093,7 +4093,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
chip_name = "navi10";
break;
@@ -4684,7 +4684,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -4818,7 +4818,7 @@ static int gfx_v10_0_sw_init(void *handle)
struct amdgpu_kiq *kiq;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -5068,8 +5068,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
bitmap = i * adev->gfx.config.max_sh_per_se + j;
- if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
- (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
+ if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
+ (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
continue;
gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -5096,7 +5096,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
/* for ASICs that integrates GFX v10.3
* pa_sc_tile_steering_override should be set to 0 */
- if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
+ if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
return 0;
/* init num_sc */
@@ -5249,7 +5249,7 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
/* TCCs are global (not instanced). */
uint32_t tcc_disable;
- if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
+ if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
} else {
@@ -5326,7 +5326,7 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
/* csib */
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
adev->gfx.rlc.clear_state_gpu_addr >> 32);
WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
@@ -5948,7 +5948,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
} else {
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
@@ -6337,7 +6337,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
}
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
}
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -6474,7 +6474,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
{
if (enable) {
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -6488,7 +6488,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
break;
}
} else {
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -6586,7 +6586,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
struct amdgpu_device *adev = ring->adev;
/* tell RLC which is KIQ queue */
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -7303,7 +7303,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
/* check if mmVGT_ESGS_RING_SIZE_UMD
* has been remapped to mmVGT_ESGS_RING_SIZE */
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 4):
@@ -7350,7 +7350,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
* index will auto-inc after each data writting */
WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -7520,19 +7520,19 @@ static int gfx_v10_0_hw_init(void *handle)
* init golden registers and rlc resume may override some registers,
* reconfig them here
*/
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 10) ||
- adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 1) ||
- adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
gfx_v10_0_tcp_harvest(adev);
r = gfx_v10_0_cp_resume(adev);
if (r)
return r;
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
gfx_v10_3_program_pbb_mode(adev);
- if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
+ if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
gfx_v10_3_set_power_brake_sequence(adev);
return r;
@@ -7584,7 +7584,7 @@ static int gfx_v10_0_hw_fini(void *handle)
if (amdgpu_sriov_vf(adev)) {
gfx_v10_0_cp_gfx_enable(adev, false);
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
- if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
+ if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
tmp &= 0xffffff00;
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
@@ -7670,7 +7670,7 @@ static int gfx_v10_0_soft_reset(void *handle)
/* GRBM_STATUS2 */
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -7726,7 +7726,7 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
{
uint64_t clock, clock_lo, clock_hi, hi_check;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 3):
clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
@@ -7784,7 +7784,7 @@ static int gfx_v10_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -7848,7 +7848,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
data = RLC_SAFE_MODE__CMD_MASK;
data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -7884,7 +7884,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
uint32_t data;
data = RLC_SAFE_MODE__CMD_MASK;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -8193,7 +8193,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d
mmCGTS_SA1_QUAD1_SM_CTRL_REG
};
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
tcp_ctrl_regs_nv12[i];
@@ -8238,8 +8238,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
/* === CGCG + CGLS === */
gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
- if ((adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 1, 10)) &&
- (adev->ip_versions[GC_HWIP] <= IP_VERSION(10, 1, 2)))
+ if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 1, 10)) &&
+ (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(10, 1, 2)))
gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
} else {
/* CGCG/CGLS should be disabled before MGCG/MGLS
@@ -8335,7 +8335,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
* Power/performance team will optimize it and might give a new value later.
*/
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 1):
data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
@@ -8399,7 +8399,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -8428,7 +8428,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -9541,7 +9541,7 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 3):
@@ -9641,8 +9641,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
bitmap = i * adev->gfx.config.max_sh_per_se + j;
- if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
- (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
+ if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
+ (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
continue;
mask = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3a160d78c98f..8f2966bcf5a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -953,7 +953,7 @@ static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
soc15_program_register_sequence(adev,
golden_settings_gc_9_0,
@@ -1009,8 +1009,8 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
break;
}
- if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
- (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2)))
+ if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
+ (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)))
soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
}
@@ -1194,14 +1194,14 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
adev->gfx.me_fw_write_wait = false;
adev->gfx.mec_fw_write_wait = false;
- if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
+ if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
((adev->gfx.mec_fw_version < 0x000001a5) ||
(adev->gfx.mec_feature_version < 46) ||
(adev->gfx.pfp_fw_version < 0x000000b7) ||
(adev->gfx.pfp_feature_version < 46)))
DRM_WARN_ONCE("CP firmware version too old, please update!");
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
if ((adev->gfx.me_fw_version >= 0x0000009c) &&
(adev->gfx.me_feature_version >= 42) &&
@@ -1301,7 +1301,7 @@ static bool is_raven_kicker(struct amdgpu_device *adev)
static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
{
- if ((adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0)) &&
+ if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) &&
(adev->gfx.me_fw_version >= 0x000000a5) &&
(adev->gfx.me_feature_version >= 52))
return true;
@@ -1314,7 +1314,7 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 2, 1):
case IP_VERSION(9, 4, 0):
@@ -1558,9 +1558,9 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)
{
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2) ||
- adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
- adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0))
return false;
return true;
@@ -1668,7 +1668,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
chip_name = "vega10";
break;
@@ -1800,7 +1800,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
if (adev->flags & AMD_IS_APU)
always_on_cu_num = 4;
- else if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1))
+ else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1))
always_on_cu_num = 8;
else
always_on_cu_num = 12;
@@ -1969,7 +1969,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
return r;
}
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 2, 2):
case IP_VERSION(9, 1, 0):
gfx_v9_0_init_lbpw(adev);
@@ -2149,7 +2149,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
@@ -2313,7 +2313,7 @@ static int gfx_v9_0_sw_init(void *handle)
struct amdgpu_kiq *kiq;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 2, 1):
case IP_VERSION(9, 4, 0):
@@ -2605,7 +2605,7 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
{
uint32_t tmp;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 4, 1):
tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
@@ -2941,7 +2941,7 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
/* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
- if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 3, 0))
+ if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0))
pwr_10_0_gfxip_control_over_cgpg(adev, true);
}
}
@@ -3053,7 +3053,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
* And it's needed by gfxoff feature.
*/
if (adev->gfx.rlc.is_rlc_v2_1) {
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1) ||
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) ||
(adev->apu_flags & AMD_APU_IS_RAVEN2))
gfx_v9_1_init_rlc_save_restore_list(adev);
gfx_v9_0_enable_save_restore_machine(adev);
@@ -3166,7 +3166,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
return r;
}
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 2, 2):
case IP_VERSION(9, 1, 0):
if (amdgpu_lbpw == 0)
@@ -3969,8 +3969,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
{
u32 tmp;
- if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1) &&
- adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2))
+ if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) &&
+ adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))
return;
tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
@@ -4010,7 +4010,7 @@ static int gfx_v9_0_hw_init(void *handle)
if (r)
return r;
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
gfx_v9_4_2_set_power_brake_sequence(adev);
return r;
@@ -4242,7 +4242,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->gfx.gpu_clock_mutex);
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
clock = gfx_v9_0_kiq_read_clock(adev);
} else {
WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
@@ -4592,7 +4592,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
if (!ring->sched.ready)
return 0;
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1)) {
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
@@ -4742,8 +4742,8 @@ static int gfx_v9_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
- adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
adev->gfx.num_gfx_rings = 0;
else
adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
@@ -4777,7 +4777,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
}
/* requires IBs so do in late init after IB pool is initialized */
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
else
r = gfx_v9_0_do_edc_gpr_workarounds(adev);
@@ -4905,7 +4905,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
/* 1 - RLC_CGTT_MGCG_OVERRIDE */
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
- if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
+ if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
@@ -4939,7 +4939,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
/* 1 - MGCG_OVERRIDE */
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
- if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
+ if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
@@ -5045,7 +5045,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
/* enable cgcg FSM(0x0000363F) */
def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1))
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1))
data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
else
@@ -5171,7 +5171,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_PG_STATE_GATE);
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 2, 2):
case IP_VERSION(9, 1, 0):
case IP_VERSION(9, 3, 0):
@@ -5218,7 +5218,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 2, 1):
case IP_VERSION(9, 4, 0):
@@ -5268,7 +5268,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
- if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) {
+ if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) {
/* AMD_CG_SUPPORT_GFX_3D_CGCG */
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
@@ -7039,7 +7039,7 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 2, 1):
case IP_VERSION(9, 4, 0):
@@ -7058,7 +7058,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
{
/* init asci gds info */
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 2, 1):
case IP_VERSION(9, 4, 0):
@@ -7080,7 +7080,7 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
break;
}
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 4, 0):
adev->gds.gds_compute_max_wave_id = 0x7ff;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 149f3843e0e7..e80d1dc43079 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -506,7 +506,7 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
u32 max_num_physical_nodes = 0;
u32 max_physical_node_id = 0;
- switch (adev->ip_versions[XGMI_HWIP]) {
+ switch (adev->ip_versions[XGMI_HWIP][0]) {
case IP_VERSION(4, 8, 0):
max_num_physical_nodes = 4;
max_physical_node_id = 3;
@@ -544,7 +544,7 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
adev->gfx.config.max_sh_per_se *
adev->gfx.config.max_shader_engines);
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3)) {
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) {
/* Get SA disabled bitmap from eFuse setting */
efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index b488257ff201..6d0586009de3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -133,7 +133,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
* the new fast GRBM interface.
*/
if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
- (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
+ (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
RREG32(hub->vm_l2_pro_fault_status);
status = RREG32(hub->vm_l2_pro_fault_status);
@@ -268,7 +268,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
* to avoid a false ACK due to the new fast GRBM interface.
*/
if ((vmhub == AMDGPU_GFXHUB_0) &&
- (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
+ (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
hub->eng_distance * eng, hub_ip);
@@ -657,7 +657,7 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[UMC_HWIP]) {
+ switch (adev->ip_versions[UMC_HWIP][0]) {
case IP_VERSION(8, 7, 0):
adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
@@ -674,7 +674,7 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 3, 0):
case IP_VERSION(2, 4, 0):
adev->mmhub.funcs = &mmhub_v2_3_funcs;
@@ -687,7 +687,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -857,7 +857,7 @@ static int gmc_v10_0_sw_init(void *handle)
adev->gmc.vram_vendor = vram_vendor;
}
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
@@ -1132,7 +1132,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
if (r)
return r;
- if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
+ if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
return athub_v2_1_set_clockgating(adev, state);
else
return athub_v2_0_set_clockgating(adev, state);
@@ -1144,7 +1144,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
adev->mmhub.funcs->get_clockgating(adev, flags);
- if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
+ if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
athub_v2_1_get_clockgating(adev, flags);
else
athub_v2_0_get_clockgating(adev, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index 88938115557b..eecfb1545c1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -49,7 +49,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
struct amdgpu_ring *ring)
{
- if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 4, 0))
+ if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
return;
if (!ring || !ring->funcs->emit_wreg)
@@ -79,7 +79,7 @@ static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
return;
- if (adev->ip_versions[HDP_HWIP] >= IP_VERSION(4, 4, 0))
+ if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
else
/*read back hdp ras counter to reset it to 0 */
@@ -91,10 +91,10 @@ static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
{
uint32_t def, data;
- if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 0) ||
- adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 1) ||
- adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 1) ||
- adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 0)) {
+ if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
+ adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
+ adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
+ adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
@@ -136,7 +136,7 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[HDP_HWIP]) {
+ switch (adev->ip_versions[HDP_HWIP][0]) {
case IP_VERSION(4, 2, 1):
WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index e0cb919b4814..25f8e93e5ec3 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -153,7 +153,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
dev_err(adev->dev,
"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
status);
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 0, 0):
case IP_VERSION(2, 0, 2):
mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
@@ -569,7 +569,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
return;
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 1, 0):
case IP_VERSION(2, 1, 1):
case IP_VERSION(2, 1, 2):
@@ -603,7 +603,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
}
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 1, 0):
case IP_VERSION(2, 1, 1):
case IP_VERSION(2, 1, 2):
@@ -629,7 +629,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
return;
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 1, 0):
case IP_VERSION(2, 1, 1):
case IP_VERSION(2, 1, 2):
@@ -646,7 +646,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
if (def != data) {
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 1, 0):
case IP_VERSION(2, 1, 1):
case IP_VERSION(2, 1, 2):
@@ -665,7 +665,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 0, 0):
case IP_VERSION(2, 0, 2):
case IP_VERSION(2, 1, 0):
@@ -690,7 +690,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
if (amdgpu_sriov_vf(adev))
*flags = 0;
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 1, 0):
case IP_VERSION(2, 1, 1):
case IP_VERSION(2, 1, 2):
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index 4cf5d0595bbe..a11d60ec6321 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -90,7 +90,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
dev_err(adev->dev,
"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
status);
- switch (adev->ip_versions[MMHUB_HWIP]) {
+ switch (adev->ip_versions[MMHUB_HWIP][0]) {
case IP_VERSION(2, 3, 0):
case IP_VERSION(2, 4, 0):
mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index c3f968d9cfcb..1d8414c3fadb 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -107,7 +107,7 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
{
u32 ih_cntl, ih_rb_cntl;
- if (adev->ip_versions[OSSSYS_HWIP] < IP_VERSION(5, 0, 3))
+ if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3))
return;
ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
@@ -332,7 +332,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
if (ih[0]->use_bus_addr) {
- switch (adev->ip_versions[OSSSYS_HWIP]) {
+ switch (adev->ip_versions[OSSSYS_HWIP][0]) {
case IP_VERSION(5, 0, 3):
case IP_VERSION(5, 2, 0):
case IP_VERSION(5, 2, 1):
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 57be517d70bf..89e32d6e2c10 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -180,7 +180,7 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
const struct amdgpu_video_codecs **codecs)
{
- switch (adev->ip_versions[UVD_HWIP]) {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(3, 0, 0):
if (amdgpu_sriov_vf(adev)) {
if (encode)
@@ -509,7 +509,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
amdgpu_reset_method);
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 5, 0):
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
@@ -1044,7 +1044,7 @@ static int nv_common_early_init(void *handle)
/* TODO: split the GC and PG flags based on the relevant IP version for which
* they are relevant.
*/
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 1, 10):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
@@ -1375,7 +1375,7 @@ static int nv_common_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[NBIO_HWIP]) {
+ switch (adev->ip_versions[NBIO_HWIP][0]) {
case IP_VERSION(2, 3, 0):
case IP_VERSION(2, 3, 1):
case IP_VERSION(2, 3, 2):
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 13dace5d2855..382cebfc2069 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -93,7 +93,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
DRM_DEBUG("\n");
- switch (adev->ip_versions[MP0_HWIP]) {
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(11, 0, 2):
chip_name = "vega20";
break;
@@ -129,7 +129,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
}
- switch (adev->ip_versions[MP0_HWIP]) {
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 4):
err = psp_init_sos_microcode(psp, chip_name);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 64b52c5ea981..17655bc6d2f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -47,7 +47,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
const char *chip_name;
int err = 0;
- switch (adev->ip_versions[MP0_HWIP]) {
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(13, 0, 2):
chip_name = "aldebaran";
break;
@@ -58,7 +58,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
default:
BUG();
}
- switch (adev->ip_versions[MP0_HWIP]) {
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(13, 0, 2):
err = psp_init_sos_microcode(psp, chip_name);
if (err)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index cb74f8c35d0a..e8e4749e9c79 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -469,7 +469,7 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 0, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma_4,
@@ -539,7 +539,7 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
* The only chips with SDMAv4 and ULV are VG10 and VG20.
* Server SKUs take a different hysteresis setting from other SKUs.
*/
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 0, 0):
if (adev->pdev->device == 0x6860)
break;
@@ -590,8 +590,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
/* arcturus shares the same FW memory across
all SDMA isntances */
- if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
- adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0))
+ if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
+ adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
break;
}
@@ -621,7 +621,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 0, 0):
chip_name = "vega10";
break;
@@ -667,8 +667,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
goto out;
for (i = 1; i < adev->sdma.num_instances; i++) {
- if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
- adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0)) {
+ if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
+ adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
/* Acturus & Aldebaran will leverage the same FW memory
for every SDMA instance */
memcpy((void *)&adev->sdma.instance[i],
@@ -1108,7 +1108,7 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
* Arcturus for the moment and firmware version 14
* and above.
*/
- if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) &&
+ if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) &&
adev->sdma.instance[i].fw_version >= 14)
WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
/* Extend page fault timeout to avoid interrupt storm */
@@ -1395,7 +1395,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
return;
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 1, 0):
case IP_VERSION(4, 1, 1):
case IP_VERSION(4, 1, 2):
@@ -1838,7 +1838,7 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
{
uint fw_version = adev->sdma.instance[0].fw_version;
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 0, 0):
return fw_version >= 430;
case IP_VERSION(4, 0, 1):
@@ -1863,7 +1863,7 @@ static int sdma_v4_0_early_init(void *handle)
}
/* TODO: Page queue breaks driver reload under SRIOV */
- if ((adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 0, 0)) &&
+ if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) &&
amdgpu_sriov_vf((adev)))
adev->sdma.has_page_queue = false;
else if (sdma_v4_0_fw_support_paging_queue(adev))
@@ -2136,14 +2136,14 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
amdgpu_fence_process(&adev->sdma.instance[instance].ring);
break;
case 1:
- if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 0))
+ if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0))
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
case 2:
/* XXX compute */
break;
case 3:
- if (adev->ip_versions[SDMA0_HWIP] != IP_VERSION(4, 2, 0))
+ if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0))
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
}
@@ -2359,7 +2359,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 1, 0):
case IP_VERSION(4, 1, 1):
case IP_VERSION(4, 1, 2):
@@ -2547,7 +2547,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
int i;
for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
+ if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
adev->sdma.instance[i].ring.funcs =
&sdma_v4_0_ring_funcs_2nd_mmhub;
else
@@ -2555,7 +2555,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
&sdma_v4_0_ring_funcs;
adev->sdma.instance[i].ring.me = i;
if (adev->sdma.has_page_queue) {
- if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
+ if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
adev->sdma.instance[i].page.funcs =
&sdma_v4_0_page_ring_funcs_2nd_mmhub;
else
@@ -2782,7 +2782,7 @@ static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 2, 0):
case IP_VERSION(4, 2, 2):
adev->sdma.funcs = &sdma_v4_0_ras_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index d3b01d2977c0..853d1511b889 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -187,7 +187,7 @@ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(5, 0, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma_5,
@@ -248,12 +248,12 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
const struct common_firmware_header *header = NULL;
const struct sdma_firmware_header_v1_0 *hdr;
- if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 0, 5)))
+ if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
return 0;
DRM_DEBUG("\n");
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(5, 0, 0):
chip_name = "navi10";
break;
@@ -1634,7 +1634,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 2):
case IP_VERSION(5, 0, 5):
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 92f29beda3b2..0fec1d9dd638 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -136,7 +136,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(5, 2, 0):
chip_name = "sienna_cichlid";
break;
@@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
(void *)&adev->sdma.instance[0],
sizeof(struct amdgpu_sdma_instance));
- if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 0)))
+ if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
return 0;
DRM_DEBUG("psp_load == '%s'\n",
@@ -1530,7 +1530,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
+ if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
@@ -1567,7 +1567,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
+ if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
@@ -1596,7 +1596,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[SDMA0_HWIP]) {
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(5, 2, 0):
case IP_VERSION(5, 2, 2):
case IP_VERSION(5, 2, 1):
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7f4cd1a4f6cb..74310bb4216a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -156,8 +156,8 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
const struct amdgpu_video_codecs **codecs)
{
- if (adev->ip_versions[VCE_HWIP]) {
- switch (adev->ip_versions[VCE_HWIP]) {
+ if (adev->ip_versions[VCE_HWIP][0]) {
+ switch (adev->ip_versions[VCE_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 1, 0):
if (encode)
@@ -169,7 +169,7 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
return -EINVAL;
}
} else {
- switch (adev->ip_versions[UVD_HWIP]) {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
if (encode)
@@ -341,11 +341,11 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
{
u32 reference_clock = adev->clock.spll.reference_freq;
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
- adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
+ adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
return 10000;
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
- adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
+ adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
return reference_clock / 4;
return reference_clock;
@@ -576,7 +576,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
amdgpu_reset_method);
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(10, 0, 0):
case IP_VERSION(10, 0, 1):
case IP_VERSION(12, 0, 0):
@@ -641,7 +641,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
static bool soc15_supports_baco(struct amdgpu_device *adev)
{
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(9, 0, 0):
case IP_VERSION(11, 0, 2):
if (adev->asic_type == CHIP_VEGA20) {
@@ -1172,7 +1172,7 @@ static int soc15_common_early_init(void *handle)
/* TODO: split the GC and PG flags based on the relevant IP version for which
* they are relevant.
*/
- switch (adev->ip_versions[GC_HWIP]) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
adev->asic_funcs = &soc15_asic_funcs;
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
@@ -1583,7 +1583,7 @@ static int soc15_common_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[NBIO_HWIP]) {
+ switch (adev->ip_versions[NBIO_HWIP][0]) {
case IP_VERSION(6, 1, 0):
case IP_VERSION(6, 2, 0):
case IP_VERSION(7, 4, 0):
@@ -1639,7 +1639,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
adev->hdp.funcs->get_clock_gating_state(adev, flags);
- if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
+ if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
/* AMD_CG_SUPPORT_DRM_MGCG */
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index e9758969fbe6..f4a7a30ecebd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1720,7 +1720,7 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
- if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
+ if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
else /* CHIP_ALDEBARAN */
adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
@@ -1737,7 +1737,7 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
if (adev->vcn.harvest_config & (1 << j))
continue;
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
+ if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
else /* CHIP_ALDEBARAN */
adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index a81d834ea0d3..6940716db1df 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -95,7 +95,7 @@ static int vcn_v3_0_early_init(void *handle)
adev->vcn.num_enc_rings = 1;
} else {
- if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
+ if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 0)) {
u32 harvest;
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
@@ -110,7 +110,7 @@ static int vcn_v3_0_early_init(void *handle)
return -ENOENT;
}
- if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
+ if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33))
adev->vcn.num_enc_rings = 0;
else
adev->vcn.num_enc_rings = 2;
@@ -1270,7 +1270,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
fw_shared->rb.wptr = lower_32_bits(ring->wptr);
fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
- if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
+ if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
ring = &adev->vcn.inst[i].ring_enc[0];
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
@@ -1642,7 +1642,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
- if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
+ if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
/* Restore */
fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fc8a30251fa4..fb89ce4dd28c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1344,7 +1344,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.flags.gpu_vm_support = true;
break;
default:
- switch (adev->ip_versions[DCE_HWIP]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0):
init_data.flags.gpu_vm_support = true;
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
@@ -1658,7 +1658,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
return 0;
break;
default:
- switch (adev->ip_versions[DCE_HWIP]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 0, 2):
case IP_VERSION(2, 0, 0):
case IP_VERSION(2, 1, 0):
@@ -1750,7 +1750,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
enum dmub_status status;
int r;
- switch (adev->ip_versions[DCE_HWIP]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0):
dmub_asic = DMUB_ASIC_DCN21;
fw_name_dmub = FIRMWARE_RENOIR_DMUB;
@@ -1758,7 +1758,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
break;
case IP_VERSION(3, 0, 0):
- if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
dmub_asic = DMUB_ASIC_DCN30;
fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
} else {
@@ -2078,7 +2078,7 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
* therefore, this function apply to navi10/12/14 but not Renoir
* *
*/
- switch (adev->ip_versions[DCE_HWIP]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 0, 2):
case IP_VERSION(2, 0, 0):
break;
@@ -4086,7 +4086,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Use Outbox interrupt */
- switch (adev->ip_versions[DCE_HWIP]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(3, 0, 0):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
@@ -4098,7 +4098,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break;
default:
DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
- adev->ip_versions[DCE_HWIP]);
+ adev->ip_versions[DCE_HWIP][0]);
}
#endif
@@ -4186,7 +4186,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break;
default:
#if defined(CONFIG_DRM_AMD_DC_DCN)
- switch (adev->ip_versions[DCE_HWIP]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
case IP_VERSION(2, 0, 2):
@@ -4205,7 +4205,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break;
default:
DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
- adev->ip_versions[DCE_HWIP]);
+ adev->ip_versions[DCE_HWIP][0]);
goto fail;
}
#endif
@@ -4357,7 +4357,7 @@ static int dm_early_init(void *handle)
break;
default:
#if defined(CONFIG_DRM_AMD_DC_DCN)
- switch (adev->ip_versions[DCE_HWIP]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 0, 2):
case IP_VERSION(3, 0, 0):
adev->mode_info.num_crtc = 6;
@@ -4387,7 +4387,7 @@ static int dm_early_init(void *handle)
break;
default:
DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
- adev->ip_versions[DCE_HWIP]);
+ adev->ip_versions[DCE_HWIP][0]);
return -EINVAL;
}
#endif
@@ -4609,7 +4609,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
tiling_info->gfx9.num_rb_per_se =
adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
tiling_info->gfx9.shaderEnable = 1;
- if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
+ if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
}
@@ -5050,7 +5050,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
case AMDGPU_FAMILY_NV:
case AMDGPU_FAMILY_VGH:
case AMDGPU_FAMILY_YC:
- if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
+ if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
add_gfx10_3_modifiers(adev, mods, &size, &capacity);
else
add_gfx10_1_modifiers(adev, mods, &size, &capacity);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 150cac4ea75c..9c601997a96a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -455,7 +455,7 @@ static int smu_get_power_num_states(void *handle,
bool is_support_sw_smu(struct amdgpu_device *adev)
{
- if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
+ if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
return true;
return false;
@@ -575,7 +575,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
smu->od_enabled = true;
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 5):
case IP_VERSION(11, 0, 9):
@@ -694,7 +694,7 @@ static int smu_late_init(void *handle)
return ret;
}
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1))
return 0;
if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
@@ -1140,10 +1140,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
if (adev->in_suspend && smu_is_dpm_running(smu)) {
dev_info(adev->dev, "dpm has been enabled\n");
/* this is needed specifically */
- if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)))
+ if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)))
ret = smu_system_features_control(smu, true);
return ret;
}
@@ -1286,7 +1286,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
int ret = 0;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- if (adev->ip_versions[MP1_HWIP] < IP_VERSION(11, 0, 0)) {
+ if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
if (smu->ppt_funcs->load_microcode) {
ret = smu->ppt_funcs->load_microcode(smu);
if (ret)
@@ -1405,14 +1405,14 @@ static int smu_disable_dpms(struct smu_context *smu)
* properly.
*/
if (smu->uploading_custom_pp_table &&
- ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))))
+ ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))))
return smu_disable_all_features_with_exception(smu,
true,
SMU_FEATURE_COUNT);
@@ -1421,10 +1421,10 @@ static int smu_disable_dpms(struct smu_context *smu)
* For Sienna_Cichlid, PMFW will handle the features disablement properly
* on BACO in. Driver involvement is unnecessary.
*/
- if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))) &&
+ if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))) &&
use_baco)
return smu_disable_all_features_with_exception(smu,
true,
@@ -1446,7 +1446,7 @@ static int smu_disable_dpms(struct smu_context *smu)
dev_err(adev->dev, "Failed to disable smu features.\n");
}
- if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0) &&
+ if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0) &&
adev->gfx.rlc.funcs->stop)
adev->gfx.rlc.funcs->stop(adev);
@@ -2283,11 +2283,11 @@ int smu_get_power_limit(void *handle,
} else {
switch (limit_level) {
case SMU_PPT_LIMIT_CURRENT:
- if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 2)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
+ if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)))
ret = smu_get_asic_power_limits(smu,
&smu->current_power_limit,
NULL,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index d96f904a765b..71161f6b78fe 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -345,7 +345,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
/* DPM UCLK enablement should be skipped for navi10 A0 secure board */
if (!(is_asic_secure(smu) &&
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
(adev->rev_id == 0)) &&
(adev->pm.pp_feature & PP_MCLK_DPM_MASK))
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
@@ -354,7 +354,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
/* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
if (is_asic_secure(smu) &&
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
(adev->rev_id == 0))
*(uint64_t *)feature_mask &=
~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
@@ -925,7 +925,7 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
return ret;
}
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 9):
if (smu_version > 0x00341C00)
ret = navi12_get_smu_metrics_data(smu, member, value);
@@ -935,8 +935,8 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 5):
default:
- if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
- ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
+ if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
+ ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
ret = navi10_get_smu_metrics_data(smu, member, value);
else
ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
@@ -1509,7 +1509,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
uint32_t sclk_freq;
pstate_table->gfxclk_pstate.min = gfx_table->min;
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 0):
switch (adev->pdev->revision) {
case 0xf0: /* XTX */
@@ -2562,8 +2562,8 @@ static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
return false;
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0) ||
- adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5))
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) ||
+ adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5))
return true;
return false;
@@ -2671,8 +2671,8 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
* - PPSMC_MSG_SetDriverDummyTableDramAddrLow
* - PPSMC_MSG_GetUMCFWWA
*/
- if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
- ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
+ if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
+ ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GET_UMC_FW_WA,
0,
@@ -2691,13 +2691,13 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
return 0;
if (umc_fw_disable_cdr) {
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
return navi10_umc_hybrid_cdr_workaround(smu);
} else {
return navi10_set_dummy_pstates_table_location(smu);
}
} else {
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
return navi10_umc_hybrid_cdr_workaround(smu);
}
@@ -3151,7 +3151,7 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
return ret;
}
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 9):
if (smu_version > 0x00341C00)
ret = navi12_get_gpu_metrics(smu, table);
@@ -3161,8 +3161,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 5):
default:
- if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
- ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
+ if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
+ ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
ret = navi10_get_gpu_metrics(smu, table);
else
ret =navi10_get_legacy_gpu_metrics(smu, table);
@@ -3180,7 +3180,7 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
uint32_t param = 0;
/* Navi12 does not support this */
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))
return 0;
/*
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 6a0fed5e33d9..15e66e1912de 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -74,7 +74,7 @@
#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
#define GET_PPTABLE_MEMBER(field, member) do {\
- if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))\
+ if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
(*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
else\
(*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
@@ -82,7 +82,7 @@
static int get_table_size(struct smu_context *smu)
{
- if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
+ if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
return sizeof(PPTable_beige_goby_t);
else
return sizeof(PPTable_t);
@@ -298,7 +298,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
}
if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
- (adev->ip_versions[MP1_HWIP] > IP_VERSION(11, 0, 7)) &&
+ (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
!(adev->flags & AMD_IS_APU))
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
@@ -496,7 +496,7 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s
uint32_t throttler_status = 0;
int i;
- if ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
+ if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
(smu->smc_fw_version >= 0x3A4300)) {
for (i = 0; i < THROTTLER_COUNT; i++)
throttler_status |=
@@ -517,7 +517,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
&(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
SmuMetrics_V2_t *metrics_v2 =
&(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
- bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
+ bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
(smu->smc_fw_version >= 0x3A4300)) ? true : false;
uint16_t average_gfx_activity;
int ret = 0;
@@ -1170,7 +1170,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
* and onwards SMU firmwares.
*/
smu_cmn_get_smc_version(smu, NULL, &smu_version);
- if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
+ if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
(smu_version < 0x003a2900))
break;
@@ -1937,7 +1937,7 @@ static void sienna_cichlid_dump_od_table(struct smu_context *smu,
od_table->UclkFmax);
smu_cmn_get_smc_version(smu, NULL, &smu_version);
- if (!((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
+ if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
(smu_version < 0x003a2900)))
dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
}
@@ -2161,7 +2161,7 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
* and onwards SMU firmwares.
*/
smu_cmn_get_smc_version(smu, NULL, &smu_version);
- if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
+ if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
(smu_version < 0x003a2900)) {
dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
"only by 58.41.0 and onwards SMU firmwares!\n");
@@ -2865,7 +2865,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
PPTable_t *pptable = table_context->driver_pptable;
int i;
- if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)) {
+ if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
beige_goby_dump_pptable(smu);
return;
}
@@ -3625,7 +3625,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
SmuMetrics_V2_t *metrics_v2 =
&(metrics_external.SmuMetrics_V2);
struct amdgpu_device *adev = smu->adev;
- bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
+ bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
(smu->smc_fw_version >= 0x3A4300)) ? true : false;
uint16_t average_gfx_activity;
int ret = 0;
@@ -3706,8 +3706,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
- if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
- ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
+ if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
+ ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
} else {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 1ae8b8dc3bd3..3470c33ee09d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -90,11 +90,11 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
struct amdgpu_firmware_info *ucode = NULL;
if (amdgpu_sriov_vf(adev) &&
- ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
- (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7))))
+ ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
+ (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7))))
return 0;
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 0):
chip_name = "navi10";
break;
@@ -121,7 +121,7 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
break;
default:
dev_err(adev->dev, "Unsupported IP version 0x%x\n",
- adev->ip_versions[MP1_HWIP]);
+ adev->ip_versions[MP1_HWIP][0]);
return -EINVAL;
}
@@ -239,7 +239,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
if (smu->is_apu)
adev->pm.fw_version = smu_version;
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 0):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
break;
@@ -272,7 +272,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
break;
default:
dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
- adev->ip_versions[MP1_HWIP]);
+ adev->ip_versions[MP1_HWIP][0]);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
break;
}
@@ -496,7 +496,7 @@ int smu_v11_0_init_power(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
struct smu_power_context *smu_power = &smu->smu_power;
- size_t size = adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ?
+ size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ?
sizeof(struct smu_11_5_power_context) :
sizeof(struct smu_11_0_power_context);
@@ -753,9 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
/* Navy_Flounder/Dimgrey_Cavefish do not support to change
* display num currently
*/
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11) ||
- adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ||
- adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) ||
+ adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ||
+ adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
return 0;
return smu_cmn_send_smc_msg_with_param(smu,
@@ -1140,7 +1140,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
int ret = 0;
struct amdgpu_device *adev = smu->adev;
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 5):
case IP_VERSION(11, 0, 9):
@@ -1634,7 +1634,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
mutex_lock(&smu_baco->mutex);
if (state == SMU_BACO_STATE_ENTER) {
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 11):
case IP_VERSION(11, 0, 12):
@@ -1653,7 +1653,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
default:
if (!ras || !adev->ras_enabled ||
adev->gmc.xgmi.pending_reset) {
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
data |= 0x80000000;
WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
@@ -1935,7 +1935,7 @@ int smu_v11_0_set_performance_level(struct smu_context *smu,
* Separate MCLK and SOCCLK soft min/max settings are not allowed
* on Arcturus.
*/
- if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
mclk_min = mclk_max = 0;
socclk_min = socclk_max = 0;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 08f3cc809fc6..05c5e61f3506 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -89,13 +89,13 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
if (amdgpu_sriov_vf(adev))
return 0;
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 2):
chip_name = "aldebaran";
break;
default:
dev_err(adev->dev, "Unsupported IP version 0x%x\n",
- adev->ip_versions[MP1_HWIP]);
+ adev->ip_versions[MP1_HWIP][0]);
return -EINVAL;
}
@@ -211,7 +211,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
smu_minor = (smu_version >> 8) & 0xff;
smu_debug = (smu_version >> 0) & 0xff;
- switch (smu->adev->ip_versions[MP1_HWIP]) {
+ switch (smu->adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 2):
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
break;
@@ -221,7 +221,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
break;
default:
dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
- smu->adev->ip_versions[MP1_HWIP]);
+ smu->adev->ip_versions[MP1_HWIP][0]);
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
break;
}
@@ -743,7 +743,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
int ret = 0;
struct amdgpu_device *adev = smu->adev;
- switch (adev->ip_versions[MP1_HWIP]) {
+ switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 61/66] drm/amdgpu: convert IP version array to include instances
2021-09-21 18:07 ` [PATCH 61/66] drm/amdgpu: convert IP version array to include instances Alex Deucher
@ 2021-09-22 9:08 ` Lazar, Lijo
2021-09-22 16:17 ` Alex Deucher
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-22 9:08 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
On 9/21/2021 11:37 PM, Alex Deucher wrote:
> Allow us to query instances versions more cleanly.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 262 +++++++++---------
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 +--
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 80 +++---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 72 ++---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/nv.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 34 +--
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 24 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 +-
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +-
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 52 ++--
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 32 +--
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 28 +-
> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 +-
> 29 files changed, 394 insertions(+), 394 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index b153c3740307..f4bceb2624fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1096,7 +1096,7 @@ struct amdgpu_device {
> struct pci_saved_state *pci_state;
>
> struct amdgpu_reset_control *reset_cntl;
> - uint32_t ip_versions[HW_ID_MAX];
> + uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
Here is the confusion. "ip_versions" is used like this -
adev->ip_versions[MMHUB_HWIP] - which means the first dimension can max
out at MAX_HWIP. So why is the array maxed to HW_ID_MAX? HWID looks
like a completely different thing.
Got this confusion while reviewing patch 52. Besides, this change
doesn't go well with that patch because HWIP is really replicating
instances.
Thanks,
Lijo
> };
>
> static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 9d8aea39f36a..eff348dee9e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -369,7 +369,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> hw_id_names[le16_to_cpu(ip->hw_id)]);
> adev->reg_offset[hw_ip][ip->number_instance] =
> ip->base_address;
> - adev->ip_versions[hw_ip + ip->number_instance] =
> + adev->ip_versions[hw_ip][ip->number_instance] =
> amdgpu_discovery_convert_version(ip->major,
> ip->minor,
> ip->revision);
> @@ -525,139 +525,139 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> case CHIP_VEGA10:
> vega10_reg_base_init(adev);
> adev->sdma.num_instances = 2;
> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
> - adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
> break;
> case CHIP_VEGA12:
> vega10_reg_base_init(adev);
> adev->sdma.num_instances = 2;
> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
> - adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
> break;
> case CHIP_RAVEN:
> vega10_reg_base_init(adev);
> adev->sdma.num_instances = 1;
> adev->vcn.num_vcn_inst = 1;
> if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
> - adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
> - adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
> - adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
> - adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
> - adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
> - adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
> + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
> } else {
> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
> - adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
> - adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
> - adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
> - adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
> - adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
> - adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
> + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
> }
> break;
> case CHIP_VEGA20:
> vega20_reg_base_init(adev);
> adev->sdma.num_instances = 2;
> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
> - adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
> - adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> - adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
> break;
> case CHIP_ARCTURUS:
> arct_reg_base_init(adev);
> adev->sdma.num_instances = 8;
> adev->vcn.num_vcn_inst = 2;
> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
> - adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
> - adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> - adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
> - adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
> break;
> case CHIP_ALDEBARAN:
> aldebaran_reg_base_init(adev);
> adev->sdma.num_instances = 5;
> adev->vcn.num_vcn_inst = 2;
> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
> - adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
> - adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
> - adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
> - adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
> - adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
> + adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
> break;
> default:
> r = amdgpu_discovery_reg_base_init(adev);
> @@ -673,7 +673,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> break;
> }
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 2, 1):
> case IP_VERSION(9, 4, 0):
> @@ -706,11 +706,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> return -EINVAL;
> }
>
> - if (adev->ip_versions[XGMI_HWIP] == IP_VERSION(4, 8, 0))
> + if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
> adev->gmc.xgmi.supported = true;
>
> /* set NBIO version */
> - switch (adev->ip_versions[NBIO_HWIP]) {
> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> case IP_VERSION(6, 1, 0):
> case IP_VERSION(6, 2, 0):
> adev->nbio.funcs = &nbio_v6_1_funcs;
> @@ -749,7 +749,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> break;
> }
>
> - switch (adev->ip_versions[HDP_HWIP]) {
> + switch (adev->ip_versions[HDP_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> case IP_VERSION(4, 0, 1):
> case IP_VERSION(4, 1, 0):
> @@ -771,7 +771,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> break;
> }
>
> - switch (adev->ip_versions[DF_HWIP]) {
> + switch (adev->ip_versions[DF_HWIP][0]) {
> case IP_VERSION(3, 6, 0):
> case IP_VERSION(3, 6, 1):
> case IP_VERSION(3, 6, 2):
> @@ -788,7 +788,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> break;
> }
>
> - switch (adev->ip_versions[SMUIO_HWIP]) {
> + switch (adev->ip_versions[SMUIO_HWIP][0]) {
> case IP_VERSION(9, 0, 0):
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(10, 0, 0):
> @@ -819,7 +819,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> /* what IP to use for this? */
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 1, 0):
> case IP_VERSION(9, 2, 1):
> @@ -847,7 +847,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> /* use GC or MMHUB IP version */
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 1, 0):
> case IP_VERSION(9, 2, 1):
> @@ -874,7 +874,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> return -EINVAL;
> }
>
> - switch (adev->ip_versions[OSSSYS_HWIP]) {
> + switch (adev->ip_versions[OSSSYS_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> case IP_VERSION(4, 0, 1):
> case IP_VERSION(4, 1, 0):
> @@ -900,7 +900,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> - switch (adev->ip_versions[MP0_HWIP]) {
> + switch (adev->ip_versions[MP0_HWIP][0]) {
> case IP_VERSION(9, 0, 0):
> amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
> break;
> @@ -938,7 +938,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(9, 0, 0):
> case IP_VERSION(10, 0, 0):
> case IP_VERSION(10, 0, 1):
> @@ -975,8 +975,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
> amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
> #if defined(CONFIG_DRM_AMD_DC)
> - } else if (adev->ip_versions[DCE_HWIP]) {
> - switch (adev->ip_versions[DCE_HWIP]) {
> + } else if (adev->ip_versions[DCE_HWIP][0]) {
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(1, 0, 0):
> case IP_VERSION(1, 0, 1):
> case IP_VERSION(2, 0, 2):
> @@ -995,8 +995,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> default:
> return -EINVAL;
> }
> - } else if (adev->ip_versions[DCI_HWIP]) {
> - switch (adev->ip_versions[DCI_HWIP]) {
> + } else if (adev->ip_versions[DCI_HWIP][0]) {
> + switch (adev->ip_versions[DCI_HWIP][0]) {
> case IP_VERSION(12, 0, 0):
> case IP_VERSION(12, 0, 1):
> case IP_VERSION(12, 1, 0):
> @@ -1007,7 +1007,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
> }
> #endif
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 1, 0):
> case IP_VERSION(9, 2, 1):
> @@ -1034,7 +1034,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> return -EINVAL;
> }
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> case IP_VERSION(4, 0, 1):
> case IP_VERSION(4, 1, 0):
> @@ -1064,7 +1064,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(9, 0, 0):
> case IP_VERSION(10, 0, 0):
> case IP_VERSION(10, 0, 1):
> @@ -1098,8 +1098,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
> }
>
> - if (adev->ip_versions[VCE_HWIP]) {
> - switch (adev->ip_versions[UVD_HWIP]) {
> + if (adev->ip_versions[VCE_HWIP][0]) {
> + switch (adev->ip_versions[UVD_HWIP][0]) {
> case IP_VERSION(7, 0, 0):
> case IP_VERSION(7, 2, 0):
> amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
> @@ -1107,7 +1107,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> default:
> return -EINVAL;
> }
> - switch (adev->ip_versions[VCE_HWIP]) {
> + switch (adev->ip_versions[VCE_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> case IP_VERSION(4, 1, 0):
> amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
> @@ -1116,7 +1116,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> return -EINVAL;
> }
> } else {
> - switch (adev->ip_versions[UVD_HWIP]) {
> + switch (adev->ip_versions[UVD_HWIP][0]) {
> case IP_VERSION(1, 0, 0):
> case IP_VERSION(1, 0, 1):
> amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
> @@ -1153,7 +1153,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> }
>
> if (adev->enable_mes) {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index c47d29689be4..7d414f1606b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -76,7 +76,7 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp
> return;
> }
>
> - switch (adev->ip_versions[MP0_HWIP]) {
> + switch (adev->ip_versions[MP0_HWIP][0]) {
> case IP_VERSION(11, 0, 4):
> case IP_VERSION(11, 0, 7):
> case IP_VERSION(11, 0, 9):
> @@ -97,7 +97,7 @@ static int psp_early_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> struct psp_context *psp = &adev->psp;
>
> - switch (adev->ip_versions[MP0_HWIP]) {
> + switch (adev->ip_versions[MP0_HWIP][0]) {
> case IP_VERSION(9, 0, 0):
> psp_v3_1_set_psp_funcs(psp);
> psp->autoload_supported = false;
> @@ -279,7 +279,7 @@ static int psp_sw_init(void *handle)
> return ret;
> }
> } else if (amdgpu_sriov_vf(adev) &&
> - adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2)) {
> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) {
> ret = psp_init_ta_microcode(psp, "aldebaran");
> if (ret) {
> DRM_ERROR("Failed to initialize ta microcode!\n");
> @@ -322,8 +322,8 @@ static int psp_sw_init(void *handle)
> }
> }
>
> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7)) {
> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
> ret= psp_sysfs_init(adev);
> if (ret) {
> return ret;
> @@ -353,8 +353,8 @@ static int psp_sw_fini(void *handle)
> psp->ta_fw = NULL;
> }
>
> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7))
> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
> psp_sysfs_fini(adev);
>
> kfree(cmd);
> @@ -613,7 +613,7 @@ static int psp_tmr_init(struct psp_context *psp)
>
> static bool psp_skip_tmr(struct psp_context *psp)
> {
> - switch (psp->adev->ip_versions[MP0_HWIP]) {
> + switch (psp->adev->ip_versions[MP0_HWIP][0]) {
> case IP_VERSION(11, 0, 9):
> case IP_VERSION(11, 0, 7):
> case IP_VERSION(13, 0, 2):
> @@ -1010,8 +1010,8 @@ int psp_xgmi_terminate(struct psp_context *psp)
> struct amdgpu_device *adev = psp->adev;
>
> /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
> adev->gmc.xgmi.connected_to_cpu))
> return 0;
>
> @@ -1113,7 +1113,7 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
>
> static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
> {
> - return psp->adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
> + return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
> psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;
> }
>
> @@ -2232,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp)
>
> if ((amdgpu_in_reset(adev) &&
> ras && adev->ras_enabled &&
> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 2)))) {
> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
> ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
> if (ret) {
> DRM_WARN("Failed to set MP1 state prepare for reload\n");
> @@ -2330,9 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
> continue;
>
> if (psp->autoload_supported &&
> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7) ||
> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 11) ||
> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 12)) &&
> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
> (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
> ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
> ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
> @@ -2920,7 +2920,7 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
> le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
>
> if (adev->gmc.xgmi.connected_to_cpu ||
> - (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2))) {
> + (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
> adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
> adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 9724f5f5f702..4d3f2386ef53 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -86,7 +86,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> for (i = 0; i < adev->vcn.num_vcn_inst; i++)
> atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
>
> - switch (adev->ip_versions[UVD_HWIP]) {
> + switch (adev->ip_versions[UVD_HWIP][0]) {
> case IP_VERSION(1, 0, 0):
> case IP_VERSION(1, 0, 1):
> if (adev->apu_flags & AMD_APU_IS_RAVEN2)
> @@ -134,7 +134,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> adev->vcn.indirect_sram = true;
> break;
> case IP_VERSION(3, 0, 0):
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
> fw_name = FIRMWARE_SIENNA_CICHLID;
> else
> fw_name = FIRMWARE_NAVY_FLOUNDER;
> diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> index d3f634eb40fb..ab6a07e5e8c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> @@ -77,7 +77,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[ATHUB_HWIP]) {
> + switch (adev->ip_versions[ATHUB_HWIP][0]) {
> case IP_VERSION(2, 0, 0):
> case IP_VERSION(2, 0, 2):
> athub_v2_0_update_medium_grain_clock_gating(adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> index 0fbeaf05204e..2edefd10e56c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> @@ -70,7 +70,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[ATHUB_HWIP]) {
> + switch (adev->ip_versions[ATHUB_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> case IP_VERSION(2, 1, 1):
> case IP_VERSION(2, 1, 2):
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 4c632306ed70..71bb3c0dc1da 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -1537,7 +1537,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
> scratch_reg3 = adev->rmmio +
> (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
>
> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> spare_int = adev->rmmio +
> (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
> + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
> @@ -3727,7 +3727,7 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
>
> static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> soc15_program_register_sequence(adev,
> golden_settings_gc_rlc_spm_10_0_nv10,
> @@ -3750,7 +3750,7 @@ static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
>
> static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> soc15_program_register_sequence(adev,
> golden_settings_gc_10_1,
> @@ -3985,7 +3985,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
> {
> adev->gfx.cp_fw_write_wait = false;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 2):
> case IP_VERSION(10, 1, 1):
> @@ -4066,7 +4066,7 @@ static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
>
> static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> @@ -4093,7 +4093,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
>
> DRM_DEBUG("\n");
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> chip_name = "navi10";
> break;
> @@ -4684,7 +4684,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
>
> adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -4818,7 +4818,7 @@ static int gfx_v10_0_sw_init(void *handle)
> struct amdgpu_kiq *kiq;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -5068,8 +5068,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
> for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
> for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
> bitmap = i * adev->gfx.config.max_sh_per_se + j;
> - if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
> - (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
> + if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
> + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
> ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
> continue;
> gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
> @@ -5096,7 +5096,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
>
> /* for ASICs that integrates GFX v10.3
> * pa_sc_tile_steering_override should be set to 0 */
> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> return 0;
>
> /* init num_sc */
> @@ -5249,7 +5249,7 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
> /* TCCs are global (not instanced). */
> uint32_t tcc_disable;
>
> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
> RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
> } else {
> @@ -5326,7 +5326,7 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
> adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
>
> /* csib */
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
> adev->gfx.rlc.clear_state_gpu_addr >> 32);
> WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
> @@ -5948,7 +5948,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
> tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
> tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
>
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
> } else {
> WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
> @@ -6337,7 +6337,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
> }
> WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
> }
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -6474,7 +6474,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
> static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
> {
> if (enable) {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -6488,7 +6488,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
> break;
> }
> } else {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -6586,7 +6586,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
> struct amdgpu_device *adev = ring->adev;
>
> /* tell RLC which is KIQ queue */
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -7303,7 +7303,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
>
> /* check if mmVGT_ESGS_RING_SIZE_UMD
> * has been remapped to mmVGT_ESGS_RING_SIZE */
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 4):
> @@ -7350,7 +7350,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
> * index will auto-inc after each data writting */
> WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -7520,19 +7520,19 @@ static int gfx_v10_0_hw_init(void *handle)
> * init golden registers and rlc resume may override some registers,
> * reconfig them here
> */
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 10) ||
> - adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 1) ||
> - adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2))
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
> gfx_v10_0_tcp_harvest(adev);
>
> r = gfx_v10_0_cp_resume(adev);
> if (r)
> return r;
>
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
> gfx_v10_3_program_pbb_mode(adev);
>
> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> gfx_v10_3_set_power_brake_sequence(adev);
>
> return r;
> @@ -7584,7 +7584,7 @@ static int gfx_v10_0_hw_fini(void *handle)
> if (amdgpu_sriov_vf(adev)) {
> gfx_v10_0_cp_gfx_enable(adev, false);
> /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
> tmp &= 0xffffff00;
> WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
> @@ -7670,7 +7670,7 @@ static int gfx_v10_0_soft_reset(void *handle)
>
> /* GRBM_STATUS2 */
> tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -7726,7 +7726,7 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> {
> uint64_t clock, clock_lo, clock_hi, hi_check;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 1):
> case IP_VERSION(10, 3, 3):
> clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
> @@ -7784,7 +7784,7 @@ static int gfx_v10_0_early_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -7848,7 +7848,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
> data = RLC_SAFE_MODE__CMD_MASK;
> data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -7884,7 +7884,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
> uint32_t data;
>
> data = RLC_SAFE_MODE__CMD_MASK;
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -8193,7 +8193,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d
> mmCGTS_SA1_QUAD1_SM_CTRL_REG
> };
>
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
> reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
> tcp_ctrl_regs_nv12[i];
> @@ -8238,8 +8238,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> /* === CGCG + CGLS === */
> gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
>
> - if ((adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 1, 10)) &&
> - (adev->ip_versions[GC_HWIP] <= IP_VERSION(10, 1, 2)))
> + if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 1, 10)) &&
> + (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(10, 1, 2)))
> gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
> } else {
> /* CGCG/CGLS should be disabled before MGCG/MGLS
> @@ -8335,7 +8335,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> * Power/performance team will optimize it and might give a new value later.
> */
> if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 1):
> data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
> WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
> @@ -8399,7 +8399,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -8428,7 +8428,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -9541,7 +9541,7 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
>
> static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 3):
> @@ -9641,8 +9641,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
> for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
> for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
> bitmap = i * adev->gfx.config.max_sh_per_se + j;
> - if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
> - (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
> + if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
> + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
> ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
> continue;
> mask = 1;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 3a160d78c98f..8f2966bcf5a4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -953,7 +953,7 @@ static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
>
> static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> soc15_program_register_sequence(adev,
> golden_settings_gc_9_0,
> @@ -1009,8 +1009,8 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
> break;
> }
>
> - if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
> - (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2)))
> + if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
> + (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)))
> soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
> (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
> }
> @@ -1194,14 +1194,14 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
> adev->gfx.me_fw_write_wait = false;
> adev->gfx.mec_fw_write_wait = false;
>
> - if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
> + if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
> ((adev->gfx.mec_fw_version < 0x000001a5) ||
> (adev->gfx.mec_feature_version < 46) ||
> (adev->gfx.pfp_fw_version < 0x000000b7) ||
> (adev->gfx.pfp_feature_version < 46)))
> DRM_WARN_ONCE("CP firmware version too old, please update!");
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> (adev->gfx.me_feature_version >= 42) &&
> @@ -1301,7 +1301,7 @@ static bool is_raven_kicker(struct amdgpu_device *adev)
>
> static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
> {
> - if ((adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0)) &&
> + if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) &&
> (adev->gfx.me_fw_version >= 0x000000a5) &&
> (adev->gfx.me_feature_version >= 52))
> return true;
> @@ -1314,7 +1314,7 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
> if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 2, 1):
> case IP_VERSION(9, 4, 0):
> @@ -1558,9 +1558,9 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
>
> static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)
> {
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2) ||
> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0))
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0))
> return false;
>
> return true;
> @@ -1668,7 +1668,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
>
> DRM_DEBUG("\n");
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> chip_name = "vega10";
> break;
> @@ -1800,7 +1800,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
>
> if (adev->flags & AMD_IS_APU)
> always_on_cu_num = 4;
> - else if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1))
> + else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1))
> always_on_cu_num = 8;
> else
> always_on_cu_num = 12;
> @@ -1969,7 +1969,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
> return r;
> }
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 2, 2):
> case IP_VERSION(9, 1, 0):
> gfx_v9_0_init_lbpw(adev);
> @@ -2149,7 +2149,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
>
> adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> adev->gfx.config.max_hw_contexts = 8;
> adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
> @@ -2313,7 +2313,7 @@ static int gfx_v9_0_sw_init(void *handle)
> struct amdgpu_kiq *kiq;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 2, 1):
> case IP_VERSION(9, 4, 0):
> @@ -2605,7 +2605,7 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
> {
> uint32_t tmp;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 4, 1):
> tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
> tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
> @@ -2941,7 +2941,7 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
> /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
> data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
> WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 3, 0))
> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0))
> pwr_10_0_gfxip_control_over_cgpg(adev, true);
> }
> }
> @@ -3053,7 +3053,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
> * And it's needed by gfxoff feature.
> */
> if (adev->gfx.rlc.is_rlc_v2_1) {
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1) ||
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) ||
> (adev->apu_flags & AMD_APU_IS_RAVEN2))
> gfx_v9_1_init_rlc_save_restore_list(adev);
> gfx_v9_0_enable_save_restore_machine(adev);
> @@ -3166,7 +3166,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
> return r;
> }
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 2, 2):
> case IP_VERSION(9, 1, 0):
> if (amdgpu_lbpw == 0)
> @@ -3969,8 +3969,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
> {
> u32 tmp;
>
> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1) &&
> - adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2))
> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) &&
> + adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))
> return;
>
> tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
> @@ -4010,7 +4010,7 @@ static int gfx_v9_0_hw_init(void *handle)
> if (r)
> return r;
>
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> gfx_v9_4_2_set_power_brake_sequence(adev);
>
> return r;
> @@ -4242,7 +4242,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>
> amdgpu_gfx_off_ctrl(adev, false);
> mutex_lock(&adev->gfx.gpu_clock_mutex);
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
> clock = gfx_v9_0_kiq_read_clock(adev);
> } else {
> WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
> @@ -4592,7 +4592,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
> if (!ring->sched.ready)
> return 0;
>
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1)) {
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
> vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
> vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
> vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
> @@ -4742,8 +4742,8 @@ static int gfx_v9_0_early_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> adev->gfx.num_gfx_rings = 0;
> else
> adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
> @@ -4777,7 +4777,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
> }
>
> /* requires IBs so do in late init after IB pool is initialized */
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
> else
> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
> @@ -4905,7 +4905,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
> /* 1 - RLC_CGTT_MGCG_OVERRIDE */
> def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>
> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
> data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
>
> data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
> @@ -4939,7 +4939,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
> /* 1 - MGCG_OVERRIDE */
> def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>
> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
> data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
>
> data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
> @@ -5045,7 +5045,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
> /* enable cgcg FSM(0x0000363F) */
> def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
>
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1))
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1))
> data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> else
> @@ -5171,7 +5171,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 2, 2):
> case IP_VERSION(9, 1, 0):
> case IP_VERSION(9, 3, 0):
> @@ -5218,7 +5218,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 2, 1):
> case IP_VERSION(9, 4, 0):
> @@ -5268,7 +5268,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
> if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
>
> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) {
> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) {
> /* AMD_CG_SUPPORT_GFX_3D_CGCG */
> data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
> if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
> @@ -7039,7 +7039,7 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
>
> static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 2, 1):
> case IP_VERSION(9, 4, 0):
> @@ -7058,7 +7058,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
> static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
> {
> /* init asci gds info */
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 2, 1):
> case IP_VERSION(9, 4, 0):
> @@ -7080,7 +7080,7 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
> break;
> }
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> case IP_VERSION(9, 4, 0):
> adev->gds.gds_compute_max_wave_id = 0x7ff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> index 149f3843e0e7..e80d1dc43079 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> @@ -506,7 +506,7 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
> u32 max_num_physical_nodes = 0;
> u32 max_physical_node_id = 0;
>
> - switch (adev->ip_versions[XGMI_HWIP]) {
> + switch (adev->ip_versions[XGMI_HWIP][0]) {
> case IP_VERSION(4, 8, 0):
> max_num_physical_nodes = 4;
> max_physical_node_id = 3;
> @@ -544,7 +544,7 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
> adev->gfx.config.max_sh_per_se *
> adev->gfx.config.max_shader_engines);
>
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3)) {
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) {
> /* Get SA disabled bitmap from eFuse setting */
> efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
> efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index b488257ff201..6d0586009de3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -133,7 +133,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
> * the new fast GRBM interface.
> */
> if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
> - (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
> + (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
> RREG32(hub->vm_l2_pro_fault_status);
>
> status = RREG32(hub->vm_l2_pro_fault_status);
> @@ -268,7 +268,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
> * to avoid a false ACK due to the new fast GRBM interface.
> */
> if ((vmhub == AMDGPU_GFXHUB_0) &&
> - (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
> + (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
> RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
> hub->eng_distance * eng, hub_ip);
>
> @@ -657,7 +657,7 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
>
> static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[UMC_HWIP]) {
> + switch (adev->ip_versions[UMC_HWIP][0]) {
> case IP_VERSION(8, 7, 0):
> adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
> adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
> @@ -674,7 +674,7 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
>
> static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 3, 0):
> case IP_VERSION(2, 4, 0):
> adev->mmhub.funcs = &mmhub_v2_3_funcs;
> @@ -687,7 +687,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
>
> static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 3, 0):
> case IP_VERSION(10, 3, 2):
> case IP_VERSION(10, 3, 1):
> @@ -857,7 +857,7 @@ static int gmc_v10_0_sw_init(void *handle)
> adev->gmc.vram_vendor = vram_vendor;
> }
>
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> case IP_VERSION(10, 1, 1):
> case IP_VERSION(10, 1, 2):
> @@ -1132,7 +1132,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
> if (r)
> return r;
>
> - if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
> + if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
> return athub_v2_1_set_clockgating(adev, state);
> else
> return athub_v2_0_set_clockgating(adev, state);
> @@ -1144,7 +1144,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
>
> adev->mmhub.funcs->get_clockgating(adev, flags);
>
> - if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
> + if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
> athub_v2_1_get_clockgating(adev, flags);
> else
> athub_v2_0_get_clockgating(adev, flags);
> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> index 88938115557b..eecfb1545c1e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> @@ -49,7 +49,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
> static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
> struct amdgpu_ring *ring)
> {
> - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 4, 0))
> + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
> return;
>
> if (!ring || !ring->funcs->emit_wreg)
> @@ -79,7 +79,7 @@ static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
> if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
> return;
>
> - if (adev->ip_versions[HDP_HWIP] >= IP_VERSION(4, 4, 0))
> + if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
> WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
> else
> /*read back hdp ras counter to reset it to 0 */
> @@ -91,10 +91,10 @@ static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
> {
> uint32_t def, data;
>
> - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 0) ||
> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 1) ||
> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 1) ||
> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 0)) {
> + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
> def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
> @@ -136,7 +136,7 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
>
> static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[HDP_HWIP]) {
> + switch (adev->ip_versions[HDP_HWIP][0]) {
> case IP_VERSION(4, 2, 1):
> WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index e0cb919b4814..25f8e93e5ec3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -153,7 +153,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
> dev_err(adev->dev,
> "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> status);
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 0, 0):
> case IP_VERSION(2, 0, 2):
> mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
> @@ -569,7 +569,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
> if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
> return;
>
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> case IP_VERSION(2, 1, 1):
> case IP_VERSION(2, 1, 2):
> @@ -603,7 +603,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
> DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
> }
>
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> case IP_VERSION(2, 1, 1):
> case IP_VERSION(2, 1, 2):
> @@ -629,7 +629,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
> if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
> return;
>
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> case IP_VERSION(2, 1, 1):
> case IP_VERSION(2, 1, 2):
> @@ -646,7 +646,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
> data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
>
> if (def != data) {
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> case IP_VERSION(2, 1, 1):
> case IP_VERSION(2, 1, 2):
> @@ -665,7 +665,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 0, 0):
> case IP_VERSION(2, 0, 2):
> case IP_VERSION(2, 1, 0):
> @@ -690,7 +690,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
> if (amdgpu_sriov_vf(adev))
> *flags = 0;
>
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> case IP_VERSION(2, 1, 1):
> case IP_VERSION(2, 1, 2):
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> index 4cf5d0595bbe..a11d60ec6321 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> @@ -90,7 +90,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
> dev_err(adev->dev,
> "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> status);
> - switch (adev->ip_versions[MMHUB_HWIP]) {
> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> case IP_VERSION(2, 3, 0):
> case IP_VERSION(2, 4, 0):
> mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index c3f968d9cfcb..1d8414c3fadb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -107,7 +107,7 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
> {
> u32 ih_cntl, ih_rb_cntl;
>
> - if (adev->ip_versions[OSSSYS_HWIP] < IP_VERSION(5, 0, 3))
> + if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3))
> return;
>
> ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
> @@ -332,7 +332,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
>
> if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
> if (ih[0]->use_bus_addr) {
> - switch (adev->ip_versions[OSSSYS_HWIP]) {
> + switch (adev->ip_versions[OSSSYS_HWIP][0]) {
> case IP_VERSION(5, 0, 3):
> case IP_VERSION(5, 2, 0):
> case IP_VERSION(5, 2, 1):
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 57be517d70bf..89e32d6e2c10 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -180,7 +180,7 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
> static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
> const struct amdgpu_video_codecs **codecs)
> {
> - switch (adev->ip_versions[UVD_HWIP]) {
> + switch (adev->ip_versions[UVD_HWIP][0]) {
> case IP_VERSION(3, 0, 0):
> if (amdgpu_sriov_vf(adev)) {
> if (encode)
> @@ -509,7 +509,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
> dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
> amdgpu_reset_method);
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 5, 0):
> case IP_VERSION(13, 0, 1):
> case IP_VERSION(13, 0, 3):
> @@ -1044,7 +1044,7 @@ static int nv_common_early_init(void *handle)
> /* TODO: split the GC and PG flags based on the relevant IP version for which
> * they are relevant.
> */
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(10, 1, 10):
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> AMD_CG_SUPPORT_GFX_CGCG |
> @@ -1375,7 +1375,7 @@ static int nv_common_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[NBIO_HWIP]) {
> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> case IP_VERSION(2, 3, 0):
> case IP_VERSION(2, 3, 1):
> case IP_VERSION(2, 3, 2):
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> index 13dace5d2855..382cebfc2069 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -93,7 +93,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
>
> DRM_DEBUG("\n");
>
> - switch (adev->ip_versions[MP0_HWIP]) {
> + switch (adev->ip_versions[MP0_HWIP][0]) {
> case IP_VERSION(11, 0, 2):
> chip_name = "vega20";
> break;
> @@ -129,7 +129,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> }
>
>
> - switch (adev->ip_versions[MP0_HWIP]) {
> + switch (adev->ip_versions[MP0_HWIP][0]) {
> case IP_VERSION(11, 0, 2):
> case IP_VERSION(11, 0, 4):
> err = psp_init_sos_microcode(psp, chip_name);
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> index 64b52c5ea981..17655bc6d2f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> @@ -47,7 +47,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
> const char *chip_name;
> int err = 0;
>
> - switch (adev->ip_versions[MP0_HWIP]) {
> + switch (adev->ip_versions[MP0_HWIP][0]) {
> case IP_VERSION(13, 0, 2):
> chip_name = "aldebaran";
> break;
> @@ -58,7 +58,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
> default:
> BUG();
> }
> - switch (adev->ip_versions[MP0_HWIP]) {
> + switch (adev->ip_versions[MP0_HWIP][0]) {
> case IP_VERSION(13, 0, 2):
> err = psp_init_sos_microcode(psp, chip_name);
> if (err)
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index cb74f8c35d0a..e8e4749e9c79 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -469,7 +469,7 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
>
> static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> soc15_program_register_sequence(adev,
> golden_settings_sdma_4,
> @@ -539,7 +539,7 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
> * The only chips with SDMAv4 and ULV are VG10 and VG20.
> * Server SKUs take a different hysteresis setting from other SKUs.
> */
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> if (adev->pdev->device == 0x6860)
> break;
> @@ -590,8 +590,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
>
> /* arcturus shares the same FW memory across
> all SDMA isntances */
> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
> - adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0))
> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
> + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
> break;
> }
>
> @@ -621,7 +621,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
>
> DRM_DEBUG("\n");
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> chip_name = "vega10";
> break;
> @@ -667,8 +667,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
> goto out;
>
> for (i = 1; i < adev->sdma.num_instances; i++) {
> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
> - adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0)) {
> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
> + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
> /* Acturus & Aldebaran will leverage the same FW memory
> for every SDMA instance */
> memcpy((void *)&adev->sdma.instance[i],
> @@ -1108,7 +1108,7 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
> * Arcturus for the moment and firmware version 14
> * and above.
> */
> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) &&
> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) &&
> adev->sdma.instance[i].fw_version >= 14)
> WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
> /* Extend page fault timeout to avoid interrupt storm */
> @@ -1395,7 +1395,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
> if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
> return;
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(4, 1, 0):
> case IP_VERSION(4, 1, 1):
> case IP_VERSION(4, 1, 2):
> @@ -1838,7 +1838,7 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
> {
> uint fw_version = adev->sdma.instance[0].fw_version;
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> return fw_version >= 430;
> case IP_VERSION(4, 0, 1):
> @@ -1863,7 +1863,7 @@ static int sdma_v4_0_early_init(void *handle)
> }
>
> /* TODO: Page queue breaks driver reload under SRIOV */
> - if ((adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 0, 0)) &&
> + if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) &&
> amdgpu_sriov_vf((adev)))
> adev->sdma.has_page_queue = false;
> else if (sdma_v4_0_fw_support_paging_queue(adev))
> @@ -2136,14 +2136,14 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
> amdgpu_fence_process(&adev->sdma.instance[instance].ring);
> break;
> case 1:
> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 0))
> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0))
> amdgpu_fence_process(&adev->sdma.instance[instance].page);
> break;
> case 2:
> /* XXX compute */
> break;
> case 3:
> - if (adev->ip_versions[SDMA0_HWIP] != IP_VERSION(4, 2, 0))
> + if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0))
> amdgpu_fence_process(&adev->sdma.instance[instance].page);
> break;
> }
> @@ -2359,7 +2359,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(4, 1, 0):
> case IP_VERSION(4, 1, 1):
> case IP_VERSION(4, 1, 2):
> @@ -2547,7 +2547,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> int i;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
> adev->sdma.instance[i].ring.funcs =
> &sdma_v4_0_ring_funcs_2nd_mmhub;
> else
> @@ -2555,7 +2555,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> &sdma_v4_0_ring_funcs;
> adev->sdma.instance[i].ring.me = i;
> if (adev->sdma.has_page_queue) {
> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
> adev->sdma.instance[i].page.funcs =
> &sdma_v4_0_page_ring_funcs_2nd_mmhub;
> else
> @@ -2782,7 +2782,7 @@ static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
>
> static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(4, 2, 0):
> case IP_VERSION(4, 2, 2):
> adev->sdma.funcs = &sdma_v4_0_ras_funcs;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index d3b01d2977c0..853d1511b889 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -187,7 +187,7 @@ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
>
> static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(5, 0, 0):
> soc15_program_register_sequence(adev,
> golden_settings_sdma_5,
> @@ -248,12 +248,12 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
> const struct common_firmware_header *header = NULL;
> const struct sdma_firmware_header_v1_0 *hdr;
>
> - if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 0, 5)))
> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
> return 0;
>
> DRM_DEBUG("\n");
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(5, 0, 0):
> chip_name = "navi10";
> break;
> @@ -1634,7 +1634,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(5, 0, 0):
> case IP_VERSION(5, 0, 2):
> case IP_VERSION(5, 0, 5):
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 92f29beda3b2..0fec1d9dd638 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -136,7 +136,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
>
> DRM_DEBUG("\n");
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(5, 2, 0):
> chip_name = "sienna_cichlid";
> break;
> @@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
> (void *)&adev->sdma.instance[0],
> sizeof(struct amdgpu_sdma_instance));
>
> - if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 0)))
> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
> return 0;
>
> DRM_DEBUG("psp_load == '%s'\n",
> @@ -1530,7 +1530,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
>
> - if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
> @@ -1567,7 +1567,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
>
> - if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
>
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
> @@ -1596,7 +1596,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[SDMA0_HWIP]) {
> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> case IP_VERSION(5, 2, 0):
> case IP_VERSION(5, 2, 2):
> case IP_VERSION(5, 2, 1):
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7f4cd1a4f6cb..74310bb4216a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -156,8 +156,8 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
> static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
> const struct amdgpu_video_codecs **codecs)
> {
> - if (adev->ip_versions[VCE_HWIP]) {
> - switch (adev->ip_versions[VCE_HWIP]) {
> + if (adev->ip_versions[VCE_HWIP][0]) {
> + switch (adev->ip_versions[VCE_HWIP][0]) {
> case IP_VERSION(4, 0, 0):
> case IP_VERSION(4, 1, 0):
> if (encode)
> @@ -169,7 +169,7 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
> return -EINVAL;
> }
> } else {
> - switch (adev->ip_versions[UVD_HWIP]) {
> + switch (adev->ip_versions[UVD_HWIP][0]) {
> case IP_VERSION(1, 0, 0):
> case IP_VERSION(1, 0, 1):
> if (encode)
> @@ -341,11 +341,11 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
> {
> u32 reference_clock = adev->clock.spll.reference_freq;
>
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
> - adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
> return 10000;
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
> - adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
> return reference_clock / 4;
>
> return reference_clock;
> @@ -576,7 +576,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
> dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
> amdgpu_reset_method);
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(10, 0, 0):
> case IP_VERSION(10, 0, 1):
> case IP_VERSION(12, 0, 0):
> @@ -641,7 +641,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
>
> static bool soc15_supports_baco(struct amdgpu_device *adev)
> {
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(9, 0, 0):
> case IP_VERSION(11, 0, 2):
> if (adev->asic_type == CHIP_VEGA20) {
> @@ -1172,7 +1172,7 @@ static int soc15_common_early_init(void *handle)
> /* TODO: split the GC and PG flags based on the relevant IP version for which
> * they are relevant.
> */
> - switch (adev->ip_versions[GC_HWIP]) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> case IP_VERSION(9, 0, 1):
> adev->asic_funcs = &soc15_asic_funcs;
> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> @@ -1583,7 +1583,7 @@ static int soc15_common_set_clockgating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[NBIO_HWIP]) {
> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> case IP_VERSION(6, 1, 0):
> case IP_VERSION(6, 2, 0):
> case IP_VERSION(7, 4, 0):
> @@ -1639,7 +1639,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
>
> adev->hdp.funcs->get_clock_gating_state(adev, flags);
>
> - if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
> + if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
>
> /* AMD_CG_SUPPORT_DRM_MGCG */
> data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index e9758969fbe6..f4a7a30ecebd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1720,7 +1720,7 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.harvest_config & (1 << i))
> continue;
> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
> adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
> else /* CHIP_ALDEBARAN */
> adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
> @@ -1737,7 +1737,7 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
> if (adev->vcn.harvest_config & (1 << j))
> continue;
> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
> adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
> else /* CHIP_ALDEBARAN */
> adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index a81d834ea0d3..6940716db1df 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -95,7 +95,7 @@ static int vcn_v3_0_early_init(void *handle)
> adev->vcn.num_enc_rings = 1;
>
> } else {
> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 0)) {
> u32 harvest;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> @@ -110,7 +110,7 @@ static int vcn_v3_0_early_init(void *handle)
> return -ENOENT;
> }
>
> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33))
> adev->vcn.num_enc_rings = 0;
> else
> adev->vcn.num_enc_rings = 2;
> @@ -1270,7 +1270,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
> fw_shared->rb.wptr = lower_32_bits(ring->wptr);
> fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
>
> - if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
> + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
> fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
> ring = &adev->vcn.inst[i].ring_enc[0];
> WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
> @@ -1642,7 +1642,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
> UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
> ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
>
> - if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
> + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
> /* Restore */
> fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
> fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index fc8a30251fa4..fb89ce4dd28c 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1344,7 +1344,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> init_data.flags.gpu_vm_support = true;
> break;
> default:
> - switch (adev->ip_versions[DCE_HWIP]) {
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> init_data.flags.gpu_vm_support = true;
> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> @@ -1658,7 +1658,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
> return 0;
> break;
> default:
> - switch (adev->ip_versions[DCE_HWIP]) {
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(2, 0, 2):
> case IP_VERSION(2, 0, 0):
> case IP_VERSION(2, 1, 0):
> @@ -1750,7 +1750,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
> enum dmub_status status;
> int r;
>
> - switch (adev->ip_versions[DCE_HWIP]) {
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> dmub_asic = DMUB_ASIC_DCN21;
> fw_name_dmub = FIRMWARE_RENOIR_DMUB;
> @@ -1758,7 +1758,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
> fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
> break;
> case IP_VERSION(3, 0, 0):
> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
> dmub_asic = DMUB_ASIC_DCN30;
> fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
> } else {
> @@ -2078,7 +2078,7 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
> * therefore, this function apply to navi10/12/14 but not Renoir
> * *
> */
> - switch (adev->ip_versions[DCE_HWIP]) {
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(2, 0, 2):
> case IP_VERSION(2, 0, 0):
> break;
> @@ -4086,7 +4086,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> /* Use Outbox interrupt */
> - switch (adev->ip_versions[DCE_HWIP]) {
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(3, 0, 0):
> case IP_VERSION(3, 1, 2):
> case IP_VERSION(3, 1, 3):
> @@ -4098,7 +4098,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> break;
> default:
> DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
> - adev->ip_versions[DCE_HWIP]);
> + adev->ip_versions[DCE_HWIP][0]);
> }
> #endif
>
> @@ -4186,7 +4186,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> break;
> default:
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> - switch (adev->ip_versions[DCE_HWIP]) {
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(1, 0, 0):
> case IP_VERSION(1, 0, 1):
> case IP_VERSION(2, 0, 2):
> @@ -4205,7 +4205,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> break;
> default:
> DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
> - adev->ip_versions[DCE_HWIP]);
> + adev->ip_versions[DCE_HWIP][0]);
> goto fail;
> }
> #endif
> @@ -4357,7 +4357,7 @@ static int dm_early_init(void *handle)
> break;
> default:
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> - switch (adev->ip_versions[DCE_HWIP]) {
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(2, 0, 2):
> case IP_VERSION(3, 0, 0):
> adev->mode_info.num_crtc = 6;
> @@ -4387,7 +4387,7 @@ static int dm_early_init(void *handle)
> break;
> default:
> DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
> - adev->ip_versions[DCE_HWIP]);
> + adev->ip_versions[DCE_HWIP][0]);
> return -EINVAL;
> }
> #endif
> @@ -4609,7 +4609,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
> tiling_info->gfx9.num_rb_per_se =
> adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
> tiling_info->gfx9.shaderEnable = 1;
> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
> }
>
> @@ -5050,7 +5050,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
> case AMDGPU_FAMILY_NV:
> case AMDGPU_FAMILY_VGH:
> case AMDGPU_FAMILY_YC:
> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> add_gfx10_3_modifiers(adev, mods, &size, &capacity);
> else
> add_gfx10_1_modifiers(adev, mods, &size, &capacity);
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 150cac4ea75c..9c601997a96a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -455,7 +455,7 @@ static int smu_get_power_num_states(void *handle,
>
> bool is_support_sw_smu(struct amdgpu_device *adev)
> {
> - if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
> + if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
> return true;
>
> return false;
> @@ -575,7 +575,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
> smu->od_enabled = true;
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 5):
> case IP_VERSION(11, 0, 9):
> @@ -694,7 +694,7 @@ static int smu_late_init(void *handle)
> return ret;
> }
>
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1))
> return 0;
>
> if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
> @@ -1140,10 +1140,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
> if (adev->in_suspend && smu_is_dpm_running(smu)) {
> dev_info(adev->dev, "dpm has been enabled\n");
> /* this is needed specifically */
> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)))
> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)))
> ret = smu_system_features_control(smu, true);
> return ret;
> }
> @@ -1286,7 +1286,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
> int ret = 0;
>
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> - if (adev->ip_versions[MP1_HWIP] < IP_VERSION(11, 0, 0)) {
> + if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
> if (smu->ppt_funcs->load_microcode) {
> ret = smu->ppt_funcs->load_microcode(smu);
> if (ret)
> @@ -1405,14 +1405,14 @@ static int smu_disable_dpms(struct smu_context *smu)
> * properly.
> */
> if (smu->uploading_custom_pp_table &&
> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))))
> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))))
> return smu_disable_all_features_with_exception(smu,
> true,
> SMU_FEATURE_COUNT);
> @@ -1421,10 +1421,10 @@ static int smu_disable_dpms(struct smu_context *smu)
> * For Sienna_Cichlid, PMFW will handle the features disablement properly
> * on BACO in. Driver involvement is unnecessary.
> */
> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))) &&
> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))) &&
> use_baco)
> return smu_disable_all_features_with_exception(smu,
> true,
> @@ -1446,7 +1446,7 @@ static int smu_disable_dpms(struct smu_context *smu)
> dev_err(adev->dev, "Failed to disable smu features.\n");
> }
>
> - if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0) &&
> + if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0) &&
> adev->gfx.rlc.funcs->stop)
> adev->gfx.rlc.funcs->stop(adev);
>
> @@ -2283,11 +2283,11 @@ int smu_get_power_limit(void *handle,
> } else {
> switch (limit_level) {
> case SMU_PPT_LIMIT_CURRENT:
> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 2)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)))
> ret = smu_get_asic_power_limits(smu,
> &smu->current_power_limit,
> NULL,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index d96f904a765b..71161f6b78fe 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -345,7 +345,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
>
> /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> if (!(is_asic_secure(smu) &&
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
> (adev->rev_id == 0)) &&
> (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> @@ -354,7 +354,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
>
> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> if (is_asic_secure(smu) &&
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
> (adev->rev_id == 0))
> *(uint64_t *)feature_mask &=
> ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
> @@ -925,7 +925,7 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
> return ret;
> }
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 0, 9):
> if (smu_version > 0x00341C00)
> ret = navi12_get_smu_metrics_data(smu, member, value);
> @@ -935,8 +935,8 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 5):
> default:
> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> ret = navi10_get_smu_metrics_data(smu, member, value);
> else
> ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
> @@ -1509,7 +1509,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
> uint32_t sclk_freq;
>
> pstate_table->gfxclk_pstate.min = gfx_table->min;
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 0, 0):
> switch (adev->pdev->revision) {
> case 0xf0: /* XTX */
> @@ -2562,8 +2562,8 @@ static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
> if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
> return false;
>
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0) ||
> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5))
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) ||
> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5))
> return true;
>
> return false;
> @@ -2671,8 +2671,8 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
> * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
> * - PPSMC_MSG_GetUMCFWWA
> */
> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
> ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_GET_UMC_FW_WA,
> 0,
> @@ -2691,13 +2691,13 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
> return 0;
>
> if (umc_fw_disable_cdr) {
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
> return navi10_umc_hybrid_cdr_workaround(smu);
> } else {
> return navi10_set_dummy_pstates_table_location(smu);
> }
> } else {
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
> return navi10_umc_hybrid_cdr_workaround(smu);
> }
>
> @@ -3151,7 +3151,7 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
> return ret;
> }
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 0, 9):
> if (smu_version > 0x00341C00)
> ret = navi12_get_gpu_metrics(smu, table);
> @@ -3161,8 +3161,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 5):
> default:
> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> ret = navi10_get_gpu_metrics(smu, table);
> else
> ret =navi10_get_legacy_gpu_metrics(smu, table);
> @@ -3180,7 +3180,7 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> uint32_t param = 0;
>
> /* Navi12 does not support this */
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))
> return 0;
>
> /*
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 6a0fed5e33d9..15e66e1912de 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -74,7 +74,7 @@
> #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
>
> #define GET_PPTABLE_MEMBER(field, member) do {\
> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))\
> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
> (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
> else\
> (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
> @@ -82,7 +82,7 @@
>
> static int get_table_size(struct smu_context *smu)
> {
> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
> return sizeof(PPTable_beige_goby_t);
> else
> return sizeof(PPTable_t);
> @@ -298,7 +298,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
> }
>
> if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
> - (adev->ip_versions[MP1_HWIP] > IP_VERSION(11, 0, 7)) &&
> + (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
> !(adev->flags & AMD_IS_APU))
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
>
> @@ -496,7 +496,7 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s
> uint32_t throttler_status = 0;
> int i;
>
> - if ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> + if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> (smu->smc_fw_version >= 0x3A4300)) {
> for (i = 0; i < THROTTLER_COUNT; i++)
> throttler_status |=
> @@ -517,7 +517,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
> &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
> SmuMetrics_V2_t *metrics_v2 =
> &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
> - bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> + bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> uint16_t average_gfx_activity;
> int ret = 0;
> @@ -1170,7 +1170,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
> * and onwards SMU firmwares.
> */
> smu_cmn_get_smc_version(smu, NULL, &smu_version);
> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> (smu_version < 0x003a2900))
> break;
>
> @@ -1937,7 +1937,7 @@ static void sienna_cichlid_dump_od_table(struct smu_context *smu,
> od_table->UclkFmax);
>
> smu_cmn_get_smc_version(smu, NULL, &smu_version);
> - if (!((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> + if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> (smu_version < 0x003a2900)))
> dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
> }
> @@ -2161,7 +2161,7 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
> * and onwards SMU firmwares.
> */
> smu_cmn_get_smc_version(smu, NULL, &smu_version);
> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> (smu_version < 0x003a2900)) {
> dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
> "only by 58.41.0 and onwards SMU firmwares!\n");
> @@ -2865,7 +2865,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
> PPTable_t *pptable = table_context->driver_pptable;
> int i;
>
> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)) {
> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
> beige_goby_dump_pptable(smu);
> return;
> }
> @@ -3625,7 +3625,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
> SmuMetrics_V2_t *metrics_v2 =
> &(metrics_external.SmuMetrics_V2);
> struct amdgpu_device *adev = smu->adev;
> - bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> + bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> uint16_t average_gfx_activity;
> int ret = 0;
> @@ -3706,8 +3706,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
>
> gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
>
> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
> gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
> gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
> } else {
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index 1ae8b8dc3bd3..3470c33ee09d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -90,11 +90,11 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
> struct amdgpu_firmware_info *ucode = NULL;
>
> if (amdgpu_sriov_vf(adev) &&
> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7))))
> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7))))
> return 0;
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 0, 0):
> chip_name = "navi10";
> break;
> @@ -121,7 +121,7 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
> break;
> default:
> dev_err(adev->dev, "Unsupported IP version 0x%x\n",
> - adev->ip_versions[MP1_HWIP]);
> + adev->ip_versions[MP1_HWIP][0]);
> return -EINVAL;
> }
>
> @@ -239,7 +239,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
> if (smu->is_apu)
> adev->pm.fw_version = smu_version;
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 0, 0):
> smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
> break;
> @@ -272,7 +272,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
> break;
> default:
> dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
> - adev->ip_versions[MP1_HWIP]);
> + adev->ip_versions[MP1_HWIP][0]);
> smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
> break;
> }
> @@ -496,7 +496,7 @@ int smu_v11_0_init_power(struct smu_context *smu)
> {
> struct amdgpu_device *adev = smu->adev;
> struct smu_power_context *smu_power = &smu->smu_power;
> - size_t size = adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ?
> + size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ?
> sizeof(struct smu_11_5_power_context) :
> sizeof(struct smu_11_0_power_context);
>
> @@ -753,9 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
> /* Navy_Flounder/Dimgrey_Cavefish do not support to change
> * display num currently
> */
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11) ||
> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ||
> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) ||
> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ||
> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
> return 0;
>
> return smu_cmn_send_smc_msg_with_param(smu,
> @@ -1140,7 +1140,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
> int ret = 0;
> struct amdgpu_device *adev = smu->adev;
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 5):
> case IP_VERSION(11, 0, 9):
> @@ -1634,7 +1634,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
> mutex_lock(&smu_baco->mutex);
>
> if (state == SMU_BACO_STATE_ENTER) {
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(11, 0, 7):
> case IP_VERSION(11, 0, 11):
> case IP_VERSION(11, 0, 12):
> @@ -1653,7 +1653,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
> default:
> if (!ras || !adev->ras_enabled ||
> adev->gmc.xgmi.pending_reset) {
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
> data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
> data |= 0x80000000;
> WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
> @@ -1935,7 +1935,7 @@ int smu_v11_0_set_performance_level(struct smu_context *smu,
> * Separate MCLK and SOCCLK soft min/max settings are not allowed
> * on Arcturus.
> */
> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
> mclk_min = mclk_max = 0;
> socclk_min = socclk_max = 0;
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index 08f3cc809fc6..05c5e61f3506 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -89,13 +89,13 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(13, 0, 2):
> chip_name = "aldebaran";
> break;
> default:
> dev_err(adev->dev, "Unsupported IP version 0x%x\n",
> - adev->ip_versions[MP1_HWIP]);
> + adev->ip_versions[MP1_HWIP][0]);
> return -EINVAL;
> }
>
> @@ -211,7 +211,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
> smu_minor = (smu_version >> 8) & 0xff;
> smu_debug = (smu_version >> 0) & 0xff;
>
> - switch (smu->adev->ip_versions[MP1_HWIP]) {
> + switch (smu->adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(13, 0, 2):
> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
> break;
> @@ -221,7 +221,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
> break;
> default:
> dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
> - smu->adev->ip_versions[MP1_HWIP]);
> + smu->adev->ip_versions[MP1_HWIP][0]);
> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
> break;
> }
> @@ -743,7 +743,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
> int ret = 0;
> struct amdgpu_device *adev = smu->adev;
>
> - switch (adev->ip_versions[MP1_HWIP]) {
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(13, 0, 1):
> case IP_VERSION(13, 0, 3):
> if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 61/66] drm/amdgpu: convert IP version array to include instances
2021-09-22 9:08 ` Lazar, Lijo
@ 2021-09-22 16:17 ` Alex Deucher
2021-09-23 4:58 ` Lazar, Lijo
0 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-22 16:17 UTC (permalink / raw)
To: Lazar, Lijo; +Cc: Alex Deucher, amd-gfx list
On Wed, Sep 22, 2021 at 5:08 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 9/21/2021 11:37 PM, Alex Deucher wrote:
> > Allow us to query instances versions more cleanly.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 262 +++++++++---------
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 +--
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 +-
> > drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 80 +++---
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 72 ++---
> > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 4 +-
> > drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 16 +-
> > drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 14 +-
> > drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 14 +-
> > drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 +-
> > drivers/gpu/drm/amd/amdgpu/nv.c | 8 +-
> > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 +-
> > drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 4 +-
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 34 +--
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +-
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +-
> > drivers/gpu/drm/amd/amdgpu/soc15.c | 24 +-
> > drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
> > drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 +-
> > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +-
> > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 52 ++--
> > .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 32 +--
> > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
> > .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 28 +-
> > .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 +-
> > 29 files changed, 394 insertions(+), 394 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index b153c3740307..f4bceb2624fb 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -1096,7 +1096,7 @@ struct amdgpu_device {
> > struct pci_saved_state *pci_state;
> >
> > struct amdgpu_reset_control *reset_cntl;
> > - uint32_t ip_versions[HW_ID_MAX];
> > + uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
>
> Here is the confusion. "ip_versions" is used like this -
> adev->ip_versions[MMHUB_HWIP] - which means the first dimension can max
> out at MAX_HWIP. So why is the array maxed to HW_ID_MAX? HWID looks
> like a completely different thing.
>
> Got this confusion while reviewing patch 52. Besides, this change
> doesn't go well with that patch because HWIP is really replicating
> instances.
It's not consistent unfortunately. SDMA is a good example. Sienna
cichlid has 8 total SDMA instances, each enumerated separately (HWIDs
42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are
enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x
HWID 43). UMC is another example. On most chips there are multiple
instances with the same HWID.
Alex
>
> Thanks,
> Lijo
>
> > };
> >
> > static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > index 9d8aea39f36a..eff348dee9e9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > @@ -369,7 +369,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> > hw_id_names[le16_to_cpu(ip->hw_id)]);
> > adev->reg_offset[hw_ip][ip->number_instance] =
> > ip->base_address;
> > - adev->ip_versions[hw_ip + ip->number_instance] =
> > + adev->ip_versions[hw_ip][ip->number_instance] =
> > amdgpu_discovery_convert_version(ip->major,
> > ip->minor,
> > ip->revision);
> > @@ -525,139 +525,139 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > case CHIP_VEGA10:
> > vega10_reg_base_init(adev);
> > adev->sdma.num_instances = 2;
> > - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
> > - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
> > - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
> > - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> > - adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
> > - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
> > - adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
> > - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> > - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> > - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
> > + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
> > + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
> > + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
> > + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
> > + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
> > + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
> > break;
> > case CHIP_VEGA12:
> > vega10_reg_base_init(adev);
> > adev->sdma.num_instances = 2;
> > - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
> > - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
> > - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
> > - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
> > - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
> > - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
> > - adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
> > - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
> > - adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> > - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
> > - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
> > - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> > - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> > - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
> > + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
> > + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
> > + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
> > + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
> > + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
> > + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
> > + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
> > + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
> > + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
> > + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
> > + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
> > + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
> > + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
> > + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
> > break;
> > case CHIP_RAVEN:
> > vega10_reg_base_init(adev);
> > adev->sdma.num_instances = 1;
> > adev->vcn.num_vcn_inst = 1;
> > if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
> > - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
> > - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
> > - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
> > - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
> > - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
> > - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
> > - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
> > - adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
> > - adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
> > - adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
> > - adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
> > - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
> > - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
> > - adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
> > - adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
> > + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
> > + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
> > + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
> > + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
> > + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
> > + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
> > + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
> > + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
> > + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
> > + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
> > + adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
> > + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
> > + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
> > + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
> > + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
> > } else {
> > - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
> > - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
> > - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
> > - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
> > - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
> > - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> > - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
> > - adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
> > - adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
> > - adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
> > - adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
> > - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
> > - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
> > - adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
> > - adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
> > + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
> > + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
> > + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
> > + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
> > + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
> > + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
> > + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
> > + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
> > + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
> > + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
> > + adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
> > + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
> > + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
> > + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
> > + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
> > }
> > break;
> > case CHIP_VEGA20:
> > vega20_reg_base_init(adev);
> > adev->sdma.num_instances = 2;
> > - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
> > - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
> > - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
> > - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
> > - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
> > - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
> > - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
> > - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
> > - adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
> > - adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> > - adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
> > - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
> > - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
> > - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
> > - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
> > - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
> > + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
> > + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
> > + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
> > + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
> > + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
> > + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
> > + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
> > + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
> > + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
> > + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
> > + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
> > + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
> > break;
> > case CHIP_ARCTURUS:
> > arct_reg_base_init(adev);
> > adev->sdma.num_instances = 8;
> > adev->vcn.num_vcn_inst = 2;
> > - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
> > - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
> > - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
> > - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
> > - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
> > - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
> > - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
> > - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
> > - adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
> > - adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> > - adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
> > - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
> > - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
> > - adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
> > + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
> > + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
> > + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
> > + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
> > + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
> > + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
> > + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
> > + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
> > + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
> > + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
> > + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
> > + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
> > + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
> > + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
> > break;
> > case CHIP_ALDEBARAN:
> > aldebaran_reg_base_init(adev);
> > adev->sdma.num_instances = 5;
> > adev->vcn.num_vcn_inst = 2;
> > - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
> > - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
> > - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
> > - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
> > - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
> > - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
> > - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
> > - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
> > - adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
> > - adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
> > - adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
> > - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
> > - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
> > - adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
> > - adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
> > + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
> > + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
> > + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
> > + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
> > + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
> > + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
> > + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
> > + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
> > + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
> > + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
> > + adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
> > + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
> > + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
> > + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
> > + adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
> > break;
> > default:
> > r = amdgpu_discovery_reg_base_init(adev);
> > @@ -673,7 +673,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > break;
> > }
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 2, 1):
> > case IP_VERSION(9, 4, 0):
> > @@ -706,11 +706,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > return -EINVAL;
> > }
> >
> > - if (adev->ip_versions[XGMI_HWIP] == IP_VERSION(4, 8, 0))
> > + if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
> > adev->gmc.xgmi.supported = true;
> >
> > /* set NBIO version */
> > - switch (adev->ip_versions[NBIO_HWIP]) {
> > + switch (adev->ip_versions[NBIO_HWIP][0]) {
> > case IP_VERSION(6, 1, 0):
> > case IP_VERSION(6, 2, 0):
> > adev->nbio.funcs = &nbio_v6_1_funcs;
> > @@ -749,7 +749,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > break;
> > }
> >
> > - switch (adev->ip_versions[HDP_HWIP]) {
> > + switch (adev->ip_versions[HDP_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > case IP_VERSION(4, 0, 1):
> > case IP_VERSION(4, 1, 0):
> > @@ -771,7 +771,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > break;
> > }
> >
> > - switch (adev->ip_versions[DF_HWIP]) {
> > + switch (adev->ip_versions[DF_HWIP][0]) {
> > case IP_VERSION(3, 6, 0):
> > case IP_VERSION(3, 6, 1):
> > case IP_VERSION(3, 6, 2):
> > @@ -788,7 +788,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > break;
> > }
> >
> > - switch (adev->ip_versions[SMUIO_HWIP]) {
> > + switch (adev->ip_versions[SMUIO_HWIP][0]) {
> > case IP_VERSION(9, 0, 0):
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(10, 0, 0):
> > @@ -819,7 +819,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > /* what IP to use for this? */
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 1, 0):
> > case IP_VERSION(9, 2, 1):
> > @@ -847,7 +847,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > /* use GC or MMHUB IP version */
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 1, 0):
> > case IP_VERSION(9, 2, 1):
> > @@ -874,7 +874,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > return -EINVAL;
> > }
> >
> > - switch (adev->ip_versions[OSSSYS_HWIP]) {
> > + switch (adev->ip_versions[OSSSYS_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > case IP_VERSION(4, 0, 1):
> > case IP_VERSION(4, 1, 0):
> > @@ -900,7 +900,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> > - switch (adev->ip_versions[MP0_HWIP]) {
> > + switch (adev->ip_versions[MP0_HWIP][0]) {
> > case IP_VERSION(9, 0, 0):
> > amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
> > break;
> > @@ -938,7 +938,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(9, 0, 0):
> > case IP_VERSION(10, 0, 0):
> > case IP_VERSION(10, 0, 1):
> > @@ -975,8 +975,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
> > amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
> > #if defined(CONFIG_DRM_AMD_DC)
> > - } else if (adev->ip_versions[DCE_HWIP]) {
> > - switch (adev->ip_versions[DCE_HWIP]) {
> > + } else if (adev->ip_versions[DCE_HWIP][0]) {
> > + switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(1, 0, 0):
> > case IP_VERSION(1, 0, 1):
> > case IP_VERSION(2, 0, 2):
> > @@ -995,8 +995,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > default:
> > return -EINVAL;
> > }
> > - } else if (adev->ip_versions[DCI_HWIP]) {
> > - switch (adev->ip_versions[DCI_HWIP]) {
> > + } else if (adev->ip_versions[DCI_HWIP][0]) {
> > + switch (adev->ip_versions[DCI_HWIP][0]) {
> > case IP_VERSION(12, 0, 0):
> > case IP_VERSION(12, 0, 1):
> > case IP_VERSION(12, 1, 0):
> > @@ -1007,7 +1007,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> > }
> > #endif
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 1, 0):
> > case IP_VERSION(9, 2, 1):
> > @@ -1034,7 +1034,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > return -EINVAL;
> > }
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > case IP_VERSION(4, 0, 1):
> > case IP_VERSION(4, 1, 0):
> > @@ -1064,7 +1064,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(9, 0, 0):
> > case IP_VERSION(10, 0, 0):
> > case IP_VERSION(10, 0, 1):
> > @@ -1098,8 +1098,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> > }
> >
> > - if (adev->ip_versions[VCE_HWIP]) {
> > - switch (adev->ip_versions[UVD_HWIP]) {
> > + if (adev->ip_versions[VCE_HWIP][0]) {
> > + switch (adev->ip_versions[UVD_HWIP][0]) {
> > case IP_VERSION(7, 0, 0):
> > case IP_VERSION(7, 2, 0):
> > amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
> > @@ -1107,7 +1107,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > default:
> > return -EINVAL;
> > }
> > - switch (adev->ip_versions[VCE_HWIP]) {
> > + switch (adev->ip_versions[VCE_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > case IP_VERSION(4, 1, 0):
> > amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
> > @@ -1116,7 +1116,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > return -EINVAL;
> > }
> > } else {
> > - switch (adev->ip_versions[UVD_HWIP]) {
> > + switch (adev->ip_versions[UVD_HWIP][0]) {
> > case IP_VERSION(1, 0, 0):
> > case IP_VERSION(1, 0, 1):
> > amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
> > @@ -1153,7 +1153,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> > }
> >
> > if (adev->enable_mes) {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > index c47d29689be4..7d414f1606b9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> > @@ -76,7 +76,7 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp
> > return;
> > }
> >
> > - switch (adev->ip_versions[MP0_HWIP]) {
> > + switch (adev->ip_versions[MP0_HWIP][0]) {
> > case IP_VERSION(11, 0, 4):
> > case IP_VERSION(11, 0, 7):
> > case IP_VERSION(11, 0, 9):
> > @@ -97,7 +97,7 @@ static int psp_early_init(void *handle)
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> > struct psp_context *psp = &adev->psp;
> >
> > - switch (adev->ip_versions[MP0_HWIP]) {
> > + switch (adev->ip_versions[MP0_HWIP][0]) {
> > case IP_VERSION(9, 0, 0):
> > psp_v3_1_set_psp_funcs(psp);
> > psp->autoload_supported = false;
> > @@ -279,7 +279,7 @@ static int psp_sw_init(void *handle)
> > return ret;
> > }
> > } else if (amdgpu_sriov_vf(adev) &&
> > - adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2)) {
> > + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) {
> > ret = psp_init_ta_microcode(psp, "aldebaran");
> > if (ret) {
> > DRM_ERROR("Failed to initialize ta microcode!\n");
> > @@ -322,8 +322,8 @@ static int psp_sw_init(void *handle)
> > }
> > }
> >
> > - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
> > - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7)) {
> > + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
> > + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
> > ret= psp_sysfs_init(adev);
> > if (ret) {
> > return ret;
> > @@ -353,8 +353,8 @@ static int psp_sw_fini(void *handle)
> > psp->ta_fw = NULL;
> > }
> >
> > - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
> > - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7))
> > + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
> > + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
> > psp_sysfs_fini(adev);
> >
> > kfree(cmd);
> > @@ -613,7 +613,7 @@ static int psp_tmr_init(struct psp_context *psp)
> >
> > static bool psp_skip_tmr(struct psp_context *psp)
> > {
> > - switch (psp->adev->ip_versions[MP0_HWIP]) {
> > + switch (psp->adev->ip_versions[MP0_HWIP][0]) {
> > case IP_VERSION(11, 0, 9):
> > case IP_VERSION(11, 0, 7):
> > case IP_VERSION(13, 0, 2):
> > @@ -1010,8 +1010,8 @@ int psp_xgmi_terminate(struct psp_context *psp)
> > struct amdgpu_device *adev = psp->adev;
> >
> > /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
> > - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
> > - (adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
> > + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
> > + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
> > adev->gmc.xgmi.connected_to_cpu))
> > return 0;
> >
> > @@ -1113,7 +1113,7 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
> >
> > static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
> > {
> > - return psp->adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
> > + return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
> > psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;
> > }
> >
> > @@ -2232,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp)
> >
> > if ((amdgpu_in_reset(adev) &&
> > ras && adev->ras_enabled &&
> > - (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
> > - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 2)))) {
> > + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
> > + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
> > ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
> > if (ret) {
> > DRM_WARN("Failed to set MP1 state prepare for reload\n");
> > @@ -2330,9 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
> > continue;
> >
> > if (psp->autoload_supported &&
> > - (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7) ||
> > - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 11) ||
> > - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 12)) &&
> > + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
> > + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
> > + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
> > (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
> > ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
> > ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
> > @@ -2920,7 +2920,7 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
> > le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
> >
> > if (adev->gmc.xgmi.connected_to_cpu ||
> > - (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2))) {
> > + (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
> > adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
> > adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> > index 9724f5f5f702..4d3f2386ef53 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> > @@ -86,7 +86,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> > for (i = 0; i < adev->vcn.num_vcn_inst; i++)
> > atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
> >
> > - switch (adev->ip_versions[UVD_HWIP]) {
> > + switch (adev->ip_versions[UVD_HWIP][0]) {
> > case IP_VERSION(1, 0, 0):
> > case IP_VERSION(1, 0, 1):
> > if (adev->apu_flags & AMD_APU_IS_RAVEN2)
> > @@ -134,7 +134,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> > adev->vcn.indirect_sram = true;
> > break;
> > case IP_VERSION(3, 0, 0):
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
> > fw_name = FIRMWARE_SIENNA_CICHLID;
> > else
> > fw_name = FIRMWARE_NAVY_FLOUNDER;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> > index d3f634eb40fb..ab6a07e5e8c4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> > @@ -77,7 +77,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[ATHUB_HWIP]) {
> > + switch (adev->ip_versions[ATHUB_HWIP][0]) {
> > case IP_VERSION(2, 0, 0):
> > case IP_VERSION(2, 0, 2):
> > athub_v2_0_update_medium_grain_clock_gating(adev,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> > index 0fbeaf05204e..2edefd10e56c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> > @@ -70,7 +70,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[ATHUB_HWIP]) {
> > + switch (adev->ip_versions[ATHUB_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > case IP_VERSION(2, 1, 1):
> > case IP_VERSION(2, 1, 2):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 4c632306ed70..71bb3c0dc1da 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -1537,7 +1537,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
> > scratch_reg3 = adev->rmmio +
> > (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
> >
> > - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> > + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> > spare_int = adev->rmmio +
> > (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
> > + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
> > @@ -3727,7 +3727,7 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
> >
> > static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > soc15_program_register_sequence(adev,
> > golden_settings_gc_rlc_spm_10_0_nv10,
> > @@ -3750,7 +3750,7 @@ static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
> >
> > static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > soc15_program_register_sequence(adev,
> > golden_settings_gc_10_1,
> > @@ -3985,7 +3985,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
> > {
> > adev->gfx.cp_fw_write_wait = false;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 2):
> > case IP_VERSION(10, 1, 1):
> > @@ -4066,7 +4066,7 @@ static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
> >
> > static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
> > adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> > @@ -4093,7 +4093,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
> >
> > DRM_DEBUG("\n");
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > chip_name = "navi10";
> > break;
> > @@ -4684,7 +4684,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
> >
> > adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -4818,7 +4818,7 @@ static int gfx_v10_0_sw_init(void *handle)
> > struct amdgpu_kiq *kiq;
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -5068,8 +5068,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
> > for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
> > for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
> > bitmap = i * adev->gfx.config.max_sh_per_se + j;
> > - if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
> > - (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
> > + if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
> > + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
> > ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
> > continue;
> > gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
> > @@ -5096,7 +5096,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
> >
> > /* for ASICs that integrates GFX v10.3
> > * pa_sc_tile_steering_override should be set to 0 */
> > - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> > + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> > return 0;
> >
> > /* init num_sc */
> > @@ -5249,7 +5249,7 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
> > /* TCCs are global (not instanced). */
> > uint32_t tcc_disable;
> >
> > - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> > + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> > tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
> > RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
> > } else {
> > @@ -5326,7 +5326,7 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
> > adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
> >
> > /* csib */
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> > WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
> > adev->gfx.rlc.clear_state_gpu_addr >> 32);
> > WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
> > @@ -5948,7 +5948,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
> > tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
> > tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
> >
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> > WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
> > } else {
> > WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
> > @@ -6337,7 +6337,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
> > }
> > WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
> > }
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -6474,7 +6474,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
> > static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
> > {
> > if (enable) {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -6488,7 +6488,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
> > break;
> > }
> > } else {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -6586,7 +6586,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
> > struct amdgpu_device *adev = ring->adev;
> >
> > /* tell RLC which is KIQ queue */
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -7303,7 +7303,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
> >
> > /* check if mmVGT_ESGS_RING_SIZE_UMD
> > * has been remapped to mmVGT_ESGS_RING_SIZE */
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 4):
> > @@ -7350,7 +7350,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
> > * index will auto-inc after each data writting */
> > WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -7520,19 +7520,19 @@ static int gfx_v10_0_hw_init(void *handle)
> > * init golden registers and rlc resume may override some registers,
> > * reconfig them here
> > */
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 10) ||
> > - adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 1) ||
> > - adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2))
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
> > + adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
> > + adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
> > gfx_v10_0_tcp_harvest(adev);
> >
> > r = gfx_v10_0_cp_resume(adev);
> > if (r)
> > return r;
> >
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
> > gfx_v10_3_program_pbb_mode(adev);
> >
> > - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> > + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> > gfx_v10_3_set_power_brake_sequence(adev);
> >
> > return r;
> > @@ -7584,7 +7584,7 @@ static int gfx_v10_0_hw_fini(void *handle)
> > if (amdgpu_sriov_vf(adev)) {
> > gfx_v10_0_cp_gfx_enable(adev, false);
> > /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
> > - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> > + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> > tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
> > tmp &= 0xffffff00;
> > WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
> > @@ -7670,7 +7670,7 @@ static int gfx_v10_0_soft_reset(void *handle)
> >
> > /* GRBM_STATUS2 */
> > tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -7726,7 +7726,7 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> > {
> > uint64_t clock, clock_lo, clock_hi, hi_check;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 1):
> > case IP_VERSION(10, 3, 3):
> > clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
> > @@ -7784,7 +7784,7 @@ static int gfx_v10_0_early_init(void *handle)
> > {
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -7848,7 +7848,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
> > data = RLC_SAFE_MODE__CMD_MASK;
> > data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -7884,7 +7884,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
> > uint32_t data;
> >
> > data = RLC_SAFE_MODE__CMD_MASK;
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -8193,7 +8193,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d
> > mmCGTS_SA1_QUAD1_SM_CTRL_REG
> > };
> >
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> > for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
> > reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
> > tcp_ctrl_regs_nv12[i];
> > @@ -8238,8 +8238,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> > /* === CGCG + CGLS === */
> > gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
> >
> > - if ((adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 1, 10)) &&
> > - (adev->ip_versions[GC_HWIP] <= IP_VERSION(10, 1, 2)))
> > + if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 1, 10)) &&
> > + (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(10, 1, 2)))
> > gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
> > } else {
> > /* CGCG/CGLS should be disabled before MGCG/MGLS
> > @@ -8335,7 +8335,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> > * Power/performance team will optimize it and might give a new value later.
> > */
> > if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 1):
> > data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
> > WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
> > @@ -8399,7 +8399,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -8428,7 +8428,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -9541,7 +9541,7 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
> >
> > static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 3):
> > @@ -9641,8 +9641,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
> > for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
> > for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
> > bitmap = i * adev->gfx.config.max_sh_per_se + j;
> > - if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
> > - (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
> > + if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
> > + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
> > ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
> > continue;
> > mask = 1;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 3a160d78c98f..8f2966bcf5a4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -953,7 +953,7 @@ static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
> >
> > static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > soc15_program_register_sequence(adev,
> > golden_settings_gc_9_0,
> > @@ -1009,8 +1009,8 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
> > break;
> > }
> >
> > - if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
> > - (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2)))
> > + if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
> > + (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)))
> > soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
> > (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
> > }
> > @@ -1194,14 +1194,14 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
> > adev->gfx.me_fw_write_wait = false;
> > adev->gfx.mec_fw_write_wait = false;
> >
> > - if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
> > + if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
> > ((adev->gfx.mec_fw_version < 0x000001a5) ||
> > (adev->gfx.mec_feature_version < 46) ||
> > (adev->gfx.pfp_fw_version < 0x000000b7) ||
> > (adev->gfx.pfp_feature_version < 46)))
> > DRM_WARN_ONCE("CP firmware version too old, please update!");
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> > (adev->gfx.me_feature_version >= 42) &&
> > @@ -1301,7 +1301,7 @@ static bool is_raven_kicker(struct amdgpu_device *adev)
> >
> > static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
> > {
> > - if ((adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0)) &&
> > + if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) &&
> > (adev->gfx.me_fw_version >= 0x000000a5) &&
> > (adev->gfx.me_feature_version >= 52))
> > return true;
> > @@ -1314,7 +1314,7 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
> > if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
> > adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 2, 1):
> > case IP_VERSION(9, 4, 0):
> > @@ -1558,9 +1558,9 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
> >
> > static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)
> > {
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2) ||
> > - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
> > - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0))
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
> > + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
> > + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0))
> > return false;
> >
> > return true;
> > @@ -1668,7 +1668,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
> >
> > DRM_DEBUG("\n");
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > chip_name = "vega10";
> > break;
> > @@ -1800,7 +1800,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
> >
> > if (adev->flags & AMD_IS_APU)
> > always_on_cu_num = 4;
> > - else if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1))
> > + else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1))
> > always_on_cu_num = 8;
> > else
> > always_on_cu_num = 12;
> > @@ -1969,7 +1969,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
> > return r;
> > }
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 2, 2):
> > case IP_VERSION(9, 1, 0):
> > gfx_v9_0_init_lbpw(adev);
> > @@ -2149,7 +2149,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
> >
> > adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > adev->gfx.config.max_hw_contexts = 8;
> > adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
> > @@ -2313,7 +2313,7 @@ static int gfx_v9_0_sw_init(void *handle)
> > struct amdgpu_kiq *kiq;
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 2, 1):
> > case IP_VERSION(9, 4, 0):
> > @@ -2605,7 +2605,7 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
> > {
> > uint32_t tmp;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 4, 1):
> > tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
> > tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
> > @@ -2941,7 +2941,7 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
> > /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
> > data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
> > WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
> > - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 3, 0))
> > + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0))
> > pwr_10_0_gfxip_control_over_cgpg(adev, true);
> > }
> > }
> > @@ -3053,7 +3053,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
> > * And it's needed by gfxoff feature.
> > */
> > if (adev->gfx.rlc.is_rlc_v2_1) {
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1) ||
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) ||
> > (adev->apu_flags & AMD_APU_IS_RAVEN2))
> > gfx_v9_1_init_rlc_save_restore_list(adev);
> > gfx_v9_0_enable_save_restore_machine(adev);
> > @@ -3166,7 +3166,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
> > return r;
> > }
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 2, 2):
> > case IP_VERSION(9, 1, 0):
> > if (amdgpu_lbpw == 0)
> > @@ -3969,8 +3969,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
> > {
> > u32 tmp;
> >
> > - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1) &&
> > - adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2))
> > + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) &&
> > + adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))
> > return;
> >
> > tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
> > @@ -4010,7 +4010,7 @@ static int gfx_v9_0_hw_init(void *handle)
> > if (r)
> > return r;
> >
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> > gfx_v9_4_2_set_power_brake_sequence(adev);
> >
> > return r;
> > @@ -4242,7 +4242,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> >
> > amdgpu_gfx_off_ctrl(adev, false);
> > mutex_lock(&adev->gfx.gpu_clock_mutex);
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
> > clock = gfx_v9_0_kiq_read_clock(adev);
> > } else {
> > WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
> > @@ -4592,7 +4592,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
> > if (!ring->sched.ready)
> > return 0;
> >
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1)) {
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
> > vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
> > vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
> > vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
> > @@ -4742,8 +4742,8 @@ static int gfx_v9_0_early_init(void *handle)
> > {
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
> > - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
> > + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> > adev->gfx.num_gfx_rings = 0;
> > else
> > adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
> > @@ -4777,7 +4777,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
> > }
> >
> > /* requires IBs so do in late init after IB pool is initialized */
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> > r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
> > else
> > r = gfx_v9_0_do_edc_gpr_workarounds(adev);
> > @@ -4905,7 +4905,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
> > /* 1 - RLC_CGTT_MGCG_OVERRIDE */
> > def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> >
> > - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
> > + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
> > data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
> >
> > data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
> > @@ -4939,7 +4939,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
> > /* 1 - MGCG_OVERRIDE */
> > def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> >
> > - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
> > + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
> > data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
> >
> > data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
> > @@ -5045,7 +5045,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
> > /* enable cgcg FSM(0x0000363F) */
> > def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> >
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1))
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1))
> > data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> > RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> > else
> > @@ -5171,7 +5171,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> > bool enable = (state == AMD_PG_STATE_GATE);
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 2, 2):
> > case IP_VERSION(9, 1, 0):
> > case IP_VERSION(9, 3, 0):
> > @@ -5218,7 +5218,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 2, 1):
> > case IP_VERSION(9, 4, 0):
> > @@ -5268,7 +5268,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
> > if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
> > *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
> >
> > - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) {
> > + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) {
> > /* AMD_CG_SUPPORT_GFX_3D_CGCG */
> > data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
> > if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
> > @@ -7039,7 +7039,7 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
> >
> > static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 2, 1):
> > case IP_VERSION(9, 4, 0):
> > @@ -7058,7 +7058,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
> > static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
> > {
> > /* init asci gds info */
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 2, 1):
> > case IP_VERSION(9, 4, 0):
> > @@ -7080,7 +7080,7 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
> > break;
> > }
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > case IP_VERSION(9, 4, 0):
> > adev->gds.gds_compute_max_wave_id = 0x7ff;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> > index 149f3843e0e7..e80d1dc43079 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> > @@ -506,7 +506,7 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
> > u32 max_num_physical_nodes = 0;
> > u32 max_physical_node_id = 0;
> >
> > - switch (adev->ip_versions[XGMI_HWIP]) {
> > + switch (adev->ip_versions[XGMI_HWIP][0]) {
> > case IP_VERSION(4, 8, 0):
> > max_num_physical_nodes = 4;
> > max_physical_node_id = 3;
> > @@ -544,7 +544,7 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
> > adev->gfx.config.max_sh_per_se *
> > adev->gfx.config.max_shader_engines);
> >
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3)) {
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) {
> > /* Get SA disabled bitmap from eFuse setting */
> > efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
> > efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> > index b488257ff201..6d0586009de3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> > @@ -133,7 +133,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
> > * the new fast GRBM interface.
> > */
> > if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
> > - (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
> > + (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
> > RREG32(hub->vm_l2_pro_fault_status);
> >
> > status = RREG32(hub->vm_l2_pro_fault_status);
> > @@ -268,7 +268,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
> > * to avoid a false ACK due to the new fast GRBM interface.
> > */
> > if ((vmhub == AMDGPU_GFXHUB_0) &&
> > - (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
> > + (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
> > RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
> > hub->eng_distance * eng, hub_ip);
> >
> > @@ -657,7 +657,7 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
> >
> > static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[UMC_HWIP]) {
> > + switch (adev->ip_versions[UMC_HWIP][0]) {
> > case IP_VERSION(8, 7, 0):
> > adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
> > adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
> > @@ -674,7 +674,7 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
> >
> > static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 3, 0):
> > case IP_VERSION(2, 4, 0):
> > adev->mmhub.funcs = &mmhub_v2_3_funcs;
> > @@ -687,7 +687,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
> >
> > static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 3, 0):
> > case IP_VERSION(10, 3, 2):
> > case IP_VERSION(10, 3, 1):
> > @@ -857,7 +857,7 @@ static int gmc_v10_0_sw_init(void *handle)
> > adev->gmc.vram_vendor = vram_vendor;
> > }
> >
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 1):
> > case IP_VERSION(10, 1, 2):
> > @@ -1132,7 +1132,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
> > if (r)
> > return r;
> >
> > - if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
> > + if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
> > return athub_v2_1_set_clockgating(adev, state);
> > else
> > return athub_v2_0_set_clockgating(adev, state);
> > @@ -1144,7 +1144,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
> >
> > adev->mmhub.funcs->get_clockgating(adev, flags);
> >
> > - if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
> > + if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
> > athub_v2_1_get_clockgating(adev, flags);
> > else
> > athub_v2_0_get_clockgating(adev, flags);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> > index 88938115557b..eecfb1545c1e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> > @@ -49,7 +49,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
> > static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
> > struct amdgpu_ring *ring)
> > {
> > - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 4, 0))
> > + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
> > return;
> >
> > if (!ring || !ring->funcs->emit_wreg)
> > @@ -79,7 +79,7 @@ static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
> > if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
> > return;
> >
> > - if (adev->ip_versions[HDP_HWIP] >= IP_VERSION(4, 4, 0))
> > + if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
> > WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
> > else
> > /*read back hdp ras counter to reset it to 0 */
> > @@ -91,10 +91,10 @@ static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
> > {
> > uint32_t def, data;
> >
> > - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 0) ||
> > - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 1) ||
> > - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 1) ||
> > - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 0)) {
> > + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
> > + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
> > + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
> > + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
> > def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
> >
> > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
> > @@ -136,7 +136,7 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
> >
> > static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[HDP_HWIP]) {
> > + switch (adev->ip_versions[HDP_HWIP][0]) {
> > case IP_VERSION(4, 2, 1):
> > WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
> > break;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> > index e0cb919b4814..25f8e93e5ec3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> > @@ -153,7 +153,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
> > dev_err(adev->dev,
> > "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> > status);
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 0, 0):
> > case IP_VERSION(2, 0, 2):
> > mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
> > @@ -569,7 +569,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
> > if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
> > return;
> >
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > case IP_VERSION(2, 1, 1):
> > case IP_VERSION(2, 1, 2):
> > @@ -603,7 +603,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
> > DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
> > }
> >
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > case IP_VERSION(2, 1, 1):
> > case IP_VERSION(2, 1, 2):
> > @@ -629,7 +629,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
> > if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
> > return;
> >
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > case IP_VERSION(2, 1, 1):
> > case IP_VERSION(2, 1, 2):
> > @@ -646,7 +646,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
> > data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
> >
> > if (def != data) {
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > case IP_VERSION(2, 1, 1):
> > case IP_VERSION(2, 1, 2):
> > @@ -665,7 +665,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 0, 0):
> > case IP_VERSION(2, 0, 2):
> > case IP_VERSION(2, 1, 0):
> > @@ -690,7 +690,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
> > if (amdgpu_sriov_vf(adev))
> > *flags = 0;
> >
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > case IP_VERSION(2, 1, 1):
> > case IP_VERSION(2, 1, 2):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > index 4cf5d0595bbe..a11d60ec6321 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> > @@ -90,7 +90,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
> > dev_err(adev->dev,
> > "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> > status);
> > - switch (adev->ip_versions[MMHUB_HWIP]) {
> > + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> > case IP_VERSION(2, 3, 0):
> > case IP_VERSION(2, 4, 0):
> > mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > index c3f968d9cfcb..1d8414c3fadb 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > @@ -107,7 +107,7 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
> > {
> > u32 ih_cntl, ih_rb_cntl;
> >
> > - if (adev->ip_versions[OSSSYS_HWIP] < IP_VERSION(5, 0, 3))
> > + if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3))
> > return;
> >
> > ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
> > @@ -332,7 +332,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
> >
> > if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
> > if (ih[0]->use_bus_addr) {
> > - switch (adev->ip_versions[OSSSYS_HWIP]) {
> > + switch (adev->ip_versions[OSSSYS_HWIP][0]) {
> > case IP_VERSION(5, 0, 3):
> > case IP_VERSION(5, 2, 0):
> > case IP_VERSION(5, 2, 1):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> > index 57be517d70bf..89e32d6e2c10 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -180,7 +180,7 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
> > static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
> > const struct amdgpu_video_codecs **codecs)
> > {
> > - switch (adev->ip_versions[UVD_HWIP]) {
> > + switch (adev->ip_versions[UVD_HWIP][0]) {
> > case IP_VERSION(3, 0, 0):
> > if (amdgpu_sriov_vf(adev)) {
> > if (encode)
> > @@ -509,7 +509,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
> > dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
> > amdgpu_reset_method);
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 5, 0):
> > case IP_VERSION(13, 0, 1):
> > case IP_VERSION(13, 0, 3):
> > @@ -1044,7 +1044,7 @@ static int nv_common_early_init(void *handle)
> > /* TODO: split the GC and PG flags based on the relevant IP version for which
> > * they are relevant.
> > */
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(10, 1, 10):
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > @@ -1375,7 +1375,7 @@ static int nv_common_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[NBIO_HWIP]) {
> > + switch (adev->ip_versions[NBIO_HWIP][0]) {
> > case IP_VERSION(2, 3, 0):
> > case IP_VERSION(2, 3, 1):
> > case IP_VERSION(2, 3, 2):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> > index 13dace5d2855..382cebfc2069 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> > @@ -93,7 +93,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> >
> > DRM_DEBUG("\n");
> >
> > - switch (adev->ip_versions[MP0_HWIP]) {
> > + switch (adev->ip_versions[MP0_HWIP][0]) {
> > case IP_VERSION(11, 0, 2):
> > chip_name = "vega20";
> > break;
> > @@ -129,7 +129,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> > }
> >
> >
> > - switch (adev->ip_versions[MP0_HWIP]) {
> > + switch (adev->ip_versions[MP0_HWIP][0]) {
> > case IP_VERSION(11, 0, 2):
> > case IP_VERSION(11, 0, 4):
> > err = psp_init_sos_microcode(psp, chip_name);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> > index 64b52c5ea981..17655bc6d2f1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> > @@ -47,7 +47,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
> > const char *chip_name;
> > int err = 0;
> >
> > - switch (adev->ip_versions[MP0_HWIP]) {
> > + switch (adev->ip_versions[MP0_HWIP][0]) {
> > case IP_VERSION(13, 0, 2):
> > chip_name = "aldebaran";
> > break;
> > @@ -58,7 +58,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
> > default:
> > BUG();
> > }
> > - switch (adev->ip_versions[MP0_HWIP]) {
> > + switch (adev->ip_versions[MP0_HWIP][0]) {
> > case IP_VERSION(13, 0, 2):
> > err = psp_init_sos_microcode(psp, chip_name);
> > if (err)
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index cb74f8c35d0a..e8e4749e9c79 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -469,7 +469,7 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
> >
> > static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > soc15_program_register_sequence(adev,
> > golden_settings_sdma_4,
> > @@ -539,7 +539,7 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
> > * The only chips with SDMAv4 and ULV are VG10 and VG20.
> > * Server SKUs take a different hysteresis setting from other SKUs.
> > */
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > if (adev->pdev->device == 0x6860)
> > break;
> > @@ -590,8 +590,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
> >
> > /* arcturus shares the same FW memory across
> > all SDMA isntances */
> > - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
> > - adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0))
> > + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
> > + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
> > break;
> > }
> >
> > @@ -621,7 +621,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
> >
> > DRM_DEBUG("\n");
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > chip_name = "vega10";
> > break;
> > @@ -667,8 +667,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
> > goto out;
> >
> > for (i = 1; i < adev->sdma.num_instances; i++) {
> > - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
> > - adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0)) {
> > + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
> > + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
> > /* Acturus & Aldebaran will leverage the same FW memory
> > for every SDMA instance */
> > memcpy((void *)&adev->sdma.instance[i],
> > @@ -1108,7 +1108,7 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
> > * Arcturus for the moment and firmware version 14
> > * and above.
> > */
> > - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) &&
> > + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) &&
> > adev->sdma.instance[i].fw_version >= 14)
> > WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
> > /* Extend page fault timeout to avoid interrupt storm */
> > @@ -1395,7 +1395,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
> > if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
> > return;
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(4, 1, 0):
> > case IP_VERSION(4, 1, 1):
> > case IP_VERSION(4, 1, 2):
> > @@ -1838,7 +1838,7 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
> > {
> > uint fw_version = adev->sdma.instance[0].fw_version;
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > return fw_version >= 430;
> > case IP_VERSION(4, 0, 1):
> > @@ -1863,7 +1863,7 @@ static int sdma_v4_0_early_init(void *handle)
> > }
> >
> > /* TODO: Page queue breaks driver reload under SRIOV */
> > - if ((adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 0, 0)) &&
> > + if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) &&
> > amdgpu_sriov_vf((adev)))
> > adev->sdma.has_page_queue = false;
> > else if (sdma_v4_0_fw_support_paging_queue(adev))
> > @@ -2136,14 +2136,14 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
> > amdgpu_fence_process(&adev->sdma.instance[instance].ring);
> > break;
> > case 1:
> > - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 0))
> > + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0))
> > amdgpu_fence_process(&adev->sdma.instance[instance].page);
> > break;
> > case 2:
> > /* XXX compute */
> > break;
> > case 3:
> > - if (adev->ip_versions[SDMA0_HWIP] != IP_VERSION(4, 2, 0))
> > + if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0))
> > amdgpu_fence_process(&adev->sdma.instance[instance].page);
> > break;
> > }
> > @@ -2359,7 +2359,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
> > {
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(4, 1, 0):
> > case IP_VERSION(4, 1, 1):
> > case IP_VERSION(4, 1, 2):
> > @@ -2547,7 +2547,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> > int i;
> >
> > for (i = 0; i < adev->sdma.num_instances; i++) {
> > - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
> > + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
> > adev->sdma.instance[i].ring.funcs =
> > &sdma_v4_0_ring_funcs_2nd_mmhub;
> > else
> > @@ -2555,7 +2555,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> > &sdma_v4_0_ring_funcs;
> > adev->sdma.instance[i].ring.me = i;
> > if (adev->sdma.has_page_queue) {
> > - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
> > + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
> > adev->sdma.instance[i].page.funcs =
> > &sdma_v4_0_page_ring_funcs_2nd_mmhub;
> > else
> > @@ -2782,7 +2782,7 @@ static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
> >
> > static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(4, 2, 0):
> > case IP_VERSION(4, 2, 2):
> > adev->sdma.funcs = &sdma_v4_0_ras_funcs;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > index d3b01d2977c0..853d1511b889 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > @@ -187,7 +187,7 @@ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
> >
> > static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(5, 0, 0):
> > soc15_program_register_sequence(adev,
> > golden_settings_sdma_5,
> > @@ -248,12 +248,12 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
> > const struct common_firmware_header *header = NULL;
> > const struct sdma_firmware_header_v1_0 *hdr;
> >
> > - if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 0, 5)))
> > + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
> > return 0;
> >
> > DRM_DEBUG("\n");
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(5, 0, 0):
> > chip_name = "navi10";
> > break;
> > @@ -1634,7 +1634,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(5, 0, 0):
> > case IP_VERSION(5, 0, 2):
> > case IP_VERSION(5, 0, 5):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > index 92f29beda3b2..0fec1d9dd638 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > @@ -136,7 +136,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
> >
> > DRM_DEBUG("\n");
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(5, 2, 0):
> > chip_name = "sienna_cichlid";
> > break;
> > @@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
> > (void *)&adev->sdma.instance[0],
> > sizeof(struct amdgpu_sdma_instance));
> >
> > - if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 0)))
> > + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
> > return 0;
> >
> > DRM_DEBUG("psp_load == '%s'\n",
> > @@ -1530,7 +1530,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
> >
> > for (i = 0; i < adev->sdma.num_instances; i++) {
> >
> > - if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> > + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
> > adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
> >
> > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
> > @@ -1567,7 +1567,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
> >
> > for (i = 0; i < adev->sdma.num_instances; i++) {
> >
> > - if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> > + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
> > adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
> >
> > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
> > @@ -1596,7 +1596,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[SDMA0_HWIP]) {
> > + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> > case IP_VERSION(5, 2, 0):
> > case IP_VERSION(5, 2, 2):
> > case IP_VERSION(5, 2, 1):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 7f4cd1a4f6cb..74310bb4216a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -156,8 +156,8 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
> > static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
> > const struct amdgpu_video_codecs **codecs)
> > {
> > - if (adev->ip_versions[VCE_HWIP]) {
> > - switch (adev->ip_versions[VCE_HWIP]) {
> > + if (adev->ip_versions[VCE_HWIP][0]) {
> > + switch (adev->ip_versions[VCE_HWIP][0]) {
> > case IP_VERSION(4, 0, 0):
> > case IP_VERSION(4, 1, 0):
> > if (encode)
> > @@ -169,7 +169,7 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
> > return -EINVAL;
> > }
> > } else {
> > - switch (adev->ip_versions[UVD_HWIP]) {
> > + switch (adev->ip_versions[UVD_HWIP][0]) {
> > case IP_VERSION(1, 0, 0):
> > case IP_VERSION(1, 0, 1):
> > if (encode)
> > @@ -341,11 +341,11 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
> > {
> > u32 reference_clock = adev->clock.spll.reference_freq;
> >
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
> > - adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
> > + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
> > return 10000;
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
> > - adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
> > + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
> > return reference_clock / 4;
> >
> > return reference_clock;
> > @@ -576,7 +576,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
> > dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
> > amdgpu_reset_method);
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(10, 0, 0):
> > case IP_VERSION(10, 0, 1):
> > case IP_VERSION(12, 0, 0):
> > @@ -641,7 +641,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
> >
> > static bool soc15_supports_baco(struct amdgpu_device *adev)
> > {
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(9, 0, 0):
> > case IP_VERSION(11, 0, 2):
> > if (adev->asic_type == CHIP_VEGA20) {
> > @@ -1172,7 +1172,7 @@ static int soc15_common_early_init(void *handle)
> > /* TODO: split the GC and PG flags based on the relevant IP version for which
> > * they are relevant.
> > */
> > - switch (adev->ip_versions[GC_HWIP]) {
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > case IP_VERSION(9, 0, 1):
> > adev->asic_funcs = &soc15_asic_funcs;
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > @@ -1583,7 +1583,7 @@ static int soc15_common_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[NBIO_HWIP]) {
> > + switch (adev->ip_versions[NBIO_HWIP][0]) {
> > case IP_VERSION(6, 1, 0):
> > case IP_VERSION(6, 2, 0):
> > case IP_VERSION(7, 4, 0):
> > @@ -1639,7 +1639,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
> >
> > adev->hdp.funcs->get_clock_gating_state(adev, flags);
> >
> > - if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
> > + if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
> >
> > /* AMD_CG_SUPPORT_DRM_MGCG */
> > data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > index e9758969fbe6..f4a7a30ecebd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > @@ -1720,7 +1720,7 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
> > for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> > if (adev->vcn.harvest_config & (1 << i))
> > continue;
> > - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
> > + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
> > adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
> > else /* CHIP_ALDEBARAN */
> > adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
> > @@ -1737,7 +1737,7 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
> > if (adev->vcn.harvest_config & (1 << j))
> > continue;
> > for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> > - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
> > + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
> > adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
> > else /* CHIP_ALDEBARAN */
> > adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> > index a81d834ea0d3..6940716db1df 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> > @@ -95,7 +95,7 @@ static int vcn_v3_0_early_init(void *handle)
> > adev->vcn.num_enc_rings = 1;
> >
> > } else {
> > - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
> > + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 0)) {
> > u32 harvest;
> >
> > for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> > @@ -110,7 +110,7 @@ static int vcn_v3_0_early_init(void *handle)
> > return -ENOENT;
> > }
> >
> > - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
> > + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33))
> > adev->vcn.num_enc_rings = 0;
> > else
> > adev->vcn.num_enc_rings = 2;
> > @@ -1270,7 +1270,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
> > fw_shared->rb.wptr = lower_32_bits(ring->wptr);
> > fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
> >
> > - if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
> > + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
> > fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
> > ring = &adev->vcn.inst[i].ring_enc[0];
> > WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
> > @@ -1642,7 +1642,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
> > UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
> > ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
> >
> > - if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
> > + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
> > /* Restore */
> > fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
> > fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index fc8a30251fa4..fb89ce4dd28c 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -1344,7 +1344,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> > init_data.flags.gpu_vm_support = true;
> > break;
> > default:
> > - switch (adev->ip_versions[DCE_HWIP]) {
> > + switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > init_data.flags.gpu_vm_support = true;
> > if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> > @@ -1658,7 +1658,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
> > return 0;
> > break;
> > default:
> > - switch (adev->ip_versions[DCE_HWIP]) {
> > + switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(2, 0, 2):
> > case IP_VERSION(2, 0, 0):
> > case IP_VERSION(2, 1, 0):
> > @@ -1750,7 +1750,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
> > enum dmub_status status;
> > int r;
> >
> > - switch (adev->ip_versions[DCE_HWIP]) {
> > + switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > dmub_asic = DMUB_ASIC_DCN21;
> > fw_name_dmub = FIRMWARE_RENOIR_DMUB;
> > @@ -1758,7 +1758,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
> > fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
> > break;
> > case IP_VERSION(3, 0, 0):
> > - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
> > + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
> > dmub_asic = DMUB_ASIC_DCN30;
> > fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
> > } else {
> > @@ -2078,7 +2078,7 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
> > * therefore, this function apply to navi10/12/14 but not Renoir
> > * *
> > */
> > - switch (adev->ip_versions[DCE_HWIP]) {
> > + switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(2, 0, 2):
> > case IP_VERSION(2, 0, 0):
> > break;
> > @@ -4086,7 +4086,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> >
> > #if defined(CONFIG_DRM_AMD_DC_DCN)
> > /* Use Outbox interrupt */
> > - switch (adev->ip_versions[DCE_HWIP]) {
> > + switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(3, 0, 0):
> > case IP_VERSION(3, 1, 2):
> > case IP_VERSION(3, 1, 3):
> > @@ -4098,7 +4098,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> > break;
> > default:
> > DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
> > - adev->ip_versions[DCE_HWIP]);
> > + adev->ip_versions[DCE_HWIP][0]);
> > }
> > #endif
> >
> > @@ -4186,7 +4186,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> > break;
> > default:
> > #if defined(CONFIG_DRM_AMD_DC_DCN)
> > - switch (adev->ip_versions[DCE_HWIP]) {
> > + switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(1, 0, 0):
> > case IP_VERSION(1, 0, 1):
> > case IP_VERSION(2, 0, 2):
> > @@ -4205,7 +4205,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> > break;
> > default:
> > DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
> > - adev->ip_versions[DCE_HWIP]);
> > + adev->ip_versions[DCE_HWIP][0]);
> > goto fail;
> > }
> > #endif
> > @@ -4357,7 +4357,7 @@ static int dm_early_init(void *handle)
> > break;
> > default:
> > #if defined(CONFIG_DRM_AMD_DC_DCN)
> > - switch (adev->ip_versions[DCE_HWIP]) {
> > + switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(2, 0, 2):
> > case IP_VERSION(3, 0, 0):
> > adev->mode_info.num_crtc = 6;
> > @@ -4387,7 +4387,7 @@ static int dm_early_init(void *handle)
> > break;
> > default:
> > DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
> > - adev->ip_versions[DCE_HWIP]);
> > + adev->ip_versions[DCE_HWIP][0]);
> > return -EINVAL;
> > }
> > #endif
> > @@ -4609,7 +4609,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
> > tiling_info->gfx9.num_rb_per_se =
> > adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
> > tiling_info->gfx9.shaderEnable = 1;
> > - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> > + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> > tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
> > }
> >
> > @@ -5050,7 +5050,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
> > case AMDGPU_FAMILY_NV:
> > case AMDGPU_FAMILY_VGH:
> > case AMDGPU_FAMILY_YC:
> > - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> > + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> > add_gfx10_3_modifiers(adev, mods, &size, &capacity);
> > else
> > add_gfx10_1_modifiers(adev, mods, &size, &capacity);
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index 150cac4ea75c..9c601997a96a 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -455,7 +455,7 @@ static int smu_get_power_num_states(void *handle,
> >
> > bool is_support_sw_smu(struct amdgpu_device *adev)
> > {
> > - if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
> > + if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
> > return true;
> >
> > return false;
> > @@ -575,7 +575,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> > if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
> > smu->od_enabled = true;
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 0, 0):
> > case IP_VERSION(11, 0, 5):
> > case IP_VERSION(11, 0, 9):
> > @@ -694,7 +694,7 @@ static int smu_late_init(void *handle)
> > return ret;
> > }
> >
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1))
> > return 0;
> >
> > if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
> > @@ -1140,10 +1140,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
> > if (adev->in_suspend && smu_is_dpm_running(smu)) {
> > dev_info(adev->dev, "dpm has been enabled\n");
> > /* this is needed specifically */
> > - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)))
> > + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)))
> > ret = smu_system_features_control(smu, true);
> > return ret;
> > }
> > @@ -1286,7 +1286,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
> > int ret = 0;
> >
> > if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> > - if (adev->ip_versions[MP1_HWIP] < IP_VERSION(11, 0, 0)) {
> > + if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
> > if (smu->ppt_funcs->load_microcode) {
> > ret = smu->ppt_funcs->load_microcode(smu);
> > if (ret)
> > @@ -1405,14 +1405,14 @@ static int smu_disable_dpms(struct smu_context *smu)
> > * properly.
> > */
> > if (smu->uploading_custom_pp_table &&
> > - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))))
> > + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))))
> > return smu_disable_all_features_with_exception(smu,
> > true,
> > SMU_FEATURE_COUNT);
> > @@ -1421,10 +1421,10 @@ static int smu_disable_dpms(struct smu_context *smu)
> > * For Sienna_Cichlid, PMFW will handle the features disablement properly
> > * on BACO in. Driver involvement is unnecessary.
> > */
> > - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))) &&
> > + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))) &&
> > use_baco)
> > return smu_disable_all_features_with_exception(smu,
> > true,
> > @@ -1446,7 +1446,7 @@ static int smu_disable_dpms(struct smu_context *smu)
> > dev_err(adev->dev, "Failed to disable smu features.\n");
> > }
> >
> > - if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0) &&
> > + if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0) &&
> > adev->gfx.rlc.funcs->stop)
> > adev->gfx.rlc.funcs->stop(adev);
> >
> > @@ -2283,11 +2283,11 @@ int smu_get_power_limit(void *handle,
> > } else {
> > switch (limit_level) {
> > case SMU_PPT_LIMIT_CURRENT:
> > - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 2)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
> > + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)))
> > ret = smu_get_asic_power_limits(smu,
> > &smu->current_power_limit,
> > NULL,
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > index d96f904a765b..71161f6b78fe 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > @@ -345,7 +345,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> >
> > /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> > if (!(is_asic_secure(smu) &&
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
> > (adev->rev_id == 0)) &&
> > (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> > *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> > @@ -354,7 +354,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> >
> > /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> > if (is_asic_secure(smu) &&
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
> > (adev->rev_id == 0))
> > *(uint64_t *)feature_mask &=
> > ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
> > @@ -925,7 +925,7 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
> > return ret;
> > }
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 0, 9):
> > if (smu_version > 0x00341C00)
> > ret = navi12_get_smu_metrics_data(smu, member, value);
> > @@ -935,8 +935,8 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
> > case IP_VERSION(11, 0, 0):
> > case IP_VERSION(11, 0, 5):
> > default:
> > - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> > - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> > + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> > + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> > ret = navi10_get_smu_metrics_data(smu, member, value);
> > else
> > ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
> > @@ -1509,7 +1509,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
> > uint32_t sclk_freq;
> >
> > pstate_table->gfxclk_pstate.min = gfx_table->min;
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 0, 0):
> > switch (adev->pdev->revision) {
> > case 0xf0: /* XTX */
> > @@ -2562,8 +2562,8 @@ static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
> > if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
> > return false;
> >
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0) ||
> > - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5))
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) ||
> > + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5))
> > return true;
> >
> > return false;
> > @@ -2671,8 +2671,8 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
> > * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
> > * - PPSMC_MSG_GetUMCFWWA
> > */
> > - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
> > - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
> > + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
> > + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
> > ret = smu_cmn_send_smc_msg_with_param(smu,
> > SMU_MSG_GET_UMC_FW_WA,
> > 0,
> > @@ -2691,13 +2691,13 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
> > return 0;
> >
> > if (umc_fw_disable_cdr) {
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
> > return navi10_umc_hybrid_cdr_workaround(smu);
> > } else {
> > return navi10_set_dummy_pstates_table_location(smu);
> > }
> > } else {
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
> > return navi10_umc_hybrid_cdr_workaround(smu);
> > }
> >
> > @@ -3151,7 +3151,7 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
> > return ret;
> > }
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 0, 9):
> > if (smu_version > 0x00341C00)
> > ret = navi12_get_gpu_metrics(smu, table);
> > @@ -3161,8 +3161,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
> > case IP_VERSION(11, 0, 0):
> > case IP_VERSION(11, 0, 5):
> > default:
> > - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> > - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> > + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> > + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> > ret = navi10_get_gpu_metrics(smu, table);
> > else
> > ret =navi10_get_legacy_gpu_metrics(smu, table);
> > @@ -3180,7 +3180,7 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> > uint32_t param = 0;
> >
> > /* Navi12 does not support this */
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))
> > return 0;
> >
> > /*
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 6a0fed5e33d9..15e66e1912de 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -74,7 +74,7 @@
> > #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
> >
> > #define GET_PPTABLE_MEMBER(field, member) do {\
> > - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))\
> > + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
> > (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
> > else\
> > (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
> > @@ -82,7 +82,7 @@
> >
> > static int get_table_size(struct smu_context *smu)
> > {
> > - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
> > + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
> > return sizeof(PPTable_beige_goby_t);
> > else
> > return sizeof(PPTable_t);
> > @@ -298,7 +298,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
> > }
> >
> > if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
> > - (adev->ip_versions[MP1_HWIP] > IP_VERSION(11, 0, 7)) &&
> > + (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
> > !(adev->flags & AMD_IS_APU))
> > *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> >
> > @@ -496,7 +496,7 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s
> > uint32_t throttler_status = 0;
> > int i;
> >
> > - if ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> > + if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> > (smu->smc_fw_version >= 0x3A4300)) {
> > for (i = 0; i < THROTTLER_COUNT; i++)
> > throttler_status |=
> > @@ -517,7 +517,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
> > &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
> > SmuMetrics_V2_t *metrics_v2 =
> > &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
> > - bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> > + bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> > (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> > uint16_t average_gfx_activity;
> > int ret = 0;
> > @@ -1170,7 +1170,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
> > * and onwards SMU firmwares.
> > */
> > smu_cmn_get_smc_version(smu, NULL, &smu_version);
> > - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> > + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> > (smu_version < 0x003a2900))
> > break;
> >
> > @@ -1937,7 +1937,7 @@ static void sienna_cichlid_dump_od_table(struct smu_context *smu,
> > od_table->UclkFmax);
> >
> > smu_cmn_get_smc_version(smu, NULL, &smu_version);
> > - if (!((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> > + if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> > (smu_version < 0x003a2900)))
> > dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
> > }
> > @@ -2161,7 +2161,7 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
> > * and onwards SMU firmwares.
> > */
> > smu_cmn_get_smc_version(smu, NULL, &smu_version);
> > - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> > + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> > (smu_version < 0x003a2900)) {
> > dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
> > "only by 58.41.0 and onwards SMU firmwares!\n");
> > @@ -2865,7 +2865,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
> > PPTable_t *pptable = table_context->driver_pptable;
> > int i;
> >
> > - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)) {
> > + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
> > beige_goby_dump_pptable(smu);
> > return;
> > }
> > @@ -3625,7 +3625,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
> > SmuMetrics_V2_t *metrics_v2 =
> > &(metrics_external.SmuMetrics_V2);
> > struct amdgpu_device *adev = smu->adev;
> > - bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> > + bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> > (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> > uint16_t average_gfx_activity;
> > int ret = 0;
> > @@ -3706,8 +3706,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
> >
> > gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
> >
> > - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
> > - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
> > + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
> > + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
> > gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
> > gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
> > } else {
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > index 1ae8b8dc3bd3..3470c33ee09d 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > @@ -90,11 +90,11 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
> > struct amdgpu_firmware_info *ucode = NULL;
> >
> > if (amdgpu_sriov_vf(adev) &&
> > - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
> > - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7))))
> > + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
> > + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7))))
> > return 0;
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 0, 0):
> > chip_name = "navi10";
> > break;
> > @@ -121,7 +121,7 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
> > break;
> > default:
> > dev_err(adev->dev, "Unsupported IP version 0x%x\n",
> > - adev->ip_versions[MP1_HWIP]);
> > + adev->ip_versions[MP1_HWIP][0]);
> > return -EINVAL;
> > }
> >
> > @@ -239,7 +239,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
> > if (smu->is_apu)
> > adev->pm.fw_version = smu_version;
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 0, 0):
> > smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
> > break;
> > @@ -272,7 +272,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
> > break;
> > default:
> > dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
> > - adev->ip_versions[MP1_HWIP]);
> > + adev->ip_versions[MP1_HWIP][0]);
> > smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
> > break;
> > }
> > @@ -496,7 +496,7 @@ int smu_v11_0_init_power(struct smu_context *smu)
> > {
> > struct amdgpu_device *adev = smu->adev;
> > struct smu_power_context *smu_power = &smu->smu_power;
> > - size_t size = adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ?
> > + size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ?
> > sizeof(struct smu_11_5_power_context) :
> > sizeof(struct smu_11_0_power_context);
> >
> > @@ -753,9 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
> > /* Navy_Flounder/Dimgrey_Cavefish do not support to change
> > * display num currently
> > */
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11) ||
> > - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ||
> > - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) ||
> > + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ||
> > + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
> > return 0;
> >
> > return smu_cmn_send_smc_msg_with_param(smu,
> > @@ -1140,7 +1140,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
> > int ret = 0;
> > struct amdgpu_device *adev = smu->adev;
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 0, 0):
> > case IP_VERSION(11, 0, 5):
> > case IP_VERSION(11, 0, 9):
> > @@ -1634,7 +1634,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
> > mutex_lock(&smu_baco->mutex);
> >
> > if (state == SMU_BACO_STATE_ENTER) {
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(11, 0, 7):
> > case IP_VERSION(11, 0, 11):
> > case IP_VERSION(11, 0, 12):
> > @@ -1653,7 +1653,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
> > default:
> > if (!ras || !adev->ras_enabled ||
> > adev->gmc.xgmi.pending_reset) {
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
> > data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
> > data |= 0x80000000;
> > WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
> > @@ -1935,7 +1935,7 @@ int smu_v11_0_set_performance_level(struct smu_context *smu,
> > * Separate MCLK and SOCCLK soft min/max settings are not allowed
> > * on Arcturus.
> > */
> > - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
> > + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
> > mclk_min = mclk_max = 0;
> > socclk_min = socclk_max = 0;
> > }
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> > index 08f3cc809fc6..05c5e61f3506 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> > @@ -89,13 +89,13 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(13, 0, 2):
> > chip_name = "aldebaran";
> > break;
> > default:
> > dev_err(adev->dev, "Unsupported IP version 0x%x\n",
> > - adev->ip_versions[MP1_HWIP]);
> > + adev->ip_versions[MP1_HWIP][0]);
> > return -EINVAL;
> > }
> >
> > @@ -211,7 +211,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
> > smu_minor = (smu_version >> 8) & 0xff;
> > smu_debug = (smu_version >> 0) & 0xff;
> >
> > - switch (smu->adev->ip_versions[MP1_HWIP]) {
> > + switch (smu->adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(13, 0, 2):
> > smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
> > break;
> > @@ -221,7 +221,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
> > break;
> > default:
> > dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
> > - smu->adev->ip_versions[MP1_HWIP]);
> > + smu->adev->ip_versions[MP1_HWIP][0]);
> > smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
> > break;
> > }
> > @@ -743,7 +743,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
> > int ret = 0;
> > struct amdgpu_device *adev = smu->adev;
> >
> > - switch (adev->ip_versions[MP1_HWIP]) {
> > + switch (adev->ip_versions[MP1_HWIP][0]) {
> > case IP_VERSION(13, 0, 1):
> > case IP_VERSION(13, 0, 3):
> > if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
> >
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 61/66] drm/amdgpu: convert IP version array to include instances
2021-09-22 16:17 ` Alex Deucher
@ 2021-09-23 4:58 ` Lazar, Lijo
2021-09-23 21:42 ` Alex Deucher
0 siblings, 1 reply; 106+ messages in thread
From: Lazar, Lijo @ 2021-09-23 4:58 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, amd-gfx list
On 9/22/2021 9:47 PM, Alex Deucher wrote:
> On Wed, Sep 22, 2021 at 5:08 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>
>>
>>
>> On 9/21/2021 11:37 PM, Alex Deucher wrote:
>>> Allow us to query instances versions more cleanly.
>>>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 262 +++++++++---------
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 +--
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 2 +-
>>> drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 2 +-
>>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 80 +++---
>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 72 ++---
>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 16 +-
>>> drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 14 +-
>>> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 14 +-
>>> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +-
>>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/nv.c | 8 +-
>>> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 34 +--
>>> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +-
>>> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +-
>>> drivers/gpu/drm/amd/amdgpu/soc15.c | 24 +-
>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 +-
>>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +-
>>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 52 ++--
>>> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 32 +--
>>> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
>>> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 28 +-
>>> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 +-
>>> 29 files changed, 394 insertions(+), 394 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index b153c3740307..f4bceb2624fb 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -1096,7 +1096,7 @@ struct amdgpu_device {
>>> struct pci_saved_state *pci_state;
>>>
>>> struct amdgpu_reset_control *reset_cntl;
>>> - uint32_t ip_versions[HW_ID_MAX];
>>> + uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
>>
>> Here is the confusion. "ip_versions" is used like this -
>> adev->ip_versions[MMHUB_HWIP] - which means the first dimension can max
>> out at MAX_HWIP. So why is the array maxed to HW_ID_MAX? HWID looks
>> like a completely different thing.
>>
>> Got this confusion while reviewing patch 52. Besides, this change
>> doesn't go well with that patch because HWIP is really replicating
>> instances.
>
> It's not consistent unfortunately. SDMA is a good example. Sienna
> cichlid has 8 total SDMA instances, each enumerated separately (HWIDs
> 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are
> enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x
> HWID 43). UMC is another example. On most chips there are multiple
> instances with the same HWID.
>
To clarify about HW_ID_MAX and HWIP/MAX_HWIP - In total there are around
300 HWIDs, however driver uses a select few using HWIP. So the max
number of possible HWIPs in driver are MAX_HWIP. Question was about
array size.
uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE]
or
uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]
On different HWIDs for SDMA or other IP - will the the below check be
good enough (assume all HWIDs carry the same IP version) or is there a
need for loop?
switch (adev->ip_versions[SDMA0_HWIP][0])
Thanks,
Lijo
> Alex
>
>>
>> Thanks,
>> Lijo
>>
>>> };
>>>
>>> static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>>> index 9d8aea39f36a..eff348dee9e9 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
>>> @@ -369,7 +369,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
>>> hw_id_names[le16_to_cpu(ip->hw_id)]);
>>> adev->reg_offset[hw_ip][ip->number_instance] =
>>> ip->base_address;
>>> - adev->ip_versions[hw_ip + ip->number_instance] =
>>> + adev->ip_versions[hw_ip][ip->number_instance] =
>>> amdgpu_discovery_convert_version(ip->major,
>>> ip->minor,
>>> ip->revision);
>>> @@ -525,139 +525,139 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> case CHIP_VEGA10:
>>> vega10_reg_base_init(adev);
>>> adev->sdma.num_instances = 2;
>>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
>>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
>>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
>>> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
>>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
>>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
>>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
>>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
>>> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
>>> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
>>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
>>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
>>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
>>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
>>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
>>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
>>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
>>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
>>> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
>>> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
>>> break;
>>> case CHIP_VEGA12:
>>> vega10_reg_base_init(adev);
>>> adev->sdma.num_instances = 2;
>>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
>>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
>>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
>>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
>>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
>>> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
>>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
>>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
>>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
>>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
>>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
>>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
>>> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
>>> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
>>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
>>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
>>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
>>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
>>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
>>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
>>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
>>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
>>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
>>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
>>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
>>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
>>> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
>>> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
>>> break;
>>> case CHIP_RAVEN:
>>> vega10_reg_base_init(adev);
>>> adev->sdma.num_instances = 1;
>>> adev->vcn.num_vcn_inst = 1;
>>> if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
>>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
>>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
>>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
>>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
>>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
>>> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
>>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
>>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
>>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
>>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
>>> - adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
>>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
>>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
>>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
>>> - adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
>>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
>>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
>>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
>>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
>>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
>>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
>>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
>>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
>>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
>>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
>>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
>>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
>>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
>>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
>>> + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
>>> } else {
>>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
>>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
>>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
>>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
>>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
>>> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
>>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
>>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
>>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
>>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
>>> - adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
>>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
>>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
>>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
>>> - adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
>>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
>>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
>>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
>>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
>>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
>>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
>>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
>>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
>>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
>>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
>>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
>>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
>>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
>>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
>>> + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
>>> }
>>> break;
>>> case CHIP_VEGA20:
>>> vega20_reg_base_init(adev);
>>> adev->sdma.num_instances = 2;
>>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
>>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
>>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
>>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
>>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
>>> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
>>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
>>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
>>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
>>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
>>> - adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
>>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
>>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
>>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
>>> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
>>> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
>>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
>>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
>>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
>>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
>>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
>>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
>>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
>>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
>>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
>>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
>>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
>>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
>>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
>>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
>>> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
>>> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
>>> break;
>>> case CHIP_ARCTURUS:
>>> arct_reg_base_init(adev);
>>> adev->sdma.num_instances = 8;
>>> adev->vcn.num_vcn_inst = 2;
>>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
>>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
>>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
>>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
>>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
>>> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
>>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
>>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
>>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
>>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
>>> - adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
>>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
>>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
>>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
>>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
>>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
>>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
>>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
>>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
>>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
>>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
>>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
>>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
>>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
>>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
>>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
>>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
>>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
>>> break;
>>> case CHIP_ALDEBARAN:
>>> aldebaran_reg_base_init(adev);
>>> adev->sdma.num_instances = 5;
>>> adev->vcn.num_vcn_inst = 2;
>>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
>>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
>>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
>>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
>>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
>>> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
>>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
>>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
>>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
>>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
>>> - adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
>>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
>>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
>>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
>>> - adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
>>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
>>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
>>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
>>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
>>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
>>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
>>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
>>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
>>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
>>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
>>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
>>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
>>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
>>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
>>> + adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
>>> break;
>>> default:
>>> r = amdgpu_discovery_reg_base_init(adev);
>>> @@ -673,7 +673,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> break;
>>> }
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 2, 1):
>>> case IP_VERSION(9, 4, 0):
>>> @@ -706,11 +706,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> return -EINVAL;
>>> }
>>>
>>> - if (adev->ip_versions[XGMI_HWIP] == IP_VERSION(4, 8, 0))
>>> + if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
>>> adev->gmc.xgmi.supported = true;
>>>
>>> /* set NBIO version */
>>> - switch (adev->ip_versions[NBIO_HWIP]) {
>>> + switch (adev->ip_versions[NBIO_HWIP][0]) {
>>> case IP_VERSION(6, 1, 0):
>>> case IP_VERSION(6, 2, 0):
>>> adev->nbio.funcs = &nbio_v6_1_funcs;
>>> @@ -749,7 +749,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> break;
>>> }
>>>
>>> - switch (adev->ip_versions[HDP_HWIP]) {
>>> + switch (adev->ip_versions[HDP_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> case IP_VERSION(4, 0, 1):
>>> case IP_VERSION(4, 1, 0):
>>> @@ -771,7 +771,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> break;
>>> }
>>>
>>> - switch (adev->ip_versions[DF_HWIP]) {
>>> + switch (adev->ip_versions[DF_HWIP][0]) {
>>> case IP_VERSION(3, 6, 0):
>>> case IP_VERSION(3, 6, 1):
>>> case IP_VERSION(3, 6, 2):
>>> @@ -788,7 +788,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> break;
>>> }
>>>
>>> - switch (adev->ip_versions[SMUIO_HWIP]) {
>>> + switch (adev->ip_versions[SMUIO_HWIP][0]) {
>>> case IP_VERSION(9, 0, 0):
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(10, 0, 0):
>>> @@ -819,7 +819,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> }
>>>
>>> /* what IP to use for this? */
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 1, 0):
>>> case IP_VERSION(9, 2, 1):
>>> @@ -847,7 +847,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> }
>>>
>>> /* use GC or MMHUB IP version */
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 1, 0):
>>> case IP_VERSION(9, 2, 1):
>>> @@ -874,7 +874,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> return -EINVAL;
>>> }
>>>
>>> - switch (adev->ip_versions[OSSSYS_HWIP]) {
>>> + switch (adev->ip_versions[OSSSYS_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> case IP_VERSION(4, 0, 1):
>>> case IP_VERSION(4, 1, 0):
>>> @@ -900,7 +900,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> }
>>>
>>> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
>>> - switch (adev->ip_versions[MP0_HWIP]) {
>>> + switch (adev->ip_versions[MP0_HWIP][0]) {
>>> case IP_VERSION(9, 0, 0):
>>> amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
>>> break;
>>> @@ -938,7 +938,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> }
>>>
>>> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(9, 0, 0):
>>> case IP_VERSION(10, 0, 0):
>>> case IP_VERSION(10, 0, 1):
>>> @@ -975,8 +975,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
>>> amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
>>> #if defined(CONFIG_DRM_AMD_DC)
>>> - } else if (adev->ip_versions[DCE_HWIP]) {
>>> - switch (adev->ip_versions[DCE_HWIP]) {
>>> + } else if (adev->ip_versions[DCE_HWIP][0]) {
>>> + switch (adev->ip_versions[DCE_HWIP][0]) {
>>> case IP_VERSION(1, 0, 0):
>>> case IP_VERSION(1, 0, 1):
>>> case IP_VERSION(2, 0, 2):
>>> @@ -995,8 +995,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> default:
>>> return -EINVAL;
>>> }
>>> - } else if (adev->ip_versions[DCI_HWIP]) {
>>> - switch (adev->ip_versions[DCI_HWIP]) {
>>> + } else if (adev->ip_versions[DCI_HWIP][0]) {
>>> + switch (adev->ip_versions[DCI_HWIP][0]) {
>>> case IP_VERSION(12, 0, 0):
>>> case IP_VERSION(12, 0, 1):
>>> case IP_VERSION(12, 1, 0):
>>> @@ -1007,7 +1007,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> }
>>> }
>>> #endif
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 1, 0):
>>> case IP_VERSION(9, 2, 1):
>>> @@ -1034,7 +1034,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> return -EINVAL;
>>> }
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> case IP_VERSION(4, 0, 1):
>>> case IP_VERSION(4, 1, 0):
>>> @@ -1064,7 +1064,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> }
>>>
>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(9, 0, 0):
>>> case IP_VERSION(10, 0, 0):
>>> case IP_VERSION(10, 0, 1):
>>> @@ -1098,8 +1098,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> }
>>> }
>>>
>>> - if (adev->ip_versions[VCE_HWIP]) {
>>> - switch (adev->ip_versions[UVD_HWIP]) {
>>> + if (adev->ip_versions[VCE_HWIP][0]) {
>>> + switch (adev->ip_versions[UVD_HWIP][0]) {
>>> case IP_VERSION(7, 0, 0):
>>> case IP_VERSION(7, 2, 0):
>>> amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
>>> @@ -1107,7 +1107,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> default:
>>> return -EINVAL;
>>> }
>>> - switch (adev->ip_versions[VCE_HWIP]) {
>>> + switch (adev->ip_versions[VCE_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> case IP_VERSION(4, 1, 0):
>>> amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
>>> @@ -1116,7 +1116,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> return -EINVAL;
>>> }
>>> } else {
>>> - switch (adev->ip_versions[UVD_HWIP]) {
>>> + switch (adev->ip_versions[UVD_HWIP][0]) {
>>> case IP_VERSION(1, 0, 0):
>>> case IP_VERSION(1, 0, 1):
>>> amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
>>> @@ -1153,7 +1153,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>>> }
>>>
>>> if (adev->enable_mes) {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 1):
>>> case IP_VERSION(10, 1, 2):
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> index c47d29689be4..7d414f1606b9 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> @@ -76,7 +76,7 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp
>>> return;
>>> }
>>>
>>> - switch (adev->ip_versions[MP0_HWIP]) {
>>> + switch (adev->ip_versions[MP0_HWIP][0]) {
>>> case IP_VERSION(11, 0, 4):
>>> case IP_VERSION(11, 0, 7):
>>> case IP_VERSION(11, 0, 9):
>>> @@ -97,7 +97,7 @@ static int psp_early_init(void *handle)
>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>> struct psp_context *psp = &adev->psp;
>>>
>>> - switch (adev->ip_versions[MP0_HWIP]) {
>>> + switch (adev->ip_versions[MP0_HWIP][0]) {
>>> case IP_VERSION(9, 0, 0):
>>> psp_v3_1_set_psp_funcs(psp);
>>> psp->autoload_supported = false;
>>> @@ -279,7 +279,7 @@ static int psp_sw_init(void *handle)
>>> return ret;
>>> }
>>> } else if (amdgpu_sriov_vf(adev) &&
>>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2)) {
>>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) {
>>> ret = psp_init_ta_microcode(psp, "aldebaran");
>>> if (ret) {
>>> DRM_ERROR("Failed to initialize ta microcode!\n");
>>> @@ -322,8 +322,8 @@ static int psp_sw_init(void *handle)
>>> }
>>> }
>>>
>>> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
>>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7)) {
>>> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
>>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
>>> ret= psp_sysfs_init(adev);
>>> if (ret) {
>>> return ret;
>>> @@ -353,8 +353,8 @@ static int psp_sw_fini(void *handle)
>>> psp->ta_fw = NULL;
>>> }
>>>
>>> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
>>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7))
>>> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
>>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
>>> psp_sysfs_fini(adev);
>>>
>>> kfree(cmd);
>>> @@ -613,7 +613,7 @@ static int psp_tmr_init(struct psp_context *psp)
>>>
>>> static bool psp_skip_tmr(struct psp_context *psp)
>>> {
>>> - switch (psp->adev->ip_versions[MP0_HWIP]) {
>>> + switch (psp->adev->ip_versions[MP0_HWIP][0]) {
>>> case IP_VERSION(11, 0, 9):
>>> case IP_VERSION(11, 0, 7):
>>> case IP_VERSION(13, 0, 2):
>>> @@ -1010,8 +1010,8 @@ int psp_xgmi_terminate(struct psp_context *psp)
>>> struct amdgpu_device *adev = psp->adev;
>>>
>>> /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
>>> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
>>> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
>>> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
>>> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
>>> adev->gmc.xgmi.connected_to_cpu))
>>> return 0;
>>>
>>> @@ -1113,7 +1113,7 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
>>>
>>> static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
>>> {
>>> - return psp->adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
>>> + return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
>>> psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;
>>> }
>>>
>>> @@ -2232,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp)
>>>
>>> if ((amdgpu_in_reset(adev) &&
>>> ras && adev->ras_enabled &&
>>> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
>>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 2)))) {
>>> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
>>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
>>> ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
>>> if (ret) {
>>> DRM_WARN("Failed to set MP1 state prepare for reload\n");
>>> @@ -2330,9 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
>>> continue;
>>>
>>> if (psp->autoload_supported &&
>>> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7) ||
>>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 11) ||
>>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 12)) &&
>>> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
>>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
>>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
>>> (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
>>> ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
>>> ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
>>> @@ -2920,7 +2920,7 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
>>> le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
>>>
>>> if (adev->gmc.xgmi.connected_to_cpu ||
>>> - (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2))) {
>>> + (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
>>> adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
>>> adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> index 9724f5f5f702..4d3f2386ef53 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> @@ -86,7 +86,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
>>> for (i = 0; i < adev->vcn.num_vcn_inst; i++)
>>> atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
>>>
>>> - switch (adev->ip_versions[UVD_HWIP]) {
>>> + switch (adev->ip_versions[UVD_HWIP][0]) {
>>> case IP_VERSION(1, 0, 0):
>>> case IP_VERSION(1, 0, 1):
>>> if (adev->apu_flags & AMD_APU_IS_RAVEN2)
>>> @@ -134,7 +134,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
>>> adev->vcn.indirect_sram = true;
>>> break;
>>> case IP_VERSION(3, 0, 0):
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
>>> fw_name = FIRMWARE_SIENNA_CICHLID;
>>> else
>>> fw_name = FIRMWARE_NAVY_FLOUNDER;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
>>> index d3f634eb40fb..ab6a07e5e8c4 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
>>> @@ -77,7 +77,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[ATHUB_HWIP]) {
>>> + switch (adev->ip_versions[ATHUB_HWIP][0]) {
>>> case IP_VERSION(2, 0, 0):
>>> case IP_VERSION(2, 0, 2):
>>> athub_v2_0_update_medium_grain_clock_gating(adev,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
>>> index 0fbeaf05204e..2edefd10e56c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
>>> @@ -70,7 +70,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[ATHUB_HWIP]) {
>>> + switch (adev->ip_versions[ATHUB_HWIP][0]) {
>>> case IP_VERSION(2, 1, 0):
>>> case IP_VERSION(2, 1, 1):
>>> case IP_VERSION(2, 1, 2):
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> index 4c632306ed70..71bb3c0dc1da 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> @@ -1537,7 +1537,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
>>> scratch_reg3 = adev->rmmio +
>>> (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
>>>
>>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
>>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
>>> spare_int = adev->rmmio +
>>> (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
>>> + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
>>> @@ -3727,7 +3727,7 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
>>>
>>> static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> soc15_program_register_sequence(adev,
>>> golden_settings_gc_rlc_spm_10_0_nv10,
>>> @@ -3750,7 +3750,7 @@ static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
>>>
>>> static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> soc15_program_register_sequence(adev,
>>> golden_settings_gc_10_1,
>>> @@ -3985,7 +3985,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
>>> {
>>> adev->gfx.cp_fw_write_wait = false;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 2):
>>> case IP_VERSION(10, 1, 1):
>>> @@ -4066,7 +4066,7 @@ static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
>>>
>>> static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
>>> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>>> @@ -4093,7 +4093,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
>>>
>>> DRM_DEBUG("\n");
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> chip_name = "navi10";
>>> break;
>>> @@ -4684,7 +4684,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
>>>
>>> adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 1):
>>> case IP_VERSION(10, 1, 2):
>>> @@ -4818,7 +4818,7 @@ static int gfx_v10_0_sw_init(void *handle)
>>> struct amdgpu_kiq *kiq;
>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 1):
>>> case IP_VERSION(10, 1, 2):
>>> @@ -5068,8 +5068,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
>>> for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
>>> for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
>>> bitmap = i * adev->gfx.config.max_sh_per_se + j;
>>> - if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
>>> - (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
>>> + if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
>>> + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
>>> ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
>>> continue;
>>> gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
>>> @@ -5096,7 +5096,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
>>>
>>> /* for ASICs that integrates GFX v10.3
>>> * pa_sc_tile_steering_override should be set to 0 */
>>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
>>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
>>> return 0;
>>>
>>> /* init num_sc */
>>> @@ -5249,7 +5249,7 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
>>> /* TCCs are global (not instanced). */
>>> uint32_t tcc_disable;
>>>
>>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
>>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
>>> tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
>>> RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
>>> } else {
>>> @@ -5326,7 +5326,7 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
>>> adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
>>>
>>> /* csib */
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
>>> WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
>>> adev->gfx.rlc.clear_state_gpu_addr >> 32);
>>> WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
>>> @@ -5948,7 +5948,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
>>> tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
>>> tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
>>>
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
>>> WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
>>> } else {
>>> WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
>>> @@ -6337,7 +6337,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
>>> }
>>> WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
>>> }
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -6474,7 +6474,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
>>> static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
>>> {
>>> if (enable) {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -6488,7 +6488,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
>>> break;
>>> }
>>> } else {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -6586,7 +6586,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
>>> struct amdgpu_device *adev = ring->adev;
>>>
>>> /* tell RLC which is KIQ queue */
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -7303,7 +7303,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
>>>
>>> /* check if mmVGT_ESGS_RING_SIZE_UMD
>>> * has been remapped to mmVGT_ESGS_RING_SIZE */
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 4):
>>> @@ -7350,7 +7350,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
>>> * index will auto-inc after each data writting */
>>> WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -7520,19 +7520,19 @@ static int gfx_v10_0_hw_init(void *handle)
>>> * init golden registers and rlc resume may override some registers,
>>> * reconfig them here
>>> */
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 10) ||
>>> - adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 1) ||
>>> - adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2))
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
>>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
>>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
>>> gfx_v10_0_tcp_harvest(adev);
>>>
>>> r = gfx_v10_0_cp_resume(adev);
>>> if (r)
>>> return r;
>>>
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
>>> gfx_v10_3_program_pbb_mode(adev);
>>>
>>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
>>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
>>> gfx_v10_3_set_power_brake_sequence(adev);
>>>
>>> return r;
>>> @@ -7584,7 +7584,7 @@ static int gfx_v10_0_hw_fini(void *handle)
>>> if (amdgpu_sriov_vf(adev)) {
>>> gfx_v10_0_cp_gfx_enable(adev, false);
>>> /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
>>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
>>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
>>> tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
>>> tmp &= 0xffffff00;
>>> WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
>>> @@ -7670,7 +7670,7 @@ static int gfx_v10_0_soft_reset(void *handle)
>>>
>>> /* GRBM_STATUS2 */
>>> tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -7726,7 +7726,7 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>>> {
>>> uint64_t clock, clock_lo, clock_hi, hi_check;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 1):
>>> case IP_VERSION(10, 3, 3):
>>> clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
>>> @@ -7784,7 +7784,7 @@ static int gfx_v10_0_early_init(void *handle)
>>> {
>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 1):
>>> case IP_VERSION(10, 1, 2):
>>> @@ -7848,7 +7848,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
>>> data = RLC_SAFE_MODE__CMD_MASK;
>>> data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -7884,7 +7884,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
>>> uint32_t data;
>>>
>>> data = RLC_SAFE_MODE__CMD_MASK;
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -8193,7 +8193,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d
>>> mmCGTS_SA1_QUAD1_SM_CTRL_REG
>>> };
>>>
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
>>> for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
>>> reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
>>> tcp_ctrl_regs_nv12[i];
>>> @@ -8238,8 +8238,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
>>> /* === CGCG + CGLS === */
>>> gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
>>>
>>> - if ((adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 1, 10)) &&
>>> - (adev->ip_versions[GC_HWIP] <= IP_VERSION(10, 1, 2)))
>>> + if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 1, 10)) &&
>>> + (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(10, 1, 2)))
>>> gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
>>> } else {
>>> /* CGCG/CGLS should be disabled before MGCG/MGLS
>>> @@ -8335,7 +8335,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
>>> * Power/performance team will optimize it and might give a new value later.
>>> */
>>> if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 1):
>>> data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
>>> WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
>>> @@ -8399,7 +8399,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 1):
>>> case IP_VERSION(10, 1, 2):
>>> @@ -8428,7 +8428,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 1):
>>> case IP_VERSION(10, 1, 2):
>>> @@ -9541,7 +9541,7 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
>>>
>>> static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 1):
>>> case IP_VERSION(10, 1, 3):
>>> @@ -9641,8 +9641,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
>>> for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
>>> for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
>>> bitmap = i * adev->gfx.config.max_sh_per_se + j;
>>> - if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
>>> - (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
>>> + if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
>>> + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
>>> ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
>>> continue;
>>> mask = 1;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> index 3a160d78c98f..8f2966bcf5a4 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> @@ -953,7 +953,7 @@ static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
>>>
>>> static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> soc15_program_register_sequence(adev,
>>> golden_settings_gc_9_0,
>>> @@ -1009,8 +1009,8 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
>>> break;
>>> }
>>>
>>> - if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
>>> - (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2)))
>>> + if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
>>> + (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)))
>>> soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
>>> (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
>>> }
>>> @@ -1194,14 +1194,14 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
>>> adev->gfx.me_fw_write_wait = false;
>>> adev->gfx.mec_fw_write_wait = false;
>>>
>>> - if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
>>> + if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
>>> ((adev->gfx.mec_fw_version < 0x000001a5) ||
>>> (adev->gfx.mec_feature_version < 46) ||
>>> (adev->gfx.pfp_fw_version < 0x000000b7) ||
>>> (adev->gfx.pfp_feature_version < 46)))
>>> DRM_WARN_ONCE("CP firmware version too old, please update!");
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> if ((adev->gfx.me_fw_version >= 0x0000009c) &&
>>> (adev->gfx.me_feature_version >= 42) &&
>>> @@ -1301,7 +1301,7 @@ static bool is_raven_kicker(struct amdgpu_device *adev)
>>>
>>> static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
>>> {
>>> - if ((adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0)) &&
>>> + if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) &&
>>> (adev->gfx.me_fw_version >= 0x000000a5) &&
>>> (adev->gfx.me_feature_version >= 52))
>>> return true;
>>> @@ -1314,7 +1314,7 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
>>> if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
>>> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 2, 1):
>>> case IP_VERSION(9, 4, 0):
>>> @@ -1558,9 +1558,9 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
>>>
>>> static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)
>>> {
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2) ||
>>> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
>>> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0))
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
>>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
>>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0))
>>> return false;
>>>
>>> return true;
>>> @@ -1668,7 +1668,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
>>>
>>> DRM_DEBUG("\n");
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> chip_name = "vega10";
>>> break;
>>> @@ -1800,7 +1800,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
>>>
>>> if (adev->flags & AMD_IS_APU)
>>> always_on_cu_num = 4;
>>> - else if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1))
>>> + else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1))
>>> always_on_cu_num = 8;
>>> else
>>> always_on_cu_num = 12;
>>> @@ -1969,7 +1969,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>>> return r;
>>> }
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 2, 2):
>>> case IP_VERSION(9, 1, 0):
>>> gfx_v9_0_init_lbpw(adev);
>>> @@ -2149,7 +2149,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
>>>
>>> adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> adev->gfx.config.max_hw_contexts = 8;
>>> adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
>>> @@ -2313,7 +2313,7 @@ static int gfx_v9_0_sw_init(void *handle)
>>> struct amdgpu_kiq *kiq;
>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 2, 1):
>>> case IP_VERSION(9, 4, 0):
>>> @@ -2605,7 +2605,7 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
>>> {
>>> uint32_t tmp;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 4, 1):
>>> tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
>>> tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
>>> @@ -2941,7 +2941,7 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
>>> /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
>>> data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
>>> WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
>>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 3, 0))
>>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0))
>>> pwr_10_0_gfxip_control_over_cgpg(adev, true);
>>> }
>>> }
>>> @@ -3053,7 +3053,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
>>> * And it's needed by gfxoff feature.
>>> */
>>> if (adev->gfx.rlc.is_rlc_v2_1) {
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1) ||
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) ||
>>> (adev->apu_flags & AMD_APU_IS_RAVEN2))
>>> gfx_v9_1_init_rlc_save_restore_list(adev);
>>> gfx_v9_0_enable_save_restore_machine(adev);
>>> @@ -3166,7 +3166,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
>>> return r;
>>> }
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 2, 2):
>>> case IP_VERSION(9, 1, 0):
>>> if (amdgpu_lbpw == 0)
>>> @@ -3969,8 +3969,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
>>> {
>>> u32 tmp;
>>>
>>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1) &&
>>> - adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2))
>>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) &&
>>> + adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))
>>> return;
>>>
>>> tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
>>> @@ -4010,7 +4010,7 @@ static int gfx_v9_0_hw_init(void *handle)
>>> if (r)
>>> return r;
>>>
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
>>> gfx_v9_4_2_set_power_brake_sequence(adev);
>>>
>>> return r;
>>> @@ -4242,7 +4242,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>>>
>>> amdgpu_gfx_off_ctrl(adev, false);
>>> mutex_lock(&adev->gfx.gpu_clock_mutex);
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
>>> clock = gfx_v9_0_kiq_read_clock(adev);
>>> } else {
>>> WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
>>> @@ -4592,7 +4592,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
>>> if (!ring->sched.ready)
>>> return 0;
>>>
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1)) {
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
>>> vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
>>> vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
>>> vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
>>> @@ -4742,8 +4742,8 @@ static int gfx_v9_0_early_init(void *handle)
>>> {
>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
>>> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
>>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
>>> adev->gfx.num_gfx_rings = 0;
>>> else
>>> adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
>>> @@ -4777,7 +4777,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
>>> }
>>>
>>> /* requires IBs so do in late init after IB pool is initialized */
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
>>> r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
>>> else
>>> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
>>> @@ -4905,7 +4905,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
>>> /* 1 - RLC_CGTT_MGCG_OVERRIDE */
>>> def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>>>
>>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
>>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
>>> data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
>>>
>>> data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
>>> @@ -4939,7 +4939,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
>>> /* 1 - MGCG_OVERRIDE */
>>> def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>>>
>>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
>>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
>>> data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
>>>
>>> data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
>>> @@ -5045,7 +5045,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>>> /* enable cgcg FSM(0x0000363F) */
>>> def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
>>>
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1))
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1))
>>> data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>>> RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>>> else
>>> @@ -5171,7 +5171,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>> bool enable = (state == AMD_PG_STATE_GATE);
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 2, 2):
>>> case IP_VERSION(9, 1, 0):
>>> case IP_VERSION(9, 3, 0):
>>> @@ -5218,7 +5218,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 2, 1):
>>> case IP_VERSION(9, 4, 0):
>>> @@ -5268,7 +5268,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
>>> if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
>>> *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
>>>
>>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) {
>>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) {
>>> /* AMD_CG_SUPPORT_GFX_3D_CGCG */
>>> data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
>>> if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
>>> @@ -7039,7 +7039,7 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
>>>
>>> static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 2, 1):
>>> case IP_VERSION(9, 4, 0):
>>> @@ -7058,7 +7058,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
>>> static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
>>> {
>>> /* init asci gds info */
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 2, 1):
>>> case IP_VERSION(9, 4, 0):
>>> @@ -7080,7 +7080,7 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
>>> break;
>>> }
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> case IP_VERSION(9, 4, 0):
>>> adev->gds.gds_compute_max_wave_id = 0x7ff;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
>>> index 149f3843e0e7..e80d1dc43079 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
>>> @@ -506,7 +506,7 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
>>> u32 max_num_physical_nodes = 0;
>>> u32 max_physical_node_id = 0;
>>>
>>> - switch (adev->ip_versions[XGMI_HWIP]) {
>>> + switch (adev->ip_versions[XGMI_HWIP][0]) {
>>> case IP_VERSION(4, 8, 0):
>>> max_num_physical_nodes = 4;
>>> max_physical_node_id = 3;
>>> @@ -544,7 +544,7 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
>>> adev->gfx.config.max_sh_per_se *
>>> adev->gfx.config.max_shader_engines);
>>>
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3)) {
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) {
>>> /* Get SA disabled bitmap from eFuse setting */
>>> efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
>>> efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>>> index b488257ff201..6d0586009de3 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>>> @@ -133,7 +133,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
>>> * the new fast GRBM interface.
>>> */
>>> if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
>>> - (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
>>> + (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
>>> RREG32(hub->vm_l2_pro_fault_status);
>>>
>>> status = RREG32(hub->vm_l2_pro_fault_status);
>>> @@ -268,7 +268,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
>>> * to avoid a false ACK due to the new fast GRBM interface.
>>> */
>>> if ((vmhub == AMDGPU_GFXHUB_0) &&
>>> - (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
>>> + (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
>>> RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
>>> hub->eng_distance * eng, hub_ip);
>>>
>>> @@ -657,7 +657,7 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
>>>
>>> static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[UMC_HWIP]) {
>>> + switch (adev->ip_versions[UMC_HWIP][0]) {
>>> case IP_VERSION(8, 7, 0):
>>> adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
>>> adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
>>> @@ -674,7 +674,7 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
>>>
>>> static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 3, 0):
>>> case IP_VERSION(2, 4, 0):
>>> adev->mmhub.funcs = &mmhub_v2_3_funcs;
>>> @@ -687,7 +687,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
>>>
>>> static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 3, 0):
>>> case IP_VERSION(10, 3, 2):
>>> case IP_VERSION(10, 3, 1):
>>> @@ -857,7 +857,7 @@ static int gmc_v10_0_sw_init(void *handle)
>>> adev->gmc.vram_vendor = vram_vendor;
>>> }
>>>
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> case IP_VERSION(10, 1, 1):
>>> case IP_VERSION(10, 1, 2):
>>> @@ -1132,7 +1132,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
>>> if (r)
>>> return r;
>>>
>>> - if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
>>> + if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
>>> return athub_v2_1_set_clockgating(adev, state);
>>> else
>>> return athub_v2_0_set_clockgating(adev, state);
>>> @@ -1144,7 +1144,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
>>>
>>> adev->mmhub.funcs->get_clockgating(adev, flags);
>>>
>>> - if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
>>> + if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
>>> athub_v2_1_get_clockgating(adev, flags);
>>> else
>>> athub_v2_0_get_clockgating(adev, flags);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
>>> index 88938115557b..eecfb1545c1e 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
>>> @@ -49,7 +49,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
>>> static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
>>> struct amdgpu_ring *ring)
>>> {
>>> - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 4, 0))
>>> + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
>>> return;
>>>
>>> if (!ring || !ring->funcs->emit_wreg)
>>> @@ -79,7 +79,7 @@ static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
>>> if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
>>> return;
>>>
>>> - if (adev->ip_versions[HDP_HWIP] >= IP_VERSION(4, 4, 0))
>>> + if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
>>> WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
>>> else
>>> /*read back hdp ras counter to reset it to 0 */
>>> @@ -91,10 +91,10 @@ static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
>>> {
>>> uint32_t def, data;
>>>
>>> - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 0) ||
>>> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 1) ||
>>> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 1) ||
>>> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 0)) {
>>> + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
>>> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
>>> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
>>> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
>>> def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
>>>
>>> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
>>> @@ -136,7 +136,7 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
>>>
>>> static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[HDP_HWIP]) {
>>> + switch (adev->ip_versions[HDP_HWIP][0]) {
>>> case IP_VERSION(4, 2, 1):
>>> WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
>>> break;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
>>> index e0cb919b4814..25f8e93e5ec3 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
>>> @@ -153,7 +153,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
>>> dev_err(adev->dev,
>>> "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
>>> status);
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 0, 0):
>>> case IP_VERSION(2, 0, 2):
>>> mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
>>> @@ -569,7 +569,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
>>> if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
>>> return;
>>>
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 1, 0):
>>> case IP_VERSION(2, 1, 1):
>>> case IP_VERSION(2, 1, 2):
>>> @@ -603,7 +603,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
>>> DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
>>> }
>>>
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 1, 0):
>>> case IP_VERSION(2, 1, 1):
>>> case IP_VERSION(2, 1, 2):
>>> @@ -629,7 +629,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
>>> if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
>>> return;
>>>
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 1, 0):
>>> case IP_VERSION(2, 1, 1):
>>> case IP_VERSION(2, 1, 2):
>>> @@ -646,7 +646,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
>>> data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
>>>
>>> if (def != data) {
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 1, 0):
>>> case IP_VERSION(2, 1, 1):
>>> case IP_VERSION(2, 1, 2):
>>> @@ -665,7 +665,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 0, 0):
>>> case IP_VERSION(2, 0, 2):
>>> case IP_VERSION(2, 1, 0):
>>> @@ -690,7 +690,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
>>> if (amdgpu_sriov_vf(adev))
>>> *flags = 0;
>>>
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 1, 0):
>>> case IP_VERSION(2, 1, 1):
>>> case IP_VERSION(2, 1, 2):
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
>>> index 4cf5d0595bbe..a11d60ec6321 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
>>> @@ -90,7 +90,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
>>> dev_err(adev->dev,
>>> "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
>>> status);
>>> - switch (adev->ip_versions[MMHUB_HWIP]) {
>>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
>>> case IP_VERSION(2, 3, 0):
>>> case IP_VERSION(2, 4, 0):
>>> mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> index c3f968d9cfcb..1d8414c3fadb 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> @@ -107,7 +107,7 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
>>> {
>>> u32 ih_cntl, ih_rb_cntl;
>>>
>>> - if (adev->ip_versions[OSSSYS_HWIP] < IP_VERSION(5, 0, 3))
>>> + if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3))
>>> return;
>>>
>>> ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
>>> @@ -332,7 +332,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
>>>
>>> if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
>>> if (ih[0]->use_bus_addr) {
>>> - switch (adev->ip_versions[OSSSYS_HWIP]) {
>>> + switch (adev->ip_versions[OSSSYS_HWIP][0]) {
>>> case IP_VERSION(5, 0, 3):
>>> case IP_VERSION(5, 2, 0):
>>> case IP_VERSION(5, 2, 1):
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
>>> index 57be517d70bf..89e32d6e2c10 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>>> @@ -180,7 +180,7 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
>>> static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
>>> const struct amdgpu_video_codecs **codecs)
>>> {
>>> - switch (adev->ip_versions[UVD_HWIP]) {
>>> + switch (adev->ip_versions[UVD_HWIP][0]) {
>>> case IP_VERSION(3, 0, 0):
>>> if (amdgpu_sriov_vf(adev)) {
>>> if (encode)
>>> @@ -509,7 +509,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
>>> dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
>>> amdgpu_reset_method);
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 5, 0):
>>> case IP_VERSION(13, 0, 1):
>>> case IP_VERSION(13, 0, 3):
>>> @@ -1044,7 +1044,7 @@ static int nv_common_early_init(void *handle)
>>> /* TODO: split the GC and PG flags based on the relevant IP version for which
>>> * they are relevant.
>>> */
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(10, 1, 10):
>>> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
>>> AMD_CG_SUPPORT_GFX_CGCG |
>>> @@ -1375,7 +1375,7 @@ static int nv_common_set_clockgating_state(void *handle,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[NBIO_HWIP]) {
>>> + switch (adev->ip_versions[NBIO_HWIP][0]) {
>>> case IP_VERSION(2, 3, 0):
>>> case IP_VERSION(2, 3, 1):
>>> case IP_VERSION(2, 3, 2):
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>>> index 13dace5d2855..382cebfc2069 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>>> @@ -93,7 +93,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
>>>
>>> DRM_DEBUG("\n");
>>>
>>> - switch (adev->ip_versions[MP0_HWIP]) {
>>> + switch (adev->ip_versions[MP0_HWIP][0]) {
>>> case IP_VERSION(11, 0, 2):
>>> chip_name = "vega20";
>>> break;
>>> @@ -129,7 +129,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
>>> }
>>>
>>>
>>> - switch (adev->ip_versions[MP0_HWIP]) {
>>> + switch (adev->ip_versions[MP0_HWIP][0]) {
>>> case IP_VERSION(11, 0, 2):
>>> case IP_VERSION(11, 0, 4):
>>> err = psp_init_sos_microcode(psp, chip_name);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
>>> index 64b52c5ea981..17655bc6d2f1 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
>>> @@ -47,7 +47,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
>>> const char *chip_name;
>>> int err = 0;
>>>
>>> - switch (adev->ip_versions[MP0_HWIP]) {
>>> + switch (adev->ip_versions[MP0_HWIP][0]) {
>>> case IP_VERSION(13, 0, 2):
>>> chip_name = "aldebaran";
>>> break;
>>> @@ -58,7 +58,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
>>> default:
>>> BUG();
>>> }
>>> - switch (adev->ip_versions[MP0_HWIP]) {
>>> + switch (adev->ip_versions[MP0_HWIP][0]) {
>>> case IP_VERSION(13, 0, 2):
>>> err = psp_init_sos_microcode(psp, chip_name);
>>> if (err)
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> index cb74f8c35d0a..e8e4749e9c79 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> @@ -469,7 +469,7 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
>>>
>>> static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> soc15_program_register_sequence(adev,
>>> golden_settings_sdma_4,
>>> @@ -539,7 +539,7 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
>>> * The only chips with SDMAv4 and ULV are VG10 and VG20.
>>> * Server SKUs take a different hysteresis setting from other SKUs.
>>> */
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> if (adev->pdev->device == 0x6860)
>>> break;
>>> @@ -590,8 +590,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
>>>
>>> /* arcturus shares the same FW memory across
>>> all SDMA isntances */
>>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
>>> - adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0))
>>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
>>> + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
>>> break;
>>> }
>>>
>>> @@ -621,7 +621,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
>>>
>>> DRM_DEBUG("\n");
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> chip_name = "vega10";
>>> break;
>>> @@ -667,8 +667,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
>>> goto out;
>>>
>>> for (i = 1; i < adev->sdma.num_instances; i++) {
>>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
>>> - adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0)) {
>>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
>>> + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
>>> /* Acturus & Aldebaran will leverage the same FW memory
>>> for every SDMA instance */
>>> memcpy((void *)&adev->sdma.instance[i],
>>> @@ -1108,7 +1108,7 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
>>> * Arcturus for the moment and firmware version 14
>>> * and above.
>>> */
>>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) &&
>>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) &&
>>> adev->sdma.instance[i].fw_version >= 14)
>>> WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
>>> /* Extend page fault timeout to avoid interrupt storm */
>>> @@ -1395,7 +1395,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
>>> if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
>>> return;
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(4, 1, 0):
>>> case IP_VERSION(4, 1, 1):
>>> case IP_VERSION(4, 1, 2):
>>> @@ -1838,7 +1838,7 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
>>> {
>>> uint fw_version = adev->sdma.instance[0].fw_version;
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> return fw_version >= 430;
>>> case IP_VERSION(4, 0, 1):
>>> @@ -1863,7 +1863,7 @@ static int sdma_v4_0_early_init(void *handle)
>>> }
>>>
>>> /* TODO: Page queue breaks driver reload under SRIOV */
>>> - if ((adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 0, 0)) &&
>>> + if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) &&
>>> amdgpu_sriov_vf((adev)))
>>> adev->sdma.has_page_queue = false;
>>> else if (sdma_v4_0_fw_support_paging_queue(adev))
>>> @@ -2136,14 +2136,14 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
>>> amdgpu_fence_process(&adev->sdma.instance[instance].ring);
>>> break;
>>> case 1:
>>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 0))
>>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0))
>>> amdgpu_fence_process(&adev->sdma.instance[instance].page);
>>> break;
>>> case 2:
>>> /* XXX compute */
>>> break;
>>> case 3:
>>> - if (adev->ip_versions[SDMA0_HWIP] != IP_VERSION(4, 2, 0))
>>> + if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0))
>>> amdgpu_fence_process(&adev->sdma.instance[instance].page);
>>> break;
>>> }
>>> @@ -2359,7 +2359,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
>>> {
>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(4, 1, 0):
>>> case IP_VERSION(4, 1, 1):
>>> case IP_VERSION(4, 1, 2):
>>> @@ -2547,7 +2547,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
>>> int i;
>>>
>>> for (i = 0; i < adev->sdma.num_instances; i++) {
>>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
>>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
>>> adev->sdma.instance[i].ring.funcs =
>>> &sdma_v4_0_ring_funcs_2nd_mmhub;
>>> else
>>> @@ -2555,7 +2555,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
>>> &sdma_v4_0_ring_funcs;
>>> adev->sdma.instance[i].ring.me = i;
>>> if (adev->sdma.has_page_queue) {
>>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
>>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
>>> adev->sdma.instance[i].page.funcs =
>>> &sdma_v4_0_page_ring_funcs_2nd_mmhub;
>>> else
>>> @@ -2782,7 +2782,7 @@ static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
>>>
>>> static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(4, 2, 0):
>>> case IP_VERSION(4, 2, 2):
>>> adev->sdma.funcs = &sdma_v4_0_ras_funcs;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>>> index d3b01d2977c0..853d1511b889 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>>> @@ -187,7 +187,7 @@ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
>>>
>>> static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(5, 0, 0):
>>> soc15_program_register_sequence(adev,
>>> golden_settings_sdma_5,
>>> @@ -248,12 +248,12 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
>>> const struct common_firmware_header *header = NULL;
>>> const struct sdma_firmware_header_v1_0 *hdr;
>>>
>>> - if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 0, 5)))
>>> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
>>> return 0;
>>>
>>> DRM_DEBUG("\n");
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(5, 0, 0):
>>> chip_name = "navi10";
>>> break;
>>> @@ -1634,7 +1634,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(5, 0, 0):
>>> case IP_VERSION(5, 0, 2):
>>> case IP_VERSION(5, 0, 5):
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>>> index 92f29beda3b2..0fec1d9dd638 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>>> @@ -136,7 +136,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
>>>
>>> DRM_DEBUG("\n");
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(5, 2, 0):
>>> chip_name = "sienna_cichlid";
>>> break;
>>> @@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
>>> (void *)&adev->sdma.instance[0],
>>> sizeof(struct amdgpu_sdma_instance));
>>>
>>> - if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 0)))
>>> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
>>> return 0;
>>>
>>> DRM_DEBUG("psp_load == '%s'\n",
>>> @@ -1530,7 +1530,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
>>>
>>> for (i = 0; i < adev->sdma.num_instances; i++) {
>>>
>>> - if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
>>> + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
>>> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
>>>
>>> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
>>> @@ -1567,7 +1567,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>>>
>>> for (i = 0; i < adev->sdma.num_instances; i++) {
>>>
>>> - if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
>>> + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
>>> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
>>>
>>> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
>>> @@ -1596,7 +1596,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[SDMA0_HWIP]) {
>>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
>>> case IP_VERSION(5, 2, 0):
>>> case IP_VERSION(5, 2, 2):
>>> case IP_VERSION(5, 2, 1):
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
>>> index 7f4cd1a4f6cb..74310bb4216a 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>>> @@ -156,8 +156,8 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
>>> static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
>>> const struct amdgpu_video_codecs **codecs)
>>> {
>>> - if (adev->ip_versions[VCE_HWIP]) {
>>> - switch (adev->ip_versions[VCE_HWIP]) {
>>> + if (adev->ip_versions[VCE_HWIP][0]) {
>>> + switch (adev->ip_versions[VCE_HWIP][0]) {
>>> case IP_VERSION(4, 0, 0):
>>> case IP_VERSION(4, 1, 0):
>>> if (encode)
>>> @@ -169,7 +169,7 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
>>> return -EINVAL;
>>> }
>>> } else {
>>> - switch (adev->ip_versions[UVD_HWIP]) {
>>> + switch (adev->ip_versions[UVD_HWIP][0]) {
>>> case IP_VERSION(1, 0, 0):
>>> case IP_VERSION(1, 0, 1):
>>> if (encode)
>>> @@ -341,11 +341,11 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
>>> {
>>> u32 reference_clock = adev->clock.spll.reference_freq;
>>>
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
>>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
>>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
>>> return 10000;
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
>>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
>>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
>>> return reference_clock / 4;
>>>
>>> return reference_clock;
>>> @@ -576,7 +576,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
>>> dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
>>> amdgpu_reset_method);
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(10, 0, 0):
>>> case IP_VERSION(10, 0, 1):
>>> case IP_VERSION(12, 0, 0):
>>> @@ -641,7 +641,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
>>>
>>> static bool soc15_supports_baco(struct amdgpu_device *adev)
>>> {
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(9, 0, 0):
>>> case IP_VERSION(11, 0, 2):
>>> if (adev->asic_type == CHIP_VEGA20) {
>>> @@ -1172,7 +1172,7 @@ static int soc15_common_early_init(void *handle)
>>> /* TODO: split the GC and PG flags based on the relevant IP version for which
>>> * they are relevant.
>>> */
>>> - switch (adev->ip_versions[GC_HWIP]) {
>>> + switch (adev->ip_versions[GC_HWIP][0]) {
>>> case IP_VERSION(9, 0, 1):
>>> adev->asic_funcs = &soc15_asic_funcs;
>>> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
>>> @@ -1583,7 +1583,7 @@ static int soc15_common_set_clockgating_state(void *handle,
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[NBIO_HWIP]) {
>>> + switch (adev->ip_versions[NBIO_HWIP][0]) {
>>> case IP_VERSION(6, 1, 0):
>>> case IP_VERSION(6, 2, 0):
>>> case IP_VERSION(7, 4, 0):
>>> @@ -1639,7 +1639,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
>>>
>>> adev->hdp.funcs->get_clock_gating_state(adev, flags);
>>>
>>> - if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
>>> + if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
>>>
>>> /* AMD_CG_SUPPORT_DRM_MGCG */
>>> data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> index e9758969fbe6..f4a7a30ecebd 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> @@ -1720,7 +1720,7 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
>>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>>> if (adev->vcn.harvest_config & (1 << i))
>>> continue;
>>> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
>>> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
>>> adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
>>> else /* CHIP_ALDEBARAN */
>>> adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
>>> @@ -1737,7 +1737,7 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
>>> if (adev->vcn.harvest_config & (1 << j))
>>> continue;
>>> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>>> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
>>> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
>>> adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
>>> else /* CHIP_ALDEBARAN */
>>> adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>>> index a81d834ea0d3..6940716db1df 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>>> @@ -95,7 +95,7 @@ static int vcn_v3_0_early_init(void *handle)
>>> adev->vcn.num_enc_rings = 1;
>>>
>>> } else {
>>> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
>>> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 0)) {
>>> u32 harvest;
>>>
>>> for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>>> @@ -110,7 +110,7 @@ static int vcn_v3_0_early_init(void *handle)
>>> return -ENOENT;
>>> }
>>>
>>> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
>>> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33))
>>> adev->vcn.num_enc_rings = 0;
>>> else
>>> adev->vcn.num_enc_rings = 2;
>>> @@ -1270,7 +1270,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
>>> fw_shared->rb.wptr = lower_32_bits(ring->wptr);
>>> fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
>>>
>>> - if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
>>> + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
>>> fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
>>> ring = &adev->vcn.inst[i].ring_enc[0];
>>> WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
>>> @@ -1642,7 +1642,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
>>> UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
>>> ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
>>>
>>> - if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
>>> + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
>>> /* Restore */
>>> fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
>>> fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> index fc8a30251fa4..fb89ce4dd28c 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> @@ -1344,7 +1344,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>>> init_data.flags.gpu_vm_support = true;
>>> break;
>>> default:
>>> - switch (adev->ip_versions[DCE_HWIP]) {
>>> + switch (adev->ip_versions[DCE_HWIP][0]) {
>>> case IP_VERSION(2, 1, 0):
>>> init_data.flags.gpu_vm_support = true;
>>> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
>>> @@ -1658,7 +1658,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
>>> return 0;
>>> break;
>>> default:
>>> - switch (adev->ip_versions[DCE_HWIP]) {
>>> + switch (adev->ip_versions[DCE_HWIP][0]) {
>>> case IP_VERSION(2, 0, 2):
>>> case IP_VERSION(2, 0, 0):
>>> case IP_VERSION(2, 1, 0):
>>> @@ -1750,7 +1750,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
>>> enum dmub_status status;
>>> int r;
>>>
>>> - switch (adev->ip_versions[DCE_HWIP]) {
>>> + switch (adev->ip_versions[DCE_HWIP][0]) {
>>> case IP_VERSION(2, 1, 0):
>>> dmub_asic = DMUB_ASIC_DCN21;
>>> fw_name_dmub = FIRMWARE_RENOIR_DMUB;
>>> @@ -1758,7 +1758,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
>>> fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
>>> break;
>>> case IP_VERSION(3, 0, 0):
>>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
>>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
>>> dmub_asic = DMUB_ASIC_DCN30;
>>> fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
>>> } else {
>>> @@ -2078,7 +2078,7 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
>>> * therefore, this function apply to navi10/12/14 but not Renoir
>>> * *
>>> */
>>> - switch (adev->ip_versions[DCE_HWIP]) {
>>> + switch (adev->ip_versions[DCE_HWIP][0]) {
>>> case IP_VERSION(2, 0, 2):
>>> case IP_VERSION(2, 0, 0):
>>> break;
>>> @@ -4086,7 +4086,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>>>
>>> #if defined(CONFIG_DRM_AMD_DC_DCN)
>>> /* Use Outbox interrupt */
>>> - switch (adev->ip_versions[DCE_HWIP]) {
>>> + switch (adev->ip_versions[DCE_HWIP][0]) {
>>> case IP_VERSION(3, 0, 0):
>>> case IP_VERSION(3, 1, 2):
>>> case IP_VERSION(3, 1, 3):
>>> @@ -4098,7 +4098,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>>> break;
>>> default:
>>> DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
>>> - adev->ip_versions[DCE_HWIP]);
>>> + adev->ip_versions[DCE_HWIP][0]);
>>> }
>>> #endif
>>>
>>> @@ -4186,7 +4186,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>>> break;
>>> default:
>>> #if defined(CONFIG_DRM_AMD_DC_DCN)
>>> - switch (adev->ip_versions[DCE_HWIP]) {
>>> + switch (adev->ip_versions[DCE_HWIP][0]) {
>>> case IP_VERSION(1, 0, 0):
>>> case IP_VERSION(1, 0, 1):
>>> case IP_VERSION(2, 0, 2):
>>> @@ -4205,7 +4205,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>>> break;
>>> default:
>>> DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
>>> - adev->ip_versions[DCE_HWIP]);
>>> + adev->ip_versions[DCE_HWIP][0]);
>>> goto fail;
>>> }
>>> #endif
>>> @@ -4357,7 +4357,7 @@ static int dm_early_init(void *handle)
>>> break;
>>> default:
>>> #if defined(CONFIG_DRM_AMD_DC_DCN)
>>> - switch (adev->ip_versions[DCE_HWIP]) {
>>> + switch (adev->ip_versions[DCE_HWIP][0]) {
>>> case IP_VERSION(2, 0, 2):
>>> case IP_VERSION(3, 0, 0):
>>> adev->mode_info.num_crtc = 6;
>>> @@ -4387,7 +4387,7 @@ static int dm_early_init(void *handle)
>>> break;
>>> default:
>>> DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
>>> - adev->ip_versions[DCE_HWIP]);
>>> + adev->ip_versions[DCE_HWIP][0]);
>>> return -EINVAL;
>>> }
>>> #endif
>>> @@ -4609,7 +4609,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
>>> tiling_info->gfx9.num_rb_per_se =
>>> adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
>>> tiling_info->gfx9.shaderEnable = 1;
>>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
>>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
>>> tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
>>> }
>>>
>>> @@ -5050,7 +5050,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
>>> case AMDGPU_FAMILY_NV:
>>> case AMDGPU_FAMILY_VGH:
>>> case AMDGPU_FAMILY_YC:
>>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
>>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
>>> add_gfx10_3_modifiers(adev, mods, &size, &capacity);
>>> else
>>> add_gfx10_1_modifiers(adev, mods, &size, &capacity);
>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>>> index 150cac4ea75c..9c601997a96a 100644
>>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>>> @@ -455,7 +455,7 @@ static int smu_get_power_num_states(void *handle,
>>>
>>> bool is_support_sw_smu(struct amdgpu_device *adev)
>>> {
>>> - if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
>>> + if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
>>> return true;
>>>
>>> return false;
>>> @@ -575,7 +575,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
>>> if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
>>> smu->od_enabled = true;
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 0, 0):
>>> case IP_VERSION(11, 0, 5):
>>> case IP_VERSION(11, 0, 9):
>>> @@ -694,7 +694,7 @@ static int smu_late_init(void *handle)
>>> return ret;
>>> }
>>>
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1))
>>> return 0;
>>>
>>> if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
>>> @@ -1140,10 +1140,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
>>> if (adev->in_suspend && smu_is_dpm_running(smu)) {
>>> dev_info(adev->dev, "dpm has been enabled\n");
>>> /* this is needed specifically */
>>> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)))
>>> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)))
>>> ret = smu_system_features_control(smu, true);
>>> return ret;
>>> }
>>> @@ -1286,7 +1286,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
>>> int ret = 0;
>>>
>>> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>>> - if (adev->ip_versions[MP1_HWIP] < IP_VERSION(11, 0, 0)) {
>>> + if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
>>> if (smu->ppt_funcs->load_microcode) {
>>> ret = smu->ppt_funcs->load_microcode(smu);
>>> if (ret)
>>> @@ -1405,14 +1405,14 @@ static int smu_disable_dpms(struct smu_context *smu)
>>> * properly.
>>> */
>>> if (smu->uploading_custom_pp_table &&
>>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))))
>>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))))
>>> return smu_disable_all_features_with_exception(smu,
>>> true,
>>> SMU_FEATURE_COUNT);
>>> @@ -1421,10 +1421,10 @@ static int smu_disable_dpms(struct smu_context *smu)
>>> * For Sienna_Cichlid, PMFW will handle the features disablement properly
>>> * on BACO in. Driver involvement is unnecessary.
>>> */
>>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))) &&
>>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))) &&
>>> use_baco)
>>> return smu_disable_all_features_with_exception(smu,
>>> true,
>>> @@ -1446,7 +1446,7 @@ static int smu_disable_dpms(struct smu_context *smu)
>>> dev_err(adev->dev, "Failed to disable smu features.\n");
>>> }
>>>
>>> - if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0) &&
>>> + if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0) &&
>>> adev->gfx.rlc.funcs->stop)
>>> adev->gfx.rlc.funcs->stop(adev);
>>>
>>> @@ -2283,11 +2283,11 @@ int smu_get_power_limit(void *handle,
>>> } else {
>>> switch (limit_level) {
>>> case SMU_PPT_LIMIT_CURRENT:
>>> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 2)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
>>> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)))
>>> ret = smu_get_asic_power_limits(smu,
>>> &smu->current_power_limit,
>>> NULL,
>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>>> index d96f904a765b..71161f6b78fe 100644
>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>>> @@ -345,7 +345,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
>>>
>>> /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
>>> if (!(is_asic_secure(smu) &&
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
>>> (adev->rev_id == 0)) &&
>>> (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
>>> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>>> @@ -354,7 +354,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
>>>
>>> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
>>> if (is_asic_secure(smu) &&
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
>>> (adev->rev_id == 0))
>>> *(uint64_t *)feature_mask &=
>>> ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
>>> @@ -925,7 +925,7 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
>>> return ret;
>>> }
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 0, 9):
>>> if (smu_version > 0x00341C00)
>>> ret = navi12_get_smu_metrics_data(smu, member, value);
>>> @@ -935,8 +935,8 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
>>> case IP_VERSION(11, 0, 0):
>>> case IP_VERSION(11, 0, 5):
>>> default:
>>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
>>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
>>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
>>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
>>> ret = navi10_get_smu_metrics_data(smu, member, value);
>>> else
>>> ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
>>> @@ -1509,7 +1509,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
>>> uint32_t sclk_freq;
>>>
>>> pstate_table->gfxclk_pstate.min = gfx_table->min;
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 0, 0):
>>> switch (adev->pdev->revision) {
>>> case 0xf0: /* XTX */
>>> @@ -2562,8 +2562,8 @@ static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
>>> if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
>>> return false;
>>>
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0) ||
>>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5))
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) ||
>>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5))
>>> return true;
>>>
>>> return false;
>>> @@ -2671,8 +2671,8 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
>>> * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
>>> * - PPSMC_MSG_GetUMCFWWA
>>> */
>>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
>>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
>>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
>>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
>>> ret = smu_cmn_send_smc_msg_with_param(smu,
>>> SMU_MSG_GET_UMC_FW_WA,
>>> 0,
>>> @@ -2691,13 +2691,13 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
>>> return 0;
>>>
>>> if (umc_fw_disable_cdr) {
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
>>> return navi10_umc_hybrid_cdr_workaround(smu);
>>> } else {
>>> return navi10_set_dummy_pstates_table_location(smu);
>>> }
>>> } else {
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
>>> return navi10_umc_hybrid_cdr_workaround(smu);
>>> }
>>>
>>> @@ -3151,7 +3151,7 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
>>> return ret;
>>> }
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 0, 9):
>>> if (smu_version > 0x00341C00)
>>> ret = navi12_get_gpu_metrics(smu, table);
>>> @@ -3161,8 +3161,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
>>> case IP_VERSION(11, 0, 0):
>>> case IP_VERSION(11, 0, 5):
>>> default:
>>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
>>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
>>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
>>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
>>> ret = navi10_get_gpu_metrics(smu, table);
>>> else
>>> ret =navi10_get_legacy_gpu_metrics(smu, table);
>>> @@ -3180,7 +3180,7 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>>> uint32_t param = 0;
>>>
>>> /* Navi12 does not support this */
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))
>>> return 0;
>>>
>>> /*
>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
>>> index 6a0fed5e33d9..15e66e1912de 100644
>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
>>> @@ -74,7 +74,7 @@
>>> #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
>>>
>>> #define GET_PPTABLE_MEMBER(field, member) do {\
>>> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))\
>>> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
>>> (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
>>> else\
>>> (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
>>> @@ -82,7 +82,7 @@
>>>
>>> static int get_table_size(struct smu_context *smu)
>>> {
>>> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
>>> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
>>> return sizeof(PPTable_beige_goby_t);
>>> else
>>> return sizeof(PPTable_t);
>>> @@ -298,7 +298,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
>>> }
>>>
>>> if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
>>> - (adev->ip_versions[MP1_HWIP] > IP_VERSION(11, 0, 7)) &&
>>> + (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
>>> !(adev->flags & AMD_IS_APU))
>>> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
>>>
>>> @@ -496,7 +496,7 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s
>>> uint32_t throttler_status = 0;
>>> int i;
>>>
>>> - if ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
>>> + if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
>>> (smu->smc_fw_version >= 0x3A4300)) {
>>> for (i = 0; i < THROTTLER_COUNT; i++)
>>> throttler_status |=
>>> @@ -517,7 +517,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
>>> &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
>>> SmuMetrics_V2_t *metrics_v2 =
>>> &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
>>> - bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
>>> + bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
>>> (smu->smc_fw_version >= 0x3A4300)) ? true : false;
>>> uint16_t average_gfx_activity;
>>> int ret = 0;
>>> @@ -1170,7 +1170,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
>>> * and onwards SMU firmwares.
>>> */
>>> smu_cmn_get_smc_version(smu, NULL, &smu_version);
>>> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
>>> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
>>> (smu_version < 0x003a2900))
>>> break;
>>>
>>> @@ -1937,7 +1937,7 @@ static void sienna_cichlid_dump_od_table(struct smu_context *smu,
>>> od_table->UclkFmax);
>>>
>>> smu_cmn_get_smc_version(smu, NULL, &smu_version);
>>> - if (!((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
>>> + if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
>>> (smu_version < 0x003a2900)))
>>> dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
>>> }
>>> @@ -2161,7 +2161,7 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
>>> * and onwards SMU firmwares.
>>> */
>>> smu_cmn_get_smc_version(smu, NULL, &smu_version);
>>> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
>>> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
>>> (smu_version < 0x003a2900)) {
>>> dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
>>> "only by 58.41.0 and onwards SMU firmwares!\n");
>>> @@ -2865,7 +2865,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
>>> PPTable_t *pptable = table_context->driver_pptable;
>>> int i;
>>>
>>> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)) {
>>> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
>>> beige_goby_dump_pptable(smu);
>>> return;
>>> }
>>> @@ -3625,7 +3625,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
>>> SmuMetrics_V2_t *metrics_v2 =
>>> &(metrics_external.SmuMetrics_V2);
>>> struct amdgpu_device *adev = smu->adev;
>>> - bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
>>> + bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
>>> (smu->smc_fw_version >= 0x3A4300)) ? true : false;
>>> uint16_t average_gfx_activity;
>>> int ret = 0;
>>> @@ -3706,8 +3706,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
>>>
>>> gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
>>>
>>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
>>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
>>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
>>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
>>> gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
>>> gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
>>> } else {
>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
>>> index 1ae8b8dc3bd3..3470c33ee09d 100644
>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
>>> @@ -90,11 +90,11 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
>>> struct amdgpu_firmware_info *ucode = NULL;
>>>
>>> if (amdgpu_sriov_vf(adev) &&
>>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
>>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7))))
>>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
>>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7))))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 0, 0):
>>> chip_name = "navi10";
>>> break;
>>> @@ -121,7 +121,7 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
>>> break;
>>> default:
>>> dev_err(adev->dev, "Unsupported IP version 0x%x\n",
>>> - adev->ip_versions[MP1_HWIP]);
>>> + adev->ip_versions[MP1_HWIP][0]);
>>> return -EINVAL;
>>> }
>>>
>>> @@ -239,7 +239,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
>>> if (smu->is_apu)
>>> adev->pm.fw_version = smu_version;
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 0, 0):
>>> smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
>>> break;
>>> @@ -272,7 +272,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
>>> break;
>>> default:
>>> dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
>>> - adev->ip_versions[MP1_HWIP]);
>>> + adev->ip_versions[MP1_HWIP][0]);
>>> smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
>>> break;
>>> }
>>> @@ -496,7 +496,7 @@ int smu_v11_0_init_power(struct smu_context *smu)
>>> {
>>> struct amdgpu_device *adev = smu->adev;
>>> struct smu_power_context *smu_power = &smu->smu_power;
>>> - size_t size = adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ?
>>> + size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ?
>>> sizeof(struct smu_11_5_power_context) :
>>> sizeof(struct smu_11_0_power_context);
>>>
>>> @@ -753,9 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
>>> /* Navy_Flounder/Dimgrey_Cavefish do not support to change
>>> * display num currently
>>> */
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11) ||
>>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ||
>>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) ||
>>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ||
>>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
>>> return 0;
>>>
>>> return smu_cmn_send_smc_msg_with_param(smu,
>>> @@ -1140,7 +1140,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
>>> int ret = 0;
>>> struct amdgpu_device *adev = smu->adev;
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 0, 0):
>>> case IP_VERSION(11, 0, 5):
>>> case IP_VERSION(11, 0, 9):
>>> @@ -1634,7 +1634,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
>>> mutex_lock(&smu_baco->mutex);
>>>
>>> if (state == SMU_BACO_STATE_ENTER) {
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(11, 0, 7):
>>> case IP_VERSION(11, 0, 11):
>>> case IP_VERSION(11, 0, 12):
>>> @@ -1653,7 +1653,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
>>> default:
>>> if (!ras || !adev->ras_enabled ||
>>> adev->gmc.xgmi.pending_reset) {
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
>>> data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
>>> data |= 0x80000000;
>>> WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
>>> @@ -1935,7 +1935,7 @@ int smu_v11_0_set_performance_level(struct smu_context *smu,
>>> * Separate MCLK and SOCCLK soft min/max settings are not allowed
>>> * on Arcturus.
>>> */
>>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
>>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
>>> mclk_min = mclk_max = 0;
>>> socclk_min = socclk_max = 0;
>>> }
>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
>>> index 08f3cc809fc6..05c5e61f3506 100644
>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
>>> @@ -89,13 +89,13 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
>>> if (amdgpu_sriov_vf(adev))
>>> return 0;
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(13, 0, 2):
>>> chip_name = "aldebaran";
>>> break;
>>> default:
>>> dev_err(adev->dev, "Unsupported IP version 0x%x\n",
>>> - adev->ip_versions[MP1_HWIP]);
>>> + adev->ip_versions[MP1_HWIP][0]);
>>> return -EINVAL;
>>> }
>>>
>>> @@ -211,7 +211,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
>>> smu_minor = (smu_version >> 8) & 0xff;
>>> smu_debug = (smu_version >> 0) & 0xff;
>>>
>>> - switch (smu->adev->ip_versions[MP1_HWIP]) {
>>> + switch (smu->adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(13, 0, 2):
>>> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
>>> break;
>>> @@ -221,7 +221,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
>>> break;
>>> default:
>>> dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
>>> - smu->adev->ip_versions[MP1_HWIP]);
>>> + smu->adev->ip_versions[MP1_HWIP][0]);
>>> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
>>> break;
>>> }
>>> @@ -743,7 +743,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
>>> int ret = 0;
>>> struct amdgpu_device *adev = smu->adev;
>>>
>>> - switch (adev->ip_versions[MP1_HWIP]) {
>>> + switch (adev->ip_versions[MP1_HWIP][0]) {
>>> case IP_VERSION(13, 0, 1):
>>> case IP_VERSION(13, 0, 3):
>>> if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
>>>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 61/66] drm/amdgpu: convert IP version array to include instances
2021-09-23 4:58 ` Lazar, Lijo
@ 2021-09-23 21:42 ` Alex Deucher
0 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-23 21:42 UTC (permalink / raw)
To: Lazar, Lijo; +Cc: Alex Deucher, amd-gfx list
On Thu, Sep 23, 2021 at 12:58 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 9/22/2021 9:47 PM, Alex Deucher wrote:
> > On Wed, Sep 22, 2021 at 5:08 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
> >>
> >>
> >>
> >> On 9/21/2021 11:37 PM, Alex Deucher wrote:
> >>> Allow us to query instances versions more cleanly.
> >>>
> >>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >>> ---
> >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
> >>> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 262 +++++++++---------
> >>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 +--
> >>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 +-
> >>> drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 2 +-
> >>> drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 2 +-
> >>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 80 +++---
> >>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 72 ++---
> >>> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 4 +-
> >>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 16 +-
> >>> drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 14 +-
> >>> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 14 +-
> >>> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +-
> >>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 +-
> >>> drivers/gpu/drm/amd/amdgpu/nv.c | 8 +-
> >>> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 +-
> >>> drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 4 +-
> >>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 34 +--
> >>> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +-
> >>> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +-
> >>> drivers/gpu/drm/amd/amdgpu/soc15.c | 24 +-
> >>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
> >>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 +-
> >>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +-
> >>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 52 ++--
> >>> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 32 +--
> >>> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
> >>> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 28 +-
> >>> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 +-
> >>> 29 files changed, 394 insertions(+), 394 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> index b153c3740307..f4bceb2624fb 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> @@ -1096,7 +1096,7 @@ struct amdgpu_device {
> >>> struct pci_saved_state *pci_state;
> >>>
> >>> struct amdgpu_reset_control *reset_cntl;
> >>> - uint32_t ip_versions[HW_ID_MAX];
> >>> + uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
> >>
> >> Here is the confusion. "ip_versions" is used like this -
> >> adev->ip_versions[MMHUB_HWIP] - which means the first dimension can max
> >> out at MAX_HWIP. So why is the array maxed to HW_ID_MAX? HWID looks
> >> like a completely different thing.
> >>
> >> Got this confusion while reviewing patch 52. Besides, this change
> >> doesn't go well with that patch because HWIP is really replicating
> >> instances.
> >
> > It's not consistent unfortunately. SDMA is a good example. Sienna
> > cichlid has 8 total SDMA instances, each enumerated separately (HWIDs
> > 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are
> > enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x
> > HWID 43). UMC is another example. On most chips there are multiple
> > instances with the same HWID.
> >
>
> To clarify about HW_ID_MAX and HWIP/MAX_HWIP - In total there are around
> 300 HWIDs, however driver uses a select few using HWIP. So the max
> number of possible HWIPs in driver are MAX_HWIP. Question was about
> array size.
>
> uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE]
> or
> uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]
>
> On different HWIDs for SDMA or other IP - will the the below check be
> good enough (assume all HWIDs carry the same IP version) or is there a
> need for loop?
> switch (adev->ip_versions[SDMA0_HWIP][0])
I think it's ok for now. On IPs where it is an issue, we'll need to
address it. For example, on sienna cichlid, there are two VCN
instances with different IP versions, each one supports a different
set of CODECs, but other than that the IPs are the same. So we could
use the the IP discovery table to determine that today rather than
just hardcoding it. I just never got that far. Theoretically there
could be chips with multiple VCN or other IP instances with multiple
completely different generations of IP (e.g., VCN 3.x and 2.x). If
that ever comes up, we'd need to walk the instances as well.
Alex
>
> Thanks,
> Lijo
>
> > Alex
> >
> >>
> >> Thanks,
> >> Lijo
> >>
> >>> };
> >>>
> >>> static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> >>> index 9d8aea39f36a..eff348dee9e9 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> >>> @@ -369,7 +369,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
> >>> hw_id_names[le16_to_cpu(ip->hw_id)]);
> >>> adev->reg_offset[hw_ip][ip->number_instance] =
> >>> ip->base_address;
> >>> - adev->ip_versions[hw_ip + ip->number_instance] =
> >>> + adev->ip_versions[hw_ip][ip->number_instance] =
> >>> amdgpu_discovery_convert_version(ip->major,
> >>> ip->minor,
> >>> ip->revision);
> >>> @@ -525,139 +525,139 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> case CHIP_VEGA10:
> >>> vega10_reg_base_init(adev);
> >>> adev->sdma.num_instances = 2;
> >>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);
> >>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);
> >>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);
> >>> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> >>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);
> >>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);
> >>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);
> >>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> >>> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> >>> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);
> >>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
> >>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
> >>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
> >>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
> >>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
> >>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
> >>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
> >>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
> >>> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
> >>> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
> >>> break;
> >>> case CHIP_VEGA12:
> >>> vega10_reg_base_init(adev);
> >>> adev->sdma.num_instances = 2;
> >>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);
> >>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);
> >>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);
> >>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);
> >>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);
> >>> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);
> >>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);
> >>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);
> >>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);
> >>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);
> >>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);
> >>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);
> >>> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);
> >>> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);
> >>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
> >>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
> >>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
> >>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
> >>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
> >>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
> >>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
> >>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
> >>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
> >>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
> >>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
> >>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
> >>> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
> >>> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
> >>> break;
> >>> case CHIP_RAVEN:
> >>> vega10_reg_base_init(adev);
> >>> adev->sdma.num_instances = 1;
> >>> adev->vcn.num_vcn_inst = 1;
> >>> if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
> >>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);
> >>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);
> >>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);
> >>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);
> >>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);
> >>> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);
> >>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);
> >>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);
> >>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);
> >>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);
> >>> - adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);
> >>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);
> >>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);
> >>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);
> >>> - adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);
> >>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
> >>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
> >>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
> >>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
> >>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
> >>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
> >>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
> >>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
> >>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
> >>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
> >>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
> >>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
> >>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
> >>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
> >>> + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
> >>> } else {
> >>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);
> >>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);
> >>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);
> >>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);
> >>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);
> >>> - adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);
> >>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);
> >>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);
> >>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);
> >>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);
> >>> - adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);
> >>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);
> >>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);
> >>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);
> >>> - adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);
> >>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
> >>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
> >>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
> >>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
> >>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
> >>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
> >>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
> >>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
> >>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
> >>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
> >>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
> >>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
> >>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
> >>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
> >>> + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
> >>> }
> >>> break;
> >>> case CHIP_VEGA20:
> >>> vega20_reg_base_init(adev);
> >>> adev->sdma.num_instances = 2;
> >>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);
> >>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);
> >>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);
> >>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);
> >>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);
> >>> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);
> >>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);
> >>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);
> >>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);
> >>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> >>> - adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);
> >>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);
> >>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);
> >>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);
> >>> - adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);
> >>> - adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);
> >>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
> >>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
> >>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
> >>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
> >>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
> >>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
> >>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
> >>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
> >>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
> >>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
> >>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
> >>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
> >>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
> >>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
> >>> + adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
> >>> + adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
> >>> break;
> >>> case CHIP_ARCTURUS:
> >>> arct_reg_base_init(adev);
> >>> adev->sdma.num_instances = 8;
> >>> adev->vcn.num_vcn_inst = 2;
> >>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);
> >>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);
> >>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);
> >>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);
> >>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);
> >>> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);
> >>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);
> >>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);
> >>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);
> >>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);
> >>> - adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);
> >>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);
> >>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);
> >>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);
> >>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
> >>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
> >>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
> >>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
> >>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
> >>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
> >>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
> >>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
> >>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
> >>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
> >>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
> >>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
> >>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
> >>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
> >>> break;
> >>> case CHIP_ALDEBARAN:
> >>> aldebaran_reg_base_init(adev);
> >>> adev->sdma.num_instances = 5;
> >>> adev->vcn.num_vcn_inst = 2;
> >>> - adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);
> >>> - adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);
> >>> - adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);
> >>> - adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);
> >>> - adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);
> >>> - adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);
> >>> - adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);
> >>> - adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);
> >>> - adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);
> >>> - adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);
> >>> - adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);
> >>> - adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);
> >>> - adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);
> >>> - adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);
> >>> - adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);
> >>> + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
> >>> + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
> >>> + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
> >>> + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
> >>> + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
> >>> + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
> >>> + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
> >>> + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
> >>> + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
> >>> + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
> >>> + adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
> >>> + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
> >>> + adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
> >>> + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
> >>> + adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
> >>> break;
> >>> default:
> >>> r = amdgpu_discovery_reg_base_init(adev);
> >>> @@ -673,7 +673,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> break;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 2, 1):
> >>> case IP_VERSION(9, 4, 0):
> >>> @@ -706,11 +706,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> return -EINVAL;
> >>> }
> >>>
> >>> - if (adev->ip_versions[XGMI_HWIP] == IP_VERSION(4, 8, 0))
> >>> + if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
> >>> adev->gmc.xgmi.supported = true;
> >>>
> >>> /* set NBIO version */
> >>> - switch (adev->ip_versions[NBIO_HWIP]) {
> >>> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> >>> case IP_VERSION(6, 1, 0):
> >>> case IP_VERSION(6, 2, 0):
> >>> adev->nbio.funcs = &nbio_v6_1_funcs;
> >>> @@ -749,7 +749,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> break;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[HDP_HWIP]) {
> >>> + switch (adev->ip_versions[HDP_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> case IP_VERSION(4, 0, 1):
> >>> case IP_VERSION(4, 1, 0):
> >>> @@ -771,7 +771,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> break;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[DF_HWIP]) {
> >>> + switch (adev->ip_versions[DF_HWIP][0]) {
> >>> case IP_VERSION(3, 6, 0):
> >>> case IP_VERSION(3, 6, 1):
> >>> case IP_VERSION(3, 6, 2):
> >>> @@ -788,7 +788,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> break;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[SMUIO_HWIP]) {
> >>> + switch (adev->ip_versions[SMUIO_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 0):
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(10, 0, 0):
> >>> @@ -819,7 +819,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> }
> >>>
> >>> /* what IP to use for this? */
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 1, 0):
> >>> case IP_VERSION(9, 2, 1):
> >>> @@ -847,7 +847,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> }
> >>>
> >>> /* use GC or MMHUB IP version */
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 1, 0):
> >>> case IP_VERSION(9, 2, 1):
> >>> @@ -874,7 +874,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> return -EINVAL;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[OSSSYS_HWIP]) {
> >>> + switch (adev->ip_versions[OSSSYS_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> case IP_VERSION(4, 0, 1):
> >>> case IP_VERSION(4, 1, 0):
> >>> @@ -900,7 +900,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> }
> >>>
> >>> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> >>> - switch (adev->ip_versions[MP0_HWIP]) {
> >>> + switch (adev->ip_versions[MP0_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 0):
> >>> amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
> >>> break;
> >>> @@ -938,7 +938,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> }
> >>>
> >>> if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 0):
> >>> case IP_VERSION(10, 0, 0):
> >>> case IP_VERSION(10, 0, 1):
> >>> @@ -975,8 +975,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
> >>> amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
> >>> #if defined(CONFIG_DRM_AMD_DC)
> >>> - } else if (adev->ip_versions[DCE_HWIP]) {
> >>> - switch (adev->ip_versions[DCE_HWIP]) {
> >>> + } else if (adev->ip_versions[DCE_HWIP][0]) {
> >>> + switch (adev->ip_versions[DCE_HWIP][0]) {
> >>> case IP_VERSION(1, 0, 0):
> >>> case IP_VERSION(1, 0, 1):
> >>> case IP_VERSION(2, 0, 2):
> >>> @@ -995,8 +995,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> default:
> >>> return -EINVAL;
> >>> }
> >>> - } else if (adev->ip_versions[DCI_HWIP]) {
> >>> - switch (adev->ip_versions[DCI_HWIP]) {
> >>> + } else if (adev->ip_versions[DCI_HWIP][0]) {
> >>> + switch (adev->ip_versions[DCI_HWIP][0]) {
> >>> case IP_VERSION(12, 0, 0):
> >>> case IP_VERSION(12, 0, 1):
> >>> case IP_VERSION(12, 1, 0):
> >>> @@ -1007,7 +1007,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> }
> >>> }
> >>> #endif
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 1, 0):
> >>> case IP_VERSION(9, 2, 1):
> >>> @@ -1034,7 +1034,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> return -EINVAL;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> case IP_VERSION(4, 0, 1):
> >>> case IP_VERSION(4, 1, 0):
> >>> @@ -1064,7 +1064,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> }
> >>>
> >>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 0):
> >>> case IP_VERSION(10, 0, 0):
> >>> case IP_VERSION(10, 0, 1):
> >>> @@ -1098,8 +1098,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> }
> >>> }
> >>>
> >>> - if (adev->ip_versions[VCE_HWIP]) {
> >>> - switch (adev->ip_versions[UVD_HWIP]) {
> >>> + if (adev->ip_versions[VCE_HWIP][0]) {
> >>> + switch (adev->ip_versions[UVD_HWIP][0]) {
> >>> case IP_VERSION(7, 0, 0):
> >>> case IP_VERSION(7, 2, 0):
> >>> amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
> >>> @@ -1107,7 +1107,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> default:
> >>> return -EINVAL;
> >>> }
> >>> - switch (adev->ip_versions[VCE_HWIP]) {
> >>> + switch (adev->ip_versions[VCE_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> case IP_VERSION(4, 1, 0):
> >>> amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
> >>> @@ -1116,7 +1116,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> return -EINVAL;
> >>> }
> >>> } else {
> >>> - switch (adev->ip_versions[UVD_HWIP]) {
> >>> + switch (adev->ip_versions[UVD_HWIP][0]) {
> >>> case IP_VERSION(1, 0, 0):
> >>> case IP_VERSION(1, 0, 1):
> >>> amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
> >>> @@ -1153,7 +1153,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
> >>> }
> >>>
> >>> if (adev->enable_mes) {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 1):
> >>> case IP_VERSION(10, 1, 2):
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> >>> index c47d29689be4..7d414f1606b9 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> >>> @@ -76,7 +76,7 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp
> >>> return;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[MP0_HWIP]) {
> >>> + switch (adev->ip_versions[MP0_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 4):
> >>> case IP_VERSION(11, 0, 7):
> >>> case IP_VERSION(11, 0, 9):
> >>> @@ -97,7 +97,7 @@ static int psp_early_init(void *handle)
> >>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>> struct psp_context *psp = &adev->psp;
> >>>
> >>> - switch (adev->ip_versions[MP0_HWIP]) {
> >>> + switch (adev->ip_versions[MP0_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 0):
> >>> psp_v3_1_set_psp_funcs(psp);
> >>> psp->autoload_supported = false;
> >>> @@ -279,7 +279,7 @@ static int psp_sw_init(void *handle)
> >>> return ret;
> >>> }
> >>> } else if (amdgpu_sriov_vf(adev) &&
> >>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2)) {
> >>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) {
> >>> ret = psp_init_ta_microcode(psp, "aldebaran");
> >>> if (ret) {
> >>> DRM_ERROR("Failed to initialize ta microcode!\n");
> >>> @@ -322,8 +322,8 @@ static int psp_sw_init(void *handle)
> >>> }
> >>> }
> >>>
> >>> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
> >>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7)) {
> >>> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
> >>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
> >>> ret= psp_sysfs_init(adev);
> >>> if (ret) {
> >>> return ret;
> >>> @@ -353,8 +353,8 @@ static int psp_sw_fini(void *handle)
> >>> psp->ta_fw = NULL;
> >>> }
> >>>
> >>> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
> >>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7))
> >>> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
> >>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
> >>> psp_sysfs_fini(adev);
> >>>
> >>> kfree(cmd);
> >>> @@ -613,7 +613,7 @@ static int psp_tmr_init(struct psp_context *psp)
> >>>
> >>> static bool psp_skip_tmr(struct psp_context *psp)
> >>> {
> >>> - switch (psp->adev->ip_versions[MP0_HWIP]) {
> >>> + switch (psp->adev->ip_versions[MP0_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 9):
> >>> case IP_VERSION(11, 0, 7):
> >>> case IP_VERSION(13, 0, 2):
> >>> @@ -1010,8 +1010,8 @@ int psp_xgmi_terminate(struct psp_context *psp)
> >>> struct amdgpu_device *adev = psp->adev;
> >>>
> >>> /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
> >>> - if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
> >>> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
> >>> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
> >>> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
> >>> adev->gmc.xgmi.connected_to_cpu))
> >>> return 0;
> >>>
> >>> @@ -1113,7 +1113,7 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
> >>>
> >>> static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
> >>> {
> >>> - return psp->adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
> >>> + return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
> >>> psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;
> >>> }
> >>>
> >>> @@ -2232,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp)
> >>>
> >>> if ((amdgpu_in_reset(adev) &&
> >>> ras && adev->ras_enabled &&
> >>> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
> >>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 2)))) {
> >>> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
> >>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
> >>> ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
> >>> if (ret) {
> >>> DRM_WARN("Failed to set MP1 state prepare for reload\n");
> >>> @@ -2330,9 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
> >>> continue;
> >>>
> >>> if (psp->autoload_supported &&
> >>> - (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7) ||
> >>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 11) ||
> >>> - adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 12)) &&
> >>> + (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
> >>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
> >>> + adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
> >>> (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
> >>> ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
> >>> ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
> >>> @@ -2920,7 +2920,7 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
> >>> le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
> >>>
> >>> if (adev->gmc.xgmi.connected_to_cpu ||
> >>> - (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2))) {
> >>> + (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
> >>> adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
> >>> adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> >>> index 9724f5f5f702..4d3f2386ef53 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> >>> @@ -86,7 +86,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> >>> for (i = 0; i < adev->vcn.num_vcn_inst; i++)
> >>> atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
> >>>
> >>> - switch (adev->ip_versions[UVD_HWIP]) {
> >>> + switch (adev->ip_versions[UVD_HWIP][0]) {
> >>> case IP_VERSION(1, 0, 0):
> >>> case IP_VERSION(1, 0, 1):
> >>> if (adev->apu_flags & AMD_APU_IS_RAVEN2)
> >>> @@ -134,7 +134,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> >>> adev->vcn.indirect_sram = true;
> >>> break;
> >>> case IP_VERSION(3, 0, 0):
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
> >>> fw_name = FIRMWARE_SIENNA_CICHLID;
> >>> else
> >>> fw_name = FIRMWARE_NAVY_FLOUNDER;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> >>> index d3f634eb40fb..ab6a07e5e8c4 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
> >>> @@ -77,7 +77,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[ATHUB_HWIP]) {
> >>> + switch (adev->ip_versions[ATHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 0, 0):
> >>> case IP_VERSION(2, 0, 2):
> >>> athub_v2_0_update_medium_grain_clock_gating(adev,
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> >>> index 0fbeaf05204e..2edefd10e56c 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
> >>> @@ -70,7 +70,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[ATHUB_HWIP]) {
> >>> + switch (adev->ip_versions[ATHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 1, 0):
> >>> case IP_VERSION(2, 1, 1):
> >>> case IP_VERSION(2, 1, 2):
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> index 4c632306ed70..71bb3c0dc1da 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> @@ -1537,7 +1537,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
> >>> scratch_reg3 = adev->rmmio +
> >>> (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> >>> spare_int = adev->rmmio +
> >>> (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
> >>> + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
> >>> @@ -3727,7 +3727,7 @@ static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
> >>>
> >>> static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> soc15_program_register_sequence(adev,
> >>> golden_settings_gc_rlc_spm_10_0_nv10,
> >>> @@ -3750,7 +3750,7 @@ static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
> >>>
> >>> static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> soc15_program_register_sequence(adev,
> >>> golden_settings_gc_10_1,
> >>> @@ -3985,7 +3985,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
> >>> {
> >>> adev->gfx.cp_fw_write_wait = false;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 2):
> >>> case IP_VERSION(10, 1, 1):
> >>> @@ -4066,7 +4066,7 @@ static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
> >>>
> >>> static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
> >>> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> >>> @@ -4093,7 +4093,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
> >>>
> >>> DRM_DEBUG("\n");
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> chip_name = "navi10";
> >>> break;
> >>> @@ -4684,7 +4684,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
> >>>
> >>> adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 1):
> >>> case IP_VERSION(10, 1, 2):
> >>> @@ -4818,7 +4818,7 @@ static int gfx_v10_0_sw_init(void *handle)
> >>> struct amdgpu_kiq *kiq;
> >>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 1):
> >>> case IP_VERSION(10, 1, 2):
> >>> @@ -5068,8 +5068,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
> >>> for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
> >>> for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
> >>> bitmap = i * adev->gfx.config.max_sh_per_se + j;
> >>> - if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
> >>> - (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
> >>> + if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
> >>> + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
> >>> ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
> >>> continue;
> >>> gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
> >>> @@ -5096,7 +5096,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
> >>>
> >>> /* for ASICs that integrates GFX v10.3
> >>> * pa_sc_tile_steering_override should be set to 0 */
> >>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> >>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> >>> return 0;
> >>>
> >>> /* init num_sc */
> >>> @@ -5249,7 +5249,7 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
> >>> /* TCCs are global (not instanced). */
> >>> uint32_t tcc_disable;
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> >>> tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
> >>> RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
> >>> } else {
> >>> @@ -5326,7 +5326,7 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
> >>> adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
> >>>
> >>> /* csib */
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> >>> WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
> >>> adev->gfx.rlc.clear_state_gpu_addr >> 32);
> >>> WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
> >>> @@ -5948,7 +5948,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
> >>> tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
> >>> tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> >>> WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
> >>> } else {
> >>> WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
> >>> @@ -6337,7 +6337,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
> >>> }
> >>> WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
> >>> }
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -6474,7 +6474,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
> >>> static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
> >>> {
> >>> if (enable) {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -6488,7 +6488,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
> >>> break;
> >>> }
> >>> } else {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -6586,7 +6586,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
> >>> struct amdgpu_device *adev = ring->adev;
> >>>
> >>> /* tell RLC which is KIQ queue */
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -7303,7 +7303,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
> >>>
> >>> /* check if mmVGT_ESGS_RING_SIZE_UMD
> >>> * has been remapped to mmVGT_ESGS_RING_SIZE */
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 4):
> >>> @@ -7350,7 +7350,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
> >>> * index will auto-inc after each data writting */
> >>> WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -7520,19 +7520,19 @@ static int gfx_v10_0_hw_init(void *handle)
> >>> * init golden registers and rlc resume may override some registers,
> >>> * reconfig them here
> >>> */
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 10) ||
> >>> - adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 1) ||
> >>> - adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2))
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
> >>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
> >>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
> >>> gfx_v10_0_tcp_harvest(adev);
> >>>
> >>> r = gfx_v10_0_cp_resume(adev);
> >>> if (r)
> >>> return r;
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
> >>> gfx_v10_3_program_pbb_mode(adev);
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> >>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> >>> gfx_v10_3_set_power_brake_sequence(adev);
> >>>
> >>> return r;
> >>> @@ -7584,7 +7584,7 @@ static int gfx_v10_0_hw_fini(void *handle)
> >>> if (amdgpu_sriov_vf(adev)) {
> >>> gfx_v10_0_cp_gfx_enable(adev, false);
> >>> /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
> >>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
> >>> tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
> >>> tmp &= 0xffffff00;
> >>> WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
> >>> @@ -7670,7 +7670,7 @@ static int gfx_v10_0_soft_reset(void *handle)
> >>>
> >>> /* GRBM_STATUS2 */
> >>> tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -7726,7 +7726,7 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> >>> {
> >>> uint64_t clock, clock_lo, clock_hi, hi_check;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 1):
> >>> case IP_VERSION(10, 3, 3):
> >>> clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
> >>> @@ -7784,7 +7784,7 @@ static int gfx_v10_0_early_init(void *handle)
> >>> {
> >>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 1):
> >>> case IP_VERSION(10, 1, 2):
> >>> @@ -7848,7 +7848,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
> >>> data = RLC_SAFE_MODE__CMD_MASK;
> >>> data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -7884,7 +7884,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
> >>> uint32_t data;
> >>>
> >>> data = RLC_SAFE_MODE__CMD_MASK;
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -8193,7 +8193,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d
> >>> mmCGTS_SA1_QUAD1_SM_CTRL_REG
> >>> };
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 1, 2)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
> >>> for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
> >>> reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
> >>> tcp_ctrl_regs_nv12[i];
> >>> @@ -8238,8 +8238,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> >>> /* === CGCG + CGLS === */
> >>> gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
> >>>
> >>> - if ((adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 1, 10)) &&
> >>> - (adev->ip_versions[GC_HWIP] <= IP_VERSION(10, 1, 2)))
> >>> + if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 1, 10)) &&
> >>> + (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(10, 1, 2)))
> >>> gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
> >>> } else {
> >>> /* CGCG/CGLS should be disabled before MGCG/MGLS
> >>> @@ -8335,7 +8335,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> >>> * Power/performance team will optimize it and might give a new value later.
> >>> */
> >>> if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 1):
> >>> data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
> >>> WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
> >>> @@ -8399,7 +8399,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 1):
> >>> case IP_VERSION(10, 1, 2):
> >>> @@ -8428,7 +8428,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 1):
> >>> case IP_VERSION(10, 1, 2):
> >>> @@ -9541,7 +9541,7 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
> >>>
> >>> static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 1):
> >>> case IP_VERSION(10, 1, 3):
> >>> @@ -9641,8 +9641,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
> >>> for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
> >>> for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
> >>> bitmap = i * adev->gfx.config.max_sh_per_se + j;
> >>> - if (((adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) ||
> >>> - (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3))) &&
> >>> + if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
> >>> + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
> >>> ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
> >>> continue;
> >>> mask = 1;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> index 3a160d78c98f..8f2966bcf5a4 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> @@ -953,7 +953,7 @@ static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
> >>>
> >>> static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> soc15_program_register_sequence(adev,
> >>> golden_settings_gc_9_0,
> >>> @@ -1009,8 +1009,8 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
> >>> break;
> >>> }
> >>>
> >>> - if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
> >>> - (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2)))
> >>> + if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
> >>> + (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)))
> >>> soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
> >>> (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
> >>> }
> >>> @@ -1194,14 +1194,14 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
> >>> adev->gfx.me_fw_write_wait = false;
> >>> adev->gfx.mec_fw_write_wait = false;
> >>>
> >>> - if ((adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) &&
> >>> + if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
> >>> ((adev->gfx.mec_fw_version < 0x000001a5) ||
> >>> (adev->gfx.mec_feature_version < 46) ||
> >>> (adev->gfx.pfp_fw_version < 0x000000b7) ||
> >>> (adev->gfx.pfp_feature_version < 46)))
> >>> DRM_WARN_ONCE("CP firmware version too old, please update!");
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> >>> (adev->gfx.me_feature_version >= 42) &&
> >>> @@ -1301,7 +1301,7 @@ static bool is_raven_kicker(struct amdgpu_device *adev)
> >>>
> >>> static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
> >>> {
> >>> - if ((adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0)) &&
> >>> + if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) &&
> >>> (adev->gfx.me_fw_version >= 0x000000a5) &&
> >>> (adev->gfx.me_feature_version >= 52))
> >>> return true;
> >>> @@ -1314,7 +1314,7 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
> >>> if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
> >>> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 2, 1):
> >>> case IP_VERSION(9, 4, 0):
> >>> @@ -1558,9 +1558,9 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
> >>>
> >>> static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)
> >>> {
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2) ||
> >>> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
> >>> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 3, 0))
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
> >>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
> >>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0))
> >>> return false;
> >>>
> >>> return true;
> >>> @@ -1668,7 +1668,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
> >>>
> >>> DRM_DEBUG("\n");
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> chip_name = "vega10";
> >>> break;
> >>> @@ -1800,7 +1800,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
> >>>
> >>> if (adev->flags & AMD_IS_APU)
> >>> always_on_cu_num = 4;
> >>> - else if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1))
> >>> + else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1))
> >>> always_on_cu_num = 8;
> >>> else
> >>> always_on_cu_num = 12;
> >>> @@ -1969,7 +1969,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
> >>> return r;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 2, 2):
> >>> case IP_VERSION(9, 1, 0):
> >>> gfx_v9_0_init_lbpw(adev);
> >>> @@ -2149,7 +2149,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
> >>>
> >>> adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> adev->gfx.config.max_hw_contexts = 8;
> >>> adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
> >>> @@ -2313,7 +2313,7 @@ static int gfx_v9_0_sw_init(void *handle)
> >>> struct amdgpu_kiq *kiq;
> >>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 2, 1):
> >>> case IP_VERSION(9, 4, 0):
> >>> @@ -2605,7 +2605,7 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
> >>> {
> >>> uint32_t tmp;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 4, 1):
> >>> tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
> >>> tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
> >>> @@ -2941,7 +2941,7 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
> >>> /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
> >>> data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
> >>> WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
> >>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 3, 0))
> >>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0))
> >>> pwr_10_0_gfxip_control_over_cgpg(adev, true);
> >>> }
> >>> }
> >>> @@ -3053,7 +3053,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
> >>> * And it's needed by gfxoff feature.
> >>> */
> >>> if (adev->gfx.rlc.is_rlc_v2_1) {
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 2, 1) ||
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) ||
> >>> (adev->apu_flags & AMD_APU_IS_RAVEN2))
> >>> gfx_v9_1_init_rlc_save_restore_list(adev);
> >>> gfx_v9_0_enable_save_restore_machine(adev);
> >>> @@ -3166,7 +3166,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
> >>> return r;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 2, 2):
> >>> case IP_VERSION(9, 1, 0):
> >>> if (amdgpu_lbpw == 0)
> >>> @@ -3969,8 +3969,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
> >>> {
> >>> u32 tmp;
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1) &&
> >>> - adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 2))
> >>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) &&
> >>> + adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))
> >>> return;
> >>>
> >>> tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
> >>> @@ -4010,7 +4010,7 @@ static int gfx_v9_0_hw_init(void *handle)
> >>> if (r)
> >>> return r;
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> >>> gfx_v9_4_2_set_power_brake_sequence(adev);
> >>>
> >>> return r;
> >>> @@ -4242,7 +4242,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> >>>
> >>> amdgpu_gfx_off_ctrl(adev, false);
> >>> mutex_lock(&adev->gfx.gpu_clock_mutex);
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
> >>> clock = gfx_v9_0_kiq_read_clock(adev);
> >>> } else {
> >>> WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
> >>> @@ -4592,7 +4592,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
> >>> if (!ring->sched.ready)
> >>> return 0;
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
> >>> vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
> >>> vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
> >>> vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
> >>> @@ -4742,8 +4742,8 @@ static int gfx_v9_0_early_init(void *handle)
> >>> {
> >>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1) ||
> >>> - adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
> >>> + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> >>> adev->gfx.num_gfx_rings = 0;
> >>> else
> >>> adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
> >>> @@ -4777,7 +4777,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
> >>> }
> >>>
> >>> /* requires IBs so do in late init after IB pool is initialized */
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 2))
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> >>> r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
> >>> else
> >>> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
> >>> @@ -4905,7 +4905,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
> >>> /* 1 - RLC_CGTT_MGCG_OVERRIDE */
> >>> def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
> >>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
> >>> data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
> >>>
> >>> data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
> >>> @@ -4939,7 +4939,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
> >>> /* 1 - MGCG_OVERRIDE */
> >>> def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 2, 1))
> >>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
> >>> data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
> >>>
> >>> data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
> >>> @@ -5045,7 +5045,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
> >>> /* enable cgcg FSM(0x0000363F) */
> >>> def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(9, 4, 1))
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1))
> >>> data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> >>> RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> >>> else
> >>> @@ -5171,7 +5171,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
> >>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>> bool enable = (state == AMD_PG_STATE_GATE);
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 2, 2):
> >>> case IP_VERSION(9, 1, 0):
> >>> case IP_VERSION(9, 3, 0):
> >>> @@ -5218,7 +5218,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 2, 1):
> >>> case IP_VERSION(9, 4, 0):
> >>> @@ -5268,7 +5268,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
> >>> if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
> >>> *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] != IP_VERSION(9, 4, 1)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) {
> >>> /* AMD_CG_SUPPORT_GFX_3D_CGCG */
> >>> data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
> >>> if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
> >>> @@ -7039,7 +7039,7 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
> >>>
> >>> static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 2, 1):
> >>> case IP_VERSION(9, 4, 0):
> >>> @@ -7058,7 +7058,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
> >>> static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
> >>> {
> >>> /* init asci gds info */
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 2, 1):
> >>> case IP_VERSION(9, 4, 0):
> >>> @@ -7080,7 +7080,7 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
> >>> break;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> case IP_VERSION(9, 4, 0):
> >>> adev->gds.gds_compute_max_wave_id = 0x7ff;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> >>> index 149f3843e0e7..e80d1dc43079 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> >>> @@ -506,7 +506,7 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
> >>> u32 max_num_physical_nodes = 0;
> >>> u32 max_physical_node_id = 0;
> >>>
> >>> - switch (adev->ip_versions[XGMI_HWIP]) {
> >>> + switch (adev->ip_versions[XGMI_HWIP][0]) {
> >>> case IP_VERSION(4, 8, 0):
> >>> max_num_physical_nodes = 4;
> >>> max_physical_node_id = 3;
> >>> @@ -544,7 +544,7 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
> >>> adev->gfx.config.max_sh_per_se *
> >>> adev->gfx.config.max_shader_engines);
> >>>
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 3)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) {
> >>> /* Get SA disabled bitmap from eFuse setting */
> >>> efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
> >>> efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> >>> index b488257ff201..6d0586009de3 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> >>> @@ -133,7 +133,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
> >>> * the new fast GRBM interface.
> >>> */
> >>> if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
> >>> - (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
> >>> + (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
> >>> RREG32(hub->vm_l2_pro_fault_status);
> >>>
> >>> status = RREG32(hub->vm_l2_pro_fault_status);
> >>> @@ -268,7 +268,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
> >>> * to avoid a false ACK due to the new fast GRBM interface.
> >>> */
> >>> if ((vmhub == AMDGPU_GFXHUB_0) &&
> >>> - (adev->ip_versions[GC_HWIP] < IP_VERSION(10, 3, 0)))
> >>> + (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
> >>> RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
> >>> hub->eng_distance * eng, hub_ip);
> >>>
> >>> @@ -657,7 +657,7 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
> >>>
> >>> static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[UMC_HWIP]) {
> >>> + switch (adev->ip_versions[UMC_HWIP][0]) {
> >>> case IP_VERSION(8, 7, 0):
> >>> adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
> >>> adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
> >>> @@ -674,7 +674,7 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
> >>>
> >>> static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 3, 0):
> >>> case IP_VERSION(2, 4, 0):
> >>> adev->mmhub.funcs = &mmhub_v2_3_funcs;
> >>> @@ -687,7 +687,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
> >>>
> >>> static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 3, 0):
> >>> case IP_VERSION(10, 3, 2):
> >>> case IP_VERSION(10, 3, 1):
> >>> @@ -857,7 +857,7 @@ static int gmc_v10_0_sw_init(void *handle)
> >>> adev->gmc.vram_vendor = vram_vendor;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> case IP_VERSION(10, 1, 1):
> >>> case IP_VERSION(10, 1, 2):
> >>> @@ -1132,7 +1132,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
> >>> if (r)
> >>> return r;
> >>>
> >>> - if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
> >>> + if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
> >>> return athub_v2_1_set_clockgating(adev, state);
> >>> else
> >>> return athub_v2_0_set_clockgating(adev, state);
> >>> @@ -1144,7 +1144,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
> >>>
> >>> adev->mmhub.funcs->get_clockgating(adev, flags);
> >>>
> >>> - if (adev->ip_versions[ATHUB_HWIP] >= IP_VERSION(2, 1, 0))
> >>> + if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
> >>> athub_v2_1_get_clockgating(adev, flags);
> >>> else
> >>> athub_v2_0_get_clockgating(adev, flags);
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> >>> index 88938115557b..eecfb1545c1e 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
> >>> @@ -49,7 +49,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
> >>> static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
> >>> struct amdgpu_ring *ring)
> >>> {
> >>> - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 4, 0))
> >>> + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
> >>> return;
> >>>
> >>> if (!ring || !ring->funcs->emit_wreg)
> >>> @@ -79,7 +79,7 @@ static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
> >>> if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
> >>> return;
> >>>
> >>> - if (adev->ip_versions[HDP_HWIP] >= IP_VERSION(4, 4, 0))
> >>> + if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
> >>> WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
> >>> else
> >>> /*read back hdp ras counter to reset it to 0 */
> >>> @@ -91,10 +91,10 @@ static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
> >>> {
> >>> uint32_t def, data;
> >>>
> >>> - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 0) ||
> >>> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 1) ||
> >>> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 1) ||
> >>> - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 0)) {
> >>> + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
> >>> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
> >>> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
> >>> + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
> >>> def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
> >>>
> >>> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
> >>> @@ -136,7 +136,7 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
> >>>
> >>> static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[HDP_HWIP]) {
> >>> + switch (adev->ip_versions[HDP_HWIP][0]) {
> >>> case IP_VERSION(4, 2, 1):
> >>> WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
> >>> break;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> >>> index e0cb919b4814..25f8e93e5ec3 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> >>> @@ -153,7 +153,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
> >>> dev_err(adev->dev,
> >>> "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> >>> status);
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 0, 0):
> >>> case IP_VERSION(2, 0, 2):
> >>> mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
> >>> @@ -569,7 +569,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
> >>> if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
> >>> return;
> >>>
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 1, 0):
> >>> case IP_VERSION(2, 1, 1):
> >>> case IP_VERSION(2, 1, 2):
> >>> @@ -603,7 +603,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
> >>> DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
> >>> }
> >>>
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 1, 0):
> >>> case IP_VERSION(2, 1, 1):
> >>> case IP_VERSION(2, 1, 2):
> >>> @@ -629,7 +629,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
> >>> if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
> >>> return;
> >>>
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 1, 0):
> >>> case IP_VERSION(2, 1, 1):
> >>> case IP_VERSION(2, 1, 2):
> >>> @@ -646,7 +646,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
> >>> data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
> >>>
> >>> if (def != data) {
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 1, 0):
> >>> case IP_VERSION(2, 1, 1):
> >>> case IP_VERSION(2, 1, 2):
> >>> @@ -665,7 +665,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 0, 0):
> >>> case IP_VERSION(2, 0, 2):
> >>> case IP_VERSION(2, 1, 0):
> >>> @@ -690,7 +690,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
> >>> if (amdgpu_sriov_vf(adev))
> >>> *flags = 0;
> >>>
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 1, 0):
> >>> case IP_VERSION(2, 1, 1):
> >>> case IP_VERSION(2, 1, 2):
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> >>> index 4cf5d0595bbe..a11d60ec6321 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> >>> @@ -90,7 +90,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
> >>> dev_err(adev->dev,
> >>> "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> >>> status);
> >>> - switch (adev->ip_versions[MMHUB_HWIP]) {
> >>> + switch (adev->ip_versions[MMHUB_HWIP][0]) {
> >>> case IP_VERSION(2, 3, 0):
> >>> case IP_VERSION(2, 4, 0):
> >>> mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >>> index c3f968d9cfcb..1d8414c3fadb 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >>> @@ -107,7 +107,7 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
> >>> {
> >>> u32 ih_cntl, ih_rb_cntl;
> >>>
> >>> - if (adev->ip_versions[OSSSYS_HWIP] < IP_VERSION(5, 0, 3))
> >>> + if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3))
> >>> return;
> >>>
> >>> ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
> >>> @@ -332,7 +332,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
> >>>
> >>> if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
> >>> if (ih[0]->use_bus_addr) {
> >>> - switch (adev->ip_versions[OSSSYS_HWIP]) {
> >>> + switch (adev->ip_versions[OSSSYS_HWIP][0]) {
> >>> case IP_VERSION(5, 0, 3):
> >>> case IP_VERSION(5, 2, 0):
> >>> case IP_VERSION(5, 2, 1):
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> >>> index 57be517d70bf..89e32d6e2c10 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> >>> @@ -180,7 +180,7 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
> >>> static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
> >>> const struct amdgpu_video_codecs **codecs)
> >>> {
> >>> - switch (adev->ip_versions[UVD_HWIP]) {
> >>> + switch (adev->ip_versions[UVD_HWIP][0]) {
> >>> case IP_VERSION(3, 0, 0):
> >>> if (amdgpu_sriov_vf(adev)) {
> >>> if (encode)
> >>> @@ -509,7 +509,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
> >>> dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
> >>> amdgpu_reset_method);
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 5, 0):
> >>> case IP_VERSION(13, 0, 1):
> >>> case IP_VERSION(13, 0, 3):
> >>> @@ -1044,7 +1044,7 @@ static int nv_common_early_init(void *handle)
> >>> /* TODO: split the GC and PG flags based on the relevant IP version for which
> >>> * they are relevant.
> >>> */
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(10, 1, 10):
> >>> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> >>> AMD_CG_SUPPORT_GFX_CGCG |
> >>> @@ -1375,7 +1375,7 @@ static int nv_common_set_clockgating_state(void *handle,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[NBIO_HWIP]) {
> >>> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> >>> case IP_VERSION(2, 3, 0):
> >>> case IP_VERSION(2, 3, 1):
> >>> case IP_VERSION(2, 3, 2):
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> >>> index 13dace5d2855..382cebfc2069 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> >>> @@ -93,7 +93,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> >>>
> >>> DRM_DEBUG("\n");
> >>>
> >>> - switch (adev->ip_versions[MP0_HWIP]) {
> >>> + switch (adev->ip_versions[MP0_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 2):
> >>> chip_name = "vega20";
> >>> break;
> >>> @@ -129,7 +129,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
> >>> }
> >>>
> >>>
> >>> - switch (adev->ip_versions[MP0_HWIP]) {
> >>> + switch (adev->ip_versions[MP0_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 2):
> >>> case IP_VERSION(11, 0, 4):
> >>> err = psp_init_sos_microcode(psp, chip_name);
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> >>> index 64b52c5ea981..17655bc6d2f1 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
> >>> @@ -47,7 +47,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
> >>> const char *chip_name;
> >>> int err = 0;
> >>>
> >>> - switch (adev->ip_versions[MP0_HWIP]) {
> >>> + switch (adev->ip_versions[MP0_HWIP][0]) {
> >>> case IP_VERSION(13, 0, 2):
> >>> chip_name = "aldebaran";
> >>> break;
> >>> @@ -58,7 +58,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
> >>> default:
> >>> BUG();
> >>> }
> >>> - switch (adev->ip_versions[MP0_HWIP]) {
> >>> + switch (adev->ip_versions[MP0_HWIP][0]) {
> >>> case IP_VERSION(13, 0, 2):
> >>> err = psp_init_sos_microcode(psp, chip_name);
> >>> if (err)
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >>> index cb74f8c35d0a..e8e4749e9c79 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >>> @@ -469,7 +469,7 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
> >>>
> >>> static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> soc15_program_register_sequence(adev,
> >>> golden_settings_sdma_4,
> >>> @@ -539,7 +539,7 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
> >>> * The only chips with SDMAv4 and ULV are VG10 and VG20.
> >>> * Server SKUs take a different hysteresis setting from other SKUs.
> >>> */
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> if (adev->pdev->device == 0x6860)
> >>> break;
> >>> @@ -590,8 +590,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
> >>>
> >>> /* arcturus shares the same FW memory across
> >>> all SDMA isntances */
> >>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
> >>> - adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0))
> >>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
> >>> + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
> >>> break;
> >>> }
> >>>
> >>> @@ -621,7 +621,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
> >>>
> >>> DRM_DEBUG("\n");
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> chip_name = "vega10";
> >>> break;
> >>> @@ -667,8 +667,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
> >>> goto out;
> >>>
> >>> for (i = 1; i < adev->sdma.num_instances; i++) {
> >>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
> >>> - adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0)) {
> >>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
> >>> + adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
> >>> /* Acturus & Aldebaran will leverage the same FW memory
> >>> for every SDMA instance */
> >>> memcpy((void *)&adev->sdma.instance[i],
> >>> @@ -1108,7 +1108,7 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
> >>> * Arcturus for the moment and firmware version 14
> >>> * and above.
> >>> */
> >>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) &&
> >>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) &&
> >>> adev->sdma.instance[i].fw_version >= 14)
> >>> WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
> >>> /* Extend page fault timeout to avoid interrupt storm */
> >>> @@ -1395,7 +1395,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
> >>> if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
> >>> return;
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(4, 1, 0):
> >>> case IP_VERSION(4, 1, 1):
> >>> case IP_VERSION(4, 1, 2):
> >>> @@ -1838,7 +1838,7 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
> >>> {
> >>> uint fw_version = adev->sdma.instance[0].fw_version;
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> return fw_version >= 430;
> >>> case IP_VERSION(4, 0, 1):
> >>> @@ -1863,7 +1863,7 @@ static int sdma_v4_0_early_init(void *handle)
> >>> }
> >>>
> >>> /* TODO: Page queue breaks driver reload under SRIOV */
> >>> - if ((adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 0, 0)) &&
> >>> + if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) &&
> >>> amdgpu_sriov_vf((adev)))
> >>> adev->sdma.has_page_queue = false;
> >>> else if (sdma_v4_0_fw_support_paging_queue(adev))
> >>> @@ -2136,14 +2136,14 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
> >>> amdgpu_fence_process(&adev->sdma.instance[instance].ring);
> >>> break;
> >>> case 1:
> >>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 0))
> >>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0))
> >>> amdgpu_fence_process(&adev->sdma.instance[instance].page);
> >>> break;
> >>> case 2:
> >>> /* XXX compute */
> >>> break;
> >>> case 3:
> >>> - if (adev->ip_versions[SDMA0_HWIP] != IP_VERSION(4, 2, 0))
> >>> + if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0))
> >>> amdgpu_fence_process(&adev->sdma.instance[instance].page);
> >>> break;
> >>> }
> >>> @@ -2359,7 +2359,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
> >>> {
> >>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(4, 1, 0):
> >>> case IP_VERSION(4, 1, 1):
> >>> case IP_VERSION(4, 1, 2):
> >>> @@ -2547,7 +2547,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> >>> int i;
> >>>
> >>> for (i = 0; i < adev->sdma.num_instances; i++) {
> >>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
> >>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
> >>> adev->sdma.instance[i].ring.funcs =
> >>> &sdma_v4_0_ring_funcs_2nd_mmhub;
> >>> else
> >>> @@ -2555,7 +2555,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> >>> &sdma_v4_0_ring_funcs;
> >>> adev->sdma.instance[i].ring.me = i;
> >>> if (adev->sdma.has_page_queue) {
> >>> - if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
> >>> + if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
> >>> adev->sdma.instance[i].page.funcs =
> >>> &sdma_v4_0_page_ring_funcs_2nd_mmhub;
> >>> else
> >>> @@ -2782,7 +2782,7 @@ static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
> >>>
> >>> static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(4, 2, 0):
> >>> case IP_VERSION(4, 2, 2):
> >>> adev->sdma.funcs = &sdma_v4_0_ras_funcs;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> >>> index d3b01d2977c0..853d1511b889 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> >>> @@ -187,7 +187,7 @@ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
> >>>
> >>> static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(5, 0, 0):
> >>> soc15_program_register_sequence(adev,
> >>> golden_settings_sdma_5,
> >>> @@ -248,12 +248,12 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
> >>> const struct common_firmware_header *header = NULL;
> >>> const struct sdma_firmware_header_v1_0 *hdr;
> >>>
> >>> - if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 0, 5)))
> >>> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
> >>> return 0;
> >>>
> >>> DRM_DEBUG("\n");
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(5, 0, 0):
> >>> chip_name = "navi10";
> >>> break;
> >>> @@ -1634,7 +1634,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(5, 0, 0):
> >>> case IP_VERSION(5, 0, 2):
> >>> case IP_VERSION(5, 0, 5):
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> >>> index 92f29beda3b2..0fec1d9dd638 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> >>> @@ -136,7 +136,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
> >>>
> >>> DRM_DEBUG("\n");
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(5, 2, 0):
> >>> chip_name = "sienna_cichlid";
> >>> break;
> >>> @@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
> >>> (void *)&adev->sdma.instance[0],
> >>> sizeof(struct amdgpu_sdma_instance));
> >>>
> >>> - if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 0)))
> >>> + if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
> >>> return 0;
> >>>
> >>> DRM_DEBUG("psp_load == '%s'\n",
> >>> @@ -1530,7 +1530,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
> >>>
> >>> for (i = 0; i < adev->sdma.num_instances; i++) {
> >>>
> >>> - if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> >>> + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
> >>> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
> >>>
> >>> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
> >>> @@ -1567,7 +1567,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
> >>>
> >>> for (i = 0; i < adev->sdma.num_instances; i++) {
> >>>
> >>> - if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
> >>> + if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
> >>> adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
> >>>
> >>> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
> >>> @@ -1596,7 +1596,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[SDMA0_HWIP]) {
> >>> + switch (adev->ip_versions[SDMA0_HWIP][0]) {
> >>> case IP_VERSION(5, 2, 0):
> >>> case IP_VERSION(5, 2, 2):
> >>> case IP_VERSION(5, 2, 1):
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> >>> index 7f4cd1a4f6cb..74310bb4216a 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> >>> @@ -156,8 +156,8 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
> >>> static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
> >>> const struct amdgpu_video_codecs **codecs)
> >>> {
> >>> - if (adev->ip_versions[VCE_HWIP]) {
> >>> - switch (adev->ip_versions[VCE_HWIP]) {
> >>> + if (adev->ip_versions[VCE_HWIP][0]) {
> >>> + switch (adev->ip_versions[VCE_HWIP][0]) {
> >>> case IP_VERSION(4, 0, 0):
> >>> case IP_VERSION(4, 1, 0):
> >>> if (encode)
> >>> @@ -169,7 +169,7 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
> >>> return -EINVAL;
> >>> }
> >>> } else {
> >>> - switch (adev->ip_versions[UVD_HWIP]) {
> >>> + switch (adev->ip_versions[UVD_HWIP][0]) {
> >>> case IP_VERSION(1, 0, 0):
> >>> case IP_VERSION(1, 0, 1):
> >>> if (encode)
> >>> @@ -341,11 +341,11 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
> >>> {
> >>> u32 reference_clock = adev->clock.spll.reference_freq;
> >>>
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
> >>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
> >>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
> >>> return 10000;
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
> >>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
> >>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
> >>> return reference_clock / 4;
> >>>
> >>> return reference_clock;
> >>> @@ -576,7 +576,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
> >>> dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
> >>> amdgpu_reset_method);
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(10, 0, 0):
> >>> case IP_VERSION(10, 0, 1):
> >>> case IP_VERSION(12, 0, 0):
> >>> @@ -641,7 +641,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
> >>>
> >>> static bool soc15_supports_baco(struct amdgpu_device *adev)
> >>> {
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 0):
> >>> case IP_VERSION(11, 0, 2):
> >>> if (adev->asic_type == CHIP_VEGA20) {
> >>> @@ -1172,7 +1172,7 @@ static int soc15_common_early_init(void *handle)
> >>> /* TODO: split the GC and PG flags based on the relevant IP version for which
> >>> * they are relevant.
> >>> */
> >>> - switch (adev->ip_versions[GC_HWIP]) {
> >>> + switch (adev->ip_versions[GC_HWIP][0]) {
> >>> case IP_VERSION(9, 0, 1):
> >>> adev->asic_funcs = &soc15_asic_funcs;
> >>> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> >>> @@ -1583,7 +1583,7 @@ static int soc15_common_set_clockgating_state(void *handle,
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[NBIO_HWIP]) {
> >>> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> >>> case IP_VERSION(6, 1, 0):
> >>> case IP_VERSION(6, 2, 0):
> >>> case IP_VERSION(7, 4, 0):
> >>> @@ -1639,7 +1639,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
> >>>
> >>> adev->hdp.funcs->get_clock_gating_state(adev, flags);
> >>>
> >>> - if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
> >>> + if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
> >>>
> >>> /* AMD_CG_SUPPORT_DRM_MGCG */
> >>> data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> >>> index e9758969fbe6..f4a7a30ecebd 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> >>> @@ -1720,7 +1720,7 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
> >>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> >>> if (adev->vcn.harvest_config & (1 << i))
> >>> continue;
> >>> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
> >>> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
> >>> adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
> >>> else /* CHIP_ALDEBARAN */
> >>> adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
> >>> @@ -1737,7 +1737,7 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
> >>> if (adev->vcn.harvest_config & (1 << j))
> >>> continue;
> >>> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> >>> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(2, 5, 0))
> >>> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
> >>> adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
> >>> else /* CHIP_ALDEBARAN */
> >>> adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> >>> index a81d834ea0d3..6940716db1df 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> >>> @@ -95,7 +95,7 @@ static int vcn_v3_0_early_init(void *handle)
> >>> adev->vcn.num_enc_rings = 1;
> >>>
> >>> } else {
> >>> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
> >>> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 0)) {
> >>> u32 harvest;
> >>>
> >>> for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> >>> @@ -110,7 +110,7 @@ static int vcn_v3_0_early_init(void *handle)
> >>> return -ENOENT;
> >>> }
> >>>
> >>> - if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
> >>> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33))
> >>> adev->vcn.num_enc_rings = 0;
> >>> else
> >>> adev->vcn.num_enc_rings = 2;
> >>> @@ -1270,7 +1270,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
> >>> fw_shared->rb.wptr = lower_32_bits(ring->wptr);
> >>> fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
> >>>
> >>> - if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
> >>> + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
> >>> fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
> >>> ring = &adev->vcn.inst[i].ring_enc[0];
> >>> WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
> >>> @@ -1642,7 +1642,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
> >>> UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
> >>> ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
> >>>
> >>> - if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
> >>> + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
> >>> /* Restore */
> >>> fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
> >>> fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
> >>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>> index fc8a30251fa4..fb89ce4dd28c 100644
> >>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>> @@ -1344,7 +1344,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> >>> init_data.flags.gpu_vm_support = true;
> >>> break;
> >>> default:
> >>> - switch (adev->ip_versions[DCE_HWIP]) {
> >>> + switch (adev->ip_versions[DCE_HWIP][0]) {
> >>> case IP_VERSION(2, 1, 0):
> >>> init_data.flags.gpu_vm_support = true;
> >>> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> >>> @@ -1658,7 +1658,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
> >>> return 0;
> >>> break;
> >>> default:
> >>> - switch (adev->ip_versions[DCE_HWIP]) {
> >>> + switch (adev->ip_versions[DCE_HWIP][0]) {
> >>> case IP_VERSION(2, 0, 2):
> >>> case IP_VERSION(2, 0, 0):
> >>> case IP_VERSION(2, 1, 0):
> >>> @@ -1750,7 +1750,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
> >>> enum dmub_status status;
> >>> int r;
> >>>
> >>> - switch (adev->ip_versions[DCE_HWIP]) {
> >>> + switch (adev->ip_versions[DCE_HWIP][0]) {
> >>> case IP_VERSION(2, 1, 0):
> >>> dmub_asic = DMUB_ASIC_DCN21;
> >>> fw_name_dmub = FIRMWARE_RENOIR_DMUB;
> >>> @@ -1758,7 +1758,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
> >>> fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
> >>> break;
> >>> case IP_VERSION(3, 0, 0):
> >>> - if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
> >>> + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
> >>> dmub_asic = DMUB_ASIC_DCN30;
> >>> fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
> >>> } else {
> >>> @@ -2078,7 +2078,7 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
> >>> * therefore, this function apply to navi10/12/14 but not Renoir
> >>> * *
> >>> */
> >>> - switch (adev->ip_versions[DCE_HWIP]) {
> >>> + switch (adev->ip_versions[DCE_HWIP][0]) {
> >>> case IP_VERSION(2, 0, 2):
> >>> case IP_VERSION(2, 0, 0):
> >>> break;
> >>> @@ -4086,7 +4086,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> >>>
> >>> #if defined(CONFIG_DRM_AMD_DC_DCN)
> >>> /* Use Outbox interrupt */
> >>> - switch (adev->ip_versions[DCE_HWIP]) {
> >>> + switch (adev->ip_versions[DCE_HWIP][0]) {
> >>> case IP_VERSION(3, 0, 0):
> >>> case IP_VERSION(3, 1, 2):
> >>> case IP_VERSION(3, 1, 3):
> >>> @@ -4098,7 +4098,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> >>> break;
> >>> default:
> >>> DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
> >>> - adev->ip_versions[DCE_HWIP]);
> >>> + adev->ip_versions[DCE_HWIP][0]);
> >>> }
> >>> #endif
> >>>
> >>> @@ -4186,7 +4186,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> >>> break;
> >>> default:
> >>> #if defined(CONFIG_DRM_AMD_DC_DCN)
> >>> - switch (adev->ip_versions[DCE_HWIP]) {
> >>> + switch (adev->ip_versions[DCE_HWIP][0]) {
> >>> case IP_VERSION(1, 0, 0):
> >>> case IP_VERSION(1, 0, 1):
> >>> case IP_VERSION(2, 0, 2):
> >>> @@ -4205,7 +4205,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
> >>> break;
> >>> default:
> >>> DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
> >>> - adev->ip_versions[DCE_HWIP]);
> >>> + adev->ip_versions[DCE_HWIP][0]);
> >>> goto fail;
> >>> }
> >>> #endif
> >>> @@ -4357,7 +4357,7 @@ static int dm_early_init(void *handle)
> >>> break;
> >>> default:
> >>> #if defined(CONFIG_DRM_AMD_DC_DCN)
> >>> - switch (adev->ip_versions[DCE_HWIP]) {
> >>> + switch (adev->ip_versions[DCE_HWIP][0]) {
> >>> case IP_VERSION(2, 0, 2):
> >>> case IP_VERSION(3, 0, 0):
> >>> adev->mode_info.num_crtc = 6;
> >>> @@ -4387,7 +4387,7 @@ static int dm_early_init(void *handle)
> >>> break;
> >>> default:
> >>> DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
> >>> - adev->ip_versions[DCE_HWIP]);
> >>> + adev->ip_versions[DCE_HWIP][0]);
> >>> return -EINVAL;
> >>> }
> >>> #endif
> >>> @@ -4609,7 +4609,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
> >>> tiling_info->gfx9.num_rb_per_se =
> >>> adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
> >>> tiling_info->gfx9.shaderEnable = 1;
> >>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> >>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> >>> tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
> >>> }
> >>>
> >>> @@ -5050,7 +5050,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
> >>> case AMDGPU_FAMILY_NV:
> >>> case AMDGPU_FAMILY_VGH:
> >>> case AMDGPU_FAMILY_YC:
> >>> - if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
> >>> + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
> >>> add_gfx10_3_modifiers(adev, mods, &size, &capacity);
> >>> else
> >>> add_gfx10_1_modifiers(adev, mods, &size, &capacity);
> >>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>> index 150cac4ea75c..9c601997a96a 100644
> >>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>> @@ -455,7 +455,7 @@ static int smu_get_power_num_states(void *handle,
> >>>
> >>> bool is_support_sw_smu(struct amdgpu_device *adev)
> >>> {
> >>> - if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
> >>> + if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
> >>> return true;
> >>>
> >>> return false;
> >>> @@ -575,7 +575,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> >>> if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
> >>> smu->od_enabled = true;
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 0):
> >>> case IP_VERSION(11, 0, 5):
> >>> case IP_VERSION(11, 0, 9):
> >>> @@ -694,7 +694,7 @@ static int smu_late_init(void *handle)
> >>> return ret;
> >>> }
> >>>
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1))
> >>> return 0;
> >>>
> >>> if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
> >>> @@ -1140,10 +1140,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
> >>> if (adev->in_suspend && smu_is_dpm_running(smu)) {
> >>> dev_info(adev->dev, "dpm has been enabled\n");
> >>> /* this is needed specifically */
> >>> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)))
> >>> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)))
> >>> ret = smu_system_features_control(smu, true);
> >>> return ret;
> >>> }
> >>> @@ -1286,7 +1286,7 @@ static int smu_start_smc_engine(struct smu_context *smu)
> >>> int ret = 0;
> >>>
> >>> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> >>> - if (adev->ip_versions[MP1_HWIP] < IP_VERSION(11, 0, 0)) {
> >>> + if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
> >>> if (smu->ppt_funcs->load_microcode) {
> >>> ret = smu->ppt_funcs->load_microcode(smu);
> >>> if (ret)
> >>> @@ -1405,14 +1405,14 @@ static int smu_disable_dpms(struct smu_context *smu)
> >>> * properly.
> >>> */
> >>> if (smu->uploading_custom_pp_table &&
> >>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))))
> >>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))))
> >>> return smu_disable_all_features_with_exception(smu,
> >>> true,
> >>> SMU_FEATURE_COUNT);
> >>> @@ -1421,10 +1421,10 @@ static int smu_disable_dpms(struct smu_context *smu)
> >>> * For Sienna_Cichlid, PMFW will handle the features disablement properly
> >>> * on BACO in. Driver involvement is unnecessary.
> >>> */
> >>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))) &&
> >>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))) &&
> >>> use_baco)
> >>> return smu_disable_all_features_with_exception(smu,
> >>> true,
> >>> @@ -1446,7 +1446,7 @@ static int smu_disable_dpms(struct smu_context *smu)
> >>> dev_err(adev->dev, "Failed to disable smu features.\n");
> >>> }
> >>>
> >>> - if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0) &&
> >>> + if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0) &&
> >>> adev->gfx.rlc.funcs->stop)
> >>> adev->gfx.rlc.funcs->stop(adev);
> >>>
> >>> @@ -2283,11 +2283,11 @@ int smu_get_power_limit(void *handle,
> >>> } else {
> >>> switch (limit_level) {
> >>> case SMU_PPT_LIMIT_CURRENT:
> >>> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 2)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 12)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)))
> >>> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)))
> >>> ret = smu_get_asic_power_limits(smu,
> >>> &smu->current_power_limit,
> >>> NULL,
> >>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>> index d96f904a765b..71161f6b78fe 100644
> >>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>> @@ -345,7 +345,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> >>>
> >>> /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> >>> if (!(is_asic_secure(smu) &&
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
> >>> (adev->rev_id == 0)) &&
> >>> (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >>> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >>> @@ -354,7 +354,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> >>>
> >>> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> >>> if (is_asic_secure(smu) &&
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) &&
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) &&
> >>> (adev->rev_id == 0))
> >>> *(uint64_t *)feature_mask &=
> >>> ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
> >>> @@ -925,7 +925,7 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
> >>> return ret;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 9):
> >>> if (smu_version > 0x00341C00)
> >>> ret = navi12_get_smu_metrics_data(smu, member, value);
> >>> @@ -935,8 +935,8 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu,
> >>> case IP_VERSION(11, 0, 0):
> >>> case IP_VERSION(11, 0, 5):
> >>> default:
> >>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> >>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> >>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> >>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> >>> ret = navi10_get_smu_metrics_data(smu, member, value);
> >>> else
> >>> ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
> >>> @@ -1509,7 +1509,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
> >>> uint32_t sclk_freq;
> >>>
> >>> pstate_table->gfxclk_pstate.min = gfx_table->min;
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 0):
> >>> switch (adev->pdev->revision) {
> >>> case 0xf0: /* XTX */
> >>> @@ -2562,8 +2562,8 @@ static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
> >>> if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
> >>> return false;
> >>>
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0) ||
> >>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5))
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) ||
> >>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5))
> >>> return true;
> >>>
> >>> return false;
> >>> @@ -2671,8 +2671,8 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
> >>> * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
> >>> * - PPSMC_MSG_GetUMCFWWA
> >>> */
> >>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
> >>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
> >>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) ||
> >>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) {
> >>> ret = smu_cmn_send_smc_msg_with_param(smu,
> >>> SMU_MSG_GET_UMC_FW_WA,
> >>> 0,
> >>> @@ -2691,13 +2691,13 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
> >>> return 0;
> >>>
> >>> if (umc_fw_disable_cdr) {
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
> >>> return navi10_umc_hybrid_cdr_workaround(smu);
> >>> } else {
> >>> return navi10_set_dummy_pstates_table_location(smu);
> >>> }
> >>> } else {
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0))
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0))
> >>> return navi10_umc_hybrid_cdr_workaround(smu);
> >>> }
> >>>
> >>> @@ -3151,7 +3151,7 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
> >>> return ret;
> >>> }
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 9):
> >>> if (smu_version > 0x00341C00)
> >>> ret = navi12_get_gpu_metrics(smu, table);
> >>> @@ -3161,8 +3161,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
> >>> case IP_VERSION(11, 0, 0):
> >>> case IP_VERSION(11, 0, 5):
> >>> default:
> >>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> >>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> >>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) ||
> >>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00))
> >>> ret = navi10_get_gpu_metrics(smu, table);
> >>> else
> >>> ret =navi10_get_legacy_gpu_metrics(smu, table);
> >>> @@ -3180,7 +3180,7 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> >>> uint32_t param = 0;
> >>>
> >>> /* Navi12 does not support this */
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9))
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9))
> >>> return 0;
> >>>
> >>> /*
> >>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> >>> index 6a0fed5e33d9..15e66e1912de 100644
> >>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> >>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> >>> @@ -74,7 +74,7 @@
> >>> #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
> >>>
> >>> #define GET_PPTABLE_MEMBER(field, member) do {\
> >>> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))\
> >>> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
> >>> (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
> >>> else\
> >>> (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
> >>> @@ -82,7 +82,7 @@
> >>>
> >>> static int get_table_size(struct smu_context *smu)
> >>> {
> >>> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
> >>> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
> >>> return sizeof(PPTable_beige_goby_t);
> >>> else
> >>> return sizeof(PPTable_t);
> >>> @@ -298,7 +298,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
> >>> }
> >>>
> >>> if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
> >>> - (adev->ip_versions[MP1_HWIP] > IP_VERSION(11, 0, 7)) &&
> >>> + (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
> >>> !(adev->flags & AMD_IS_APU))
> >>> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> >>>
> >>> @@ -496,7 +496,7 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s
> >>> uint32_t throttler_status = 0;
> >>> int i;
> >>>
> >>> - if ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> >>> + if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> >>> (smu->smc_fw_version >= 0x3A4300)) {
> >>> for (i = 0; i < THROTTLER_COUNT; i++)
> >>> throttler_status |=
> >>> @@ -517,7 +517,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
> >>> &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
> >>> SmuMetrics_V2_t *metrics_v2 =
> >>> &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
> >>> - bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> >>> + bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> >>> (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> >>> uint16_t average_gfx_activity;
> >>> int ret = 0;
> >>> @@ -1170,7 +1170,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
> >>> * and onwards SMU firmwares.
> >>> */
> >>> smu_cmn_get_smc_version(smu, NULL, &smu_version);
> >>> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> >>> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> >>> (smu_version < 0x003a2900))
> >>> break;
> >>>
> >>> @@ -1937,7 +1937,7 @@ static void sienna_cichlid_dump_od_table(struct smu_context *smu,
> >>> od_table->UclkFmax);
> >>>
> >>> smu_cmn_get_smc_version(smu, NULL, &smu_version);
> >>> - if (!((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> >>> + if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> >>> (smu_version < 0x003a2900)))
> >>> dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
> >>> }
> >>> @@ -2161,7 +2161,7 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
> >>> * and onwards SMU firmwares.
> >>> */
> >>> smu_cmn_get_smc_version(smu, NULL, &smu_version);
> >>> - if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> >>> + if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> >>> (smu_version < 0x003a2900)) {
> >>> dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
> >>> "only by 58.41.0 and onwards SMU firmwares!\n");
> >>> @@ -2865,7 +2865,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
> >>> PPTable_t *pptable = table_context->driver_pptable;
> >>> int i;
> >>>
> >>> - if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)) {
> >>> + if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
> >>> beige_goby_dump_pptable(smu);
> >>> return;
> >>> }
> >>> @@ -3625,7 +3625,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
> >>> SmuMetrics_V2_t *metrics_v2 =
> >>> &(metrics_external.SmuMetrics_V2);
> >>> struct amdgpu_device *adev = smu->adev;
> >>> - bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
> >>> + bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> >>> (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> >>> uint16_t average_gfx_activity;
> >>> int ret = 0;
> >>> @@ -3706,8 +3706,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
> >>>
> >>> gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
> >>>
> >>> - if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
> >>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
> >>> + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
> >>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
> >>> gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
> >>> gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
> >>> } else {
> >>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> >>> index 1ae8b8dc3bd3..3470c33ee09d 100644
> >>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> >>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> >>> @@ -90,11 +90,11 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
> >>> struct amdgpu_firmware_info *ucode = NULL;
> >>>
> >>> if (amdgpu_sriov_vf(adev) &&
> >>> - ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
> >>> - (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7))))
> >>> + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
> >>> + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7))))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 0):
> >>> chip_name = "navi10";
> >>> break;
> >>> @@ -121,7 +121,7 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
> >>> break;
> >>> default:
> >>> dev_err(adev->dev, "Unsupported IP version 0x%x\n",
> >>> - adev->ip_versions[MP1_HWIP]);
> >>> + adev->ip_versions[MP1_HWIP][0]);
> >>> return -EINVAL;
> >>> }
> >>>
> >>> @@ -239,7 +239,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
> >>> if (smu->is_apu)
> >>> adev->pm.fw_version = smu_version;
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 0):
> >>> smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
> >>> break;
> >>> @@ -272,7 +272,7 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
> >>> break;
> >>> default:
> >>> dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
> >>> - adev->ip_versions[MP1_HWIP]);
> >>> + adev->ip_versions[MP1_HWIP][0]);
> >>> smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
> >>> break;
> >>> }
> >>> @@ -496,7 +496,7 @@ int smu_v11_0_init_power(struct smu_context *smu)
> >>> {
> >>> struct amdgpu_device *adev = smu->adev;
> >>> struct smu_power_context *smu_power = &smu->smu_power;
> >>> - size_t size = adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ?
> >>> + size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ?
> >>> sizeof(struct smu_11_5_power_context) :
> >>> sizeof(struct smu_11_0_power_context);
> >>>
> >>> @@ -753,9 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
> >>> /* Navy_Flounder/Dimgrey_Cavefish do not support to change
> >>> * display num currently
> >>> */
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11) ||
> >>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ||
> >>> - adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) ||
> >>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ||
> >>> + adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
> >>> return 0;
> >>>
> >>> return smu_cmn_send_smc_msg_with_param(smu,
> >>> @@ -1140,7 +1140,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
> >>> int ret = 0;
> >>> struct amdgpu_device *adev = smu->adev;
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 0):
> >>> case IP_VERSION(11, 0, 5):
> >>> case IP_VERSION(11, 0, 9):
> >>> @@ -1634,7 +1634,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
> >>> mutex_lock(&smu_baco->mutex);
> >>>
> >>> if (state == SMU_BACO_STATE_ENTER) {
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(11, 0, 7):
> >>> case IP_VERSION(11, 0, 11):
> >>> case IP_VERSION(11, 0, 12):
> >>> @@ -1653,7 +1653,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
> >>> default:
> >>> if (!ras || !adev->ras_enabled ||
> >>> adev->gmc.xgmi.pending_reset) {
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
> >>> data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
> >>> data |= 0x80000000;
> >>> WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
> >>> @@ -1935,7 +1935,7 @@ int smu_v11_0_set_performance_level(struct smu_context *smu,
> >>> * Separate MCLK and SOCCLK soft min/max settings are not allowed
> >>> * on Arcturus.
> >>> */
> >>> - if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 2)) {
> >>> + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
> >>> mclk_min = mclk_max = 0;
> >>> socclk_min = socclk_max = 0;
> >>> }
> >>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> >>> index 08f3cc809fc6..05c5e61f3506 100644
> >>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> >>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> >>> @@ -89,13 +89,13 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
> >>> if (amdgpu_sriov_vf(adev))
> >>> return 0;
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(13, 0, 2):
> >>> chip_name = "aldebaran";
> >>> break;
> >>> default:
> >>> dev_err(adev->dev, "Unsupported IP version 0x%x\n",
> >>> - adev->ip_versions[MP1_HWIP]);
> >>> + adev->ip_versions[MP1_HWIP][0]);
> >>> return -EINVAL;
> >>> }
> >>>
> >>> @@ -211,7 +211,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
> >>> smu_minor = (smu_version >> 8) & 0xff;
> >>> smu_debug = (smu_version >> 0) & 0xff;
> >>>
> >>> - switch (smu->adev->ip_versions[MP1_HWIP]) {
> >>> + switch (smu->adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(13, 0, 2):
> >>> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
> >>> break;
> >>> @@ -221,7 +221,7 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
> >>> break;
> >>> default:
> >>> dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
> >>> - smu->adev->ip_versions[MP1_HWIP]);
> >>> + smu->adev->ip_versions[MP1_HWIP][0]);
> >>> smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
> >>> break;
> >>> }
> >>> @@ -743,7 +743,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
> >>> int ret = 0;
> >>> struct amdgpu_device *adev = smu->adev;
> >>>
> >>> - switch (adev->ip_versions[MP1_HWIP]) {
> >>> + switch (adev->ip_versions[MP1_HWIP][0]) {
> >>> case IP_VERSION(13, 0, 1):
> >>> case IP_VERSION(13, 0, 3):
> >>> if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
> >>>
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 62/66] drm/amdgpu: clean up set IP function
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (60 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 61/66] drm/amdgpu: convert IP version array to include instances Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 63/66] drm/amdgpu: add support for SRIOV in IP discovery path Alex Deucher
` (4 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Split into several smaller per IP functions to make it
easier to handle ordering issues for things like
SR-IOV in a follow up patch.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1028 +++++++++--------
1 file changed, 540 insertions(+), 488 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index eff348dee9e9..44ab3d6739e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -517,336 +517,218 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
return 0;
}
-int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
+static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
{
- int r;
-
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- vega10_reg_base_init(adev);
- adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
- adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
- break;
- case CHIP_VEGA12:
- vega10_reg_base_init(adev);
- adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
- adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
- break;
- case CHIP_RAVEN:
- vega10_reg_base_init(adev);
- adev->sdma.num_instances = 1;
- adev->vcn.num_vcn_inst = 1;
- if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
- adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
- } else {
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
- adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
- }
- break;
- case CHIP_VEGA20:
- vega20_reg_base_init(adev);
- adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
- adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
- adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
- break;
- case CHIP_ARCTURUS:
- arct_reg_base_init(adev);
- adev->sdma.num_instances = 8;
- adev->vcn.num_vcn_inst = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
- break;
- case CHIP_ALDEBARAN:
- aldebaran_reg_base_init(adev);
- adev->sdma.num_instances = 5;
- adev->vcn.num_vcn_inst = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
- adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
- break;
- default:
- r = amdgpu_discovery_reg_base_init(adev);
- if (r)
- return -EINVAL;
-
- amdgpu_discovery_harvest_ip(adev);
-
- if (!adev->mman.discovery_bin) {
- DRM_ERROR("ip discovery uninitialized\n");
- return -EINVAL;
- }
- break;
- }
-
+ /* what IP to use for this? */
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 1, 0):
case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
case IP_VERSION(9, 4, 0):
case IP_VERSION(9, 4, 1):
case IP_VERSION(9, 4, 2):
- adev->family = AMDGPU_FAMILY_AI;
- break;
- case IP_VERSION(9, 1, 0):
- case IP_VERSION(9, 2, 2):
- case IP_VERSION(9, 3, 0):
- adev->family = AMDGPU_FAMILY_RV;
+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
break;
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
case IP_VERSION(10, 3, 4):
case IP_VERSION(10, 3, 5):
- adev->family = AMDGPU_FAMILY_NV;
- break;
- case IP_VERSION(10, 3, 1):
- adev->family = AMDGPU_FAMILY_VGH;
- break;
- case IP_VERSION(10, 3, 3):
- adev->family = AMDGPU_FAMILY_YC;
+ amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
break;
default:
return -EINVAL;
}
+ return 0;
+}
- if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
- adev->gmc.xgmi.supported = true;
-
- /* set NBIO version */
- switch (adev->ip_versions[NBIO_HWIP][0]) {
- case IP_VERSION(6, 1, 0):
- case IP_VERSION(6, 2, 0):
- adev->nbio.funcs = &nbio_v6_1_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
- break;
- case IP_VERSION(7, 0, 0):
- case IP_VERSION(7, 0, 1):
- case IP_VERSION(2, 5, 0):
- adev->nbio.funcs = &nbio_v7_0_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
- break;
- case IP_VERSION(7, 4, 0):
- case IP_VERSION(7, 4, 1):
- case IP_VERSION(7, 4, 4):
- adev->nbio.funcs = &nbio_v7_4_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
- break;
- case IP_VERSION(7, 2, 0):
- case IP_VERSION(7, 2, 1):
- case IP_VERSION(7, 5, 0):
- adev->nbio.funcs = &nbio_v7_2_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
+static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
+{
+ /* use GC or MMHUB IP version */
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
break;
- case IP_VERSION(2, 1, 1):
- case IP_VERSION(2, 3, 0):
- case IP_VERSION(2, 3, 1):
- case IP_VERSION(2, 3, 2):
- case IP_VERSION(3, 3, 0):
- case IP_VERSION(3, 3, 1):
- case IP_VERSION(3, 3, 2):
- case IP_VERSION(3, 3, 3):
- adev->nbio.funcs = &nbio_v2_3_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
break;
default:
- break;
+ return -EINVAL;
}
+ return 0;
+}
- switch (adev->ip_versions[HDP_HWIP][0]) {
+static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[OSSSYS_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 3, 0):
+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+ break;
case IP_VERSION(4, 2, 0):
case IP_VERSION(4, 2, 1):
case IP_VERSION(4, 4, 0):
- adev->hdp.funcs = &hdp_v4_0_funcs;
+ amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
case IP_VERSION(5, 0, 3):
- case IP_VERSION(5, 0, 4):
case IP_VERSION(5, 2, 0):
- adev->hdp.funcs = &hdp_v5_0_funcs;
- break;
- default:
- break;
- }
-
- switch (adev->ip_versions[DF_HWIP][0]) {
- case IP_VERSION(3, 6, 0):
- case IP_VERSION(3, 6, 1):
- case IP_VERSION(3, 6, 2):
- adev->df.funcs = &df_v3_6_funcs;
- break;
- case IP_VERSION(2, 1, 0):
- case IP_VERSION(2, 1, 1):
- case IP_VERSION(2, 5, 0):
- case IP_VERSION(3, 5, 1):
- case IP_VERSION(3, 5, 2):
- adev->df.funcs = &df_v1_7_funcs;
+ case IP_VERSION(5, 2, 1):
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
break;
default:
- break;
+ return -EINVAL;
}
+ return 0;
+}
- switch (adev->ip_versions[SMUIO_HWIP][0]) {
+static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(9, 0, 0):
- case IP_VERSION(9, 0, 1):
+ amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+ break;
case IP_VERSION(10, 0, 0):
case IP_VERSION(10, 0, 1):
- case IP_VERSION(10, 0, 2):
- adev->smuio.funcs = &smuio_v9_0_funcs;
+ amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
break;
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 2):
- case IP_VERSION(11, 0, 3):
case IP_VERSION(11, 0, 4):
+ case IP_VERSION(11, 0, 5):
+ case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 7):
- case IP_VERSION(11, 0, 8):
- adev->smuio.funcs = &smuio_v11_0_funcs;
- break;
- case IP_VERSION(11, 0, 6):
- case IP_VERSION(11, 0, 10):
case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
case IP_VERSION(11, 5, 0):
- case IP_VERSION(13, 0, 1):
- adev->smuio.funcs = &smuio_v11_0_6_funcs;
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ break;
+ case IP_VERSION(11, 0, 8):
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
break;
+ case IP_VERSION(11, 0, 3):
+ case IP_VERSION(12, 0, 1):
+ amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
+ break;
+ case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 2):
- adev->smuio.funcs = &smuio_v13_0_funcs;
+ case IP_VERSION(13, 0, 3):
+ amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
break;
default:
- break;
+ return -EINVAL;
}
+ return 0;
+}
- /* what IP to use for this? */
- switch (adev->ip_versions[GC_HWIP][0]) {
- case IP_VERSION(9, 0, 1):
- case IP_VERSION(9, 1, 0):
- case IP_VERSION(9, 2, 1):
- case IP_VERSION(9, 2, 2):
- case IP_VERSION(9, 3, 0):
- case IP_VERSION(9, 4, 0):
- case IP_VERSION(9, 4, 1):
- case IP_VERSION(9, 4, 2):
- amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[MP1_HWIP][0]) {
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ case IP_VERSION(11, 0, 2):
+ if (adev->asic_type == CHIP_ARCTURUS)
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ else
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
break;
- case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 1):
- case IP_VERSION(10, 1, 2):
- case IP_VERSION(10, 1, 3):
- case IP_VERSION(10, 3, 0):
- case IP_VERSION(10, 3, 1):
- case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 3):
- case IP_VERSION(10, 3, 4):
- case IP_VERSION(10, 3, 5):
- amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 8):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
+ case IP_VERSION(11, 5, 0):
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ break;
+ case IP_VERSION(12, 0, 0):
+ case IP_VERSION(12, 0, 1):
+ amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
+ break;
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 2):
+ case IP_VERSION(13, 0, 3):
+ amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
break;
default:
return -EINVAL;
}
+ return 0;
+}
+
+static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
+{
+ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
+ amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+ } else if (adev->ip_versions[DCE_HWIP][0]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 3):
+ case IP_VERSION(3, 0, 1):
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ break;
+ case IP_VERSION(2, 0, 3):
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (adev->ip_versions[DCI_HWIP][0]) {
+ switch (adev->ip_versions[DCI_HWIP][0]) {
+ case IP_VERSION(12, 0, 0):
+ case IP_VERSION(12, 0, 1):
+ case IP_VERSION(12, 1, 0):
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+#endif
+ }
+ return 0;
+}
- /* use GC or MMHUB IP version */
+static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
+{
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 1, 0):
@@ -856,319 +738,489 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(9, 4, 0):
case IP_VERSION(9, 4, 1):
case IP_VERSION(9, 4, 2):
- amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
break;
case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 3):
case IP_VERSION(10, 3, 0):
- case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 4):
case IP_VERSION(10, 3, 5):
- amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ case IP_VERSION(10, 3, 3):
+ amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
break;
default:
return -EINVAL;
}
+ return 0;
+}
- switch (adev->ip_versions[OSSSYS_HWIP][0]) {
+static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
case IP_VERSION(4, 1, 1):
- case IP_VERSION(4, 3, 0):
- amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
- break;
+ case IP_VERSION(4, 1, 2):
case IP_VERSION(4, 2, 0):
- case IP_VERSION(4, 2, 1):
+ case IP_VERSION(4, 2, 2):
case IP_VERSION(4, 4, 0):
- amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
- case IP_VERSION(5, 0, 3):
+ case IP_VERSION(5, 0, 5):
+ amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
+ break;
case IP_VERSION(5, 2, 0):
+ case IP_VERSION(5, 2, 2):
+ case IP_VERSION(5, 2, 4):
+ case IP_VERSION(5, 2, 5):
+ case IP_VERSION(5, 2, 3):
case IP_VERSION(5, 2, 1):
- amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
break;
default:
return -EINVAL;
}
+ return 0;
+}
- if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
- switch (adev->ip_versions[MP0_HWIP][0]) {
- case IP_VERSION(9, 0, 0):
- amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
- break;
- case IP_VERSION(10, 0, 0):
- case IP_VERSION(10, 0, 1):
- amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
- break;
- case IP_VERSION(11, 0, 0):
- case IP_VERSION(11, 0, 2):
- case IP_VERSION(11, 0, 4):
- case IP_VERSION(11, 0, 5):
- case IP_VERSION(11, 0, 9):
- case IP_VERSION(11, 0, 7):
- case IP_VERSION(11, 0, 11):
- case IP_VERSION(11, 0, 12):
- case IP_VERSION(11, 0, 13):
- case IP_VERSION(11, 5, 0):
- amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
- break;
- case IP_VERSION(11, 0, 8):
- amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
- break;
- case IP_VERSION(11, 0, 3):
- case IP_VERSION(12, 0, 1):
- amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
- break;
- case IP_VERSION(13, 0, 1):
- case IP_VERSION(13, 0, 2):
- case IP_VERSION(13, 0, 3):
- amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
+static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
+{
+ if (adev->ip_versions[VCE_HWIP][0]) {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
+ case IP_VERSION(7, 0, 0):
+ case IP_VERSION(7, 2, 0):
+ amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
break;
default:
return -EINVAL;
}
- }
-
- if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
- switch (adev->ip_versions[MP1_HWIP][0]) {
- case IP_VERSION(9, 0, 0):
- case IP_VERSION(10, 0, 0):
- case IP_VERSION(10, 0, 1):
- case IP_VERSION(11, 0, 2):
- if (adev->asic_type == CHIP_ARCTURUS)
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- else
- amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
- break;
- case IP_VERSION(11, 0, 0):
- case IP_VERSION(11, 0, 9):
- case IP_VERSION(11, 0, 7):
- case IP_VERSION(11, 0, 8):
- case IP_VERSION(11, 0, 11):
- case IP_VERSION(11, 0, 12):
- case IP_VERSION(11, 0, 13):
- case IP_VERSION(11, 5, 0):
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- break;
- case IP_VERSION(12, 0, 0):
- case IP_VERSION(12, 0, 1):
- amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
- break;
- case IP_VERSION(13, 0, 1):
- case IP_VERSION(13, 0, 2):
- case IP_VERSION(13, 0, 3):
- amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
+ switch (adev->ip_versions[VCE_HWIP][0]) {
+ case IP_VERSION(4, 0, 0):
+ case IP_VERSION(4, 1, 0):
+ amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
break;
default:
return -EINVAL;
}
- }
-
- if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
- amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
-#if defined(CONFIG_DRM_AMD_DC)
- } else if (adev->ip_versions[DCE_HWIP][0]) {
- switch (adev->ip_versions[DCE_HWIP][0]) {
+ } else {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
- case IP_VERSION(2, 0, 2):
+ amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
+ break;
case IP_VERSION(2, 0, 0):
- case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 2, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ break;
+ case IP_VERSION(2, 0, 3):
+ break;
+ case IP_VERSION(2, 5, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
+ break;
+ case IP_VERSION(2, 6, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
+ break;
case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 16):
+ case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 0, 2):
- case IP_VERSION(3, 0, 3):
- case IP_VERSION(3, 0, 1):
- case IP_VERSION(3, 1, 2):
- case IP_VERSION(3, 1, 3):
- amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
break;
- case IP_VERSION(2, 0, 3):
+ case IP_VERSION(3, 0, 33):
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
break;
default:
return -EINVAL;
- }
- } else if (adev->ip_versions[DCI_HWIP][0]) {
- switch (adev->ip_versions[DCI_HWIP][0]) {
- case IP_VERSION(12, 0, 0):
- case IP_VERSION(12, 0, 1):
- case IP_VERSION(12, 1, 0):
- amdgpu_device_ip_block_add(adev, &dm_ip_block);
- break;
- default:
+ }
+ }
+ return 0;
+}
+
+static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
+ break;
+ default:
+ break;;
+ }
+ return 0;
+}
+
+int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
+{
+ int r;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA10:
+ vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
+ break;
+ case CHIP_VEGA12:
+ vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
+ break;
+ case CHIP_RAVEN:
+ vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 1;
+ adev->vcn.num_vcn_inst = 1;
+ if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
+ adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
+ } else {
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
+ adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
+ }
+ break;
+ case CHIP_VEGA20:
+ vega20_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
+ break;
+ case CHIP_ARCTURUS:
+ arct_reg_base_init(adev);
+ adev->sdma.num_instances = 8;
+ adev->vcn.num_vcn_inst = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
+ break;
+ case CHIP_ALDEBARAN:
+ aldebaran_reg_base_init(adev);
+ adev->sdma.num_instances = 5;
+ adev->vcn.num_vcn_inst = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
+ adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
+ break;
+ default:
+ r = amdgpu_discovery_reg_base_init(adev);
+ if (r)
+ return -EINVAL;
+
+ amdgpu_discovery_harvest_ip(adev);
+
+ if (!adev->mman.discovery_bin) {
+ DRM_ERROR("ip discovery uninitialized\n");
return -EINVAL;
}
+ break;
}
-#endif
+
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
- case IP_VERSION(9, 1, 0):
case IP_VERSION(9, 2, 1):
- case IP_VERSION(9, 2, 2):
- case IP_VERSION(9, 3, 0):
case IP_VERSION(9, 4, 0):
case IP_VERSION(9, 4, 1):
case IP_VERSION(9, 4, 2):
- amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ adev->family = AMDGPU_FAMILY_AI;
+ break;
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ adev->family = AMDGPU_FAMILY_RV;
break;
case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 4):
case IP_VERSION(10, 3, 5):
+ adev->family = AMDGPU_FAMILY_NV;
+ break;
+ case IP_VERSION(10, 3, 1):
+ adev->family = AMDGPU_FAMILY_VGH;
+ break;
case IP_VERSION(10, 3, 3):
- amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ adev->family = AMDGPU_FAMILY_YC;
break;
default:
return -EINVAL;
}
- switch (adev->ip_versions[SDMA0_HWIP][0]) {
+ if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
+ adev->gmc.xgmi.supported = true;
+
+ /* set NBIO version */
+ switch (adev->ip_versions[NBIO_HWIP][0]) {
+ case IP_VERSION(6, 1, 0):
+ case IP_VERSION(6, 2, 0):
+ adev->nbio.funcs = &nbio_v6_1_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
+ break;
+ case IP_VERSION(7, 0, 0):
+ case IP_VERSION(7, 0, 1):
+ case IP_VERSION(2, 5, 0):
+ adev->nbio.funcs = &nbio_v7_0_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
+ break;
+ case IP_VERSION(7, 4, 0):
+ case IP_VERSION(7, 4, 1):
+ case IP_VERSION(7, 4, 4):
+ adev->nbio.funcs = &nbio_v7_4_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
+ break;
+ case IP_VERSION(7, 2, 0):
+ case IP_VERSION(7, 2, 1):
+ case IP_VERSION(7, 5, 0):
+ adev->nbio.funcs = &nbio_v7_2_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
+ break;
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 3, 0):
+ case IP_VERSION(2, 3, 1):
+ case IP_VERSION(2, 3, 2):
+ case IP_VERSION(3, 3, 0):
+ case IP_VERSION(3, 3, 1):
+ case IP_VERSION(3, 3, 2):
+ case IP_VERSION(3, 3, 3):
+ adev->nbio.funcs = &nbio_v2_3_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ break;
+ default:
+ break;
+ }
+
+ switch (adev->ip_versions[HDP_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
case IP_VERSION(4, 1, 1):
- case IP_VERSION(4, 1, 2):
case IP_VERSION(4, 2, 0):
- case IP_VERSION(4, 2, 2):
+ case IP_VERSION(4, 2, 1):
case IP_VERSION(4, 4, 0):
- amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ adev->hdp.funcs = &hdp_v4_0_funcs;
break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
- case IP_VERSION(5, 0, 5):
- amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
- break;
+ case IP_VERSION(5, 0, 3):
+ case IP_VERSION(5, 0, 4):
case IP_VERSION(5, 2, 0):
- case IP_VERSION(5, 2, 2):
- case IP_VERSION(5, 2, 4):
- case IP_VERSION(5, 2, 5):
- case IP_VERSION(5, 2, 3):
- case IP_VERSION(5, 2, 1):
- amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+ adev->hdp.funcs = &hdp_v5_0_funcs;
break;
default:
- return -EINVAL;
+ break;
}
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- switch (adev->ip_versions[MP1_HWIP][0]) {
- case IP_VERSION(9, 0, 0):
- case IP_VERSION(10, 0, 0):
- case IP_VERSION(10, 0, 1):
- case IP_VERSION(11, 0, 2):
- if (adev->asic_type == CHIP_ARCTURUS)
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- else
- amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
- break;
- case IP_VERSION(11, 0, 0):
- case IP_VERSION(11, 0, 9):
- case IP_VERSION(11, 0, 7):
- case IP_VERSION(11, 0, 8):
- case IP_VERSION(11, 0, 11):
- case IP_VERSION(11, 0, 12):
- case IP_VERSION(11, 0, 13):
- case IP_VERSION(11, 5, 0):
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- break;
- case IP_VERSION(12, 0, 0):
- case IP_VERSION(12, 0, 1):
- amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
- break;
- case IP_VERSION(13, 0, 1):
- case IP_VERSION(13, 0, 2):
- case IP_VERSION(13, 0, 3):
- amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
- break;
- default:
- return -EINVAL;
- }
+ switch (adev->ip_versions[DF_HWIP][0]) {
+ case IP_VERSION(3, 6, 0):
+ case IP_VERSION(3, 6, 1):
+ case IP_VERSION(3, 6, 2):
+ adev->df.funcs = &df_v3_6_funcs;
+ break;
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 5, 0):
+ case IP_VERSION(3, 5, 1):
+ case IP_VERSION(3, 5, 2):
+ adev->df.funcs = &df_v1_7_funcs;
+ break;
+ default:
+ break;
}
- if (adev->ip_versions[VCE_HWIP][0]) {
- switch (adev->ip_versions[UVD_HWIP][0]) {
- case IP_VERSION(7, 0, 0):
- case IP_VERSION(7, 2, 0):
- amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
- break;
- default:
- return -EINVAL;
- }
- switch (adev->ip_versions[VCE_HWIP][0]) {
- case IP_VERSION(4, 0, 0):
- case IP_VERSION(4, 1, 0):
- amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
- break;
- default:
- return -EINVAL;
- }
- } else {
- switch (adev->ip_versions[UVD_HWIP][0]) {
- case IP_VERSION(1, 0, 0):
- case IP_VERSION(1, 0, 1):
- amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
- break;
- case IP_VERSION(2, 0, 0):
- case IP_VERSION(2, 0, 2):
- case IP_VERSION(2, 2, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
- break;
- case IP_VERSION(2, 0, 3):
- break;
- case IP_VERSION(2, 5, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
- break;
- case IP_VERSION(2, 6, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
- break;
- case IP_VERSION(3, 0, 0):
- case IP_VERSION(3, 0, 16):
- case IP_VERSION(3, 1, 1):
- case IP_VERSION(3, 0, 2):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
- break;
- case IP_VERSION(3, 0, 33):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
- break;
- default:
- return -EINVAL;
- }
+ switch (adev->ip_versions[SMUIO_HWIP][0]) {
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ case IP_VERSION(10, 0, 2):
+ adev->smuio.funcs = &smuio_v9_0_funcs;
+ break;
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 2):
+ case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 8):
+ adev->smuio.funcs = &smuio_v11_0_funcs;
+ break;
+ case IP_VERSION(11, 0, 6):
+ case IP_VERSION(11, 0, 10):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 5, 0):
+ case IP_VERSION(13, 0, 1):
+ adev->smuio.funcs = &smuio_v11_0_6_funcs;
+ break;
+ case IP_VERSION(13, 0, 2):
+ adev->smuio.funcs = &smuio_v13_0_funcs;
+ break;
+ default:
+ break;
+ }
+
+ r = amdgpu_discovery_set_common_ip_blocks(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_discovery_set_gmc_ip_blocks(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_discovery_set_ih_ip_blocks(adev);
+ if (r)
+ return r;
+
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ r = amdgpu_discovery_set_psp_ip_blocks(adev);
+ if (r)
+ return r;
+ }
+
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ r = amdgpu_discovery_set_smu_ip_blocks(adev);
+ if (r)
+ return r;
}
+ r = amdgpu_discovery_set_display_ip_blocks(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_discovery_set_gc_ip_blocks(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_discovery_set_sdma_ip_blocks(adev);
+ if (r)
+ return r;
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ r = amdgpu_discovery_set_smu_ip_blocks(adev);
+ if (r)
+ return r;
+ }
+
+ r = amdgpu_discovery_set_mm_ip_blocks(adev);
+ if (r)
+ return r;
+
if (adev->enable_mes) {
- switch (adev->ip_versions[GC_HWIP][0]) {
- case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 1):
- case IP_VERSION(10, 1, 2):
- case IP_VERSION(10, 1, 3):
- case IP_VERSION(10, 3, 0):
- case IP_VERSION(10, 3, 1):
- case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 3):
- case IP_VERSION(10, 3, 4):
- case IP_VERSION(10, 3, 5):
- amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
- break;
- default:
- break;;
- }
+ r = amdgpu_discovery_set_mes_ip_blocks(adev);
+ if (r)
+ return r;
}
return 0;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 63/66] drm/amdgpu: add support for SRIOV in IP discovery path
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (61 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 62/66] drm/amdgpu: clean up set IP function Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 64/66] drm/amdkfd: clean up parameters in kgd2kfd_probe Alex Deucher
` (3 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Handle SRIOV requirements when adding IP blocks.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 32 +++++++++++++------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 44ab3d6739e3..821665fb73b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -797,7 +797,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(7, 0, 0):
case IP_VERSION(7, 2, 0):
- amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
+ if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
+ amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
break;
default:
return -EINVAL;
@@ -805,7 +806,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
switch (adev->ip_versions[VCE_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 1, 0):
- amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
+ if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
+ amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
break;
default:
return -EINVAL;
@@ -837,7 +839,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 0, 2):
amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
+ if (!amdgpu_sriov_vf(adev))
+ amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
break;
case IP_VERSION(3, 0, 33):
amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
@@ -1179,14 +1182,24 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
if (r)
return r;
- r = amdgpu_discovery_set_ih_ip_blocks(adev);
- if (r)
- return r;
-
- if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ /* For SR-IOV, PSP needs to be initialized before IH */
+ if (amdgpu_sriov_vf(adev)) {
r = amdgpu_discovery_set_psp_ip_blocks(adev);
if (r)
return r;
+ r = amdgpu_discovery_set_ih_ip_blocks(adev);
+ if (r)
+ return r;
+ } else {
+ r = amdgpu_discovery_set_ih_ip_blocks(adev);
+ if (r)
+ return r;
+
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ r = amdgpu_discovery_set_psp_ip_blocks(adev);
+ if (r)
+ return r;
+ }
}
if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
@@ -1207,7 +1220,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
if (r)
return r;
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
+ !amdgpu_sriov_vf(adev)) {
r = amdgpu_discovery_set_smu_ip_blocks(adev);
if (r)
return r;
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 64/66] drm/amdkfd: clean up parameters in kgd2kfd_probe
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (62 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 63/66] drm/amdgpu: add support for SRIOV in IP discovery path Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version Alex Deucher
` (2 subsequent siblings)
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
We can get the pdev and asic type from the adev. No need
to pass them explicitly.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 +--
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 +++++--
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 1d41c2c00623..ce60f42647bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -70,8 +70,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
if (!kfd_initialized)
return;
- adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
- adev->pdev, adev->asic_type, vf);
+ adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, vf);
if (adev->kfd.dev)
amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 3bc52b2c604f..1f16bd772ca8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -321,8 +321,7 @@ int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
#if IS_ENABLED(CONFIG_HSA_AMD)
int kgd2kfd_init(void);
void kgd2kfd_exit(void);
-struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
- unsigned int asic_type, bool vf);
+struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf);
bool kgd2kfd_device_init(struct kfd_dev *kfd,
struct drm_device *ddev,
const struct kgd2kfd_shared_resources *gpu_resources);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 98d1b3ab3a46..9269b5e3aed1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -32,6 +32,7 @@
#include "amdgpu_amdkfd.h"
#include "kfd_smi_events.h"
#include "kfd_migrate.h"
+#include "amdgpu.h"
#define MQD_SIZE_ALIGNED 768
@@ -691,12 +692,14 @@ static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
static int kfd_resume(struct kfd_dev *kfd);
-struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
- struct pci_dev *pdev, unsigned int asic_type, bool vf)
+struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf)
{
struct kfd_dev *kfd;
const struct kfd_device_info *device_info;
const struct kfd2kgd_calls *f2g;
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ unsigned int asic_type = adev->asic_type;
+ struct pci_dev *pdev = adev->pdev;
if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
|| asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (63 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 64/66] drm/amdkfd: clean up parameters in kgd2kfd_probe Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-21 21:00 ` ernstp
2021-09-22 16:55 ` Felix Kuehling
2021-09-21 18:07 ` [PATCH 66/66] drm/amdgpu: add an option to override IP discovery table from a file Alex Deucher
2021-09-22 7:54 ` [PATCH 00/66] Move to IP driven device enumeration Christian König
66 siblings, 2 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
rather than asic type.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 254 +++++++++++++++++-------
1 file changed, 178 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 9269b5e3aed1..25614a86b2c9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -53,41 +53,6 @@ extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
-static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
-#ifdef KFD_SUPPORT_IOMMU_V2
-#ifdef CONFIG_DRM_AMDGPU_CIK
- [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
-#endif
- [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
- [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
-#endif
-#ifdef CONFIG_DRM_AMDGPU_CIK
- [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
-#endif
- [CHIP_TONGA] = &gfx_v8_kfd2kgd,
- [CHIP_FIJI] = &gfx_v8_kfd2kgd,
- [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
- [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
- [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
- [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
- [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
- [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
- [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
- [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
- [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
- [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd,
- [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
- [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
- [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
- [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
- [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
- [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
- [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd,
- [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd,
- [CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd,
- [CHIP_CYAN_SKILLFISH] = &gfx_v10_kfd2kgd,
-};
-
#ifdef KFD_SUPPORT_IOMMU_V2
static const struct kfd_device_info kaveri_device_info = {
.asic_family = CHIP_KAVERI,
@@ -654,38 +619,6 @@ static const struct kfd_device_info cyan_skillfish_device_info = {
.num_sdma_queues_per_engine = 8,
};
-/* For each entry, [0] is regular and [1] is virtualisation device. */
-static const struct kfd_device_info *kfd_supported_devices[][2] = {
-#ifdef KFD_SUPPORT_IOMMU_V2
- [CHIP_KAVERI] = {&kaveri_device_info, NULL},
- [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
-#endif
- [CHIP_RAVEN] = {&raven_device_info, NULL},
- [CHIP_HAWAII] = {&hawaii_device_info, NULL},
- [CHIP_TONGA] = {&tonga_device_info, NULL},
- [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
- [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
- [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
- [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
- [CHIP_VEGAM] = {&vegam_device_info, NULL},
- [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
- [CHIP_VEGA12] = {&vega12_device_info, NULL},
- [CHIP_VEGA20] = {&vega20_device_info, NULL},
- [CHIP_RENOIR] = {&renoir_device_info, NULL},
- [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
- [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info},
- [CHIP_NAVI10] = {&navi10_device_info, NULL},
- [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
- [CHIP_NAVI14] = {&navi14_device_info, NULL},
- [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
- [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
- [CHIP_VANGOGH] = {&vangogh_device_info, NULL},
- [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info},
- [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info},
- [CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL},
- [CHIP_CYAN_SKILLFISH] = {&cyan_skillfish_device_info, NULL},
-};
-
static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
unsigned int chunk_size);
static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
@@ -698,21 +631,190 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf)
const struct kfd_device_info *device_info;
const struct kfd2kgd_calls *f2g;
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
- unsigned int asic_type = adev->asic_type;
struct pci_dev *pdev = adev->pdev;
- if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
- || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
- dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
- return NULL; /* asic_type out of range */
+ switch (adev->asic_type) {
+#ifdef KFD_SUPPORT_IOMMU_V2
+#ifdef CONFIG_DRM_AMDGPU_CIK
+ case CHIP_KAVERI:
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &kaveri_device_info;
+ f2g = &gfx_v7_kfd2kgd;
+ break;
+#endif
+ case CHIP_CARRIZO:
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &kaveri_device_info;
+ f2g = &gfx_v8_kfd2kgd;
+ break;
+#endif
+#ifdef CONFIG_DRM_AMDGPU_CIK
+ case CHIP_HAWAII:
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &hawaii_device_info;
+ f2g = &gfx_v7_kfd2kgd;
+ break;
+#endif
+ case CHIP_TONGA:
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &tonga_device_info;
+ f2g = &gfx_v8_kfd2kgd;
+ break;
+ case CHIP_FIJI:
+ if (vf)
+ device_info = &fiji_vf_device_info;
+ else
+ device_info = &fiji_device_info;
+ f2g = &gfx_v8_kfd2kgd;
+ break;
+ case CHIP_POLARIS10:
+ if (vf)
+ device_info = &polaris10_vf_device_info;
+ else
+ device_info = &polaris10_device_info;
+ f2g = &gfx_v8_kfd2kgd;
+ break;
+ case CHIP_POLARIS11:
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &polaris11_device_info;
+ f2g = &gfx_v8_kfd2kgd;
+ break;
+ case CHIP_POLARIS12:
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &polaris12_device_info;
+ f2g = &gfx_v8_kfd2kgd;
+ break;
+ case CHIP_VEGAM:
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &vegam_device_info;
+ f2g = &gfx_v8_kfd2kgd;
+ break;
+ default:
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 0, 1):
+ if (vf)
+ device_info = &vega10_vf_device_info;
+ else
+ device_info = &vega10_device_info;
+ f2g = &gfx_v9_kfd2kgd;
+ break;
+#ifdef KFD_SUPPORT_IOMMU_V2
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &raven_device_info;
+ f2g = &gfx_v9_kfd2kgd;
+ break;
+#endif
+ case IP_VERSION(9, 2, 1):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &vega12_device_info;
+ f2g = &gfx_v9_kfd2kgd;
+ break;
+ case IP_VERSION(9, 3, 0):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &renoir_device_info;
+ f2g = &gfx_v9_kfd2kgd;
+ break;
+ case IP_VERSION(9, 4, 0):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &vega20_device_info;
+ f2g = &gfx_v9_kfd2kgd;
+ break;
+ case IP_VERSION(9, 4, 1):
+ device_info = &arcturus_device_info;
+ f2g = &arcturus_kfd2kgd;
+ break;
+ case IP_VERSION(9, 4, 2):
+ device_info = &aldebaran_device_info;
+ f2g = &aldebaran_kfd2kgd;
+ break;
+ case IP_VERSION(10, 1, 10):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &navi10_device_info;
+ f2g = &gfx_v10_kfd2kgd;
+ break;
+ case IP_VERSION(10, 1, 2):
+ device_info = &navi12_device_info;
+ f2g = &gfx_v10_kfd2kgd;
+ break;
+ case IP_VERSION(10, 1, 1):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &navi14_device_info;
+ f2g = &gfx_v10_kfd2kgd;
+ break;
+ case IP_VERSION(10, 1, 3):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &cyan_skillfish_device_info;
+ f2g = &gfx_v10_kfd2kgd;
+ break;
+ case IP_VERSION(10, 3, 0):
+ device_info = &sienna_cichlid_device_info;
+ f2g = &gfx_v10_3_kfd2kgd;
+ break;
+ case IP_VERSION(10, 3, 2):
+ device_info = &navy_flounder_device_info;
+ f2g = &gfx_v10_3_kfd2kgd;
+ break;
+ case IP_VERSION(10, 3, 1):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &vangogh_device_info;
+ f2g = &gfx_v10_3_kfd2kgd;
+ break;
+ case IP_VERSION(10, 3, 4):
+ device_info = &dimgrey_cavefish_device_info;
+ f2g = &gfx_v10_3_kfd2kgd;
+ break;
+ case IP_VERSION(10, 3, 5):
+ device_info = &beige_goby_device_info;
+ f2g = &gfx_v10_3_kfd2kgd;
+ break;
+ case IP_VERSION(10, 3, 3):
+ if (vf)
+ device_info = NULL;
+ else
+ device_info = &yellow_carp_device_info;
+ f2g = &gfx_v10_3_kfd2kgd;
+ break;
+ default:
+ return NULL;
+ }
+ break;
}
- device_info = kfd_supported_devices[asic_type][vf];
- f2g = kfd2kgd_funcs[asic_type];
-
if (!device_info || !f2g) {
dev_err(kfd_device, "%s %s not supported in kfd\n",
- amdgpu_asic_name[asic_type], vf ? "VF" : "");
+ amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
return NULL;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version
2021-09-21 18:07 ` [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version Alex Deucher
@ 2021-09-21 21:00 ` ernstp
2021-09-22 1:44 ` Alex Deucher
2021-09-22 16:55 ` Felix Kuehling
1 sibling, 1 reply; 106+ messages in thread
From: ernstp @ 2021-09-21 21:00 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
tis 2021-09-21 klockan 14:07 -0400 skrev Alex Deucher:
> rather than asic type.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 254 +++++++++++++++++-------
> 1 file changed, 178 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index 9269b5e3aed1..25614a86b2c9 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -53,41 +53,6 @@ extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
> extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
> extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
>
>
> -static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
> -#ifdef KFD_SUPPORT_IOMMU_V2
> -#ifdef CONFIG_DRM_AMDGPU_CIK
> - [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
> -#endif
> - [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
> - [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
> -#endif
> -#ifdef CONFIG_DRM_AMDGPU_CIK
> - [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
> -#endif
> - [CHIP_TONGA] = &gfx_v8_kfd2kgd,
> - [CHIP_FIJI] = &gfx_v8_kfd2kgd,
> - [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
> - [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
> - [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
> - [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
> - [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
> - [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
> - [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
> - [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
> - [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
> - [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd,
> - [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
> - [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
> - [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
> - [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
> - [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
> - [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
> - [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd,
> - [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd,
> - [CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd,
> - [CHIP_CYAN_SKILLFISH] = &gfx_v10_kfd2kgd,
> -};
> -
> #ifdef KFD_SUPPORT_IOMMU_V2
> static const struct kfd_device_info kaveri_device_info = {
> .asic_family = CHIP_KAVERI,
> @@ -654,38 +619,6 @@ static const struct kfd_device_info cyan_skillfish_device_info = {
> .num_sdma_queues_per_engine = 8,
> };
>
>
> -/* For each entry, [0] is regular and [1] is virtualisation device. */
> -static const struct kfd_device_info *kfd_supported_devices[][2] = {
> -#ifdef KFD_SUPPORT_IOMMU_V2
> - [CHIP_KAVERI] = {&kaveri_device_info, NULL},
> - [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
> -#endif
> - [CHIP_RAVEN] = {&raven_device_info, NULL},
> - [CHIP_HAWAII] = {&hawaii_device_info, NULL},
> - [CHIP_TONGA] = {&tonga_device_info, NULL},
> - [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
> - [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
> - [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
> - [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
> - [CHIP_VEGAM] = {&vegam_device_info, NULL},
> - [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
> - [CHIP_VEGA12] = {&vega12_device_info, NULL},
> - [CHIP_VEGA20] = {&vega20_device_info, NULL},
> - [CHIP_RENOIR] = {&renoir_device_info, NULL},
> - [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
> - [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info},
> - [CHIP_NAVI10] = {&navi10_device_info, NULL},
> - [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
> - [CHIP_NAVI14] = {&navi14_device_info, NULL},
> - [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
> - [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
> - [CHIP_VANGOGH] = {&vangogh_device_info, NULL},
> - [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info},
> - [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info},
> - [CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL},
> - [CHIP_CYAN_SKILLFISH] = {&cyan_skillfish_device_info, NULL},
> -};
> -
> static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
> unsigned int chunk_size);
> static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
> @@ -698,21 +631,190 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf)
> const struct kfd_device_info *device_info;
> const struct kfd2kgd_calls *f2g;
> struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
> - unsigned int asic_type = adev->asic_type;
> struct pci_dev *pdev = adev->pdev;
>
>
> - if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
> - || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
> - dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
> - return NULL; /* asic_type out of range */
> + switch (adev->asic_type) {
> +#ifdef KFD_SUPPORT_IOMMU_V2
> +#ifdef CONFIG_DRM_AMDGPU_CIK
> + case CHIP_KAVERI:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &kaveri_device_info;
> + f2g = &gfx_v7_kfd2kgd;
> + break;
> +#endif
> + case CHIP_CARRIZO:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &kaveri_device_info;
That should probably be carrizo. Found with W=1.
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> +#endif
> +#ifdef CONFIG_DRM_AMDGPU_CIK
> + case CHIP_HAWAII:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &hawaii_device_info;
> + f2g = &gfx_v7_kfd2kgd;
> + break;
> +#endif
> + case CHIP_TONGA:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &tonga_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_FIJI:
> + if (vf)
> + device_info = &fiji_vf_device_info;
> + else
> + device_info = &fiji_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_POLARIS10:
> + if (vf)
> + device_info = &polaris10_vf_device_info;
> + else
> + device_info = &polaris10_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_POLARIS11:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &polaris11_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_POLARIS12:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &polaris12_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_VEGAM:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &vegam_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + default:
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + if (vf)
> + device_info = &vega10_vf_device_info;
> + else
> + device_info = &vega10_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> +#ifdef KFD_SUPPORT_IOMMU_V2
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &raven_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> +#endif
> + case IP_VERSION(9, 2, 1):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &vega12_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> + case IP_VERSION(9, 3, 0):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &renoir_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> + case IP_VERSION(9, 4, 0):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &vega20_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> + case IP_VERSION(9, 4, 1):
> + device_info = &arcturus_device_info;
> + f2g = &arcturus_kfd2kgd;
> + break;
> + case IP_VERSION(9, 4, 2):
> + device_info = &aldebaran_device_info;
> + f2g = &aldebaran_kfd2kgd;
> + break;
> + case IP_VERSION(10, 1, 10):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &navi10_device_info;
> + f2g = &gfx_v10_kfd2kgd;
> + break;
> + case IP_VERSION(10, 1, 2):
> + device_info = &navi12_device_info;
> + f2g = &gfx_v10_kfd2kgd;
> + break;
> + case IP_VERSION(10, 1, 1):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &navi14_device_info;
> + f2g = &gfx_v10_kfd2kgd;
> + break;
> + case IP_VERSION(10, 1, 3):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &cyan_skillfish_device_info;
> + f2g = &gfx_v10_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 0):
> + device_info = &sienna_cichlid_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 2):
> + device_info = &navy_flounder_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 1):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &vangogh_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 4):
> + device_info = &dimgrey_cavefish_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 5):
> + device_info = &beige_goby_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 3):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &yellow_carp_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + default:
> + return NULL;
> + }
> + break;
> }
>
>
> - device_info = kfd_supported_devices[asic_type][vf];
> - f2g = kfd2kgd_funcs[asic_type];
> -
> if (!device_info || !f2g) {
> dev_err(kfd_device, "%s %s not supported in kfd\n",
> - amdgpu_asic_name[asic_type], vf ? "VF" : "");
> + amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
> return NULL;
> }
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version
2021-09-21 21:00 ` ernstp
@ 2021-09-22 1:44 ` Alex Deucher
0 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-22 1:44 UTC (permalink / raw)
To: Ernst Sjöstrand; +Cc: Alex Deucher, amd-gfx list
On Tue, Sep 21, 2021 at 5:00 PM <ernstp@gmail.com> wrote:
>
> tis 2021-09-21 klockan 14:07 -0400 skrev Alex Deucher:
> > rather than asic type.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_device.c | 254 +++++++++++++++++-------
> > 1 file changed, 178 insertions(+), 76 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > index 9269b5e3aed1..25614a86b2c9 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > @@ -53,41 +53,6 @@ extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
> > extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
> > extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
> >
> >
> > -static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
> > -#ifdef KFD_SUPPORT_IOMMU_V2
> > -#ifdef CONFIG_DRM_AMDGPU_CIK
> > - [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
> > -#endif
> > - [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
> > - [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
> > -#endif
> > -#ifdef CONFIG_DRM_AMDGPU_CIK
> > - [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
> > -#endif
> > - [CHIP_TONGA] = &gfx_v8_kfd2kgd,
> > - [CHIP_FIJI] = &gfx_v8_kfd2kgd,
> > - [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
> > - [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
> > - [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
> > - [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
> > - [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
> > - [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
> > - [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
> > - [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
> > - [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
> > - [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd,
> > - [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
> > - [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
> > - [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
> > - [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
> > - [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
> > - [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
> > - [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd,
> > - [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd,
> > - [CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd,
> > - [CHIP_CYAN_SKILLFISH] = &gfx_v10_kfd2kgd,
> > -};
> > -
> > #ifdef KFD_SUPPORT_IOMMU_V2
> > static const struct kfd_device_info kaveri_device_info = {
> > .asic_family = CHIP_KAVERI,
> > @@ -654,38 +619,6 @@ static const struct kfd_device_info cyan_skillfish_device_info = {
> > .num_sdma_queues_per_engine = 8,
> > };
> >
> >
> > -/* For each entry, [0] is regular and [1] is virtualisation device. */
> > -static const struct kfd_device_info *kfd_supported_devices[][2] = {
> > -#ifdef KFD_SUPPORT_IOMMU_V2
> > - [CHIP_KAVERI] = {&kaveri_device_info, NULL},
> > - [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
> > -#endif
> > - [CHIP_RAVEN] = {&raven_device_info, NULL},
> > - [CHIP_HAWAII] = {&hawaii_device_info, NULL},
> > - [CHIP_TONGA] = {&tonga_device_info, NULL},
> > - [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
> > - [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
> > - [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
> > - [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
> > - [CHIP_VEGAM] = {&vegam_device_info, NULL},
> > - [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
> > - [CHIP_VEGA12] = {&vega12_device_info, NULL},
> > - [CHIP_VEGA20] = {&vega20_device_info, NULL},
> > - [CHIP_RENOIR] = {&renoir_device_info, NULL},
> > - [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
> > - [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info},
> > - [CHIP_NAVI10] = {&navi10_device_info, NULL},
> > - [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
> > - [CHIP_NAVI14] = {&navi14_device_info, NULL},
> > - [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
> > - [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
> > - [CHIP_VANGOGH] = {&vangogh_device_info, NULL},
> > - [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info},
> > - [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info},
> > - [CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL},
> > - [CHIP_CYAN_SKILLFISH] = {&cyan_skillfish_device_info, NULL},
> > -};
> > -
> > static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
> > unsigned int chunk_size);
> > static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
> > @@ -698,21 +631,190 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf)
> > const struct kfd_device_info *device_info;
> > const struct kfd2kgd_calls *f2g;
> > struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
> > - unsigned int asic_type = adev->asic_type;
> > struct pci_dev *pdev = adev->pdev;
> >
> >
> > - if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
> > - || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
> > - dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
> > - return NULL; /* asic_type out of range */
> > + switch (adev->asic_type) {
> > +#ifdef KFD_SUPPORT_IOMMU_V2
> > +#ifdef CONFIG_DRM_AMDGPU_CIK
> > + case CHIP_KAVERI:
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &kaveri_device_info;
> > + f2g = &gfx_v7_kfd2kgd;
> > + break;
> > +#endif
> > + case CHIP_CARRIZO:
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &kaveri_device_info;
>
> That should probably be carrizo. Found with W=1.
Thanks. Fixed locally.
Alex
>
> > + f2g = &gfx_v8_kfd2kgd;
> > + break;
> > +#endif
> > +#ifdef CONFIG_DRM_AMDGPU_CIK
> > + case CHIP_HAWAII:
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &hawaii_device_info;
> > + f2g = &gfx_v7_kfd2kgd;
> > + break;
> > +#endif
> > + case CHIP_TONGA:
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &tonga_device_info;
> > + f2g = &gfx_v8_kfd2kgd;
> > + break;
> > + case CHIP_FIJI:
> > + if (vf)
> > + device_info = &fiji_vf_device_info;
> > + else
> > + device_info = &fiji_device_info;
> > + f2g = &gfx_v8_kfd2kgd;
> > + break;
> > + case CHIP_POLARIS10:
> > + if (vf)
> > + device_info = &polaris10_vf_device_info;
> > + else
> > + device_info = &polaris10_device_info;
> > + f2g = &gfx_v8_kfd2kgd;
> > + break;
> > + case CHIP_POLARIS11:
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &polaris11_device_info;
> > + f2g = &gfx_v8_kfd2kgd;
> > + break;
> > + case CHIP_POLARIS12:
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &polaris12_device_info;
> > + f2g = &gfx_v8_kfd2kgd;
> > + break;
> > + case CHIP_VEGAM:
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &vegam_device_info;
> > + f2g = &gfx_v8_kfd2kgd;
> > + break;
> > + default:
> > + switch (adev->ip_versions[GC_HWIP][0]) {
> > + case IP_VERSION(9, 0, 1):
> > + if (vf)
> > + device_info = &vega10_vf_device_info;
> > + else
> > + device_info = &vega10_device_info;
> > + f2g = &gfx_v9_kfd2kgd;
> > + break;
> > +#ifdef KFD_SUPPORT_IOMMU_V2
> > + case IP_VERSION(9, 1, 0):
> > + case IP_VERSION(9, 2, 2):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &raven_device_info;
> > + f2g = &gfx_v9_kfd2kgd;
> > + break;
> > +#endif
> > + case IP_VERSION(9, 2, 1):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &vega12_device_info;
> > + f2g = &gfx_v9_kfd2kgd;
> > + break;
> > + case IP_VERSION(9, 3, 0):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &renoir_device_info;
> > + f2g = &gfx_v9_kfd2kgd;
> > + break;
> > + case IP_VERSION(9, 4, 0):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &vega20_device_info;
> > + f2g = &gfx_v9_kfd2kgd;
> > + break;
> > + case IP_VERSION(9, 4, 1):
> > + device_info = &arcturus_device_info;
> > + f2g = &arcturus_kfd2kgd;
> > + break;
> > + case IP_VERSION(9, 4, 2):
> > + device_info = &aldebaran_device_info;
> > + f2g = &aldebaran_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 1, 10):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &navi10_device_info;
> > + f2g = &gfx_v10_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 1, 2):
> > + device_info = &navi12_device_info;
> > + f2g = &gfx_v10_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 1, 1):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &navi14_device_info;
> > + f2g = &gfx_v10_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 1, 3):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &cyan_skillfish_device_info;
> > + f2g = &gfx_v10_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 3, 0):
> > + device_info = &sienna_cichlid_device_info;
> > + f2g = &gfx_v10_3_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 3, 2):
> > + device_info = &navy_flounder_device_info;
> > + f2g = &gfx_v10_3_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 3, 1):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &vangogh_device_info;
> > + f2g = &gfx_v10_3_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 3, 4):
> > + device_info = &dimgrey_cavefish_device_info;
> > + f2g = &gfx_v10_3_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 3, 5):
> > + device_info = &beige_goby_device_info;
> > + f2g = &gfx_v10_3_kfd2kgd;
> > + break;
> > + case IP_VERSION(10, 3, 3):
> > + if (vf)
> > + device_info = NULL;
> > + else
> > + device_info = &yellow_carp_device_info;
> > + f2g = &gfx_v10_3_kfd2kgd;
> > + break;
> > + default:
> > + return NULL;
> > + }
> > + break;
> > }
> >
> >
> > - device_info = kfd_supported_devices[asic_type][vf];
> > - f2g = kfd2kgd_funcs[asic_type];
> > -
> > if (!device_info || !f2g) {
> > dev_err(kfd_device, "%s %s not supported in kfd\n",
> > - amdgpu_asic_name[asic_type], vf ? "VF" : "");
> > + amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
> > return NULL;
> > }
> >
> >
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version
2021-09-21 18:07 ` [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version Alex Deucher
2021-09-21 21:00 ` ernstp
@ 2021-09-22 16:55 ` Felix Kuehling
1 sibling, 0 replies; 106+ messages in thread
From: Felix Kuehling @ 2021-09-22 16:55 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
Am 2021-09-21 um 2:07 p.m. schrieb Alex Deucher:
> rather than asic type.
I think this works as a first step. I'd like to clean up KFD and replace
a lot of the asic_family-based conditions with IP-version-based
conditions in a follow-up patch series.
Regards,
Felix
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 254 +++++++++++++++++-------
> 1 file changed, 178 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index 9269b5e3aed1..25614a86b2c9 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -53,41 +53,6 @@ extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
> extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
> extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
>
> -static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
> -#ifdef KFD_SUPPORT_IOMMU_V2
> -#ifdef CONFIG_DRM_AMDGPU_CIK
> - [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
> -#endif
> - [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
> - [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
> -#endif
> -#ifdef CONFIG_DRM_AMDGPU_CIK
> - [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
> -#endif
> - [CHIP_TONGA] = &gfx_v8_kfd2kgd,
> - [CHIP_FIJI] = &gfx_v8_kfd2kgd,
> - [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
> - [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
> - [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
> - [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
> - [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
> - [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
> - [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
> - [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
> - [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
> - [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd,
> - [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
> - [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
> - [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
> - [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
> - [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
> - [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
> - [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd,
> - [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd,
> - [CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd,
> - [CHIP_CYAN_SKILLFISH] = &gfx_v10_kfd2kgd,
> -};
> -
> #ifdef KFD_SUPPORT_IOMMU_V2
> static const struct kfd_device_info kaveri_device_info = {
> .asic_family = CHIP_KAVERI,
> @@ -654,38 +619,6 @@ static const struct kfd_device_info cyan_skillfish_device_info = {
> .num_sdma_queues_per_engine = 8,
> };
>
> -/* For each entry, [0] is regular and [1] is virtualisation device. */
> -static const struct kfd_device_info *kfd_supported_devices[][2] = {
> -#ifdef KFD_SUPPORT_IOMMU_V2
> - [CHIP_KAVERI] = {&kaveri_device_info, NULL},
> - [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
> -#endif
> - [CHIP_RAVEN] = {&raven_device_info, NULL},
> - [CHIP_HAWAII] = {&hawaii_device_info, NULL},
> - [CHIP_TONGA] = {&tonga_device_info, NULL},
> - [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
> - [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
> - [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
> - [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
> - [CHIP_VEGAM] = {&vegam_device_info, NULL},
> - [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
> - [CHIP_VEGA12] = {&vega12_device_info, NULL},
> - [CHIP_VEGA20] = {&vega20_device_info, NULL},
> - [CHIP_RENOIR] = {&renoir_device_info, NULL},
> - [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
> - [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info},
> - [CHIP_NAVI10] = {&navi10_device_info, NULL},
> - [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
> - [CHIP_NAVI14] = {&navi14_device_info, NULL},
> - [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
> - [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
> - [CHIP_VANGOGH] = {&vangogh_device_info, NULL},
> - [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info},
> - [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info},
> - [CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL},
> - [CHIP_CYAN_SKILLFISH] = {&cyan_skillfish_device_info, NULL},
> -};
> -
> static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
> unsigned int chunk_size);
> static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
> @@ -698,21 +631,190 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf)
> const struct kfd_device_info *device_info;
> const struct kfd2kgd_calls *f2g;
> struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
> - unsigned int asic_type = adev->asic_type;
> struct pci_dev *pdev = adev->pdev;
>
> - if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
> - || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
> - dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
> - return NULL; /* asic_type out of range */
> + switch (adev->asic_type) {
> +#ifdef KFD_SUPPORT_IOMMU_V2
> +#ifdef CONFIG_DRM_AMDGPU_CIK
> + case CHIP_KAVERI:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &kaveri_device_info;
> + f2g = &gfx_v7_kfd2kgd;
> + break;
> +#endif
> + case CHIP_CARRIZO:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &kaveri_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> +#endif
> +#ifdef CONFIG_DRM_AMDGPU_CIK
> + case CHIP_HAWAII:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &hawaii_device_info;
> + f2g = &gfx_v7_kfd2kgd;
> + break;
> +#endif
> + case CHIP_TONGA:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &tonga_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_FIJI:
> + if (vf)
> + device_info = &fiji_vf_device_info;
> + else
> + device_info = &fiji_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_POLARIS10:
> + if (vf)
> + device_info = &polaris10_vf_device_info;
> + else
> + device_info = &polaris10_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_POLARIS11:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &polaris11_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_POLARIS12:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &polaris12_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + case CHIP_VEGAM:
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &vegam_device_info;
> + f2g = &gfx_v8_kfd2kgd;
> + break;
> + default:
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + if (vf)
> + device_info = &vega10_vf_device_info;
> + else
> + device_info = &vega10_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> +#ifdef KFD_SUPPORT_IOMMU_V2
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &raven_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> +#endif
> + case IP_VERSION(9, 2, 1):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &vega12_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> + case IP_VERSION(9, 3, 0):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &renoir_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> + case IP_VERSION(9, 4, 0):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &vega20_device_info;
> + f2g = &gfx_v9_kfd2kgd;
> + break;
> + case IP_VERSION(9, 4, 1):
> + device_info = &arcturus_device_info;
> + f2g = &arcturus_kfd2kgd;
> + break;
> + case IP_VERSION(9, 4, 2):
> + device_info = &aldebaran_device_info;
> + f2g = &aldebaran_kfd2kgd;
> + break;
> + case IP_VERSION(10, 1, 10):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &navi10_device_info;
> + f2g = &gfx_v10_kfd2kgd;
> + break;
> + case IP_VERSION(10, 1, 2):
> + device_info = &navi12_device_info;
> + f2g = &gfx_v10_kfd2kgd;
> + break;
> + case IP_VERSION(10, 1, 1):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &navi14_device_info;
> + f2g = &gfx_v10_kfd2kgd;
> + break;
> + case IP_VERSION(10, 1, 3):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &cyan_skillfish_device_info;
> + f2g = &gfx_v10_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 0):
> + device_info = &sienna_cichlid_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 2):
> + device_info = &navy_flounder_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 1):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &vangogh_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 4):
> + device_info = &dimgrey_cavefish_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 5):
> + device_info = &beige_goby_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + case IP_VERSION(10, 3, 3):
> + if (vf)
> + device_info = NULL;
> + else
> + device_info = &yellow_carp_device_info;
> + f2g = &gfx_v10_3_kfd2kgd;
> + break;
> + default:
> + return NULL;
> + }
> + break;
> }
>
> - device_info = kfd_supported_devices[asic_type][vf];
> - f2g = kfd2kgd_funcs[asic_type];
> -
> if (!device_info || !f2g) {
> dev_err(kfd_device, "%s %s not supported in kfd\n",
> - amdgpu_asic_name[asic_type], vf ? "VF" : "");
> + amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
> return NULL;
> }
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH 66/66] drm/amdgpu: add an option to override IP discovery table from a file
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (64 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version Alex Deucher
@ 2021-09-21 18:07 ` Alex Deucher
2021-09-22 7:54 ` [PATCH 00/66] Move to IP driven device enumeration Christian König
66 siblings, 0 replies; 106+ messages in thread
From: Alex Deucher @ 2021-09-21 18:07 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
If you set amdgpu.discovery=2 you can force the the driver to
fetch the IP discovery table from a file rather than from the
table shipped on the device. This is useful for debugging and
for device bring up and emulation when the tables may be in flux.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 24 +++++++++++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 821665fb73b0..7ff8b551b64f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -21,6 +21,8 @@
*
*/
+#include <linux/firmware.h>
+
#include "amdgpu.h"
#include "amdgpu_discovery.h"
#include "soc15_hw_ip.h"
@@ -67,6 +69,8 @@
#include "smuio_v11_0_6.h"
#include "smuio_v13_0.h"
+MODULE_FIRMWARE("amdgpu/ip_discovery.bin");
+
#define mmRCC_CONFIG_MEMSIZE 0xde3
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
@@ -206,6 +210,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)
struct binary_header *bhdr;
struct ip_discovery_header *ihdr;
struct gpu_info_header *ghdr;
+ const struct firmware *fw;
uint16_t offset;
uint16_t size;
uint16_t checksum;
@@ -216,10 +221,21 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)
if (!adev->mman.discovery_bin)
return -ENOMEM;
- r = amdgpu_discovery_read_binary(adev, adev->mman.discovery_bin);
- if (r) {
- DRM_ERROR("failed to read ip discovery binary\n");
- goto out;
+ if (amdgpu_discovery == 2) {
+ r = request_firmware(&fw, "amdgpu/ip_discovery.bin", adev->dev);
+ if (r)
+ goto get_from_vram;
+ dev_info(adev->dev, "Using IP discovery from file\n");
+ memcpy((u8 *)adev->mman.discovery_bin, (u8 *)fw->data,
+ adev->mman.discovery_tmr_size);
+ release_firmware(fw);
+ } else {
+get_from_vram:
+ r = amdgpu_discovery_read_binary(adev, adev->mman.discovery_bin);
+ if (r) {
+ DRM_ERROR("failed to read ip discovery binary\n");
+ goto out;
+ }
}
bhdr = (struct binary_header *)adev->mman.discovery_bin;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c7da1f7cc880..ec0a2fd7c163 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -628,7 +628,7 @@ module_param_named(mcbp, amdgpu_mcbp, int, 0444);
/**
* DOC: discovery (int)
* Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
- * (-1 = auto (default), 0 = disabled, 1 = enabled)
+ * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
*/
MODULE_PARM_DESC(discovery,
"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
--
2.31.1
^ permalink raw reply related [flat|nested] 106+ messages in thread* Re: [PATCH 00/66] Move to IP driven device enumeration
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
` (65 preceding siblings ...)
2021-09-21 18:07 ` [PATCH 66/66] drm/amdgpu: add an option to override IP discovery table from a file Alex Deucher
@ 2021-09-22 7:54 ` Christian König
2021-09-22 20:25 ` Alex Deucher
66 siblings, 1 reply; 106+ messages in thread
From: Christian König @ 2021-09-22 7:54 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
OMFG what mother of all patch sets.
Patches #1-#6, #12, #14-#15, #27, #31, #35-#36, #59-#60, #64, #66 are
Reviewed-by: Christian König <christian.koenig@amd.com>
Patches #7-#11, #13, #16-#26, #29-#30, #33-#34, #37-#50, #53, #55-#56,
#58, #62, #65 are Acked-by: Christian König <christian.koenig@amd.com>
Comment for patch #28:
Doesn't this one needs to come before #27?
Comment for patch #32:
Maybe adjust the commit subject, otherwise somebody could think it's a
revert the the previous patch.
Comment on patch #51, #52 and #61:
That looks just a little bit questionable. Could we clean that up or
would that be to much churn for little gain?
Comment on patch #54:
Looks like this is only adding SDMA instances and not VCN as said in the
subject.
Comment on patch #57:
Where is the removing of the harvest register access?
Comment on patch #63:
> case IP_VERSION(7, 2, 0):
> - amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
> + if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
> + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
Checking the IP version and then the chip type looks questionable. I
have an idea where this comes from, but please confirm with a comment.
Regards,
Christian.
Am 21.09.21 um 20:06 schrieb Alex Deucher:
> This patch set moves the driver to an IP driven discovery model
> rather than one tied to PCI device ids. This allows the
> GPU driver to claim all ATI PCI display class devices. The
> driver will then either load or not based on the IPs (GC, SDMA,
> DCN, VCN, etc.) that are enumerated on the device. All recent
> asics contain an IP discovery table which enumerates the
> number and version of all IPs on the board. This avoids the need
> to add new DIDs for new parts even if the driver would already
> otherwise support the new chip (i.e., support for all of the IPs
> are in place). It also better handles asics which have different
> numbers of instances of IPs. We can just use the IP discovery
> table rather than maintaining hardcoded information in the
> driver. Finally, we can avoid adding lots of asic type checks
> all over the driver to add a new asic if the IP version is
> already supported.
>
> Alex Deucher (64):
> drm/amdgpu: move headless sku check into harvest function
> drm/amdgpu: add debugfs access to the IP discovery table
> drm/amdgpu: store HW IP versions in the driver structure
> drm/amdgpu: fill in IP versions from IP discovery table
> drm/amdgpu: add XGMI HWIP
> drm/amdgpu/nv: export common IP functions
> drm/amdgpu: add initial IP enumeration via IP discovery table
> drm/amdgpu/sdma5.0: convert to IP version checking
> drm/amdgpu/sdma5.2: convert to IP version checking
> drm/amdgpu/gfx10: convert to IP version checking
> drm/amdgpu: filter out radeon PCI device IDs
> drm/amdgpu: bind to any 0x1002 PCI diplay class device
> drm/amdgpu/gmc10.0: convert to IP version checking
> drm/amdgpu: Use IP discovery to drive setting IP blocks by default
> drm/amdgpu: drive nav10 from the IP discovery table
> drm/amdgpu/gfxhub2.1: convert to IP version checking
> drm/amdgpu/mmhub2.0: convert to IP version checking
> drm/amdgpu/mmhub2.1: convert to IP version checking
> drm/amdgpu/vcn3.0: convert to IP version checking
> drm/amdgpu/athub2.0: convert to IP version checking
> drm/amdgpu/athub2.1: convert to IP version checking
> drm/amdgpu/navi10_ih: convert to IP version checking
> drm/amdgpu/amdgpu_smu: convert to IP version checking
> drm/amdgpu/smu11.0: convert to IP version checking
> drm/amdgpu/navi10_ppt: convert to IP version checking
> drm/amdgpu/sienna_cichlid_ppt: convert to IP version checking
> drm/amdgpu: drive all navi asics from the IP discovery table
> drm/amdgpu/nv: convert to IP version checking
> drm/amdgpu/display/dm: convert to IP version checking
> drm/amdgpu: add DCI HWIP
> drm/amdgpu: make soc15_common_ip_funcs static
> drm/amdgpu/soc15: export common IP functions
> drm/amdgpu: add initial IP discovery support for vega based parts
> drm/amdgpu/soc15: get rev_id in soc15_common_early_init
> drm/amdgpu: drive all vega asics from the IP discovery table
> drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support
> drm/amdgpu/display/dm: convert RAVEN to IP version checking
> drm/amdgpu/sdma4.0: convert to IP version checking
> drm/amdgpu/hdp4.0: convert to IP version checking
> drm/amdgpu/gfx9.0: convert to IP version checking
> drm/amdgpu/amdgpu_psp: convert to IP version checking
> drm/amdgpu/psp_v11.0: convert to IP version checking
> drm/amdgpu/psp_v13.0: convert to IP version checking
> drm/amdgpu/pm/smu_v11.0: update IP version checking
> drm/amdgpu/pm/smu_v13.0: convert IP version checking
> drm/amdgpu/pm/amdgpu_smu: convert more IP version checking
> drm/amdgpu/amdgpu_vcn: convert to IP version checking
> drm/amdgpu/vcn2.5: convert to IP version checking
> drm/amdgpu/soc15: convert to IP version checking
> drm/amdgpu: add VCN1 hardware IP
> drm/amdgpu: store all instances of IPs in the IP version table
> drm/amdgpu: get VCN and SDMA instances from IP discovery table
> drm/amdgpu/sdma: remove manual instance setting
> drm/amdgpu/vcn: remove manual instance setting
> drm/amdgpu: get VCN harvest information from IP discovery table
> drm/amdgpu/ucode: add default behavior
> drm/amdgpu: add new asic_type for IP discovery
> drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default
> drm/amdgpu: convert IP version array to include instances
> drm/amdgpu: clean up set IP function
> drm/amdgpu: add support for SRIOV in IP discovery path
> drm/amdkfd: clean up parameters in kgd2kfd_probe
> drm/amdkfd: convert kfd_device.c to use GC IP version
> drm/amdgpu: add an option to override IP discovery table from a file
>
> Guchun Chen (2):
> drm/amd/display: fix error case handling
> drm/amdgpu: add HWID of SDMA instance 2 and 3
>
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 5 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 818 +++++++++++++++++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 578 ++++++++++++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 101 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 7 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 47 +-
> drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 7 +-
> drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 9 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 380 ++++----
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 227 ++---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 91 +-
> drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 15 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 73 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 13 +-
> drivers/gpu/drm/amd/amdgpu/nv.c | 91 +-
> drivers/gpu/drm/amd/amdgpu/nv.h | 2 +
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 44 +-
> drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 100 +--
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 32 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 51 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 167 ++--
> drivers/gpu/drm/amd/amdgpu/soc15.h | 4 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 -
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 -
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 +-
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 259 ++++--
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 216 ++---
> drivers/gpu/drm/amd/include/soc15_hw_ip.h | 2 +
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 89 +-
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 50 +-
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 96 +-
> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 22 +-
> include/drm/amd_asic_type.h | 1 +
> 43 files changed, 2595 insertions(+), 1131 deletions(-)
>
^ permalink raw reply [flat|nested] 106+ messages in thread* Re: [PATCH 00/66] Move to IP driven device enumeration
2021-09-22 7:54 ` [PATCH 00/66] Move to IP driven device enumeration Christian König
@ 2021-09-22 20:25 ` Alex Deucher
2021-09-23 6:43 ` Christian König
0 siblings, 1 reply; 106+ messages in thread
From: Alex Deucher @ 2021-09-22 20:25 UTC (permalink / raw)
To: Christian König; +Cc: Alex Deucher, amd-gfx list
On Wed, Sep 22, 2021 at 3:54 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> OMFG what mother of all patch sets.
>
> Patches #1-#6, #12, #14-#15, #27, #31, #35-#36, #59-#60, #64, #66 are
> Reviewed-by: Christian König <christian.koenig@amd.com>
>
> Patches #7-#11, #13, #16-#26, #29-#30, #33-#34, #37-#50, #53, #55-#56,
> #58, #62, #65 are Acked-by: Christian König <christian.koenig@amd.com>
>
> Comment for patch #28:
>
> Doesn't this one needs to come before #27?
I've swapped them, but the order doesn't matter in this case as we
still set the asic_type for all existing chips so it will work either
way.
>
> Comment for patch #32:
>
> Maybe adjust the commit subject, otherwise somebody could think it's a
> revert the the previous patch.
I was thinking I could just apply 31 independently of what happens to
this patch set. I meant to split it out as a separate bug fix patch,
but it got lost in the other patches.
>
> Comment on patch #51, #52 and #61:
>
> That looks just a little bit questionable. Could we clean that up or
> would that be to much churn for little gain?
What did you have in mind? As I mentioned in the reply to Lijo, the
IP discovery table uses a mix of separate HWIDs and multiple instances
of the same HWID to handle instancing.
>
> Comment on patch #54:
>
> Looks like this is only adding SDMA instances and not VCN as said in the
> subject.
Fixed.
>
> Comment on patch #57:
>
> Where is the removing of the harvest register access?
fixed.
>
> Comment on patch #63:
>
> > case IP_VERSION(7, 2, 0):
> > - amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
> > + if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
> > + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
>
> Checking the IP version and then the chip type looks questionable. I
> have an idea where this comes from, but please confirm with a comment.
It's just because SR-IOV is only enabled on certain asics and that is
the way the old code looked. I guess I could drop the asic_type
checks. We'd never end up in with amdgpu_sriov_vf() returning true on
a asic without SR-IOV support in the first place.
Alex
>
> Regards,
> Christian.
>
> Am 21.09.21 um 20:06 schrieb Alex Deucher:
> > This patch set moves the driver to an IP driven discovery model
> > rather than one tied to PCI device ids. This allows the
> > GPU driver to claim all ATI PCI display class devices. The
> > driver will then either load or not based on the IPs (GC, SDMA,
> > DCN, VCN, etc.) that are enumerated on the device. All recent
> > asics contain an IP discovery table which enumerates the
> > number and version of all IPs on the board. This avoids the need
> > to add new DIDs for new parts even if the driver would already
> > otherwise support the new chip (i.e., support for all of the IPs
> > are in place). It also better handles asics which have different
> > numbers of instances of IPs. We can just use the IP discovery
> > table rather than maintaining hardcoded information in the
> > driver. Finally, we can avoid adding lots of asic type checks
> > all over the driver to add a new asic if the IP version is
> > already supported.
> >
> > Alex Deucher (64):
> > drm/amdgpu: move headless sku check into harvest function
> > drm/amdgpu: add debugfs access to the IP discovery table
> > drm/amdgpu: store HW IP versions in the driver structure
> > drm/amdgpu: fill in IP versions from IP discovery table
> > drm/amdgpu: add XGMI HWIP
> > drm/amdgpu/nv: export common IP functions
> > drm/amdgpu: add initial IP enumeration via IP discovery table
> > drm/amdgpu/sdma5.0: convert to IP version checking
> > drm/amdgpu/sdma5.2: convert to IP version checking
> > drm/amdgpu/gfx10: convert to IP version checking
> > drm/amdgpu: filter out radeon PCI device IDs
> > drm/amdgpu: bind to any 0x1002 PCI diplay class device
> > drm/amdgpu/gmc10.0: convert to IP version checking
> > drm/amdgpu: Use IP discovery to drive setting IP blocks by default
> > drm/amdgpu: drive nav10 from the IP discovery table
> > drm/amdgpu/gfxhub2.1: convert to IP version checking
> > drm/amdgpu/mmhub2.0: convert to IP version checking
> > drm/amdgpu/mmhub2.1: convert to IP version checking
> > drm/amdgpu/vcn3.0: convert to IP version checking
> > drm/amdgpu/athub2.0: convert to IP version checking
> > drm/amdgpu/athub2.1: convert to IP version checking
> > drm/amdgpu/navi10_ih: convert to IP version checking
> > drm/amdgpu/amdgpu_smu: convert to IP version checking
> > drm/amdgpu/smu11.0: convert to IP version checking
> > drm/amdgpu/navi10_ppt: convert to IP version checking
> > drm/amdgpu/sienna_cichlid_ppt: convert to IP version checking
> > drm/amdgpu: drive all navi asics from the IP discovery table
> > drm/amdgpu/nv: convert to IP version checking
> > drm/amdgpu/display/dm: convert to IP version checking
> > drm/amdgpu: add DCI HWIP
> > drm/amdgpu: make soc15_common_ip_funcs static
> > drm/amdgpu/soc15: export common IP functions
> > drm/amdgpu: add initial IP discovery support for vega based parts
> > drm/amdgpu/soc15: get rev_id in soc15_common_early_init
> > drm/amdgpu: drive all vega asics from the IP discovery table
> > drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support
> > drm/amdgpu/display/dm: convert RAVEN to IP version checking
> > drm/amdgpu/sdma4.0: convert to IP version checking
> > drm/amdgpu/hdp4.0: convert to IP version checking
> > drm/amdgpu/gfx9.0: convert to IP version checking
> > drm/amdgpu/amdgpu_psp: convert to IP version checking
> > drm/amdgpu/psp_v11.0: convert to IP version checking
> > drm/amdgpu/psp_v13.0: convert to IP version checking
> > drm/amdgpu/pm/smu_v11.0: update IP version checking
> > drm/amdgpu/pm/smu_v13.0: convert IP version checking
> > drm/amdgpu/pm/amdgpu_smu: convert more IP version checking
> > drm/amdgpu/amdgpu_vcn: convert to IP version checking
> > drm/amdgpu/vcn2.5: convert to IP version checking
> > drm/amdgpu/soc15: convert to IP version checking
> > drm/amdgpu: add VCN1 hardware IP
> > drm/amdgpu: store all instances of IPs in the IP version table
> > drm/amdgpu: get VCN and SDMA instances from IP discovery table
> > drm/amdgpu/sdma: remove manual instance setting
> > drm/amdgpu/vcn: remove manual instance setting
> > drm/amdgpu: get VCN harvest information from IP discovery table
> > drm/amdgpu/ucode: add default behavior
> > drm/amdgpu: add new asic_type for IP discovery
> > drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default
> > drm/amdgpu: convert IP version array to include instances
> > drm/amdgpu: clean up set IP function
> > drm/amdgpu: add support for SRIOV in IP discovery path
> > drm/amdkfd: clean up parameters in kgd2kfd_probe
> > drm/amdkfd: convert kfd_device.c to use GC IP version
> > drm/amdgpu: add an option to override IP discovery table from a file
> >
> > Guchun Chen (2):
> > drm/amd/display: fix error case handling
> > drm/amdgpu: add HWID of SDMA instance 2 and 3
> >
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 5 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 818 +++++++++++++++++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 1 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 578 ++++++++++++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 101 ++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 7 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 47 +-
> > drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 7 +-
> > drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 9 +-
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 380 ++++----
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 227 ++---
> > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 6 +-
> > drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 91 +-
> > drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 15 +-
> > drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 73 +-
> > drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 6 +-
> > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 13 +-
> > drivers/gpu/drm/amd/amdgpu/nv.c | 91 +-
> > drivers/gpu/drm/amd/amdgpu/nv.h | 2 +
> > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 44 +-
> > drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 14 +-
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 100 +--
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 32 +-
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 51 +-
> > drivers/gpu/drm/amd/amdgpu/soc15.c | 167 ++--
> > drivers/gpu/drm/amd/amdgpu/soc15.h | 4 +-
> > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 -
> > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 -
> > drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +-
> > drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_device.c | 259 ++++--
> > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 216 ++---
> > drivers/gpu/drm/amd/include/soc15_hw_ip.h | 2 +
> > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 89 +-
> > .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 50 +-
> > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
> > .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 96 +-
> > .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 22 +-
> > include/drm/amd_asic_type.h | 1 +
> > 43 files changed, 2595 insertions(+), 1131 deletions(-)
> >
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH 00/66] Move to IP driven device enumeration
2021-09-22 20:25 ` Alex Deucher
@ 2021-09-23 6:43 ` Christian König
0 siblings, 0 replies; 106+ messages in thread
From: Christian König @ 2021-09-23 6:43 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, amd-gfx list
Am 22.09.21 um 22:25 schrieb Alex Deucher:
> On Wed, Sep 22, 2021 at 3:54 AM Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>> [SNIP]
>> Comment for patch #32:
>>
>> Maybe adjust the commit subject, otherwise somebody could think it's a
>> revert the the previous patch.
> I was thinking I could just apply 31 independently of what happens to
> this patch set. I meant to split it out as a separate bug fix patch,
> but it got lost in the other patches.
Good point. I suggest to just push it to amd-staging-drm-next ASAP and
not consider it part of this set any more.
>> Comment on patch #51, #52 and #61:
>>
>> That looks just a little bit questionable. Could we clean that up or
>> would that be to much churn for little gain?
> What did you have in mind? As I mentioned in the reply to Lijo, the
> IP discovery table uses a mix of separate HWIDs and multiple instances
> of the same HWID to handle instancing.
Patch #52 adds something like: "adev->ip_versions[hw_ip +
ip->number_instance] =..."
While patch #61 then cleans that up towards:
"adev->ip_versions[hw_ip][ip->number_instance] =..."
It would be nice to have some clean concept which handles all of the
hw_ip oddies gracefully in the first place. And then add what you wrote
to Lijo as comment somewhere as well.
Not a must have, but I think it would make things a bit cleaner and more
review- and maintain-able.
>> Comment on patch #63:
>>
>>> case IP_VERSION(7, 2, 0):
>>> - amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
>>> + if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
>>> + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
>> Checking the IP version and then the chip type looks questionable. I
>> have an idea where this comes from, but please confirm with a comment.
> It's just because SR-IOV is only enabled on certain asics and that is
> the way the old code looked. I guess I could drop the asic_type
> checks. We'd never end up in with amdgpu_sriov_vf() returning true on
> a asic without SR-IOV support in the first place.
Yeah, either that our just add something like "SRIOV is only enabled on
certain asics" as comment.
Christian.
>
> Alex
>
^ permalink raw reply [flat|nested] 106+ messages in thread