* [PATCH v4 00/11] Initial Meteorlake Support
@ 2022-09-02 6:03 Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
` (10 more replies)
0 siblings, 11 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
The PCI Id's and platform definition are posted earlier.
This series adds handful of early enablement patches including
support for display power wells, VBT and AUX Channel mapping,
PCH and gmbus support, dbus, mbus, sagv and memory bandwidth support.
This series also add the support for a new way to read Graphics,
Media and Display versions
This is based out of the earlier series posted at [1]. Several
of the patches from the earlier series got merged. This version is
rebased on top of the earlier patches that got merged.
[1] https://patchwork.freedesktop.org/series/106786/
Imre Deak (2):
drm/i915/mtl: Add display power wells
drm/i915/mtl: Add DP AUX support on TypeC ports
José Roberto de Souza (1):
drm/i915: Parse and set stepping for platforms with GMD
Madhumitha Tolakanahalli Pradeep (1):
drm/i915/mtl: Update CHICKEN_TRANS* register addresses
Matt Roper (2):
drm/i915: Read graphics/media/display arch version from hw
drm/i915/mtl: Define engine context layouts
Radhakrishna Sripada (5):
drm/i915: Move display and media IP version to runtime info
drm/i915/mtl: Add gmbus and gpio support
drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox
drm/i915/mtl: Update MBUS_DBOX credits
drm/i915/mtl: Do not update GV point, mask value
drivers/gpu/drm/i915/display/intel_bw.c | 42 ++++++-
drivers/gpu/drm/i915/display/intel_display.c | 14 ++-
.../i915/display/intel_display_power_map.c | 115 +++++++++++++++++-
.../i915/display/intel_display_power_well.c | 44 +++++++
.../i915/display/intel_display_power_well.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_aux.c | 53 +++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++
drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 81 +++++++++++-
drivers/gpu/drm/i915/i915_driver.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 16 +--
drivers/gpu/drm/i915/i915_pci.c | 39 +++---
drivers/gpu/drm/i915/i915_reg.h | 83 ++++++++++++-
drivers/gpu/drm/i915/intel_device_info.c | 102 ++++++++++++++--
drivers/gpu/drm/i915/intel_device_info.h | 27 ++--
drivers/gpu/drm/i915/intel_dram.c | 41 ++++++-
drivers/gpu/drm/i915/intel_pm.c | 73 ++++++++++-
drivers/gpu/drm/i915/intel_step.c | 60 +++++++++
21 files changed, 754 insertions(+), 72 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-02 16:49 ` kernel test robot
2022-09-02 22:10 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
` (9 subsequent siblings)
10 siblings, 2 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Future platforms can read the IP version from a register and the
IP version numbers need not be hard coded in device info. Move the
ip version for media and display to runtime info.
On platforms where hard coding of IP version is required, update
the IP version in __runtime under device_info.
v2:
- Avoid name collision for ip versions(Jani)
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 14 ++++-----
drivers/gpu/drm/i915/i915_pci.c | 38 ++++++++++++------------
drivers/gpu/drm/i915/intel_device_info.c | 28 ++++++++++-------
drivers/gpu/drm/i915/intel_device_info.h | 15 ++++++----
4 files changed, 53 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9cca165bf5d..f85a470397a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -469,19 +469,19 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
-#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ver)
-#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ver, \
- RUNTIME_INFO(i915)->graphics.rel)
+#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.version.ver)
+#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.version.ver, \
+ RUNTIME_INFO(i915)->graphics.version.rel)
#define IS_GRAPHICS_VER(i915, from, until) \
(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
-#define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver)
-#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.ver, \
- INTEL_INFO(i915)->media.rel)
+#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.version.ver)
+#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.version.ver, \
+ RUNTIME_INFO(i915)->media.version.rel)
#define IS_MEDIA_VER(i915, from, until) \
(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
-#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
+#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.version.ver)
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 26b25d9434d6..f6aaf938c53c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -34,9 +34,9 @@
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
- .__runtime.graphics.ver = (x), \
- .media.ver = (x), \
- .display.ver = (x)
+ .__runtime.graphics.version.ver = (x), \
+ .__runtime.media.version.ver = (x), \
+ .__runtime.display.version.ver = (x)
#define I845_PIPE_OFFSETS \
.display.pipe_offsets = { \
@@ -740,7 +740,7 @@ static const struct intel_device_info bxt_info = {
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
- .display.ver = 10,
+ .__runtime.display.version.ver = 10,
.display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
GLK_COLORS,
};
@@ -919,7 +919,7 @@ static const struct intel_device_info rkl_info = {
static const struct intel_device_info dg1_info = {
GEN12_FEATURES,
DGFX_FEATURES,
- .__runtime.graphics.rel = 10,
+ .__runtime.graphics.version.rel = 10,
PLATFORM(INTEL_DG1),
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.require_force_probe = 1,
@@ -962,7 +962,7 @@ static const struct intel_device_info adl_s_info = {
.display.has_hotplug = 1, \
.display.has_ipc = 1, \
.display.has_psr = 1, \
- .display.ver = 13, \
+ .__runtime.display.version.ver = 13, \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
.display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
@@ -1006,8 +1006,8 @@ static const struct intel_device_info adl_p_info = {
I915_GTT_PAGE_SIZE_2M
#define XE_HP_FEATURES \
- .__runtime.graphics.ver = 12, \
- .__runtime.graphics.rel = 50, \
+ .__runtime.graphics.version.ver = 12, \
+ .__runtime.graphics.version.rel = 50, \
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_3d_pipeline = 1, \
@@ -1027,8 +1027,8 @@ static const struct intel_device_info adl_p_info = {
.__runtime.ppgtt_type = INTEL_PPGTT_FULL
#define XE_HPM_FEATURES \
- .media.ver = 12, \
- .media.rel = 50
+ .__runtime.media.version.ver = 12, \
+ .__runtime.media.version.rel = 50
__maybe_unused
static const struct intel_device_info xehpsdv_info = {
@@ -1053,8 +1053,8 @@ static const struct intel_device_info xehpsdv_info = {
XE_HP_FEATURES, \
XE_HPM_FEATURES, \
DGFX_FEATURES, \
- .__runtime.graphics.rel = 55, \
- .media.rel = 55, \
+ .__runtime.graphics.version.rel = 55, \
+ .__runtime.media.version.rel = 55, \
PLATFORM(INTEL_DG2), \
.has_4tile = 1, \
.has_64k_pages = 1, \
@@ -1097,8 +1097,8 @@ static const struct intel_device_info pvc_info = {
XE_HPC_FEATURES,
XE_HPM_FEATURES,
DGFX_FEATURES,
- .__runtime.graphics.rel = 60,
- .media.rel = 60,
+ .__runtime.graphics.version.rel = 60,
+ .__runtime.media.version.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
.display = { 0 },
.has_flat_ccs = 0,
@@ -1111,7 +1111,7 @@ static const struct intel_device_info pvc_info = {
#define XE_LPDP_FEATURES \
XE_LPD_FEATURES, \
- .display.ver = 14, \
+ .__runtime.display.version.ver = 14, \
.display.has_cdclk_crawl = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
@@ -1123,9 +1123,9 @@ static const struct intel_device_info mtl_info = {
* Real graphics IP version will be obtained from hardware GMD_ID
* register. Value provided here is just for sanity checking.
*/
- .__runtime.graphics.ver = 12,
- .__runtime.graphics.rel = 70,
- .media.ver = 13,
+ .__runtime.graphics.version.ver = 12,
+ .__runtime.graphics.version.rel = 70,
+ .__runtime.media.version.ver = 13,
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
.has_flat_ccs = 0,
@@ -1281,7 +1281,7 @@ bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
{
- int gttmmaddr_bar = intel_info->__runtime.graphics.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
+ int gttmmaddr_bar = intel_info->__runtime.graphics.version.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
return i915_pci_resource_valid(pdev, gttmmaddr_bar);
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0a1f97b35f2b..56f19683dd55 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -92,21 +92,29 @@ void intel_device_info_print(const struct intel_device_info *info,
const struct intel_runtime_info *runtime,
struct drm_printer *p)
{
- if (runtime->graphics.rel)
- drm_printf(p, "graphics version: %u.%02u\n", runtime->graphics.ver,
- runtime->graphics.rel);
+ if (runtime->graphics.version.rel)
+ drm_printf(p, "graphics version: %u.%02u\n",
+ runtime->graphics.version.ver,
+ runtime->graphics.version.rel);
else
- drm_printf(p, "graphics version: %u\n", runtime->graphics.ver);
+ drm_printf(p, "graphics version: %u\n",
+ runtime->graphics.version.ver);
- if (info->media.rel)
- drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel);
+ if (runtime->media.version.rel)
+ drm_printf(p, "media version: %u.%02u\n",
+ runtime->media.version.ver,
+ runtime->media.version.rel);
else
- drm_printf(p, "media version: %u\n", info->media.ver);
+ drm_printf(p, "media version: %u\n",
+ runtime->media.version.ver);
- if (info->display.rel)
- drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel);
+ if (runtime->display.version.rel)
+ drm_printf(p, "display version: %u.%02u\n",
+ runtime->display.version.ver,
+ runtime->display.version.rel);
else
- drm_printf(p, "display version: %u\n", info->display.ver);
+ drm_printf(p, "display version: %u\n",
+ runtime->display.version.ver);
drm_printf(p, "gt: %d\n", info->gt);
drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6904ad03ca19..d36cf25f1d5f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -200,7 +200,15 @@ struct ip_version {
};
struct intel_runtime_info {
- struct ip_version graphics;
+ struct {
+ struct ip_version version;
+ } graphics;
+ struct {
+ struct ip_version version;
+ } media;
+ struct {
+ struct ip_version version;
+ } display;
/*
* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
@@ -246,8 +254,6 @@ struct intel_runtime_info {
};
struct intel_device_info {
- struct ip_version media;
-
enum intel_platform platform;
unsigned int dma_mask_size; /* available DMA address bits */
@@ -259,9 +265,6 @@ struct intel_device_info {
#undef DEFINE_FLAG
struct {
- u8 ver;
- u8 rel;
-
u8 abox_mask;
struct {
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-07 20:49 ` [Intel-gfx] " Lucas De Marchi
2022-09-07 23:32 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
` (8 subsequent siblings)
10 siblings, 2 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Matt Roper <matthew.d.roper@intel.com>
Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space. New hardware programming
styles, features, and workarounds should be conditional solely on the
architecture version, and should no longer be derived from the PCI
device ID, revision ID, or platform-specific feature flags.
Bspec: 63361, 64111
v2:
- Move the IP version readout to intel_device_info.c
- Convert the macro into a function
v3:
- Move subplatform init to runtime early init
- Cache runtime ver, release info to compare with hardware values.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
drivers/gpu/drm/i915/i915_driver.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 7 +++
drivers/gpu/drm/i915/intel_device_info.c | 74 +++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
7 files changed, 98 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..579da62158c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -39,6 +39,8 @@
#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
+#define GMD_ID_GRAPHICS _MMIO(0xd8c)
+
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
#define SF_MCR_SELECTOR _MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 56a2bcddb2af..a1ab49521d19 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
- intel_device_info_subplatform_init(dev_priv);
+ intel_device_info_runtime_init_early(dev_priv);
+
intel_step_init(dev_priv);
intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f85a470397a5..405b59b8c05c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
+#define HAS_GMD_ID(i915) INTEL_INFO(i915)->has_gmd_id
+
#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f6aaf938c53c..4672894f4bc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
.has_flat_ccs = 0,
+ .has_gmd_id = 1,
.has_snoop = 1,
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e6239864c35..e02e461a4b5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5798,6 +5798,11 @@
#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
+#define GMD_ID_DISPLAY _MMIO(0x510a0)
+#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
+#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
+#define GMD_ID_STEP REG_GENMASK(5, 0)
+
/*GEN11 chicken */
#define _PIPEA_CHICKEN 0x70038
#define _PIPEB_CHICKEN 0x71038
@@ -8298,4 +8303,6 @@ enum skl_power_gate {
#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
+#define MTL_MEDIA_GSI_BASE 0x380000
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 56f19683dd55..a5bafc9be1fa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -29,6 +29,7 @@
#include "display/intel_cdclk.h"
#include "display/intel_de.h"
+#include "gt/intel_gt_regs.h"
#include "intel_device_info.h"
#include "i915_drv.h"
#include "i915_utils.h"
@@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p, unsigned int num)
return false;
}
-void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
{
const struct intel_device_info *info = INTEL_INFO(i915);
const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
@@ -288,6 +289,77 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
}
+static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct ip_version *ip)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ void __iomem *addr;
+ u32 val;
+ u8 ver = ip->ver;
+ u8 rel = ip->rel;
+
+ addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
+ if (drm_WARN_ON(&i915->drm, !addr))
+ return;
+
+ val = ioread32(addr);
+ pci_iounmap(pdev, addr);
+
+ ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
+ ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
+ ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
+
+ /* Sanity check against expected versions from device info */
+ if (ip->ver != ver || ip->rel > rel)
+ drm_dbg(&i915->drm,
+ "Hardware reports GMD IP version %u.%u but minimum expected is %u.%u\n",
+ ip->ver, ip->rel, ver, rel);
+}
+
+/**
+ * Setup the graphics version for the current device. This must be done before
+ * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
+ * function should be called very early in the driver initialization sequence.
+ *
+ * Regular MMIO access is not yet setup at the point this function is called so
+ * we peek at the appropriate MMIO offset directly. The GMD_ID register is
+ * part of an 'always on' power well by design, so we don't need to worry about
+ * forcewake while reading it.
+ */
+static void intel_ipver_early_init(struct drm_i915_private *i915)
+{
+ struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
+
+ if (!HAS_GMD_ID(i915))
+ return;
+
+ ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
+ &runtime->graphics.version);
+ ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
+ &runtime->display.version);
+ ip_ver_read(i915, MTL_MEDIA_GSI_BASE + i915_mmio_reg_offset(GMD_ID_GRAPHICS),
+ &runtime->media.version);
+}
+
+/**
+ * intel_device_info_runtime_init_early - initialize early runtime info
+ * @i915: the i915 device
+ *
+ * Determine early intel_device_info fields at runtime.
+ *
+ * Use it when:
+ * - Early init of certain runtime info fields are to be initialized
+ *
+ * This function needs to be called:
+ * - before the MMIO has been setup as we are reading registers,
+ * - before the PCH has been detected,
+ * - before the first usage of the fields it can tweak.
+ */
+void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
+{
+ intel_ipver_early_init(i915);
+ intel_device_info_subplatform_init(i915);
+}
+
/**
* intel_device_info_runtime_init - initialize runtime info
* @dev_priv: the i915 device
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d36cf25f1d5f..4a938cb897d0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -152,6 +152,7 @@ enum intel_ppgtt_type {
func(has_4tile); \
func(has_flat_ccs); \
func(has_global_mocs); \
+ func(has_gmd_id); \
func(has_gt_uc); \
func(has_heci_pxp); \
func(has_heci_gscfi); \
@@ -197,9 +198,18 @@ enum intel_ppgtt_type {
struct ip_version {
u8 ver;
u8 rel;
+ u8 step;
};
struct intel_runtime_info {
+ /*
+ * On modern platforms, the architecture major.minor version numbers
+ * and stepping are read directly from the hardware rather than derived
+ * from the PCI device and revision ID's.
+ *
+ * Note that the hardware gives us a single "graphics" number that
+ * should represent render, compute, and copy behavior.
+ */
struct {
struct ip_version version;
} graphics;
@@ -305,7 +315,7 @@ struct intel_driver_caps {
const char *intel_platform_name(enum intel_platform platform);
-void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
+void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_print(const struct intel_device_info *info,
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-08 17:42 ` [Intel-gfx] " Matt Roper
2022-09-02 6:03 ` [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
` (7 subsequent siblings)
10 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: José Roberto de Souza <jose.souza@intel.com>
The GMD step field do not properly match the current stepping convention
that we use(STEP_A0, STEP_A1, STEP_B0...).
One platform could have { arch = 12, rel = 70, step = 1 } and the
actual stepping is STEP_B0 but without the translation of the step
field would mean STEP_A1.
That is why we will need to have gmd_to_intel_step tables for each IP.
v2:
- Pass the updated ip version structure
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_step.c | 60 +++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 42b3133d8387..14ea103d6dab 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -135,6 +135,48 @@ static const struct intel_step_info adlp_n_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
};
+struct gmd_to_intel_step {
+ struct ip_version gmd;
+ enum intel_step step;
+};
+
+static const struct gmd_to_intel_step gmd_graphics_table[] = {
+ { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
+ { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 4, .step = STEP_B0 },
+ { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static const struct gmd_to_intel_step gmd_media_table[] = {
+ { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static const struct gmd_to_intel_step gmd_display_table[] = {
+ { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static u8 gmd_to_intel_step(struct drm_i915_private *i915,
+ struct ip_version *gmd,
+ const struct gmd_to_intel_step *table,
+ int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (table[i].gmd.ver == gmd->ver &&
+ table[i].gmd.rel == gmd->rel &&
+ table[i].gmd.step == gmd->step)
+ return table[i].step;
+ }
+
+ drm_dbg(&i915->drm, "Using future steppings\n");
+ return STEP_FUTURE;
+}
+
static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
void intel_step_init(struct drm_i915_private *i915)
@@ -144,6 +186,24 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
+ if (HAS_GMD_ID(i915)) {
+ step.graphics_step = gmd_to_intel_step(i915,
+ &RUNTIME_INFO(i915)->graphics.version,
+ gmd_graphics_table,
+ ARRAY_SIZE(gmd_graphics_table));
+ step.media_step = gmd_to_intel_step(i915,
+ &RUNTIME_INFO(i915)->media.version,
+ gmd_media_table,
+ ARRAY_SIZE(gmd_media_table));
+ step.display_step = gmd_to_intel_step(i915,
+ &RUNTIME_INFO(i915)->display.version,
+ gmd_display_table,
+ ARRAY_SIZE(gmd_display_table));
+ RUNTIME_INFO(i915)->step = step;
+
+ return;
+ }
+
if (IS_PONTEVECCHIO(i915)) {
pvc_step_init(i915, revid);
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
` (2 preceding siblings ...)
2022-09-02 6:03 ` [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-06 12:16 ` Balasubramani Vivekanandan
2022-09-07 23:33 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
` (6 subsequent siblings)
10 siblings, 2 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Matt Roper <matthew.d.roper@intel.com>
The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.
For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.
v2:
- Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
- Drop unused registers in mtl rcs offsets.(Bala)
Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 81 ++++++++++++++++++++++++++++-
1 file changed, 79 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4..ecb030ee39cd 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,38 @@ static const u8 dg2_xcs_offsets[] = {
END
};
+static const u8 mtl_xcs_offsets[] = {
+ NOP(1),
+ LRI(13, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ END
+};
+
static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -606,6 +638,47 @@ static const u8 dg2_rcs_offsets[] = {
END
};
+static const u8 mtl_rcs_offsets[] = {
+ NOP(1),
+ LRI(13, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ NOP(2),
+ LRI(2, POSTED),
+ REG16(0x5a8),
+ REG16(0x5ac),
+
+ NOP(6),
+ LRI(1, 0),
+ REG(0x0c8),
+
+ END
+};
+
#undef END
#undef REG16
#undef REG
@@ -624,7 +697,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
!intel_engine_has_relative_mmio(engine));
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_rcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
@@ -637,7 +712,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
else
return gen8_rcs_offsets;
} else {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_xcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
` (3 preceding siblings ...)
2022-09-02 6:03 ` [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-08 13:05 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-09-08 18:02 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 06/11] drm/i915/mtl: Add display power wells Radhakrishna Sripada
` (5 subsequent siblings)
10 siblings, 2 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
GPIO_CTL[9-12] are mapped to TC ports.
v2:
- Drop unused GPIO pins(MattR)
BSpec: 49306
Cc: Matt Roper <matthew.d.roper@intel.com>
Original Author: Brian J Lovin
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++++
drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6f6cfccad477..74443f57f62d 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -117,6 +117,18 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
};
+static const struct gmbus_pin gmbus_pins_mtp[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+ [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+ [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+ [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+ [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+};
+
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
unsigned int pin)
{
@@ -129,6 +141,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
pins = gmbus_pins_dg1;
size = ARRAY_SIZE(gmbus_pins_dg1);
+ } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
+ pins = gmbus_pins_mtp;
+ size = ARRAY_SIZE(gmbus_pins_mtp);
} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
pins = gmbus_pins_icp;
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
index 8edc2e99cf53..20f704bd4e70 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
@@ -24,6 +24,7 @@ struct i2c_adapter;
#define GMBUS_PIN_2_BXT 2
#define GMBUS_PIN_3_BXT 3
#define GMBUS_PIN_4_CNP 4
+#define GMBUS_PIN_5_MTP 5
#define GMBUS_PIN_9_TC1_ICP 9
#define GMBUS_PIN_10_TC2_ICP 10
#define GMBUS_PIN_11_TC3_ICP 11
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 06/11] drm/i915/mtl: Add display power wells
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
` (4 preceding siblings ...)
2022-09-02 6:03 ` [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-08 18:07 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
` (4 subsequent siblings)
10 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Imre Deak <imre.deak@intel.com>
Add support for display power wells on MTL. The differences from XE_LPD:
- The AUX HW block is moved to the PICA block, where the registers are on
an always-on power well and the functionality needs to be powered on/off
via the AUX_CH_CTL register: [1], [2]
- The DDI IO power on/off programming sequence is moved to the PHY PLL
enable/disable sequence. [3], [4], [5]
Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
v2:
- Update the comment in aux power well enable
- Reuse the noop sync fn for aux sync.
- Use REG_BIT for new register bit definitions
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
.../i915/display/intel_display_power_map.c | 115 +++++++++++++++++-
.../i915/display/intel_display_power_well.c | 44 +++++++
.../i915/display/intel_display_power_well.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++
drivers/gpu/drm/i915/i915_reg.h | 21 ++++
5 files changed, 191 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 5ddd1b93751c..dc04afc6cc8f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list xelpd_power_wells[] = {
I915_PW_DESCRIPTORS(xelpd_power_wells_main),
};
+/*
+ * MTL is based on XELPD power domains with the exception of power gating for:
+ * - DDI_IO (moved to PLL logic)
+ * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on)
+ */
+#define XELPDP_PW_2_POWER_DOMAINS \
+ XELPD_PW_B_POWER_DOMAINS, \
+ XELPD_PW_C_POWER_DOMAINS, \
+ XELPD_PW_D_POWER_DOMAINS, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
+ XELPDP_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
+ XELPDP_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_TBT1);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_TBT2);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_TBT3);
+
+I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_TBT4);
+
+static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
+ {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &xelpdp_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
+ .ops = &gen9_dc_off_power_well_ops,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &xelpdp_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
+ .ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .has_fuses = true,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_A", &xelpd_pwdoms_pw_a,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
+ ),
+ .ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_A),
+ .has_fuses = true,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_B", &xelpd_pwdoms_pw_b,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
+ ),
+ .ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_fuses = true,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_C", &xelpd_pwdoms_pw_c,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
+ ),
+ .ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_C),
+ .has_fuses = true,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_D", &xelpd_pwdoms_pw_d,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
+ ),
+ .ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_D),
+ .has_fuses = true,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),
+ I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),
+ I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),
+ I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3),
+ I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4),
+ ),
+ .ops = &xelpdp_aux_power_well_ops,
+ },
+};
+
+static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1457,7 +1568,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
return 0;
}
- if (DISPLAY_VER(i915) >= 13)
+ if (DISPLAY_VER(i915) >= 14)
+ return set_power_wells(power_domains, xelpdp_power_wells);
+ else if (DISPLAY_VER(i915) >= 13)
return set_power_wells(power_domains, xelpd_power_wells);
else if (IS_DG1(i915))
return set_power_wells(power_domains, dg1_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 29cc05c04c65..9bf98a37204b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1798,6 +1798,43 @@ tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
return intel_power_well_refcount(power_well);
}
+static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+
+ intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
+ XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
+
+ /*
+ * The power status flag cannot be used to determine whether aux
+ * power wells have finished powering up. Instead we're
+ * expected to just wait a fixed 600us after raising the request
+ * bit.
+ */
+ usleep_range(600, 1200);
+}
+
+static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+
+ intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
+ 0);
+ usleep_range(10, 30);
+}
+
+static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+
+ return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
+ XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
+}
const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
@@ -1911,3 +1948,10 @@ const struct i915_power_well_ops tgl_tc_cold_off_ops = {
.disable = tgl_tc_cold_off_power_well_disable,
.is_enabled = tgl_tc_cold_off_power_well_is_enabled,
};
+
+const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = xelpdp_aux_power_well_enable,
+ .disable = xelpdp_aux_power_well_disable,
+ .is_enabled = xelpdp_aux_power_well_enabled,
+};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 31a898176ebb..e13b521e322a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -80,6 +80,9 @@ struct i915_power_well_instance {
*/
u8 idx;
} hsw;
+ struct {
+ u8 aux_ch;
+ } xelpdp;
};
};
@@ -169,5 +172,6 @@ extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
extern const struct i915_power_well_ops icl_aux_power_well_ops;
extern const struct i915_power_well_ops icl_ddi_power_well_ops;
extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
+extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index f2ad1d09ab43..98bd33645b43 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -150,6 +150,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
u32 unused)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
u32 ret;
/*
@@ -170,6 +171,13 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
if (intel_tc_port_in_tbt_alt_mode(dig_port))
ret |= DP_AUX_CH_CTL_TBT_IO;
+ /*
+ * Power request bit is already set during aux power well enable.
+ * Preserve the bit across aux transactions.
+ */
+ if (DISPLAY_VER(i915) >= 14)
+ ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST;
+
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e02e461a4b5d..99b2cd2abca4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3451,6 +3451,25 @@
#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
+#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
+#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
+#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
+#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
+
+#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
+#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
+#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
+#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
+
+#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
+ _DPA_AUX_CH_CTL, \
+ _DPB_AUX_CH_CTL, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_CTL, \
+ _XELPDP_USBC2_AUX_CH_CTL, \
+ _XELPDP_USBC3_AUX_CH_CTL, \
+ _XELPDP_USBC4_AUX_CH_CTL))
+
#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
#define DP_AUX_CH_CTL_DONE (1 << 30)
#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
@@ -3463,6 +3482,8 @@
#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
+#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
+#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
` (5 preceding siblings ...)
2022-09-02 6:03 ` [PATCH v4 06/11] drm/i915/mtl: Add display power wells Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-08 18:13 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 08/11] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
` (3 subsequent siblings)
10 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Imre Deak <imre.deak@intel.com>
On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
changed wrt. previous platforms, adjust the code accordingly.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 ++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 9 +++++
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 98bd33645b43..48c375c65a41 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -637,6 +637,46 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
}
}
+static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XELPDP_DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
void intel_dp_aux_fini(struct intel_dp *intel_dp)
{
if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
@@ -652,7 +692,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_encoder *encoder = &dig_port->base;
enum aux_ch aux_ch = dig_port->aux_ch;
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
} else if (DISPLAY_VER(dev_priv) >= 9) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 99b2cd2abca4..4ec6a3dd1f2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3470,6 +3470,15 @@
_XELPDP_USBC3_AUX_CH_CTL, \
_XELPDP_USBC4_AUX_CH_CTL))
+#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
+ _DPA_AUX_CH_DATA1, \
+ _DPB_AUX_CH_DATA1, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_DATA1, \
+ _XELPDP_USBC2_AUX_CH_DATA1, \
+ _XELPDP_USBC3_AUX_CH_DATA1, \
+ _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+
#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
#define DP_AUX_CH_CTL_DONE (1 << 30)
#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 08/11] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
` (6 preceding siblings ...)
2022-09-02 6:03 ` [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
` (2 subsequent siblings)
10 siblings, 0 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From Meteorlake, Latency Level, SAGV bloack time are read from
LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type
and QGV information are also to be read from Mem SS registers.
v2:
- Simplify MTL_MEM_SS_INFO_QGV_POINT macro(MattR)
- Nit: Rearrange the bit def's from higher to lower(MattR)
- Restore platform definition for ADL-P(MattR)
- Move back intel_qgv_point def to intel_bw.c(Jani)
Bspec: 64636, 64608
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Original Author: Caz Yokoyama
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 42 ++++++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++
drivers/gpu/drm/i915/intel_dram.c | 41 +++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_pm.c | 8 ++++-
4 files changed, 101 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 61308ebe48aa..b13c4e240619 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -137,6 +137,42 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
return 0;
}
+static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
+ struct intel_qgv_point *sp, int point)
+{
+ u32 val, val2;
+ u16 dclk;
+
+ val = intel_uncore_read(&dev_priv->uncore,
+ MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
+ val2 = intel_uncore_read(&dev_priv->uncore,
+ MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
+ dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
+ sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
+ sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
+ sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
+
+ sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
+ sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
+
+ sp->t_rc = sp->t_rp + sp->t_ras;
+
+ return 0;
+}
+
+static int
+intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
+ struct intel_qgv_point *sp,
+ int point)
+{
+ if (DISPLAY_VER(dev_priv) >= 14)
+ return mtl_read_qgv_point_info(dev_priv, sp, point);
+ else if (IS_DG1(dev_priv))
+ return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
+ else
+ return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi,
bool is_y_tile)
@@ -218,11 +254,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
for (i = 0; i < qi->num_points; i++) {
struct intel_qgv_point *sp = &qi->points[i];
- if (IS_DG1(dev_priv))
- ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
- else
- ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
-
+ ret = intel_read_qgv_point_info(dev_priv, sp, i);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ec6a3dd1f2b..d22fabe35a0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8335,4 +8335,21 @@ enum skl_power_gate {
#define MTL_MEDIA_GSI_BASE 0x380000
+#define MTL_LATENCY_SAGV _MMIO(0x4578c)
+#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
+
+#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
+#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
+#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
+#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
+
+#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2)
+#define MTL_TRCD_MASK REG_GENMASK(31, 24)
+#define MTL_TRP_MASK REG_GENMASK(23, 16)
+#define MTL_DCLK_MASK REG_GENMASK(15, 0)
+
+#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2)
+#define MTL_TRAS_MASK REG_GENMASK(16, 8)
+#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 437447119770..2403ccd52c74 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -466,6 +466,43 @@ static int gen12_get_dram_info(struct drm_i915_private *i915)
return icl_pcode_read_mem_global_info(i915);
}
+static int xelpdp_get_dram_info(struct drm_i915_private *i915)
+{
+ u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
+ struct dram_info *dram_info = &i915->dram_info;
+
+ val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val);
+ switch (val) {
+ case 0:
+ dram_info->type = INTEL_DRAM_DDR4;
+ break;
+ case 1:
+ dram_info->type = INTEL_DRAM_DDR5;
+ break;
+ case 2:
+ dram_info->type = INTEL_DRAM_LPDDR5;
+ break;
+ case 3:
+ dram_info->type = INTEL_DRAM_LPDDR4;
+ break;
+ case 4:
+ dram_info->type = INTEL_DRAM_DDR3;
+ break;
+ case 5:
+ dram_info->type = INTEL_DRAM_LPDDR3;
+ break;
+ default:
+ MISSING_CASE(val);
+ return -EINVAL;
+ }
+
+ dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);
+ dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
+ /* PSF GV points not supported in D14+ */
+
+ return 0;
+}
+
void intel_dram_detect(struct drm_i915_private *i915)
{
struct dram_info *dram_info = &i915->dram_info;
@@ -480,7 +517,9 @@ void intel_dram_detect(struct drm_i915_private *i915)
*/
dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
- if (GRAPHICS_VER(i915) >= 12)
+ if (DISPLAY_VER(i915) >= 14)
+ ret = xelpdp_get_dram_info(i915);
+ else if (GRAPHICS_VER(i915) >= 12)
ret = gen12_get_dram_info(i915);
else if (GRAPHICS_VER(i915) >= 11)
ret = gen11_get_dram_info(i915);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 210c1f78cc90..ebce6171ccef 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3697,7 +3697,13 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
static u32
intel_sagv_block_time(struct drm_i915_private *dev_priv)
{
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ u32 val;
+
+ val = intel_uncore_read(&dev_priv->uncore, MTL_LATENCY_SAGV);
+
+ return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val);
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
u32 val = 0;
int ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
` (7 preceding siblings ...)
2022-09-02 6:03 ` [PATCH v4 08/11] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-08 20:02 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 11/11] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
10 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Display version 14 platforms have different credits values
compared to ADL-P. Update the credits based on pipe usage.
v2: Simplify DBOX BW Credit definition(MattR)
Bspec: 49213
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Original Author: Caz Yokoyama
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++
drivers/gpu/drm/i915/intel_pm.c | 47 ++++++++++++++++++++++++++++++---
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d22fabe35a0c..f9237586ab4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1125,8 +1125,12 @@
#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
#define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
+#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
+#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
#define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
#define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
+#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
+#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
#define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
#define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ebce6171ccef..b19a1ecb010e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8448,6 +8448,27 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
new_dbuf_state->enabled_slices);
}
+static bool xelpdp_is_one_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
+{
+ switch (pipe) {
+ case PIPE_A:
+ case PIPE_D:
+ if (is_power_of_2(active_pipes & (BIT(PIPE_A) | BIT(PIPE_D))))
+ return true;
+ break;
+ case PIPE_B:
+ case PIPE_C:
+ if (is_power_of_2(active_pipes & (BIT(PIPE_B) | BIT(PIPE_C))))
+ return true;
+ break;
+ default: /* to suppress compiler warning */
+ MISSING_CASE(pipe);
+ break;
+ }
+
+ return false;
+}
+
void intel_mbus_dbox_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
@@ -8467,20 +8488,28 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
return;
+ if (DISPLAY_VER(i915) >= 14)
+ val |= MBUS_DBOX_I_CREDIT(2);
+
if (DISPLAY_VER(i915) >= 12) {
val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
}
- /* Wa_22010947358:adl-p */
- if (IS_ALDERLAKE_P(i915))
+ if (DISPLAY_VER(i915) >= 14)
+ val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
+ MBUS_DBOX_A_CREDIT(8);
+ else if (IS_ALDERLAKE_P(i915))
+ /* Wa_22010947358:adl-p */
val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
MBUS_DBOX_A_CREDIT(4);
else
val |= MBUS_DBOX_A_CREDIT(2);
- if (IS_ALDERLAKE_P(i915)) {
+ if (DISPLAY_VER(i915) >= 14) {
+ val |= MBUS_DBOX_B_CREDIT(0xA);
+ } else if (IS_ALDERLAKE_P(i915)) {
val |= MBUS_DBOX_BW_CREDIT(2);
val |= MBUS_DBOX_B_CREDIT(8);
} else if (DISPLAY_VER(i915) >= 12) {
@@ -8492,10 +8521,20 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
}
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ u32 pipe_val = val;
+
if (!new_crtc_state->hw.active ||
!intel_crtc_needs_modeset(new_crtc_state))
continue;
- intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val);
+ if (DISPLAY_VER(i915) >= 14) {
+ if (xelpdp_is_one_pipe_per_dbuf_bank(crtc->pipe,
+ new_dbuf_state->active_pipes))
+ pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
+ else
+ pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
+ }
+
+ intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
` (8 preceding siblings ...)
2022-09-02 6:03 ` [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-08 20:30 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 11/11] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
10 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
In Display version 14, Transcoder Chicken Registers have updated address.
This patch performs checks to use the right register when required.
v2: Omit display version check in i915_reg.h(Jani)
Bspec: 34387, 50054
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++-
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++--
drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++-----
4 files changed, 38 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index be7cff722196..a3d0d12084a9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -618,7 +618,10 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
if (!IS_I830(dev_priv))
val &= ~PIPECONF_ENABLE;
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
+ FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
+ else if (DISPLAY_VER(dev_priv) >= 12)
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
@@ -1838,7 +1841,9 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
+ enum transcoder transcoder = crtc_state->cpu_transcoder;
+ i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
+ CHICKEN_TRANS(transcoder);
u32 val;
val = intel_de_read(dev_priv, reg);
@@ -4033,6 +4038,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display_power_domain_set power_domain_set = { };
+ i915_reg_t reg;
bool active;
u32 tmp;
@@ -4124,7 +4130,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
}
if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder));
+ reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
+ CHICKEN_TRANS(pipe_config->cpu_transcoder);
+ tmp = intel_de_read(dev_priv, reg);
pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 13abe2b2170e..298004cae5a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -568,7 +568,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
drm_atomic_get_mst_payload_state(mst_state, connector->port));
- if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
+ if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
+ intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
+ FECSTALL_DIS_DPTSTREAM_DPTTG);
+ else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
FECSTALL_DIS_DPTSTREAM_DPTTG);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 079b7d3d0c53..da2d0661b630 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1139,7 +1139,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (intel_dp->psr.psr2_enabled) {
if (DISPLAY_VER(dev_priv) == 9)
- intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
+ intel_de_rmw(dev_priv,
+ CHICKEN_TRANS(cpu_transcoder), 0,
PSR2_VSC_ENABLE_PROG_HEADER |
PSR2_ADD_VERTICAL_LINE_COUNT);
@@ -1149,7 +1150,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
* cause issues if non-supported panels are used.
*/
if (IS_ALDERLAKE_P(dev_priv))
- intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
+ intel_de_rmw(dev_priv,
+ CHICKEN_TRANS(cpu_transcoder), 0,
ADLP_1_BASED_X_GRANULARITY);
/* Wa_16011168373:adl-p */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f9237586ab4f..8be7685e8a3e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5717,17 +5717,30 @@
#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define _MTL_CHICKEN_TRANS_A 0x604e0
+#define _MTL_CHICKEN_TRANS_B 0x614e0
+#define _MTL_CHICKEN_TRANS_C 0x624e0
+#define _MTL_CHICKEN_TRANS_D 0x634e0
+
#define _CHICKEN_TRANS_A 0x420c0
#define _CHICKEN_TRANS_B 0x420c4
#define _CHICKEN_TRANS_C 0x420c8
#define _CHICKEN_TRANS_EDP 0x420cc
#define _CHICKEN_TRANS_D 0x420d8
-#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
- [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
- [TRANSCODER_A] = _CHICKEN_TRANS_A, \
- [TRANSCODER_B] = _CHICKEN_TRANS_B, \
- [TRANSCODER_C] = _CHICKEN_TRANS_C, \
- [TRANSCODER_D] = _CHICKEN_TRANS_D))
+
+#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
+ [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
+ [TRANSCODER_A] = _CHICKEN_TRANS_A, \
+ [TRANSCODER_B] = _CHICKEN_TRANS_B, \
+ [TRANSCODER_C] = _CHICKEN_TRANS_C, \
+ [TRANSCODER_D] = _CHICKEN_TRANS_D))
+
+#define MTL_CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
+ [TRANSCODER_A] = _MTL_CHICKEN_TRANS_A, \
+ [TRANSCODER_B] = _MTL_CHICKEN_TRANS_B, \
+ [TRANSCODER_C] = _MTL_CHICKEN_TRANS_C, \
+ [TRANSCODER_D] = _MTL_CHICKEN_TRANS_D))
+
#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 11/11] drm/i915/mtl: Do not update GV point, mask value
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
` (9 preceding siblings ...)
2022-09-02 6:03 ` [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
@ 2022-09-02 6:03 ` Radhakrishna Sripada
2022-09-09 17:14 ` [Intel-gfx] " Balasubramani Vivekanandan
10 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 6:03 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Display 14 and future platforms do not directly communicate to Pcode
via mailbox the SAGV bandwidth information. PM Demand registers are
used to communicate display power requirements to the PUnit which would
include GV point and mask value.
Skip programming GV point and mask values through legacy pcode mailbox
interface.
Bspec: 64636
Cc: Matt Roper <matthew.d.roper@intel.com>
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b19a1ecb010e..69efd613bbde 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3923,6 +3923,14 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ /*
+ * No need to update mask value/restrict because
+ * "Pcode only wants to use GV bandwidth value, not the mask value."
+ * for DISPLAY_VER() >= 14.
+ */
+ if (DISPLAY_VER(i915) >= 14)
+ return;
+
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
@@ -3943,6 +3951,16 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ /*
+ * No need to update mask value/restrict because
+ * "Pcode only wants to use GV bandwidth value, not the mask value."
+ * for DISPLAY_VER() >= 14.
+ *
+ * GV bandwidth will be set by intel_pmdemand_post_plane_update()
+ */
+ if (DISPLAY_VER(i915) >= 14)
+ return;
+
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info
2022-09-02 6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
@ 2022-09-02 16:49 ` kernel test robot
2022-09-02 22:10 ` [PATCH v4.1] " Radhakrishna Sripada
1 sibling, 0 replies; 36+ messages in thread
From: kernel test robot @ 2022-09-02 16:49 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: kbuild-all, dri-devel
Hi Radhakrishna,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[also build test ERROR on next-20220901]
[cannot apply to drm-intel/for-linux-next drm/drm-next drm-misc/drm-misc-next linus/master v6.0-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Radhakrishna-Sripada/Initial-Meteorlake-Support/20220902-140730
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20220903/202209030003.YLxzpG2i-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-5) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/159b13997e25c824f0404a44fd47e559eb56b97d
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Radhakrishna-Sripada/Initial-Meteorlake-Support/20220902-140730
git checkout 159b13997e25c824f0404a44fd47e559eb56b97d
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/i915_gem.c:1267:
drivers/gpu/drm/i915/selftests/mock_gem_device.c: In function 'mock_gem_device':
>> drivers/gpu/drm/i915/selftests/mock_gem_device.c:175:37: error: 'struct <anonymous>' has no member named 'ver'
175 | RUNTIME_INFO(i915)->graphics.ver = -1;
| ^
vim +175 drivers/gpu/drm/i915/selftests/mock_gem_device.c
bec68cc9ea42d8 Tvrtko Ursulin 2022-03-19 119
66d9cb5d805af7 Chris Wilson 2017-02-13 120 struct drm_i915_private *mock_gem_device(void)
66d9cb5d805af7 Chris Wilson 2017-02-13 121 {
01b9d4e21148c8 Joerg Roedel 2020-06-25 122 #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
9f9f4101fc98db Chris Wilson 2020-09-16 123 static struct dev_iommu fake_iommu = { .priv = (void *)-1 };
01b9d4e21148c8 Joerg Roedel 2020-06-25 124 #endif
9f9f4101fc98db Chris Wilson 2020-09-16 125 struct drm_i915_private *i915;
9f9f4101fc98db Chris Wilson 2020-09-16 126 struct pci_dev *pdev;
d148738923fdb5 Thomas Hellström 2021-06-02 127 int ret;
66d9cb5d805af7 Chris Wilson 2017-02-13 128
7fb81e9d80738e Daniel Vetter 2020-03-23 129 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
66d9cb5d805af7 Chris Wilson 2017-02-13 130 if (!pdev)
7fb81e9d80738e Daniel Vetter 2020-03-23 131 return NULL;
66d9cb5d805af7 Chris Wilson 2017-02-13 132 device_initialize(&pdev->dev);
29f31623d7a830 Chris Wilson 2017-05-18 133 pdev->class = PCI_BASE_CLASS_DISPLAY << 16;
66d9cb5d805af7 Chris Wilson 2017-02-13 134 pdev->dev.release = release_dev;
66d9cb5d805af7 Chris Wilson 2017-02-13 135 dev_set_name(&pdev->dev, "mock");
d58f0083d39a17 Chris Wilson 2019-01-07 136 dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
66d9cb5d805af7 Chris Wilson 2017-02-13 137
764d2997ec0edb Arnd Bergmann 2017-10-05 138 #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
9f9f4101fc98db Chris Wilson 2020-09-16 139 /* HACK to disable iommu for the fake device; force identity mapping */
9f9f4101fc98db Chris Wilson 2020-09-16 140 pdev->dev.iommu = &fake_iommu;
f46f156ea7704a Chris Wilson 2017-09-18 141 #endif
cd01269d11a352 Daniel Vetter 2020-09-19 142 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
cd01269d11a352 Daniel Vetter 2020-09-19 143 put_device(&pdev->dev);
cd01269d11a352 Daniel Vetter 2020-09-19 144 return NULL;
cd01269d11a352 Daniel Vetter 2020-09-19 145 }
cd01269d11a352 Daniel Vetter 2020-09-19 146
cd01269d11a352 Daniel Vetter 2020-09-19 147 i915 = devm_drm_dev_alloc(&pdev->dev, &mock_driver,
cd01269d11a352 Daniel Vetter 2020-09-19 148 struct drm_i915_private, drm);
cd01269d11a352 Daniel Vetter 2020-09-19 149 if (IS_ERR(i915)) {
cd01269d11a352 Daniel Vetter 2020-09-19 150 pr_err("Failed to allocate mock GEM device: err=%ld\n", PTR_ERR(i915));
cd01269d11a352 Daniel Vetter 2020-09-19 151 devres_release_group(&pdev->dev, NULL);
cd01269d11a352 Daniel Vetter 2020-09-19 152 put_device(&pdev->dev);
cd01269d11a352 Daniel Vetter 2020-09-19 153
cd01269d11a352 Daniel Vetter 2020-09-19 154 return NULL;
cd01269d11a352 Daniel Vetter 2020-09-19 155 }
b5891fb520f742 Chris Wilson 2017-09-14 156
bd780f37a3617d Chris Wilson 2019-01-14 157 pci_set_drvdata(pdev, i915);
bd780f37a3617d Chris Wilson 2019-01-14 158
1a0c19248a2f69 Chris Wilson 2017-07-18 159 dev_pm_domain_set(&pdev->dev, &pm_domain);
1a0c19248a2f69 Chris Wilson 2017-07-18 160 pm_runtime_enable(&pdev->dev);
66d9cb5d805af7 Chris Wilson 2017-02-13 161 pm_runtime_dont_use_autosuspend(&pdev->dev);
07e070e1e3b24e Chris Wilson 2018-07-06 162 if (pm_runtime_enabled(&pdev->dev))
1a0c19248a2f69 Chris Wilson 2017-07-18 163 WARN_ON(pm_runtime_get_sync(&pdev->dev));
66d9cb5d805af7 Chris Wilson 2017-02-13 164
66d9cb5d805af7 Chris Wilson 2017-02-13 165
c499f6cb5ea470 Chris Wilson 2020-07-28 166 i915_params_copy(&i915->params, &i915_modparams);
c499f6cb5ea470 Chris Wilson 2020-07-28 167
69c663554452e6 Daniele Ceraolo Spurio 2019-06-13 168 intel_runtime_pm_init_early(&i915->runtime_pm);
985a0256df3290 Ville Syrjälä 2022-02-04 169 /* wakeref tracking has significant overhead */
985a0256df3290 Ville Syrjälä 2022-02-04 170 i915->runtime_pm.no_wakeref_tracking = true;
d5b6c275d04aac Daniele Ceraolo Spurio 2019-06-13 171
3b5bb0a37665ce Chris Wilson 2017-02-13 172 /* Using the global GTT may ask questions about KMS users, so prepare */
3b5bb0a37665ce Chris Wilson 2017-02-13 173 drm_mode_config_init(&i915->drm);
3b5bb0a37665ce Chris Wilson 2017-02-13 174
43ba44a176a420 Jani Nikula 2022-08-19 @175 RUNTIME_INFO(i915)->graphics.ver = -1;
66d9cb5d805af7 Chris Wilson 2017-02-13 176
9d0bad177af9fd Jani Nikula 2022-08-19 177 RUNTIME_INFO(i915)->page_sizes =
f1f3f98272b9bb Matthew Auld 2017-10-06 178 I915_GTT_PAGE_SIZE_4K |
a883241c392200 Matthew Auld 2017-10-06 179 I915_GTT_PAGE_SIZE_64K |
a883241c392200 Matthew Auld 2017-10-06 180 I915_GTT_PAGE_SIZE_2M;
2a9654b2cdd8f9 Matthew Auld 2017-10-06 181
f81f30b305d2c7 Jani Nikula 2022-08-19 182 RUNTIME_INFO(i915)->memory_regions = REGION_SMEM;
3fc794f27fec8f Chris Wilson 2019-10-26 183 intel_memory_regions_hw_probe(i915);
da1184cd41d4c6 Matthew Auld 2019-10-18 184
9a7fc952717ea6 Tvrtko Ursulin 2021-11-11 185 spin_lock_init(&i915->gpu_error.lock);
9a7fc952717ea6 Tvrtko Ursulin 2021-11-11 186
9c52d1c816baa5 Chris Wilson 2017-11-10 187 i915_gem_init__mm(i915);
bec68cc9ea42d8 Tvrtko Ursulin 2022-03-19 188 intel_root_gt_init_early(i915);
030def2cc91f51 Michał Winiarski 2021-12-14 189 mock_uncore_init(&i915->uncore, i915);
8c2699fad60e3f Andi Shyti 2021-12-14 190 atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw support */
8c2699fad60e3f Andi Shyti 2021-12-14 191 to_gt(i915)->awake = -ENODEV;
bec68cc9ea42d8 Tvrtko Ursulin 2022-03-19 192 mock_gt_probe(i915);
66d9cb5d805af7 Chris Wilson 2017-02-13 193
d148738923fdb5 Thomas Hellström 2021-06-02 194 ret = intel_region_ttm_device_init(i915);
d148738923fdb5 Thomas Hellström 2021-06-02 195 if (ret)
d148738923fdb5 Thomas Hellström 2021-06-02 196 goto err_ttm;
d148738923fdb5 Thomas Hellström 2021-06-02 197
0daf0113cff688 Chris Wilson 2017-02-13 198 i915->wq = alloc_ordered_workqueue("mock", 0);
0daf0113cff688 Chris Wilson 2017-02-13 199 if (!i915->wq)
19553d57dcddf6 Chris Wilson 2017-12-09 200 goto err_drv;
0daf0113cff688 Chris Wilson 2017-02-13 201
5f09a9c8ab6b16 Chris Wilson 2017-06-20 202 mock_init_contexts(i915);
0daf0113cff688 Chris Wilson 2017-02-13 203
cdeea858d8df98 Andi Shyti 2021-12-19 204 /* allocate the ggtt */
cdeea858d8df98 Andi Shyti 2021-12-19 205 ret = intel_gt_assign_ggtt(to_gt(i915));
cdeea858d8df98 Andi Shyti 2021-12-19 206 if (ret)
cdeea858d8df98 Andi Shyti 2021-12-19 207 goto err_unlock;
cdeea858d8df98 Andi Shyti 2021-12-19 208
cdeea858d8df98 Andi Shyti 2021-12-19 209 mock_init_ggtt(to_gt(i915));
cdeea858d8df98 Andi Shyti 2021-12-19 210 to_gt(i915)->vm = i915_vm_get(&to_gt(i915)->ggtt->vm);
3b5bb0a37665ce Chris Wilson 2017-02-13 211
488e29fedc1f2b Jani Nikula 2022-08-19 212 RUNTIME_INFO(i915)->platform_engine_mask = BIT(0);
8c2699fad60e3f Andi Shyti 2021-12-14 213 to_gt(i915)->info.engine_mask = BIT(0);
4a774ee35c9f57 Chris Wilson 2018-05-23 214
8c2699fad60e3f Andi Shyti 2021-12-14 215 to_gt(i915)->engine[RCS0] = mock_engine(i915, "mock", RCS0);
8c2699fad60e3f Andi Shyti 2021-12-14 216 if (!to_gt(i915)->engine[RCS0])
11334c6aad9500 Chris Wilson 2019-04-26 217 goto err_unlock;
11334c6aad9500 Chris Wilson 2019-04-26 218
8c2699fad60e3f Andi Shyti 2021-12-14 219 if (mock_engine_init(to_gt(i915)->engine[RCS0]))
4a774ee35c9f57 Chris Wilson 2018-05-23 220 goto err_context;
0daf0113cff688 Chris Wilson 2017-02-13 221
8c2699fad60e3f Andi Shyti 2021-12-14 222 __clear_bit(I915_WEDGED, &to_gt(i915)->reset.flags);
cbb153c50ebe4f Chris Wilson 2019-08-08 223 intel_engines_driver_register(i915);
1d7a99f5148fdc Chris Wilson 2018-05-08 224
7fb81e9d80738e Daniel Vetter 2020-03-23 225 i915->do_release = true;
d148738923fdb5 Thomas Hellström 2021-06-02 226 ida_init(&i915->selftest.mock_region_instances);
7fb81e9d80738e Daniel Vetter 2020-03-23 227
66d9cb5d805af7 Chris Wilson 2017-02-13 228 return i915;
66d9cb5d805af7 Chris Wilson 2017-02-13 229
4a774ee35c9f57 Chris Wilson 2018-05-23 230 err_context:
8c2699fad60e3f Andi Shyti 2021-12-14 231 intel_gt_driver_remove(to_gt(i915));
1d7a99f5148fdc Chris Wilson 2018-05-08 232 err_unlock:
0daf0113cff688 Chris Wilson 2017-02-13 233 destroy_workqueue(i915->wq);
19553d57dcddf6 Chris Wilson 2017-12-09 234 err_drv:
d148738923fdb5 Thomas Hellström 2021-06-02 235 intel_region_ttm_device_fini(i915);
d148738923fdb5 Thomas Hellström 2021-06-02 236 err_ttm:
bec68cc9ea42d8 Tvrtko Ursulin 2022-03-19 237 intel_gt_driver_late_release_all(i915);
3fc794f27fec8f Chris Wilson 2019-10-26 238 intel_memory_regions_driver_release(i915);
19553d57dcddf6 Chris Wilson 2017-12-09 239 drm_mode_config_cleanup(&i915->drm);
82be0d7540b104 Daniel Vetter 2020-09-18 240 mock_destroy_device(i915);
7fb81e9d80738e Daniel Vetter 2020-03-23 241
66d9cb5d805af7 Chris Wilson 2017-02-13 242 return NULL;
66d9cb5d805af7 Chris Wilson 2017-02-13 243 }
82be0d7540b104 Daniel Vetter 2020-09-18 244
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4.1] drm/i915: Move display and media IP version to runtime info
2022-09-02 6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
2022-09-02 16:49 ` kernel test robot
@ 2022-09-02 22:10 ` Radhakrishna Sripada
2022-09-08 17:21 ` Matt Roper
1 sibling, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Future platforms can read the IP version from a register and the
IP version numbers need not be hard coded in device info. Move the
ip version for media and display to runtime info.
On platforms where hard coding of IP version is required, update
the IP version in __runtime under device_info.
v2:
- Avoid name collision for ip versions(Jani)
v4.1:
- Fix build error in mock_gem_device.c
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 14 +++----
drivers/gpu/drm/i915/i915_pci.c | 38 +++++++++----------
drivers/gpu/drm/i915/intel_device_info.c | 28 +++++++++-----
drivers/gpu/drm/i915/intel_device_info.h | 15 +++++---
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
5 files changed, 54 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9cca165bf5d..f85a470397a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -469,19 +469,19 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
-#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ver)
-#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ver, \
- RUNTIME_INFO(i915)->graphics.rel)
+#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.version.ver)
+#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.version.ver, \
+ RUNTIME_INFO(i915)->graphics.version.rel)
#define IS_GRAPHICS_VER(i915, from, until) \
(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
-#define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver)
-#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.ver, \
- INTEL_INFO(i915)->media.rel)
+#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.version.ver)
+#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.version.ver, \
+ RUNTIME_INFO(i915)->media.version.rel)
#define IS_MEDIA_VER(i915, from, until) \
(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
-#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
+#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.version.ver)
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 26b25d9434d6..f6aaf938c53c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -34,9 +34,9 @@
#define PLATFORM(x) .platform = (x)
#define GEN(x) \
- .__runtime.graphics.ver = (x), \
- .media.ver = (x), \
- .display.ver = (x)
+ .__runtime.graphics.version.ver = (x), \
+ .__runtime.media.version.ver = (x), \
+ .__runtime.display.version.ver = (x)
#define I845_PIPE_OFFSETS \
.display.pipe_offsets = { \
@@ -740,7 +740,7 @@ static const struct intel_device_info bxt_info = {
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
- .display.ver = 10,
+ .__runtime.display.version.ver = 10,
.display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
GLK_COLORS,
};
@@ -919,7 +919,7 @@ static const struct intel_device_info rkl_info = {
static const struct intel_device_info dg1_info = {
GEN12_FEATURES,
DGFX_FEATURES,
- .__runtime.graphics.rel = 10,
+ .__runtime.graphics.version.rel = 10,
PLATFORM(INTEL_DG1),
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
.require_force_probe = 1,
@@ -962,7 +962,7 @@ static const struct intel_device_info adl_s_info = {
.display.has_hotplug = 1, \
.display.has_ipc = 1, \
.display.has_psr = 1, \
- .display.ver = 13, \
+ .__runtime.display.version.ver = 13, \
.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
.display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
@@ -1006,8 +1006,8 @@ static const struct intel_device_info adl_p_info = {
I915_GTT_PAGE_SIZE_2M
#define XE_HP_FEATURES \
- .__runtime.graphics.ver = 12, \
- .__runtime.graphics.rel = 50, \
+ .__runtime.graphics.version.ver = 12, \
+ .__runtime.graphics.version.rel = 50, \
XE_HP_PAGE_SIZES, \
.dma_mask_size = 46, \
.has_3d_pipeline = 1, \
@@ -1027,8 +1027,8 @@ static const struct intel_device_info adl_p_info = {
.__runtime.ppgtt_type = INTEL_PPGTT_FULL
#define XE_HPM_FEATURES \
- .media.ver = 12, \
- .media.rel = 50
+ .__runtime.media.version.ver = 12, \
+ .__runtime.media.version.rel = 50
__maybe_unused
static const struct intel_device_info xehpsdv_info = {
@@ -1053,8 +1053,8 @@ static const struct intel_device_info xehpsdv_info = {
XE_HP_FEATURES, \
XE_HPM_FEATURES, \
DGFX_FEATURES, \
- .__runtime.graphics.rel = 55, \
- .media.rel = 55, \
+ .__runtime.graphics.version.rel = 55, \
+ .__runtime.media.version.rel = 55, \
PLATFORM(INTEL_DG2), \
.has_4tile = 1, \
.has_64k_pages = 1, \
@@ -1097,8 +1097,8 @@ static const struct intel_device_info pvc_info = {
XE_HPC_FEATURES,
XE_HPM_FEATURES,
DGFX_FEATURES,
- .__runtime.graphics.rel = 60,
- .media.rel = 60,
+ .__runtime.graphics.version.rel = 60,
+ .__runtime.media.version.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
.display = { 0 },
.has_flat_ccs = 0,
@@ -1111,7 +1111,7 @@ static const struct intel_device_info pvc_info = {
#define XE_LPDP_FEATURES \
XE_LPD_FEATURES, \
- .display.ver = 14, \
+ .__runtime.display.version.ver = 14, \
.display.has_cdclk_crawl = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
@@ -1123,9 +1123,9 @@ static const struct intel_device_info mtl_info = {
* Real graphics IP version will be obtained from hardware GMD_ID
* register. Value provided here is just for sanity checking.
*/
- .__runtime.graphics.ver = 12,
- .__runtime.graphics.rel = 70,
- .media.ver = 13,
+ .__runtime.graphics.version.ver = 12,
+ .__runtime.graphics.version.rel = 70,
+ .__runtime.media.version.ver = 13,
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
.has_flat_ccs = 0,
@@ -1281,7 +1281,7 @@ bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
{
- int gttmmaddr_bar = intel_info->__runtime.graphics.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
+ int gttmmaddr_bar = intel_info->__runtime.graphics.version.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
return i915_pci_resource_valid(pdev, gttmmaddr_bar);
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0a1f97b35f2b..56f19683dd55 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -92,21 +92,29 @@ void intel_device_info_print(const struct intel_device_info *info,
const struct intel_runtime_info *runtime,
struct drm_printer *p)
{
- if (runtime->graphics.rel)
- drm_printf(p, "graphics version: %u.%02u\n", runtime->graphics.ver,
- runtime->graphics.rel);
+ if (runtime->graphics.version.rel)
+ drm_printf(p, "graphics version: %u.%02u\n",
+ runtime->graphics.version.ver,
+ runtime->graphics.version.rel);
else
- drm_printf(p, "graphics version: %u\n", runtime->graphics.ver);
+ drm_printf(p, "graphics version: %u\n",
+ runtime->graphics.version.ver);
- if (info->media.rel)
- drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel);
+ if (runtime->media.version.rel)
+ drm_printf(p, "media version: %u.%02u\n",
+ runtime->media.version.ver,
+ runtime->media.version.rel);
else
- drm_printf(p, "media version: %u\n", info->media.ver);
+ drm_printf(p, "media version: %u\n",
+ runtime->media.version.ver);
- if (info->display.rel)
- drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel);
+ if (runtime->display.version.rel)
+ drm_printf(p, "display version: %u.%02u\n",
+ runtime->display.version.ver,
+ runtime->display.version.rel);
else
- drm_printf(p, "display version: %u\n", info->display.ver);
+ drm_printf(p, "display version: %u\n",
+ runtime->display.version.ver);
drm_printf(p, "gt: %d\n", info->gt);
drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6904ad03ca19..d36cf25f1d5f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -200,7 +200,15 @@ struct ip_version {
};
struct intel_runtime_info {
- struct ip_version graphics;
+ struct {
+ struct ip_version version;
+ } graphics;
+ struct {
+ struct ip_version version;
+ } media;
+ struct {
+ struct ip_version version;
+ } display;
/*
* Platform mask is used for optimizing or-ed IS_PLATFORM calls into
@@ -246,8 +254,6 @@ struct intel_runtime_info {
};
struct intel_device_info {
- struct ip_version media;
-
enum intel_platform platform;
unsigned int dma_mask_size; /* available DMA address bits */
@@ -259,9 +265,6 @@ struct intel_device_info {
#undef DEFINE_FLAG
struct {
- u8 ver;
- u8 rel;
-
u8 abox_mask;
struct {
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index f5904e659ef2..869b952c13a0 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -172,7 +172,7 @@ struct drm_i915_private *mock_gem_device(void)
/* Using the global GTT may ask questions about KMS users, so prepare */
drm_mode_config_init(&i915->drm);
- RUNTIME_INFO(i915)->graphics.ver = -1;
+ RUNTIME_INFO(i915)->graphics.version.ver = -1;
RUNTIME_INFO(i915)->page_sizes =
I915_GTT_PAGE_SIZE_4K |
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts
2022-09-02 6:03 ` [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
@ 2022-09-06 12:16 ` Balasubramani Vivekanandan
2022-09-07 23:33 ` [PATCH v4.1] " Radhakrishna Sripada
1 sibling, 0 replies; 36+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-06 12:16 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: dri-devel
On 01.09.2022 23:03, Radhakrishna Sripada wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the driver conditions to re-use the DG2
> context table.
>
> For render/compute engines, the part of the context images are nearly
> the same, although the layout had a very slight change --- one POSH
> register was removed and the placement of some LRI/noops adjusted
> slightly to compensate.
>
> v2:
> - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> - Drop unused registers in mtl rcs offsets.(Bala)
>
> Bspec: 46261, 46260, 45585
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 81 ++++++++++++++++++++++++++++-
> 1 file changed, 79 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 070cec4ff8a4..ecb030ee39cd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -264,6 +264,38 @@ static const u8 dg2_xcs_offsets[] = {
> END
> };
>
> +static const u8 mtl_xcs_offsets[] = {
> + NOP(1),
> + LRI(13, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
Comparing Bspec 45585, there are few NOP missing here
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + END
> +};
> +
> static const u8 gen8_rcs_offsets[] = {
> NOP(1),
> LRI(14, POSTED),
> @@ -606,6 +638,47 @@ static const u8 dg2_rcs_offsets[] = {
> END
> };
>
> +static const u8 mtl_rcs_offsets[] = {
> + NOP(1),
> + LRI(13, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + NOP(2),
> + LRI(2, POSTED),
> + REG16(0x5a8),
> + REG16(0x5ac),
> +
> + NOP(6),
> + LRI(1, 0),
> + REG(0x0c8),
> +
> + END
> +};
> +
> #undef END
> #undef REG16
> #undef REG
> @@ -624,7 +697,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> !intel_engine_has_relative_mmio(engine));
>
> if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_rcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_rcs_offsets;
> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> return xehp_rcs_offsets;
> @@ -637,7 +712,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> else
> return gen8_rcs_offsets;
> } else {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_xcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_xcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_xcs_offsets;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw
2022-09-02 6:03 ` [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
@ 2022-09-07 20:49 ` Lucas De Marchi
2022-09-07 22:13 ` Matt Roper
2022-09-07 23:32 ` [PATCH v4.1] " Radhakrishna Sripada
1 sibling, 1 reply; 36+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:49 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel, Rodrigo Vivi
On Thu, Sep 01, 2022 at 11:03:33PM -0700, Radhakrishna Sripada wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Going forward, the hardware teams no longer consider new platforms to
>have a "generation" in the way we've defined it for past platforms.
>Instead, each IP block (graphics, media, display) will have their own
>architecture major.minor versions and stepping ID's which should be read
>directly from a register in the MMIO space. New hardware programming
>styles, features, and workarounds should be conditional solely on the
>architecture version, and should no longer be derived from the PCI
>device ID, revision ID, or platform-specific feature flags.
>
>Bspec: 63361, 64111
>
>v2:
> - Move the IP version readout to intel_device_info.c
> - Convert the macro into a function
>
>v3:
> - Move subplatform init to runtime early init
> - Cache runtime ver, release info to compare with hardware values.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
> drivers/gpu/drm/i915/i915_driver.c | 3 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 7 +++
> drivers/gpu/drm/i915/intel_device_info.c | 74 +++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
> 7 files changed, 98 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>index d414785003cc..579da62158c4 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>@@ -39,6 +39,8 @@
> #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
> #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
>
>+#define GMD_ID_GRAPHICS _MMIO(0xd8c)
>+
> #define MCFG_MCR_SELECTOR _MMIO(0xfd0)
> #define SF_MCR_SELECTOR _MMIO(0xfd8)
> #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
>diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>index 56a2bcddb2af..a1ab49521d19 100644
>--- a/drivers/gpu/drm/i915/i915_driver.c
>+++ b/drivers/gpu/drm/i915/i915_driver.c
>@@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> if (i915_inject_probe_failure(dev_priv))
> return -ENODEV;
>
>- intel_device_info_subplatform_init(dev_priv);
>+ intel_device_info_runtime_init_early(dev_priv);
>+
> intel_step_init(dev_priv);
>
> intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index f85a470397a5..405b59b8c05c 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>
>+#define HAS_GMD_ID(i915) INTEL_INFO(i915)->has_gmd_id
>+
> #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
>
> #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index f6aaf938c53c..4672894f4bc1 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
> PLATFORM(INTEL_METEORLAKE),
> .display.has_modular_fia = 1,
> .has_flat_ccs = 0,
>+ .has_gmd_id = 1,
> .has_snoop = 1,
> .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
> .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 5e6239864c35..e02e461a4b5d 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -5798,6 +5798,11 @@
> #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
>
>+#define GMD_ID_DISPLAY _MMIO(0x510a0)
>+#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
>+#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
>+#define GMD_ID_STEP REG_GENMASK(5, 0)
>+
> /*GEN11 chicken */
> #define _PIPEA_CHICKEN 0x70038
> #define _PIPEB_CHICKEN 0x71038
>@@ -8298,4 +8303,6 @@ enum skl_power_gate {
> #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
> #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
>
>+#define MTL_MEDIA_GSI_BASE 0x380000
>+
> #endif /* _I915_REG_H_ */
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index 56f19683dd55..a5bafc9be1fa 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -29,6 +29,7 @@
>
> #include "display/intel_cdclk.h"
> #include "display/intel_de.h"
>+#include "gt/intel_gt_regs.h"
> #include "intel_device_info.h"
> #include "i915_drv.h"
> #include "i915_utils.h"
>@@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p, unsigned int num)
> return false;
> }
>
>-void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>+static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> {
> const struct intel_device_info *info = INTEL_INFO(i915);
> const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
>@@ -288,6 +289,77 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
> }
>
>+static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct ip_version *ip)
>+{
>+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>+ void __iomem *addr;
>+ u32 val;
>+ u8 ver = ip->ver;
>+ u8 rel = ip->rel;
>+
>+ addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
>+ if (drm_WARN_ON(&i915->drm, !addr))
>+ return;
>+
>+ val = ioread32(addr);
>+ pci_iounmap(pdev, addr);
>+
>+ ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
>+ ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
>+ ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
>+
>+ /* Sanity check against expected versions from device info */
>+ if (ip->ver != ver || ip->rel > rel)
this doesn't seem correct.. if we have
ip->ver == 12, ip->rel == 1
ver == 12, rel == 0
we will print
Hardware reports GMD IP version 12.1 but minimum expected is 12.0"
should it be `|| ip->rel < rel`? Once we land the static number in
device info, we can only expect new .rel versions greater than that.
Lucas De Marchi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw
2022-09-07 20:49 ` [Intel-gfx] " Lucas De Marchi
@ 2022-09-07 22:13 ` Matt Roper
2022-09-07 22:21 ` Lucas De Marchi
0 siblings, 1 reply; 36+ messages in thread
From: Matt Roper @ 2022-09-07 22:13 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Rodrigo Vivi, dri-devel, Radhakrishna Sripada
On Wed, Sep 07, 2022 at 01:49:25PM -0700, Lucas De Marchi wrote:
> On Thu, Sep 01, 2022 at 11:03:33PM -0700, Radhakrishna Sripada wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> >
> > Going forward, the hardware teams no longer consider new platforms to
> > have a "generation" in the way we've defined it for past platforms.
> > Instead, each IP block (graphics, media, display) will have their own
> > architecture major.minor versions and stepping ID's which should be read
> > directly from a register in the MMIO space. New hardware programming
> > styles, features, and workarounds should be conditional solely on the
> > architecture version, and should no longer be derived from the PCI
> > device ID, revision ID, or platform-specific feature flags.
> >
> > Bspec: 63361, 64111
> >
> > v2:
> > - Move the IP version readout to intel_device_info.c
> > - Convert the macro into a function
> >
> > v3:
> > - Move subplatform init to runtime early init
> > - Cache runtime ver, release info to compare with hardware values.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
> > drivers/gpu/drm/i915/i915_driver.c | 3 +-
> > drivers/gpu/drm/i915/i915_drv.h | 2 +
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 7 +++
> > drivers/gpu/drm/i915/intel_device_info.c | 74 +++++++++++++++++++++++-
> > drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
> > 7 files changed, 98 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index d414785003cc..579da62158c4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -39,6 +39,8 @@
> > #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
> > #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
> >
> > +#define GMD_ID_GRAPHICS _MMIO(0xd8c)
> > +
> > #define MCFG_MCR_SELECTOR _MMIO(0xfd0)
> > #define SF_MCR_SELECTOR _MMIO(0xfd8)
> > #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > index 56a2bcddb2af..a1ab49521d19 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> > if (i915_inject_probe_failure(dev_priv))
> > return -ENODEV;
> >
> > - intel_device_info_subplatform_init(dev_priv);
> > + intel_device_info_runtime_init_early(dev_priv);
> > +
> > intel_step_init(dev_priv);
> >
> > intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index f85a470397a5..405b59b8c05c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >
> > #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
> >
> > +#define HAS_GMD_ID(i915) INTEL_INFO(i915)->has_gmd_id
> > +
> > #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
> >
> > #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index f6aaf938c53c..4672894f4bc1 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
> > PLATFORM(INTEL_METEORLAKE),
> > .display.has_modular_fia = 1,
> > .has_flat_ccs = 0,
> > + .has_gmd_id = 1,
> > .has_snoop = 1,
> > .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
> > .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 5e6239864c35..e02e461a4b5d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5798,6 +5798,11 @@
> > #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> > #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> >
> > +#define GMD_ID_DISPLAY _MMIO(0x510a0)
> > +#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
> > +#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> > +#define GMD_ID_STEP REG_GENMASK(5, 0)
> > +
> > /*GEN11 chicken */
> > #define _PIPEA_CHICKEN 0x70038
> > #define _PIPEB_CHICKEN 0x71038
> > @@ -8298,4 +8303,6 @@ enum skl_power_gate {
> > #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
> > #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
> >
> > +#define MTL_MEDIA_GSI_BASE 0x380000
> > +
> > #endif /* _I915_REG_H_ */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index 56f19683dd55..a5bafc9be1fa 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -29,6 +29,7 @@
> >
> > #include "display/intel_cdclk.h"
> > #include "display/intel_de.h"
> > +#include "gt/intel_gt_regs.h"
> > #include "intel_device_info.h"
> > #include "i915_drv.h"
> > #include "i915_utils.h"
> > @@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p, unsigned int num)
> > return false;
> > }
> >
> > -void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> > +static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> > {
> > const struct intel_device_info *info = INTEL_INFO(i915);
> > const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
> > @@ -288,6 +289,77 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> > RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
> > }
> >
> > +static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct ip_version *ip)
> > +{
> > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > + void __iomem *addr;
> > + u32 val;
> > + u8 ver = ip->ver;
> > + u8 rel = ip->rel;
> > +
> > + addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
> > + if (drm_WARN_ON(&i915->drm, !addr))
> > + return;
> > +
> > + val = ioread32(addr);
> > + pci_iounmap(pdev, addr);
> > +
> > + ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> > + ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> > + ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
> > +
> > + /* Sanity check against expected versions from device info */
> > + if (ip->ver != ver || ip->rel > rel)
>
> this doesn't seem correct.. if we have
>
> ip->ver == 12, ip->rel == 1
> ver == 12, rel == 0
>
> we will print
>
> Hardware reports GMD IP version 12.1 but minimum expected is 12.0"
>
> should it be `|| ip->rel < rel`? Once we land the static number in
> device info, we can only expect new .rel versions greater than that.
I'm not sure how much value there is in keeping this sanity check at all
given that we plan to remove the device info versions completely for
platforms with GMD_ID. But if you want to test this in an easy-to-read
manner in the short term,
if (IP_VER(ip->ver, ip->rel) < IP_VER(ver, rel))
would probably be best.
Matt
>
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw
2022-09-07 22:13 ` Matt Roper
@ 2022-09-07 22:21 ` Lucas De Marchi
2022-09-07 22:38 ` Sripada, Radhakrishna
0 siblings, 1 reply; 36+ messages in thread
From: Lucas De Marchi @ 2022-09-07 22:21 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, Rodrigo Vivi, dri-devel, Radhakrishna Sripada
On Wed, Sep 07, 2022 at 03:13:31PM -0700, Matt Roper wrote:
>On Wed, Sep 07, 2022 at 01:49:25PM -0700, Lucas De Marchi wrote:
>> On Thu, Sep 01, 2022 at 11:03:33PM -0700, Radhakrishna Sripada wrote:
>> > From: Matt Roper <matthew.d.roper@intel.com>
>> >
>> > Going forward, the hardware teams no longer consider new platforms to
>> > have a "generation" in the way we've defined it for past platforms.
>> > Instead, each IP block (graphics, media, display) will have their own
>> > architecture major.minor versions and stepping ID's which should be read
>> > directly from a register in the MMIO space. New hardware programming
>> > styles, features, and workarounds should be conditional solely on the
>> > architecture version, and should no longer be derived from the PCI
>> > device ID, revision ID, or platform-specific feature flags.
>> >
>> > Bspec: 63361, 64111
>> >
>> > v2:
>> > - Move the IP version readout to intel_device_info.c
>> > - Convert the macro into a function
>> >
>> > v3:
>> > - Move subplatform init to runtime early init
>> > - Cache runtime ver, release info to compare with hardware values.
>> >
>> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
>> > drivers/gpu/drm/i915/i915_driver.c | 3 +-
>> > drivers/gpu/drm/i915/i915_drv.h | 2 +
>> > drivers/gpu/drm/i915/i915_pci.c | 1 +
>> > drivers/gpu/drm/i915/i915_reg.h | 7 +++
>> > drivers/gpu/drm/i915/intel_device_info.c | 74 +++++++++++++++++++++++-
>> > drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
>> > 7 files changed, 98 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> > index d414785003cc..579da62158c4 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> > @@ -39,6 +39,8 @@
>> > #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
>> > #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
>> >
>> > +#define GMD_ID_GRAPHICS _MMIO(0xd8c)
>> > +
>> > #define MCFG_MCR_SELECTOR _MMIO(0xfd0)
>> > #define SF_MCR_SELECTOR _MMIO(0xfd8)
>> > #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
>> > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>> > index 56a2bcddb2af..a1ab49521d19 100644
>> > --- a/drivers/gpu/drm/i915/i915_driver.c
>> > +++ b/drivers/gpu/drm/i915/i915_driver.c
>> > @@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>> > if (i915_inject_probe_failure(dev_priv))
>> > return -ENODEV;
>> >
>> > - intel_device_info_subplatform_init(dev_priv);
>> > + intel_device_info_runtime_init_early(dev_priv);
>> > +
>> > intel_step_init(dev_priv);
>> >
>> > intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> > index f85a470397a5..405b59b8c05c 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> >
>> > #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>> >
>> > +#define HAS_GMD_ID(i915) INTEL_INFO(i915)->has_gmd_id
>> > +
>> > #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
>> >
>> > #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
>> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> > index f6aaf938c53c..4672894f4bc1 100644
>> > --- a/drivers/gpu/drm/i915/i915_pci.c
>> > +++ b/drivers/gpu/drm/i915/i915_pci.c
>> > @@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
>> > PLATFORM(INTEL_METEORLAKE),
>> > .display.has_modular_fia = 1,
>> > .has_flat_ccs = 0,
>> > + .has_gmd_id = 1,
>> > .has_snoop = 1,
>> > .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
>> > .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 5e6239864c35..e02e461a4b5d 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -5798,6 +5798,11 @@
>> > #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
>> > #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
>> >
>> > +#define GMD_ID_DISPLAY _MMIO(0x510a0)
>> > +#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
>> > +#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
>> > +#define GMD_ID_STEP REG_GENMASK(5, 0)
>> > +
>> > /*GEN11 chicken */
>> > #define _PIPEA_CHICKEN 0x70038
>> > #define _PIPEB_CHICKEN 0x71038
>> > @@ -8298,4 +8303,6 @@ enum skl_power_gate {
>> > #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
>> > #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
>> >
>> > +#define MTL_MEDIA_GSI_BASE 0x380000
>> > +
>> > #endif /* _I915_REG_H_ */
>> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> > index 56f19683dd55..a5bafc9be1fa 100644
>> > --- a/drivers/gpu/drm/i915/intel_device_info.c
>> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> > @@ -29,6 +29,7 @@
>> >
>> > #include "display/intel_cdclk.h"
>> > #include "display/intel_de.h"
>> > +#include "gt/intel_gt_regs.h"
>> > #include "intel_device_info.h"
>> > #include "i915_drv.h"
>> > #include "i915_utils.h"
>> > @@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p, unsigned int num)
>> > return false;
>> > }
>> >
>> > -void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>> > +static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>> > {
>> > const struct intel_device_info *info = INTEL_INFO(i915);
>> > const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
>> > @@ -288,6 +289,77 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>> > RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
>> > }
>> >
>> > +static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct ip_version *ip)
>> > +{
>> > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> > + void __iomem *addr;
>> > + u32 val;
>> > + u8 ver = ip->ver;
>> > + u8 rel = ip->rel;
>> > +
>> > + addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
>> > + if (drm_WARN_ON(&i915->drm, !addr))
>> > + return;
>> > +
>> > + val = ioread32(addr);
>> > + pci_iounmap(pdev, addr);
>> > +
>> > + ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
>> > + ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
>> > + ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
>> > +
>> > + /* Sanity check against expected versions from device info */
>> > + if (ip->ver != ver || ip->rel > rel)
>>
>> this doesn't seem correct.. if we have
>>
>> ip->ver == 12, ip->rel == 1
>> ver == 12, rel == 0
>>
>> we will print
>>
>> Hardware reports GMD IP version 12.1 but minimum expected is 12.0"
>>
>> should it be `|| ip->rel < rel`? Once we land the static number in
>> device info, we can only expect new .rel versions greater than that.
>
>I'm not sure how much value there is in keeping this sanity check at all
>given that we plan to remove the device info versions completely for
>platforms with GMD_ID. But if you want to test this in an easy-to-read
>manner in the short term,
>
> if (IP_VER(ip->ver, ip->rel) < IP_VER(ver, rel))
>
>would probably be best.
I'm ok with removing the sanity check as long as we log the value read.
We still do when printing all the info, so lgtm.
Lucas De Marchi
>
>
>Matt
>
>>
>> Lucas De Marchi
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw
2022-09-07 22:21 ` Lucas De Marchi
@ 2022-09-07 22:38 ` Sripada, Radhakrishna
0 siblings, 0 replies; 36+ messages in thread
From: Sripada, Radhakrishna @ 2022-09-07 22:38 UTC (permalink / raw)
To: De Marchi, Lucas, Roper, Matthew D; +Cc: intel-gfx, dri-devel, Vivi, Rodrigo
Hi Lucas/Matt,
> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, September 7, 2022 3:21 PM
> To: Roper, Matthew D <matthew.d.roper@intel.com>
> Cc: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display
> arch version from hw
>
> On Wed, Sep 07, 2022 at 03:13:31PM -0700, Matt Roper wrote:
> >On Wed, Sep 07, 2022 at 01:49:25PM -0700, Lucas De Marchi wrote:
> >> On Thu, Sep 01, 2022 at 11:03:33PM -0700, Radhakrishna Sripada wrote:
> >> > From: Matt Roper <matthew.d.roper@intel.com>
> >> >
> >> > Going forward, the hardware teams no longer consider new platforms to
> >> > have a "generation" in the way we've defined it for past platforms.
> >> > Instead, each IP block (graphics, media, display) will have their own
> >> > architecture major.minor versions and stepping ID's which should be read
> >> > directly from a register in the MMIO space. New hardware programming
> >> > styles, features, and workarounds should be conditional solely on the
> >> > architecture version, and should no longer be derived from the PCI
> >> > device ID, revision ID, or platform-specific feature flags.
> >> >
> >> > Bspec: 63361, 64111
> >> >
> >> > v2:
> >> > - Move the IP version readout to intel_device_info.c
> >> > - Convert the macro into a function
> >> >
> >> > v3:
> >> > - Move subplatform init to runtime early init
> >> > - Cache runtime ver, release info to compare with hardware values.
> >> >
> >> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
> >> > drivers/gpu/drm/i915/i915_driver.c | 3 +-
> >> > drivers/gpu/drm/i915/i915_drv.h | 2 +
> >> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> >> > drivers/gpu/drm/i915/i915_reg.h | 7 +++
> >> > drivers/gpu/drm/i915/intel_device_info.c | 74
> +++++++++++++++++++++++-
> >> > drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
> >> > 7 files changed, 98 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> > index d414785003cc..579da62158c4 100644
> >> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> > @@ -39,6 +39,8 @@
> >> > #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
> >> > #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
> >> >
> >> > +#define GMD_ID_GRAPHICS
> _MMIO(0xd8c)
> >> > +
> >> > #define MCFG_MCR_SELECTOR _MMIO(0xfd0)
> >> > #define SF_MCR_SELECTOR _MMIO(0xfd8)
> >> > #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
> >> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> >> > index 56a2bcddb2af..a1ab49521d19 100644
> >> > --- a/drivers/gpu/drm/i915/i915_driver.c
> >> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> >> > @@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> >> > if (i915_inject_probe_failure(dev_priv))
> >> > return -ENODEV;
> >> >
> >> > - intel_device_info_subplatform_init(dev_priv);
> >> > + intel_device_info_runtime_init_early(dev_priv);
> >> > +
> >> > intel_step_init(dev_priv);
> >> >
> >> > intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
> >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> >> > index f85a470397a5..405b59b8c05c 100644
> >> > --- a/drivers/gpu/drm/i915/i915_drv.h
> >> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> > @@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> >> >
> >> > #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
> >> >
> >> > +#define HAS_GMD_ID(i915) INTEL_INFO(i915)->has_gmd_id
> >> > +
> >> > #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
> >> >
> >> > #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
> >> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> >> > index f6aaf938c53c..4672894f4bc1 100644
> >> > --- a/drivers/gpu/drm/i915/i915_pci.c
> >> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> > @@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
> >> > PLATFORM(INTEL_METEORLAKE),
> >> > .display.has_modular_fia = 1,
> >> > .has_flat_ccs = 0,
> >> > + .has_gmd_id = 1,
> >> > .has_snoop = 1,
> >> > .__runtime.memory_regions = REGION_SMEM |
> REGION_STOLEN_LMEM,
> >> > .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> >> > index 5e6239864c35..e02e461a4b5d 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -5798,6 +5798,11 @@
> >> > #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> >> > #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> >> >
> >> > +#define GMD_ID_DISPLAY _MMIO(0x510a0)
> >> > +#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
> >> > +#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> >> > +#define GMD_ID_STEP REG_GENMASK(5, 0)
> >> > +
> >> > /*GEN11 chicken */
> >> > #define _PIPEA_CHICKEN 0x70038
> >> > #define _PIPEB_CHICKEN 0x71038
> >> > @@ -8298,4 +8303,6 @@ enum skl_power_gate {
> >> > #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
> >> > #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
> >> >
> >> > +#define MTL_MEDIA_GSI_BASE 0x380000
> >> > +
> >> > #endif /* _I915_REG_H_ */
> >> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> >> > index 56f19683dd55..a5bafc9be1fa 100644
> >> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> > @@ -29,6 +29,7 @@
> >> >
> >> > #include "display/intel_cdclk.h"
> >> > #include "display/intel_de.h"
> >> > +#include "gt/intel_gt_regs.h"
> >> > #include "intel_device_info.h"
> >> > #include "i915_drv.h"
> >> > #include "i915_utils.h"
> >> > @@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p,
> unsigned int num)
> >> > return false;
> >> > }
> >> >
> >> > -void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> >> > +static void intel_device_info_subplatform_init(struct drm_i915_private
> *i915)
> >> > {
> >> > const struct intel_device_info *info = INTEL_INFO(i915);
> >> > const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
> >> > @@ -288,6 +289,77 @@ void intel_device_info_subplatform_init(struct
> drm_i915_private *i915)
> >> > RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
> >> > }
> >> >
> >> > +static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct
> ip_version *ip)
> >> > +{
> >> > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >> > + void __iomem *addr;
> >> > + u32 val;
> >> > + u8 ver = ip->ver;
> >> > + u8 rel = ip->rel;
> >> > +
> >> > + addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
> >> > + if (drm_WARN_ON(&i915->drm, !addr))
> >> > + return;
> >> > +
> >> > + val = ioread32(addr);
> >> > + pci_iounmap(pdev, addr);
> >> > +
> >> > + ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> >> > + ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> >> > + ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
> >> > +
> >> > + /* Sanity check against expected versions from device info */
> >> > + if (ip->ver != ver || ip->rel > rel)
> >>
> >> this doesn't seem correct.. if we have
> >>
> >> ip->ver == 12, ip->rel == 1
> >> ver == 12, rel == 0
> >>
> >> we will print
> >>
> >> Hardware reports GMD IP version 12.1 but minimum expected is 12.0"
> >>
> >> should it be `|| ip->rel < rel`? Once we land the static number in
> >> device info, we can only expect new .rel versions greater than that.
> >
> >I'm not sure how much value there is in keeping this sanity check at all
> >given that we plan to remove the device info versions completely for
> >platforms with GMD_ID. But if you want to test this in an easy-to-read
> >manner in the short term,
> >
> > if (IP_VER(ip->ver, ip->rel) < IP_VER(ver, rel))
> >
> >would probably be best.
>
> I'm ok with removing the sanity check as long as we log the value read.
> We still do when printing all the info, so lgtm.
I agree with Matt's suggestion. Will spin a new rev with IP_VER based check.
Although we print the info later. It is worth doing a sanity check as we read the info.
-RK
>
> Lucas De Marchi
>
> >
> >
> >Matt
> >
> >>
> >> Lucas De Marchi
> >
> >--
> >Matt Roper
> >Graphics Software Engineer
> >VTT-OSGC Platform Enablement
> >Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4.1] drm/i915: Read graphics/media/display arch version from hw
2022-09-02 6:03 ` [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-09-07 20:49 ` [Intel-gfx] " Lucas De Marchi
@ 2022-09-07 23:32 ` Radhakrishna Sripada
1 sibling, 0 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-07 23:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Matt Roper <matthew.d.roper@intel.com>
Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space. New hardware programming
styles, features, and workarounds should be conditional solely on the
architecture version, and should no longer be derived from the PCI
device ID, revision ID, or platform-specific feature flags.
Bspec: 63361, 64111
v2:
- Move the IP version readout to intel_device_info.c
- Convert the macro into a function
v3:
- Move subplatform init to runtime early init
- Cache runtime ver, release info to compare with hardware values.
- Use IP_VER for snaity check(MattR)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
drivers/gpu/drm/i915/i915_driver.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 7 +++
drivers/gpu/drm/i915/intel_device_info.c | 74 +++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
7 files changed, 98 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..579da62158c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -39,6 +39,8 @@
#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
+#define GMD_ID_GRAPHICS _MMIO(0xd8c)
+
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
#define SF_MCR_SELECTOR _MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 56a2bcddb2af..a1ab49521d19 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
- intel_device_info_subplatform_init(dev_priv);
+ intel_device_info_runtime_init_early(dev_priv);
+
intel_step_init(dev_priv);
intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2702e3dbed53..bfb69b65ad67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
+#define HAS_GMD_ID(i915) INTEL_INFO(i915)->has_gmd_id
+
#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f6aaf938c53c..4672894f4bc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
.has_flat_ccs = 0,
+ .has_gmd_id = 1,
.has_snoop = 1,
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c413eec3373f..885ff4598fd4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5798,6 +5798,11 @@
#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
+#define GMD_ID_DISPLAY _MMIO(0x510a0)
+#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
+#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
+#define GMD_ID_STEP REG_GENMASK(5, 0)
+
/*GEN11 chicken */
#define _PIPEA_CHICKEN 0x70038
#define _PIPEB_CHICKEN 0x71038
@@ -8298,4 +8303,6 @@ enum skl_power_gate {
#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
+#define MTL_MEDIA_GSI_BASE 0x380000
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 56f19683dd55..f7472f40ab51 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -29,6 +29,7 @@
#include "display/intel_cdclk.h"
#include "display/intel_de.h"
+#include "gt/intel_gt_regs.h"
#include "intel_device_info.h"
#include "i915_drv.h"
#include "i915_utils.h"
@@ -231,7 +232,7 @@ static bool find_devid(u16 id, const u16 *p, unsigned int num)
return false;
}
-void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
{
const struct intel_device_info *info = INTEL_INFO(i915);
const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
@@ -288,6 +289,77 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
}
+static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct ip_version *ip)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ void __iomem *addr;
+ u32 val;
+ u8 ver = ip->ver;
+ u8 rel = ip->rel;
+
+ addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
+ if (drm_WARN_ON(&i915->drm, !addr))
+ return;
+
+ val = ioread32(addr);
+ pci_iounmap(pdev, addr);
+
+ ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
+ ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
+ ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
+
+ /* Sanity check against expected versions from device info */
+ if (IP_VER(ip->ver, ip->rel) < IP_VER(ver, rel))
+ drm_dbg(&i915->drm,
+ "Hardware reports GMD IP version %u.%u but minimum expected is %u.%u\n",
+ ip->ver, ip->rel, ver, rel);
+}
+
+/**
+ * Setup the graphics version for the current device. This must be done before
+ * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
+ * function should be called very early in the driver initialization sequence.
+ *
+ * Regular MMIO access is not yet setup at the point this function is called so
+ * we peek at the appropriate MMIO offset directly. The GMD_ID register is
+ * part of an 'always on' power well by design, so we don't need to worry about
+ * forcewake while reading it.
+ */
+static void intel_ipver_early_init(struct drm_i915_private *i915)
+{
+ struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
+
+ if (!HAS_GMD_ID(i915))
+ return;
+
+ ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
+ &runtime->graphics.version);
+ ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
+ &runtime->display.version);
+ ip_ver_read(i915, MTL_MEDIA_GSI_BASE + i915_mmio_reg_offset(GMD_ID_GRAPHICS),
+ &runtime->media.version);
+}
+
+/**
+ * intel_device_info_runtime_init_early - initialize early runtime info
+ * @i915: the i915 device
+ *
+ * Determine early intel_device_info fields at runtime.
+ *
+ * Use it when:
+ * - Early init of certain runtime info fields are to be initialized
+ *
+ * This function needs to be called:
+ * - before the MMIO has been setup as we are reading registers,
+ * - before the PCH has been detected,
+ * - before the first usage of the fields it can tweak.
+ */
+void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
+{
+ intel_ipver_early_init(i915);
+ intel_device_info_subplatform_init(i915);
+}
+
/**
* intel_device_info_runtime_init - initialize runtime info
* @dev_priv: the i915 device
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d36cf25f1d5f..4a938cb897d0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -152,6 +152,7 @@ enum intel_ppgtt_type {
func(has_4tile); \
func(has_flat_ccs); \
func(has_global_mocs); \
+ func(has_gmd_id); \
func(has_gt_uc); \
func(has_heci_pxp); \
func(has_heci_gscfi); \
@@ -197,9 +198,18 @@ enum intel_ppgtt_type {
struct ip_version {
u8 ver;
u8 rel;
+ u8 step;
};
struct intel_runtime_info {
+ /*
+ * On modern platforms, the architecture major.minor version numbers
+ * and stepping are read directly from the hardware rather than derived
+ * from the PCI device and revision ID's.
+ *
+ * Note that the hardware gives us a single "graphics" number that
+ * should represent render, compute, and copy behavior.
+ */
struct {
struct ip_version version;
} graphics;
@@ -305,7 +315,7 @@ struct intel_driver_caps {
const char *intel_platform_name(enum intel_platform platform);
-void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
+void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_print(const struct intel_device_info *info,
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4.1] drm/i915/mtl: Define engine context layouts
2022-09-02 6:03 ` [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-09-06 12:16 ` Balasubramani Vivekanandan
@ 2022-09-07 23:33 ` Radhakrishna Sripada
2022-09-08 18:00 ` [Intel-gfx] " Matt Roper
1 sibling, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-07 23:33 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Matt Roper <matthew.d.roper@intel.com>
The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.
For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.
v2:
- Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
- Drop unused registers in mtl rcs offsets.(Bala)
- Add missing nop in xcs offsets(Bala)
Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 82 ++++++++++++++++++++++++++++-
1 file changed, 80 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4..a2247d39bdb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
END
};
+static const u8 mtl_xcs_offsets[] = {
+ NOP(1),
+ LRI(13, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+ NOP(1),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ END
+};
+
static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -606,6 +639,47 @@ static const u8 dg2_rcs_offsets[] = {
END
};
+static const u8 mtl_rcs_offsets[] = {
+ NOP(1),
+ LRI(13, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ NOP(2),
+ LRI(2, POSTED),
+ REG16(0x5a8),
+ REG16(0x5ac),
+
+ NOP(6),
+ LRI(1, 0),
+ REG(0x0c8),
+
+ END
+};
+
#undef END
#undef REG16
#undef REG
@@ -624,7 +698,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
!intel_engine_has_relative_mmio(engine));
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_rcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
@@ -637,7 +713,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
else
return gen8_rcs_offsets;
} else {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_xcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support
2022-09-02 6:03 ` [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
@ 2022-09-08 13:05 ` Balasubramani Vivekanandan
2022-09-08 18:02 ` Matt Roper
1 sibling, 0 replies; 36+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-08 13:05 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: dri-devel
On 01.09.2022 23:03, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-12] are mapped to TC ports.
>
> v2:
> - Drop unused GPIO pins(MattR)
>
> BSpec: 49306
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Original Author: Brian J Lovin
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
> 2 files changed, 16 insertions(+)
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 6f6cfccad477..74443f57f62d 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -117,6 +117,18 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
> [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> };
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4.1] drm/i915: Move display and media IP version to runtime info
2022-09-02 22:10 ` [PATCH v4.1] " Radhakrishna Sripada
@ 2022-09-08 17:21 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-09-08 17:21 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Fri, Sep 02, 2022 at 03:10:54PM -0700, Radhakrishna Sripada wrote:
> Future platforms can read the IP version from a register and the
> IP version numbers need not be hard coded in device info. Move the
> ip version for media and display to runtime info.
>
> On platforms where hard coding of IP version is required, update
> the IP version in __runtime under device_info.
>
> v2:
> - Avoid name collision for ip versions(Jani)
> v4.1:
> - Fix build error in mock_gem_device.c
>
> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 14 +++----
> drivers/gpu/drm/i915/i915_pci.c | 38 +++++++++----------
> drivers/gpu/drm/i915/intel_device_info.c | 28 +++++++++-----
> drivers/gpu/drm/i915/intel_device_info.h | 15 +++++---
> .../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
> 5 files changed, 54 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c9cca165bf5d..f85a470397a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -469,19 +469,19 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>
> #define IP_VER(ver, rel) ((ver) << 8 | (rel))
>
> -#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ver)
> -#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ver, \
> - RUNTIME_INFO(i915)->graphics.rel)
> +#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.version.ver)
> +#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.version.ver, \
> + RUNTIME_INFO(i915)->graphics.version.rel)
> #define IS_GRAPHICS_VER(i915, from, until) \
> (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
>
> -#define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver)
> -#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.ver, \
> - INTEL_INFO(i915)->media.rel)
> +#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.version.ver)
> +#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.version.ver, \
> + RUNTIME_INFO(i915)->media.version.rel)
> #define IS_MEDIA_VER(i915, from, until) \
> (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
>
> -#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
> +#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.version.ver)
> #define IS_DISPLAY_VER(i915, from, until) \
> (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 26b25d9434d6..f6aaf938c53c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -34,9 +34,9 @@
>
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) \
> - .__runtime.graphics.ver = (x), \
> - .media.ver = (x), \
> - .display.ver = (x)
> + .__runtime.graphics.version.ver = (x), \
> + .__runtime.media.version.ver = (x), \
> + .__runtime.display.version.ver = (x)
>
> #define I845_PIPE_OFFSETS \
> .display.pipe_offsets = { \
> @@ -740,7 +740,7 @@ static const struct intel_device_info bxt_info = {
> static const struct intel_device_info glk_info = {
> GEN9_LP_FEATURES,
> PLATFORM(INTEL_GEMINILAKE),
> - .display.ver = 10,
> + .__runtime.display.version.ver = 10,
> .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
> GLK_COLORS,
> };
> @@ -919,7 +919,7 @@ static const struct intel_device_info rkl_info = {
> static const struct intel_device_info dg1_info = {
> GEN12_FEATURES,
> DGFX_FEATURES,
> - .__runtime.graphics.rel = 10,
> + .__runtime.graphics.version.rel = 10,
> PLATFORM(INTEL_DG1),
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> .require_force_probe = 1,
> @@ -962,7 +962,7 @@ static const struct intel_device_info adl_s_info = {
> .display.has_hotplug = 1, \
> .display.has_ipc = 1, \
> .display.has_psr = 1, \
> - .display.ver = 13, \
> + .__runtime.display.version.ver = 13, \
> .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> .display.pipe_offsets = { \
> [TRANSCODER_A] = PIPE_A_OFFSET, \
> @@ -1006,8 +1006,8 @@ static const struct intel_device_info adl_p_info = {
> I915_GTT_PAGE_SIZE_2M
>
> #define XE_HP_FEATURES \
> - .__runtime.graphics.ver = 12, \
> - .__runtime.graphics.rel = 50, \
> + .__runtime.graphics.version.ver = 12, \
> + .__runtime.graphics.version.rel = 50, \
> XE_HP_PAGE_SIZES, \
> .dma_mask_size = 46, \
> .has_3d_pipeline = 1, \
> @@ -1027,8 +1027,8 @@ static const struct intel_device_info adl_p_info = {
> .__runtime.ppgtt_type = INTEL_PPGTT_FULL
>
> #define XE_HPM_FEATURES \
> - .media.ver = 12, \
> - .media.rel = 50
> + .__runtime.media.version.ver = 12, \
> + .__runtime.media.version.rel = 50
>
> __maybe_unused
> static const struct intel_device_info xehpsdv_info = {
> @@ -1053,8 +1053,8 @@ static const struct intel_device_info xehpsdv_info = {
> XE_HP_FEATURES, \
> XE_HPM_FEATURES, \
> DGFX_FEATURES, \
> - .__runtime.graphics.rel = 55, \
> - .media.rel = 55, \
> + .__runtime.graphics.version.rel = 55, \
> + .__runtime.media.version.rel = 55, \
> PLATFORM(INTEL_DG2), \
> .has_4tile = 1, \
> .has_64k_pages = 1, \
> @@ -1097,8 +1097,8 @@ static const struct intel_device_info pvc_info = {
> XE_HPC_FEATURES,
> XE_HPM_FEATURES,
> DGFX_FEATURES,
> - .__runtime.graphics.rel = 60,
> - .media.rel = 60,
> + .__runtime.graphics.version.rel = 60,
> + .__runtime.media.version.rel = 60,
> PLATFORM(INTEL_PONTEVECCHIO),
> .display = { 0 },
> .has_flat_ccs = 0,
> @@ -1111,7 +1111,7 @@ static const struct intel_device_info pvc_info = {
>
> #define XE_LPDP_FEATURES \
> XE_LPD_FEATURES, \
> - .display.ver = 14, \
> + .__runtime.display.version.ver = 14, \
> .display.has_cdclk_crawl = 1, \
> .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
>
> @@ -1123,9 +1123,9 @@ static const struct intel_device_info mtl_info = {
> * Real graphics IP version will be obtained from hardware GMD_ID
> * register. Value provided here is just for sanity checking.
> */
> - .__runtime.graphics.ver = 12,
> - .__runtime.graphics.rel = 70,
> - .media.ver = 13,
> + .__runtime.graphics.version.ver = 12,
> + .__runtime.graphics.version.rel = 70,
> + .__runtime.media.version.ver = 13,
> PLATFORM(INTEL_METEORLAKE),
> .display.has_modular_fia = 1,
> .has_flat_ccs = 0,
> @@ -1281,7 +1281,7 @@ bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
>
> static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
> {
> - int gttmmaddr_bar = intel_info->__runtime.graphics.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
> + int gttmmaddr_bar = intel_info->__runtime.graphics.version.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
>
> return i915_pci_resource_valid(pdev, gttmmaddr_bar);
> }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 0a1f97b35f2b..56f19683dd55 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -92,21 +92,29 @@ void intel_device_info_print(const struct intel_device_info *info,
> const struct intel_runtime_info *runtime,
> struct drm_printer *p)
> {
> - if (runtime->graphics.rel)
> - drm_printf(p, "graphics version: %u.%02u\n", runtime->graphics.ver,
> - runtime->graphics.rel);
> + if (runtime->graphics.version.rel)
> + drm_printf(p, "graphics version: %u.%02u\n",
> + runtime->graphics.version.ver,
> + runtime->graphics.version.rel);
> else
> - drm_printf(p, "graphics version: %u\n", runtime->graphics.ver);
> + drm_printf(p, "graphics version: %u\n",
> + runtime->graphics.version.ver);
>
> - if (info->media.rel)
> - drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel);
> + if (runtime->media.version.rel)
> + drm_printf(p, "media version: %u.%02u\n",
> + runtime->media.version.ver,
> + runtime->media.version.rel);
> else
> - drm_printf(p, "media version: %u\n", info->media.ver);
> + drm_printf(p, "media version: %u\n",
> + runtime->media.version.ver);
>
> - if (info->display.rel)
> - drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel);
> + if (runtime->display.version.rel)
> + drm_printf(p, "display version: %u.%02u\n",
> + runtime->display.version.ver,
> + runtime->display.version.rel);
> else
> - drm_printf(p, "display version: %u\n", info->display.ver);
> + drm_printf(p, "display version: %u\n",
> + runtime->display.version.ver);
>
> drm_printf(p, "gt: %d\n", info->gt);
> drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6904ad03ca19..d36cf25f1d5f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -200,7 +200,15 @@ struct ip_version {
> };
>
> struct intel_runtime_info {
> - struct ip_version graphics;
> + struct {
> + struct ip_version version;
Bikeshed: It might be more natural to name these inner structures 'ip'
rather than 'version' so that elsewhere in the code we'll be dealing
with things like runtime->graphics.ip.ver and runtime->graphics.ip.rel.
Up to you though. Either way,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> + } graphics;
> + struct {
> + struct ip_version version;
> + } media;
> + struct {
> + struct ip_version version;
> + } display;
>
> /*
> * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
> @@ -246,8 +254,6 @@ struct intel_runtime_info {
> };
>
> struct intel_device_info {
> - struct ip_version media;
> -
> enum intel_platform platform;
>
> unsigned int dma_mask_size; /* available DMA address bits */
> @@ -259,9 +265,6 @@ struct intel_device_info {
> #undef DEFINE_FLAG
>
> struct {
> - u8 ver;
> - u8 rel;
> -
> u8 abox_mask;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index f5904e659ef2..869b952c13a0 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -172,7 +172,7 @@ struct drm_i915_private *mock_gem_device(void)
> /* Using the global GTT may ask questions about KMS users, so prepare */
> drm_mode_config_init(&i915->drm);
>
> - RUNTIME_INFO(i915)->graphics.ver = -1;
> + RUNTIME_INFO(i915)->graphics.version.ver = -1;
>
> RUNTIME_INFO(i915)->page_sizes =
> I915_GTT_PAGE_SIZE_4K |
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD
2022-09-02 6:03 ` [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
@ 2022-09-08 17:42 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-09-08 17:42 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Thu, Sep 01, 2022 at 11:03:34PM -0700, Radhakrishna Sripada wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> The GMD step field do not properly match the current stepping convention
> that we use(STEP_A0, STEP_A1, STEP_B0...).
>
> One platform could have { arch = 12, rel = 70, step = 1 } and the
> actual stepping is STEP_B0 but without the translation of the step
> field would mean STEP_A1.
> That is why we will need to have gmd_to_intel_step tables for each IP.
The (unofficial) claim by the hardware team when GMD_ID was introduced
was that they planned to standardize stepping numbering going forward
such that they would leave space for up to four minor steppings between
each major stepping. I.e., B0 is expected to be 0x4 on all future
platforms, C0 is expected to be 0x8, etc.
While I'm not super confident that they'll actually stick with that plan
forever (e.g., what happens if we wind up having an A5 stepping
someday?), it seems like we could at least start with that as our
initial assumption and write generic translation code for now; if/when
we encounter a platform that deviates, we can add a platform-specific
table for it at that time.
Matt
>
> v2:
> - Pass the updated ip version structure
>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_step.c | 60 +++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 42b3133d8387..14ea103d6dab 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -135,6 +135,48 @@ static const struct intel_step_info adlp_n_revids[] = {
> [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
> };
>
> +struct gmd_to_intel_step {
> + struct ip_version gmd;
> + enum intel_step step;
> +};
> +
> +static const struct gmd_to_intel_step gmd_graphics_table[] = {
> + { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
> + { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
> + { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 0, .step = STEP_A0 },
> + { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 4, .step = STEP_B0 },
> + { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 0, .step = STEP_A0 },
> + { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 4, .step = STEP_B0 },
> +};
> +
> +static const struct gmd_to_intel_step gmd_media_table[] = {
> + { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
> + { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
> +};
> +
> +static const struct gmd_to_intel_step gmd_display_table[] = {
> + { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 0, .step = STEP_A0 },
> + { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 4, .step = STEP_B0 },
> +};
> +
> +static u8 gmd_to_intel_step(struct drm_i915_private *i915,
> + struct ip_version *gmd,
> + const struct gmd_to_intel_step *table,
> + int len)
> +{
> + int i;
> +
> + for (i = 0; i < len; i++) {
> + if (table[i].gmd.ver == gmd->ver &&
> + table[i].gmd.rel == gmd->rel &&
> + table[i].gmd.step == gmd->step)
> + return table[i].step;
> + }
> +
> + drm_dbg(&i915->drm, "Using future steppings\n");
> + return STEP_FUTURE;
> +}
> +
> static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
>
> void intel_step_init(struct drm_i915_private *i915)
> @@ -144,6 +186,24 @@ void intel_step_init(struct drm_i915_private *i915)
> int revid = INTEL_REVID(i915);
> struct intel_step_info step = {};
>
> + if (HAS_GMD_ID(i915)) {
> + step.graphics_step = gmd_to_intel_step(i915,
> + &RUNTIME_INFO(i915)->graphics.version,
> + gmd_graphics_table,
> + ARRAY_SIZE(gmd_graphics_table));
> + step.media_step = gmd_to_intel_step(i915,
> + &RUNTIME_INFO(i915)->media.version,
> + gmd_media_table,
> + ARRAY_SIZE(gmd_media_table));
> + step.display_step = gmd_to_intel_step(i915,
> + &RUNTIME_INFO(i915)->display.version,
> + gmd_display_table,
> + ARRAY_SIZE(gmd_display_table));
> + RUNTIME_INFO(i915)->step = step;
> +
> + return;
> + }
> +
> if (IS_PONTEVECCHIO(i915)) {
> pvc_step_init(i915, revid);
> return;
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts
2022-09-07 23:33 ` [PATCH v4.1] " Radhakrishna Sripada
@ 2022-09-08 18:00 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-09-08 18:00 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 04:33:17PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the driver conditions to re-use the DG2
> context table.
>
> For render/compute engines, the part of the context images are nearly
> the same, although the layout had a very slight change --- one POSH
> register was removed and the placement of some LRI/noops adjusted
> slightly to compensate.
>
> v2:
> - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> - Drop unused registers in mtl rcs offsets.(Bala)
> - Add missing nop in xcs offsets(Bala)
>
> Bspec: 46261, 46260, 45585
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 82 ++++++++++++++++++++++++++++-
> 1 file changed, 80 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 070cec4ff8a4..a2247d39bdb7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
> END
> };
>
> +static const u8 mtl_xcs_offsets[] = {
> + NOP(1),
> + LRI(13, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> + NOP(1),
Shouldn't this be NOP(4)?
Matt
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + END
> +};
> +
> static const u8 gen8_rcs_offsets[] = {
> NOP(1),
> LRI(14, POSTED),
> @@ -606,6 +639,47 @@ static const u8 dg2_rcs_offsets[] = {
> END
> };
>
> +static const u8 mtl_rcs_offsets[] = {
> + NOP(1),
> + LRI(13, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + NOP(2),
> + LRI(2, POSTED),
> + REG16(0x5a8),
> + REG16(0x5ac),
> +
> + NOP(6),
> + LRI(1, 0),
> + REG(0x0c8),
> +
> + END
> +};
> +
> #undef END
> #undef REG16
> #undef REG
> @@ -624,7 +698,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> !intel_engine_has_relative_mmio(engine));
>
> if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_rcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_rcs_offsets;
> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> return xehp_rcs_offsets;
> @@ -637,7 +713,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> else
> return gen8_rcs_offsets;
> } else {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_xcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_xcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_xcs_offsets;
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support
2022-09-02 6:03 ` [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
2022-09-08 13:05 ` [Intel-gfx] " Balasubramani Vivekanandan
@ 2022-09-08 18:02 ` Matt Roper
1 sibling, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-09-08 18:02 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Thu, Sep 01, 2022 at 11:03:36PM -0700, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-12] are mapped to TC ports.
>
> v2:
> - Drop unused GPIO pins(MattR)
>
> BSpec: 49306
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Original Author: Brian J Lovin
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 6f6cfccad477..74443f57f62d 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -117,6 +117,18 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
> [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> };
>
> +static const struct gmbus_pin gmbus_pins_mtp[] = {
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> + [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> +};
> +
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> unsigned int pin)
> {
> @@ -129,6 +141,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> pins = gmbus_pins_dg1;
> size = ARRAY_SIZE(gmbus_pins_dg1);
> + } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
> + pins = gmbus_pins_mtp;
> + size = ARRAY_SIZE(gmbus_pins_mtp);
> } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
> pins = gmbus_pins_icp;
> size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_PIN_2_BXT 2
> #define GMBUS_PIN_3_BXT 3
> #define GMBUS_PIN_4_CNP 4
> +#define GMBUS_PIN_5_MTP 5
> #define GMBUS_PIN_9_TC1_ICP 9
> #define GMBUS_PIN_10_TC2_ICP 10
> #define GMBUS_PIN_11_TC3_ICP 11
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 06/11] drm/i915/mtl: Add display power wells
2022-09-02 6:03 ` [PATCH v4 06/11] drm/i915/mtl: Add display power wells Radhakrishna Sripada
@ 2022-09-08 18:07 ` Matt Roper
2022-09-08 18:11 ` Matt Roper
0 siblings, 1 reply; 36+ messages in thread
From: Matt Roper @ 2022-09-08 18:07 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Thu, Sep 01, 2022 at 11:03:37PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Add support for display power wells on MTL. The differences from XE_LPD:
> - The AUX HW block is moved to the PICA block, where the registers are on
> an always-on power well and the functionality needs to be powered on/off
> via the AUX_CH_CTL register: [1], [2]
> - The DDI IO power on/off programming sequence is moved to the PHY PLL
> enable/disable sequence. [3], [4], [5]
>
> Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
>
> v2:
> - Update the comment in aux power well enable
> - Reuse the noop sync fn for aux sync.
> - Use REG_BIT for new register bit definitions
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../i915/display/intel_display_power_map.c | 115 +++++++++++++++++-
> .../i915/display/intel_display_power_well.c | 44 +++++++
> .../i915/display/intel_display_power_well.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++
> drivers/gpu/drm/i915/i915_reg.h | 21 ++++
> 5 files changed, 191 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 5ddd1b93751c..dc04afc6cc8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list xelpd_power_wells[] = {
> I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> };
>
> +/*
> + * MTL is based on XELPD power domains with the exception of power gating for:
> + * - DDI_IO (moved to PLL logic)
> + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on)
> + */
> +#define XELPDP_PW_2_POWER_DOMAINS \
> + XELPD_PW_B_POWER_DOMAINS, \
> + XELPD_PW_C_POWER_DOMAINS, \
> + XELPD_PW_D_POWER_DOMAINS, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC4
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
> + XELPDP_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
> + XELPDP_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
> + POWER_DOMAIN_AUX_USBC1,
> + POWER_DOMAIN_AUX_TBT1);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
> + POWER_DOMAIN_AUX_USBC2,
> + POWER_DOMAIN_AUX_TBT2);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
> + POWER_DOMAIN_AUX_USBC3,
> + POWER_DOMAIN_AUX_TBT3);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
> + POWER_DOMAIN_AUX_USBC4,
> + POWER_DOMAIN_AUX_TBT4);
> +
> +static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
> + {
> + .instances = &I915_PW_INSTANCES(
> + I915_PW("DC_off", &xelpdp_pwdoms_dc_off,
> + .id = SKL_DISP_DC_OFF),
> + ),
> + .ops = &gen9_dc_off_power_well_ops,
> + }, {
> + .instances = &I915_PW_INSTANCES(
> + I915_PW("PW_2", &xelpdp_pwdoms_pw_2,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .id = SKL_DISP_PW_2),
> + ),
> + .ops = &hsw_power_well_ops,
> + .has_vga = true,
> + .has_fuses = true,
> + }, {
> + .instances = &I915_PW_INSTANCES(
> + I915_PW("PW_A", &xelpd_pwdoms_pw_a,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
> + ),
> + .ops = &hsw_power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_A),
> + .has_fuses = true,
> + }, {
> + .instances = &I915_PW_INSTANCES(
> + I915_PW("PW_B", &xelpd_pwdoms_pw_b,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
> + ),
> + .ops = &hsw_power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_B),
> + .has_fuses = true,
> + }, {
> + .instances = &I915_PW_INSTANCES(
> + I915_PW("PW_C", &xelpd_pwdoms_pw_c,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
> + ),
> + .ops = &hsw_power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_C),
> + .has_fuses = true,
> + }, {
> + .instances = &I915_PW_INSTANCES(
> + I915_PW("PW_D", &xelpd_pwdoms_pw_d,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
> + ),
> + .ops = &hsw_power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_D),
> + .has_fuses = true,
> + }, {
> + .instances = &I915_PW_INSTANCES(
> + I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),
> + I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),
> + I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),
> + I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),
> + I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3),
> + I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4),
> + ),
> + .ops = &xelpdp_aux_power_well_ops,
> + },
> +};
> +
> +static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
> + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> + I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> + I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> +};
> +
> static void init_power_well_domains(const struct i915_power_well_instance *inst,
> struct i915_power_well *power_well)
> {
> @@ -1457,7 +1568,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
> return 0;
> }
>
> - if (DISPLAY_VER(i915) >= 13)
> + if (DISPLAY_VER(i915) >= 14)
> + return set_power_wells(power_domains, xelpdp_power_wells);
> + else if (DISPLAY_VER(i915) >= 13)
> return set_power_wells(power_domains, xelpd_power_wells);
> else if (IS_DG1(i915))
> return set_power_wells(power_domains, dg1_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 29cc05c04c65..9bf98a37204b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1798,6 +1798,43 @@ tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
> return intel_power_well_refcount(power_well);
> }
>
> +static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> +
> + intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
> +
> + /*
> + * The power status flag cannot be used to determine whether aux
> + * power wells have finished powering up. Instead we're
> + * expected to just wait a fixed 600us after raising the request
> + * bit.
> + */
> + usleep_range(600, 1200);
> +}
> +
> +static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> +
> + intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> + 0);
> + usleep_range(10, 30);
> +}
> +
> +static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> +
> + return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
> + XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
> +}
>
> const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> @@ -1911,3 +1948,10 @@ const struct i915_power_well_ops tgl_tc_cold_off_ops = {
> .disable = tgl_tc_cold_off_power_well_disable,
> .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
> };
> +
> +const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = xelpdp_aux_power_well_enable,
> + .disable = xelpdp_aux_power_well_disable,
> + .is_enabled = xelpdp_aux_power_well_enabled,
> +};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index 31a898176ebb..e13b521e322a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -80,6 +80,9 @@ struct i915_power_well_instance {
> */
> u8 idx;
> } hsw;
> + struct {
> + u8 aux_ch;
> + } xelpdp;
> };
> };
>
> @@ -169,5 +172,6 @@ extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
> extern const struct i915_power_well_ops icl_aux_power_well_ops;
> extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> +extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index f2ad1d09ab43..98bd33645b43 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -150,6 +150,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> u32 unused)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> u32 ret;
>
> /*
> @@ -170,6 +171,13 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> if (intel_tc_port_in_tbt_alt_mode(dig_port))
> ret |= DP_AUX_CH_CTL_TBT_IO;
>
> + /*
> + * Power request bit is already set during aux power well enable.
> + * Preserve the bit across aux transactions.
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST;
> +
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e02e461a4b5d..99b2cd2abca4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3451,6 +3451,25 @@
> #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>
> +#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
> +#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
> +#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
> +#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
> +
> +#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
> +#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
> +#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
> +#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
> +
> +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
> + _DPA_AUX_CH_CTL, \
> + _DPB_AUX_CH_CTL, \
> + 0, /* port/aux_ch C is non-existent */ \
> + _XELPDP_USBC1_AUX_CH_CTL, \
> + _XELPDP_USBC2_AUX_CH_CTL, \
> + _XELPDP_USBC3_AUX_CH_CTL, \
> + _XELPDP_USBC4_AUX_CH_CTL))
> +
> #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
> #define DP_AUX_CH_CTL_DONE (1 << 30)
> #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
> @@ -3463,6 +3482,8 @@
> #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
> +#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
> +#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
> #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
> #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
> #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 06/11] drm/i915/mtl: Add display power wells
2022-09-08 18:07 ` Matt Roper
@ 2022-09-08 18:11 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-09-08 18:11 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Thu, Sep 08, 2022 at 11:07:16AM -0700, Matt Roper wrote:
> On Thu, Sep 01, 2022 at 11:03:37PM -0700, Radhakrishna Sripada wrote:
> > From: Imre Deak <imre.deak@intel.com>
> >
> > Add support for display power wells on MTL. The differences from XE_LPD:
> > - The AUX HW block is moved to the PICA block, where the registers are on
> > an always-on power well and the functionality needs to be powered on/off
> > via the AUX_CH_CTL register: [1], [2]
> > - The DDI IO power on/off programming sequence is moved to the PHY PLL
> > enable/disable sequence. [3], [4], [5]
> >
> > Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
> >
> > v2:
> > - Update the comment in aux power well enable
> > - Reuse the noop sync fn for aux sync.
> > - Use REG_BIT for new register bit definitions
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Oops, one very minor comment down at the bottom.
>
> > ---
> > .../i915/display/intel_display_power_map.c | 115 +++++++++++++++++-
> > .../i915/display/intel_display_power_well.c | 44 +++++++
> > .../i915/display/intel_display_power_well.h | 4 +
> > drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++
> > drivers/gpu/drm/i915/i915_reg.h | 21 ++++
> > 5 files changed, 191 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 5ddd1b93751c..dc04afc6cc8f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list xelpd_power_wells[] = {
> > I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> > };
> >
> > +/*
> > + * MTL is based on XELPD power domains with the exception of power gating for:
> > + * - DDI_IO (moved to PLL logic)
> > + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on)
> > + */
> > +#define XELPDP_PW_2_POWER_DOMAINS \
> > + XELPD_PW_B_POWER_DOMAINS, \
> > + XELPD_PW_C_POWER_DOMAINS, \
> > + XELPD_PW_D_POWER_DOMAINS, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC4
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
> > + XELPDP_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
> > + XELPDP_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
> > + POWER_DOMAIN_AUX_USBC1,
> > + POWER_DOMAIN_AUX_TBT1);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
> > + POWER_DOMAIN_AUX_USBC2,
> > + POWER_DOMAIN_AUX_TBT2);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
> > + POWER_DOMAIN_AUX_USBC3,
> > + POWER_DOMAIN_AUX_TBT3);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
> > + POWER_DOMAIN_AUX_USBC4,
> > + POWER_DOMAIN_AUX_TBT4);
> > +
> > +static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
> > + {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("DC_off", &xelpdp_pwdoms_dc_off,
> > + .id = SKL_DISP_DC_OFF),
> > + ),
> > + .ops = &gen9_dc_off_power_well_ops,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("PW_2", &xelpdp_pwdoms_pw_2,
> > + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> > + .id = SKL_DISP_PW_2),
> > + ),
> > + .ops = &hsw_power_well_ops,
> > + .has_vga = true,
> > + .has_fuses = true,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("PW_A", &xelpd_pwdoms_pw_a,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
> > + ),
> > + .ops = &hsw_power_well_ops,
> > + .irq_pipe_mask = BIT(PIPE_A),
> > + .has_fuses = true,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("PW_B", &xelpd_pwdoms_pw_b,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
> > + ),
> > + .ops = &hsw_power_well_ops,
> > + .irq_pipe_mask = BIT(PIPE_B),
> > + .has_fuses = true,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("PW_C", &xelpd_pwdoms_pw_c,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
> > + ),
> > + .ops = &hsw_power_well_ops,
> > + .irq_pipe_mask = BIT(PIPE_C),
> > + .has_fuses = true,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("PW_D", &xelpd_pwdoms_pw_d,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
> > + ),
> > + .ops = &hsw_power_well_ops,
> > + .irq_pipe_mask = BIT(PIPE_D),
> > + .has_fuses = true,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),
> > + I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),
> > + I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),
> > + I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),
> > + I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3),
> > + I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4),
> > + ),
> > + .ops = &xelpdp_aux_power_well_ops,
> > + },
> > +};
> > +
> > +static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
> > + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> > + I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> > + I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> > +};
> > +
> > static void init_power_well_domains(const struct i915_power_well_instance *inst,
> > struct i915_power_well *power_well)
> > {
> > @@ -1457,7 +1568,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
> > return 0;
> > }
> >
> > - if (DISPLAY_VER(i915) >= 13)
> > + if (DISPLAY_VER(i915) >= 14)
> > + return set_power_wells(power_domains, xelpdp_power_wells);
> > + else if (DISPLAY_VER(i915) >= 13)
> > return set_power_wells(power_domains, xelpd_power_wells);
> > else if (IS_DG1(i915))
> > return set_power_wells(power_domains, dg1_power_wells);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 29cc05c04c65..9bf98a37204b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -1798,6 +1798,43 @@ tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
> > return intel_power_well_refcount(power_well);
> > }
> >
> > +static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
> > + struct i915_power_well *power_well)
> > +{
> > + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> > +
> > + intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> > + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> > + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
> > +
> > + /*
> > + * The power status flag cannot be used to determine whether aux
> > + * power wells have finished powering up. Instead we're
> > + * expected to just wait a fixed 600us after raising the request
> > + * bit.
> > + */
> > + usleep_range(600, 1200);
> > +}
> > +
> > +static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
> > + struct i915_power_well *power_well)
> > +{
> > + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> > +
> > + intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> > + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> > + 0);
> > + usleep_range(10, 30);
> > +}
> > +
> > +static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
> > + struct i915_power_well *power_well)
> > +{
> > + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> > +
> > + return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
> > + XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
> > +}
> >
> > const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> > .sync_hw = i9xx_power_well_sync_hw_noop,
> > @@ -1911,3 +1948,10 @@ const struct i915_power_well_ops tgl_tc_cold_off_ops = {
> > .disable = tgl_tc_cold_off_power_well_disable,
> > .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
> > };
> > +
> > +const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
> > + .sync_hw = i9xx_power_well_sync_hw_noop,
> > + .enable = xelpdp_aux_power_well_enable,
> > + .disable = xelpdp_aux_power_well_disable,
> > + .is_enabled = xelpdp_aux_power_well_enabled,
> > +};
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > index 31a898176ebb..e13b521e322a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> > @@ -80,6 +80,9 @@ struct i915_power_well_instance {
> > */
> > u8 idx;
> > } hsw;
> > + struct {
> > + u8 aux_ch;
> > + } xelpdp;
> > };
> > };
> >
> > @@ -169,5 +172,6 @@ extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
> > extern const struct i915_power_well_ops icl_aux_power_well_ops;
> > extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> > extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> > +extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
> >
> > #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > index f2ad1d09ab43..98bd33645b43 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > @@ -150,6 +150,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> > u32 unused)
> > {
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > u32 ret;
> >
> > /*
> > @@ -170,6 +171,13 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> > if (intel_tc_port_in_tbt_alt_mode(dig_port))
> > ret |= DP_AUX_CH_CTL_TBT_IO;
> >
> > + /*
> > + * Power request bit is already set during aux power well enable.
> > + * Preserve the bit across aux transactions.
> > + */
> > + if (DISPLAY_VER(i915) >= 14)
> > + ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST;
> > +
> > return ret;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e02e461a4b5d..99b2cd2abca4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3451,6 +3451,25 @@
> > #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> > #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >
> > +#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
> > +#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
> > +#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
> > +#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
> > +
> > +#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
> > +#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
> > +#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
> > +#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
These data register definitions aren't used until the next patch, so you
should probably move them there.
Aside from that, the r-b still stands.
Matt
> > +
> > +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
> > + _DPA_AUX_CH_CTL, \
> > + _DPB_AUX_CH_CTL, \
> > + 0, /* port/aux_ch C is non-existent */ \
> > + _XELPDP_USBC1_AUX_CH_CTL, \
> > + _XELPDP_USBC2_AUX_CH_CTL, \
> > + _XELPDP_USBC3_AUX_CH_CTL, \
> > + _XELPDP_USBC4_AUX_CH_CTL))
> > +
> > #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
> > #define DP_AUX_CH_CTL_DONE (1 << 30)
> > #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
> > @@ -3463,6 +3482,8 @@
> > #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
> > #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
> > #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
> > +#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
> > +#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
> > #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
> > #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
> > #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
> > --
> > 2.34.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports
2022-09-02 6:03 ` [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
@ 2022-09-08 18:13 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-09-08 18:13 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Thu, Sep 01, 2022 at 11:03:38PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
> changed wrt. previous platforms, adjust the code accordingly.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
As noted on the previous patch, the _XELPDP_USBC1_AUX_CH_DATA*
definitions aren't used until this patch so they should probably move
into this one. Aside from that,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 ++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++
> 2 files changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 98bd33645b43..48c375c65a41 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -637,6 +637,46 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
> }
> }
>
> +static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + return XELPDP_DP_AUX_CH_CTL(aux_ch);
> + default:
> + MISSING_CASE(aux_ch);
> + return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
> + }
> +}
> +
> +static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
> + default:
> + MISSING_CASE(aux_ch);
> + return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
> + }
> +}
> +
> void intel_dp_aux_fini(struct intel_dp *intel_dp)
> {
> if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
> @@ -652,7 +692,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
> struct intel_encoder *encoder = &dig_port->base;
> enum aux_ch aux_ch = dig_port->aux_ch;
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
> intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
> } else if (DISPLAY_VER(dev_priv) >= 9) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 99b2cd2abca4..4ec6a3dd1f2b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3470,6 +3470,15 @@
> _XELPDP_USBC3_AUX_CH_CTL, \
> _XELPDP_USBC4_AUX_CH_CTL))
>
> +#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
> + _DPA_AUX_CH_DATA1, \
> + _DPB_AUX_CH_DATA1, \
> + 0, /* port/aux_ch C is non-existent */ \
> + _XELPDP_USBC1_AUX_CH_DATA1, \
> + _XELPDP_USBC2_AUX_CH_DATA1, \
> + _XELPDP_USBC3_AUX_CH_DATA1, \
> + _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> +
> #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
> #define DP_AUX_CH_CTL_DONE (1 << 30)
> #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits
2022-09-02 6:03 ` [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
@ 2022-09-08 20:02 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-09-08 20:02 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Thu, Sep 01, 2022 at 11:03:40PM -0700, Radhakrishna Sripada wrote:
> Display version 14 platforms have different credits values
> compared to ADL-P. Update the credits based on pipe usage.
>
> v2: Simplify DBOX BW Credit definition(MattR)
>
> Bspec: 49213
>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Original Author: Caz Yokoyama
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++
> drivers/gpu/drm/i915/intel_pm.c | 47 ++++++++++++++++++++++++++++++---
> 2 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d22fabe35a0c..f9237586ab4f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1125,8 +1125,12 @@
> #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
> #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
> #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
> +#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
> +#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
> #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
> #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
> +#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
> +#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
> #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
> #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ebce6171ccef..b19a1ecb010e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8448,6 +8448,27 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> new_dbuf_state->enabled_slices);
> }
>
> +static bool xelpdp_is_one_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
Bikeshed: s/one/only/ might be slightly more clear?
> +{
> + switch (pipe) {
> + case PIPE_A:
> + case PIPE_D:
> + if (is_power_of_2(active_pipes & (BIT(PIPE_A) | BIT(PIPE_D))))
Bikeshed: writing this with hweight might be more intuitive than
power_of_2? Or even just a direct check of the other pipe like
case PIPE_A:
return !(active_pipes & BIT(PIPE_D))
case PIPE_D:
return !(active_pipes & BIT(PIPE_A))
...
> + return true;
> + break;
> + case PIPE_B:
> + case PIPE_C:
> + if (is_power_of_2(active_pipes & (BIT(PIPE_B) | BIT(PIPE_C))))
> + return true;
> + break;
> + default: /* to suppress compiler warning */
> + MISSING_CASE(pipe);
> + break;
> + }
> +
> + return false;
> +}
> +
> void intel_mbus_dbox_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> @@ -8467,20 +8488,28 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
> return;
>
> + if (DISPLAY_VER(i915) >= 14)
> + val |= MBUS_DBOX_I_CREDIT(2);
> +
> if (DISPLAY_VER(i915) >= 12) {
> val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> }
>
> - /* Wa_22010947358:adl-p */
> - if (IS_ALDERLAKE_P(i915))
> + if (DISPLAY_VER(i915) >= 14)
> + val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
> + MBUS_DBOX_A_CREDIT(8);
> + else if (IS_ALDERLAKE_P(i915))
> + /* Wa_22010947358:adl-p */
> val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> MBUS_DBOX_A_CREDIT(4);
> else
> val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (IS_ALDERLAKE_P(i915)) {
> + if (DISPLAY_VER(i915) >= 14) {
> + val |= MBUS_DBOX_B_CREDIT(0xA);
> + } else if (IS_ALDERLAKE_P(i915)) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(8);
> } else if (DISPLAY_VER(i915) >= 12) {
> @@ -8492,10 +8521,20 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> }
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + u32 pipe_val = val;
> +
> if (!new_crtc_state->hw.active ||
> !intel_crtc_needs_modeset(new_crtc_state))
> continue;
What if the number of BW credits for a pipe changes when this pipe
itself isn't undergoing a modeset? E.g., what if you initially had pipe
A active as the only pipe and thus programmed 8 BW credits. Then you
turn on pipe D; since we're not touching pipe A directly we skip any
programming here (leaving it at 8 credits) and only program the 4
credits for pipe D's instance of the register. Am I missing something
here?
Matt
>
> - intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val);
> + if (DISPLAY_VER(i915) >= 14) {
> + if (xelpdp_is_one_pipe_per_dbuf_bank(crtc->pipe,
> + new_dbuf_state->active_pipes))
> + pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
> + else
> + pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
> + }
> +
> + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
> }
> }
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses
2022-09-02 6:03 ` [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
@ 2022-09-08 20:30 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-09-08 20:30 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Thu, Sep 01, 2022 at 11:03:41PM -0700, Radhakrishna Sripada wrote:
> From: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
>
> In Display version 14, Transcoder Chicken Registers have updated address.
> This patch performs checks to use the right register when required.
>
> v2: Omit display version check in i915_reg.h(Jani)
>
> Bspec: 34387, 50054
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++-
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +++--
> drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++-----
> 4 files changed, 38 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index be7cff722196..a3d0d12084a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -618,7 +618,10 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
> if (!IS_I830(dev_priv))
> val &= ~PIPECONF_ENABLE;
>
> - if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 14)
> + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
> + FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
> + else if (DISPLAY_VER(dev_priv) >= 12)
> intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
> FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
>
> @@ -1838,7 +1841,9 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
> + enum transcoder transcoder = crtc_state->cpu_transcoder;
> + i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
> + CHICKEN_TRANS(transcoder);
> u32 val;
>
> val = intel_de_read(dev_priv, reg);
> @@ -4033,6 +4038,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_display_power_domain_set power_domain_set = { };
> + i915_reg_t reg;
> bool active;
> u32 tmp;
>
> @@ -4124,7 +4130,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> }
>
> if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> - tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder));
> + reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
> + CHICKEN_TRANS(pipe_config->cpu_transcoder);
> + tmp = intel_de_read(dev_priv, reg);
>
> pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
> } else {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 13abe2b2170e..298004cae5a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -568,7 +568,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
> drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
> drm_atomic_get_mst_payload_state(mst_state, connector->port));
>
> - if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
> + if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
> + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
> + FECSTALL_DIS_DPTSTREAM_DPTTG);
> + else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
> intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
> FECSTALL_DIS_DPTSTREAM_DPTTG);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 079b7d3d0c53..da2d0661b630 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1139,7 +1139,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>
> if (intel_dp->psr.psr2_enabled) {
> if (DISPLAY_VER(dev_priv) == 9)
> - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
> + intel_de_rmw(dev_priv,
> + CHICKEN_TRANS(cpu_transcoder), 0,
This whitespace-only change on a non-MTL codepath doesn't look
necessary.
> PSR2_VSC_ENABLE_PROG_HEADER |
> PSR2_ADD_VERTICAL_LINE_COUNT);
>
> @@ -1149,7 +1150,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> * cause issues if non-supported panels are used.
> */
> if (IS_ALDERLAKE_P(dev_priv))
> - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
> + intel_de_rmw(dev_priv,
> + CHICKEN_TRANS(cpu_transcoder), 0,
Ditto.
> ADLP_1_BASED_X_GRANULARITY);
>
> /* Wa_16011168373:adl-p */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f9237586ab4f..8be7685e8a3e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5717,17 +5717,30 @@
> #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> +#define _MTL_CHICKEN_TRANS_A 0x604e0
> +#define _MTL_CHICKEN_TRANS_B 0x614e0
> +#define _MTL_CHICKEN_TRANS_C 0x624e0
> +#define _MTL_CHICKEN_TRANS_D 0x634e0
> +
> #define _CHICKEN_TRANS_A 0x420c0
> #define _CHICKEN_TRANS_B 0x420c4
> #define _CHICKEN_TRANS_C 0x420c8
> #define _CHICKEN_TRANS_EDP 0x420cc
> #define _CHICKEN_TRANS_D 0x420d8
> -#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> - [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
> - [TRANSCODER_A] = _CHICKEN_TRANS_A, \
> - [TRANSCODER_B] = _CHICKEN_TRANS_B, \
> - [TRANSCODER_C] = _CHICKEN_TRANS_C, \
> - [TRANSCODER_D] = _CHICKEN_TRANS_D))
> +
> +#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
Nitpick: there's an extra space between 'define' and the register name
that shouldn't be there (same with the MTL definition below). It looks
like some of the subsequent register definitions in i915_reg.h are
misformatted, but we shouldn't copy that mistake here.
> + [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
> + [TRANSCODER_A] = _CHICKEN_TRANS_A, \
> + [TRANSCODER_B] = _CHICKEN_TRANS_B, \
> + [TRANSCODER_C] = _CHICKEN_TRANS_C, \
> + [TRANSCODER_D] = _CHICKEN_TRANS_D))
> +
> +#define MTL_CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> + [TRANSCODER_A] = _MTL_CHICKEN_TRANS_A, \
> + [TRANSCODER_B] = _MTL_CHICKEN_TRANS_B, \
> + [TRANSCODER_C] = _MTL_CHICKEN_TRANS_C, \
> + [TRANSCODER_D] = _MTL_CHICKEN_TRANS_D))
The registers are equally-spaced and there's no edp transcoder anymore,
so this definition can be simplified down to just
#define MTL_CHICKEN_TRANS _MMIO_TRANS((trans), \
_MTL_CHICKEN_TRANS_A, \
_MTL_CHICKEN_TRANS_B)
and we can drop the definitions of _MTL_CHICKEN_TRANS_C and
_MTL_CHICKEN_TRANS_D.
Matt
> +
> #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
> #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
> #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 11/11] drm/i915/mtl: Do not update GV point, mask value
2022-09-02 6:03 ` [PATCH v4 11/11] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
@ 2022-09-09 17:14 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 36+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-09 17:14 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: dri-devel
On 01.09.2022 23:03, Radhakrishna Sripada wrote:
> Display 14 and future platforms do not directly communicate to Pcode
> via mailbox the SAGV bandwidth information. PM Demand registers are
> used to communicate display power requirements to the PUnit which would
> include GV point and mask value.
>
> Skip programming GV point and mask values through legacy pcode mailbox
> interface.
I agree to Matt's suggestion in v2 of this patch series, to move this
patch to the future series where we would introduce the new pm_demand
interface. It would make more sense there.
>
> Bspec: 64636
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b19a1ecb010e..69efd613bbde 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3923,6 +3923,14 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>
> + /*
> + * No need to update mask value/restrict because
> + * "Pcode only wants to use GV bandwidth value, not the mask value."
> + * for DISPLAY_VER() >= 14.
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + return;
> +
My suggestion would be to remove the DISPLAY version check here and do
it at the place where this function is invoked from. So for versions
<14, intel_sagv_pre_plane_update can be called and for higher we need to
implement the new pm_demand interface.
> /*
> * Just return if we can't control SAGV or don't have it.
> * This is different from situation when we have SAGV but just can't
> @@ -3943,6 +3951,16 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>
> + /*
> + * No need to update mask value/restrict because
> + * "Pcode only wants to use GV bandwidth value, not the mask value."
> + * for DISPLAY_VER() >= 14.
> + *
> + * GV bandwidth will be set by intel_pmdemand_post_plane_update()
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + return;
ditto
> +
> /*
> * Just return if we can't control SAGV or don't have it.
> * This is different from situation when we have SAGV but just can't
Regards,
Bala
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v4.1] drm/i915/mtl: Define engine context layouts
2022-09-30 0:10 ` Lucas De Marchi
@ 2022-10-03 15:33 ` Sripada, Radhakrishna
0 siblings, 0 replies; 36+ messages in thread
From: Sripada, Radhakrishna @ 2022-10-03 15:33 UTC (permalink / raw)
To: De Marchi, Lucas; +Cc: intel-gfx, dri-devel
> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Thursday, September 29, 2022 5:11 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: Re: [PATCH v4.1] drm/i915/mtl: Define engine context layouts
>
> On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote:
> >From: Matt Roper <matthew.d.roper@intel.com>
> >
> >The part of the media and blitter engine contexts that we care about for
> >setting up an initial state on MTL are nearly similar to DG2 (and PVC).
> >The difference being PRT_BB_STATE being replaced with NOP.
> >
> >For render/compute engines, the part of the context images are nearly
> >the same, although the layout had a very slight change --- one POSH
> >register was removed and the placement of some LRI/noops adjusted
> >slightly to compensate.
> >
> >v2:
> > - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> > - Add missing nop in xcs offsets(Bala)
> >v3:
> > - Fix the spacing for nop in xcs offset(MattR)
> >v4:
> > - Fix rcs register offset(MattR)
> >v4.1:
> > - Fix commit message(Lucas)
> >
> >Bspec: 46261, 46260, 45585
> >Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> >Cc: Licas De Marchi <lucas.demarchi@intel.com>
> >Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Pushed the patch, Thanks for the review.
-Radhakrishna Sripada
>
> Lucas De Marchi
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4.1] drm/i915/mtl: Define engine context layouts
2022-09-28 15:55 Radhakrishna Sripada
@ 2022-09-30 0:10 ` Lucas De Marchi
2022-10-03 15:33 ` Sripada, Radhakrishna
0 siblings, 1 reply; 36+ messages in thread
From: Lucas De Marchi @ 2022-09-30 0:10 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, dri-devel
On Wed, Sep 28, 2022 at 08:55:11AM -0700, Radhakrishna Sripada wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>The part of the media and blitter engine contexts that we care about for
>setting up an initial state on MTL are nearly similar to DG2 (and PVC).
>The difference being PRT_BB_STATE being replaced with NOP.
>
>For render/compute engines, the part of the context images are nearly
>the same, although the layout had a very slight change --- one POSH
>register was removed and the placement of some LRI/noops adjusted
>slightly to compensate.
>
>v2:
> - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> - Add missing nop in xcs offsets(Bala)
>v3:
> - Fix the spacing for nop in xcs offset(MattR)
>v4:
> - Fix rcs register offset(MattR)
>v4.1:
> - Fix commit message(Lucas)
>
>Bspec: 46261, 46260, 45585
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Cc: Licas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4.1] drm/i915/mtl: Define engine context layouts
@ 2022-09-28 15:55 Radhakrishna Sripada
2022-09-30 0:10 ` Lucas De Marchi
0 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-28 15:55 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Matt Roper <matthew.d.roper@intel.com>
The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.
For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.
v2:
- Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
- Add missing nop in xcs offsets(Bala)
v3:
- Fix the spacing for nop in xcs offset(MattR)
v4:
- Fix rcs register offset(MattR)
v4.1:
- Fix commit message(Lucas)
Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Licas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 82d899f170fb..e84ef3859934 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
END
};
+static const u8 mtl_xcs_offsets[] = {
+ NOP(1),
+ LRI(13, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+ NOP(4),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ END
+};
+
static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
END
};
+static const u8 mtl_rcs_offsets[] = {
+ NOP(1),
+ LRI(15, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+ REG(0x120),
+ REG(0x124),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ NOP(2),
+ LRI(2, POSTED),
+ REG16(0x5a8),
+ REG16(0x5ac),
+
+ NOP(6),
+ LRI(1, 0),
+ REG(0x0c8),
+
+ END
+};
+
#undef END
#undef REG16
#undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
!intel_engine_has_relative_mmio(engine));
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_rcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
else
return gen8_rcs_offsets;
} else {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_xcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4.1] drm/i915/mtl: Define engine context layouts
2022-09-16 1:46 [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
@ 2022-09-26 21:43 ` Radhakrishna Sripada
0 siblings, 0 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-26 21:43 UTC (permalink / raw)
To: intel-gfx
Cc: lucas.demarchi, Balasubramani Vivekanandan, dri-devel,
Radhakrishna Sripada
From: Matt Roper <matthew.d.roper@intel.com>
The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.
For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.
v2:
- Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
- Add missing nop in xcs offsets(Bala)
v3:
- Fix the spacing for nop in xcs offset(MattR)
v4:
- Fix rcs register offset(MattR)
v4.1:
- Fix commit message(Lucas)
Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Licas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 82d899f170fb..e84ef3859934 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
END
};
+static const u8 mtl_xcs_offsets[] = {
+ NOP(1),
+ LRI(13, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+ NOP(4),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ END
+};
+
static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
END
};
+static const u8 mtl_rcs_offsets[] = {
+ NOP(1),
+ LRI(15, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+ REG(0x120),
+ REG(0x124),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ NOP(2),
+ LRI(2, POSTED),
+ REG16(0x5a8),
+ REG16(0x5ac),
+
+ NOP(6),
+ LRI(1, 0),
+ REG(0x0c8),
+
+ END
+};
+
#undef END
#undef REG16
#undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
!intel_engine_has_relative_mmio(engine));
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_rcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
else
return gen8_rcs_offsets;
} else {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+ return mtl_xcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread
end of thread, other threads:[~2022-10-03 15:33 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
2022-09-02 16:49 ` kernel test robot
2022-09-02 22:10 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-08 17:21 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-09-07 20:49 ` [Intel-gfx] " Lucas De Marchi
2022-09-07 22:13 ` Matt Roper
2022-09-07 22:21 ` Lucas De Marchi
2022-09-07 22:38 ` Sripada, Radhakrishna
2022-09-07 23:32 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
2022-09-08 17:42 ` [Intel-gfx] " Matt Roper
2022-09-02 6:03 ` [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-09-06 12:16 ` Balasubramani Vivekanandan
2022-09-07 23:33 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-08 18:00 ` [Intel-gfx] " Matt Roper
2022-09-02 6:03 ` [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
2022-09-08 13:05 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-09-08 18:02 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 06/11] drm/i915/mtl: Add display power wells Radhakrishna Sripada
2022-09-08 18:07 ` Matt Roper
2022-09-08 18:11 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
2022-09-08 18:13 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 08/11] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
2022-09-08 20:02 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-09-08 20:30 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 11/11] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
2022-09-09 17:14 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-09-16 1:46 [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-09-26 21:43 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-28 15:55 Radhakrishna Sripada
2022-09-30 0:10 ` Lucas De Marchi
2022-10-03 15:33 ` Sripada, Radhakrishna
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