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* [PATCH v4 00/11] Initial Meteorlake Support
@ 2022-09-02  6:03 Radhakrishna Sripada
  2022-09-02  6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
                   ` (10 more replies)
  0 siblings, 11 replies; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-02  6:03 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

The PCI Id's and platform definition are posted earlier.
This series adds handful of early enablement patches including
support for display power wells, VBT and AUX Channel mapping,
PCH and gmbus support, dbus, mbus, sagv and memory bandwidth support.

This series also add the support for a new way to read Graphics,
Media and Display versions

This is based out of the earlier series posted at [1]. Several
of the patches from the earlier series got merged. This version is
rebased on top of the earlier patches that got merged.

[1] https://patchwork.freedesktop.org/series/106786/

Imre Deak (2):
  drm/i915/mtl: Add display power wells
  drm/i915/mtl: Add DP AUX support on TypeC ports

José Roberto de Souza (1):
  drm/i915: Parse and set stepping for platforms with GMD

Madhumitha Tolakanahalli Pradeep (1):
  drm/i915/mtl: Update CHICKEN_TRANS* register addresses

Matt Roper (2):
  drm/i915: Read graphics/media/display arch version from hw
  drm/i915/mtl: Define engine context layouts

Radhakrishna Sripada (5):
  drm/i915: Move display and media IP version to runtime info
  drm/i915/mtl: Add gmbus and gpio support
  drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox
  drm/i915/mtl: Update MBUS_DBOX credits
  drm/i915/mtl: Do not update GV point, mask value

 drivers/gpu/drm/i915/display/intel_bw.c       |  42 ++++++-
 drivers/gpu/drm/i915/display/intel_display.c  |  14 ++-
 .../i915/display/intel_display_power_map.c    | 115 +++++++++++++++++-
 .../i915/display/intel_display_power_well.c   |  44 +++++++
 .../i915/display/intel_display_power_well.h   |   4 +
 drivers/gpu/drm/i915/display/intel_dp_aux.c   |  53 +++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   5 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  15 +++
 drivers/gpu/drm/i915/display/intel_gmbus.h    |   1 +
 drivers/gpu/drm/i915/display/intel_psr.c      |   6 +-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h       |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  81 +++++++++++-
 drivers/gpu/drm/i915/i915_driver.c            |   3 +-
 drivers/gpu/drm/i915/i915_drv.h               |  16 +--
 drivers/gpu/drm/i915/i915_pci.c               |  39 +++---
 drivers/gpu/drm/i915/i915_reg.h               |  83 ++++++++++++-
 drivers/gpu/drm/i915/intel_device_info.c      | 102 ++++++++++++++--
 drivers/gpu/drm/i915/intel_device_info.h      |  27 ++--
 drivers/gpu/drm/i915/intel_dram.c             |  41 ++++++-
 drivers/gpu/drm/i915/intel_pm.c               |  73 ++++++++++-
 drivers/gpu/drm/i915/intel_step.c             |  60 +++++++++
 21 files changed, 754 insertions(+), 72 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 36+ messages in thread
* [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts
@ 2022-09-16  1:46 Radhakrishna Sripada
  2022-09-26 21:43 ` [PATCH v4.1] " Radhakrishna Sripada
  0 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-16  1:46 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3955292483a6..c7937d8d120a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	NOP(4),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+	NOP(1),
+	LRI(15, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	REG(0x120),
+	REG(0x124),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	NOP(2),
+	LRI(2, POSTED),
+	REG16(0x5a8),
+	REG16(0x5ac),
+
+	NOP(6),
+	LRI(1, 0),
+	REG(0x0c8),
+
+	END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [PATCH v4.1] drm/i915/mtl: Define engine context layouts
@ 2022-09-28 15:55 Radhakrishna Sripada
  2022-09-30  0:10 ` Lucas De Marchi
  0 siblings, 1 reply; 36+ messages in thread
From: Radhakrishna Sripada @ 2022-09-28 15:55 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

From: Matt Roper <matthew.d.roper@intel.com>

The part of the media and blitter engine contexts that we care about for
setting up an initial state on MTL are nearly similar to DG2 (and PVC).
The difference being PRT_BB_STATE being replaced with NOP.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Add missing nop in xcs offsets(Bala)
v3:
 - Fix the spacing for nop in xcs offset(MattR)
v4:
 - Fix rcs register offset(MattR)
v4.1:
 - Fix commit message(Lucas)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Licas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 84 ++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 82d899f170fb..e84ef3859934 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+	NOP(1),
+	LRI(13, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	NOP(4),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	END
+};
+
 static const u8 gen8_rcs_offsets[] = {
 	NOP(1),
 	LRI(14, POSTED),
@@ -606,6 +639,49 @@ static const u8 dg2_rcs_offsets[] = {
 	END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+	NOP(1),
+	LRI(15, POSTED),
+	REG16(0x244),
+	REG(0x034),
+	REG(0x030),
+	REG(0x038),
+	REG(0x03c),
+	REG(0x168),
+	REG(0x140),
+	REG(0x110),
+	REG(0x1c0),
+	REG(0x1c4),
+	REG(0x1c8),
+	REG(0x180),
+	REG16(0x2b4),
+	REG(0x120),
+	REG(0x124),
+
+	NOP(1),
+	LRI(9, POSTED),
+	REG16(0x3a8),
+	REG16(0x28c),
+	REG16(0x288),
+	REG16(0x284),
+	REG16(0x280),
+	REG16(0x27c),
+	REG16(0x278),
+	REG16(0x274),
+	REG16(0x270),
+
+	NOP(2),
+	LRI(2, POSTED),
+	REG16(0x5a8),
+	REG16(0x5ac),
+
+	NOP(6),
+	LRI(1, 0),
+	REG(0x0c8),
+
+	END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +700,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		   !intel_engine_has_relative_mmio(engine));
 
 	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_rcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_rcs_offsets;
 		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
 			return xehp_rcs_offsets;
@@ -637,7 +715,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 		else
 			return gen8_rcs_offsets;
 	} else {
-		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+			return mtl_xcs_offsets;
+		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 			return dg2_xcs_offsets;
 		else if (GRAPHICS_VER(engine->i915) >= 12)
 			return gen12_xcs_offsets;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread
end of thread, other threads:[~2022-10-03 15:33 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-02  6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
2022-09-02  6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
2022-09-02 16:49   ` kernel test robot
2022-09-02 22:10   ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-08 17:21     ` Matt Roper
2022-09-02  6:03 ` [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-09-07 20:49   ` [Intel-gfx] " Lucas De Marchi
2022-09-07 22:13     ` Matt Roper
2022-09-07 22:21       ` Lucas De Marchi
2022-09-07 22:38         ` Sripada, Radhakrishna
2022-09-07 23:32   ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-02  6:03 ` [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
2022-09-08 17:42   ` [Intel-gfx] " Matt Roper
2022-09-02  6:03 ` [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-09-06 12:16   ` Balasubramani Vivekanandan
2022-09-07 23:33   ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-08 18:00     ` [Intel-gfx] " Matt Roper
2022-09-02  6:03 ` [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
2022-09-08 13:05   ` [Intel-gfx] " Balasubramani Vivekanandan
2022-09-08 18:02   ` Matt Roper
2022-09-02  6:03 ` [PATCH v4 06/11] drm/i915/mtl: Add display power wells Radhakrishna Sripada
2022-09-08 18:07   ` Matt Roper
2022-09-08 18:11     ` Matt Roper
2022-09-02  6:03 ` [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
2022-09-08 18:13   ` Matt Roper
2022-09-02  6:03 ` [PATCH v4 08/11] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
2022-09-02  6:03 ` [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
2022-09-08 20:02   ` Matt Roper
2022-09-02  6:03 ` [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-09-08 20:30   ` Matt Roper
2022-09-02  6:03 ` [PATCH v4 11/11] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
2022-09-09 17:14   ` [Intel-gfx] " Balasubramani Vivekanandan
2022-09-16  1:46 [PATCH v6 3/3] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-09-26 21:43 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-28 15:55 Radhakrishna Sripada
2022-09-30  0:10 ` Lucas De Marchi
2022-10-03 15:33   ` Sripada, Radhakrishna

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