From: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com>
To: Michal Wajdeczko <michal.wajdeczko@intel.com>,
<intel-gfx@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 15/16] drm/i915/guc/slpc: slpc selftest
Date: Tue, 20 Jul 2021 18:06:49 -0700 [thread overview]
Message-ID: <35a43f9e-d110-889e-b0f3-aba89df573db@intel.com> (raw)
In-Reply-To: <6b181891-b36d-2cf0-6282-0941d2b872b1@intel.com>
On 7/10/2021 11:29 AM, Michal Wajdeczko wrote:
>
>
> On 10.07.2021 03:20, Vinay Belgaumkar wrote:
>> Tests that exercise the slpc get/set frequency interfaces.
>>
>> Clamp_max will set max frequency to multiple levels and check
>> that slpc requests frequency lower than or equal to it.
>>
>> Clamp_min will set min frequency to different levels and check
>> if slpc requests are higher or equal to those levels.
>
> 2x s/slpc/SLPC
Done.
>
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_rps.c | 1 +
>> drivers/gpu/drm/i915/gt/selftest_slpc.c | 333 ++++++++++++++++++
>> drivers/gpu/drm/i915/gt/selftest_slpc.h | 12 +
>> .../drm/i915/selftests/i915_live_selftests.h | 1 +
>> 4 files changed, 347 insertions(+)
>> create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.c
>> create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.h
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index 88ffc5d90730..16ac2e840881 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -2288,4 +2288,5 @@ EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
>>
>> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>> #include "selftest_rps.c"
>> +#include "selftest_slpc.c"
>> #endif
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c b/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> new file mode 100644
>> index 000000000000..f440c1cb2afa
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> @@ -0,0 +1,333 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2020 Intel Corporation
>
> 2021
Done.
>
>> + */
>> +#include "selftest_slpc.h"
>> +#include "selftest_rps.h"
>> +
>> +#include <linux/pm_qos.h>
>> +#include <linux/sort.h>
>
> system headers should go first
Cleaned up and removed the unwanted headers.
>
>> +
>> +#include "intel_engine_heartbeat.h"
>> +#include "intel_engine_pm.h"
>> +#include "intel_gpu_commands.h"
>> +#include "intel_gt_clock_utils.h"
>> +#include "intel_gt_pm.h"
>> +#include "intel_rc6.h"
>> +#include "selftest_engine_heartbeat.h"
>> +#include "intel_rps.h"
>> +#include "selftests/igt_flush_test.h"
>> +#include "selftests/igt_spinner.h"
>
> wrong order ?
Removed all includes, since these are already included in
selftest_rps.c. This gets included in intel_rps.c while compiling the
slpc selftest.
>
>> +
>> +#define NUM_STEPS 5
>> +#define H2G_DELAY 50000
>> +#define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 10000)
>> +
>> +static int set_min_freq(struct intel_guc_slpc *slpc, int freq)
>> +{
>> + int ret;
>
> add empty line
done.
>
>> + ret = intel_guc_slpc_set_min_freq(slpc, freq);
>> + if (ret) {
>> + pr_err("Could not set min frequency to [%d]\n", freq);
>> + return ret;
>> + } else {
>> + /* Delay to ensure h2g completes */
>> + delay_for_h2g();
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int set_max_freq(struct intel_guc_slpc *slpc, int freq)
>> +{
>> + int ret;
>
> add empty line
done.
>
>> + ret = intel_guc_slpc_set_max_freq(slpc, freq);
>> + if (ret) {
>> + pr_err("Could not set maximum frequency [%d]\n",
>> + freq);
>> + return ret;
>> + } else {
>> + /* Delay to ensure h2g completes */
>> + delay_for_h2g();
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +int live_slpc_clamp_min(void *arg)
>> +{
>> + struct drm_i915_private *i915 = arg;
>> + struct intel_gt *gt = &i915->gt;
>> + struct intel_guc_slpc *slpc;
>> + struct intel_rps *rps;
>> + struct intel_engine_cs *engine;
>> + enum intel_engine_id id;
>> + struct igt_spinner spin;
>> + int err = 0;
>
> usually "err" is last decl
ok.
>
>> + u32 slpc_min_freq, slpc_max_freq;
>> +
>> +
>
> too many empty lines
removed.
>
>> + slpc = >->uc.guc.slpc;
>> + rps = >->rps;
>
> could be initialized in decl above
ok.
>
>> +
>> + if (!intel_uc_uses_guc_slpc(>->uc))
>> + return 0;
>> +
>> + if (igt_spinner_init(&spin, gt))
>> + return -ENOMEM;
>> +
>> + if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
>> + pr_err("Could not get SLPC max freq");
>> + return -EIO;
>> + }
>> +
>> + if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
>> + pr_err("Could not get SLPC min freq");
>> + return -EIO;
>> + }
>> +
>> + if (slpc_min_freq == slpc_max_freq) {
>> + pr_err("Min/Max are fused to the same value");
>> + return -EINVAL;
>> + }
>
> 3x missing \n
done.
>
>> +
>> + intel_gt_pm_wait_for_idle(gt);
>> + intel_gt_pm_get(gt);
>> + for_each_engine(engine, gt, id) {
>> + struct i915_request *rq;
>> + u32 step, min_freq, req_freq;
>> + u32 act_freq, max_act_freq;
>> +
>> + if (!intel_engine_can_store_dword(engine))
>> + continue;
>> +
>> + /* Go from min to max in 5 steps */
>> + step = (slpc_max_freq - slpc_min_freq)/NUM_STEPS;
>
> add spaces ") / NUM"
ok.
>
>> + max_act_freq = slpc_min_freq;
>> + for (min_freq = slpc_min_freq; min_freq < slpc_max_freq; min_freq+=step)
>
> add spaces " += "
ok.
>
>> + {
>> + err = set_min_freq(slpc, min_freq);
>> + if (err)
>> + break;
>> +
>> + st_engine_heartbeat_disable(engine);
>> +
>> +
>
> keep only one empty line
ok.
>
>> + rq = igt_spinner_create_request(&spin,
>> + engine->kernel_context,
>> + MI_NOOP);
>> + if (IS_ERR(rq)) {
>> + err = PTR_ERR(rq);
>> + st_engine_heartbeat_enable(engine);
>> + break;
>> + }
>> +
>> + i915_request_add(rq);
>> +
>> + if (!igt_wait_for_spinner(&spin, rq)) {
>> + pr_err("%s: Spinner did not start\n",
>> + engine->name);
>> + igt_spinner_end(&spin);
>> + st_engine_heartbeat_enable(engine);
>> + intel_gt_set_wedged(engine->gt);
>> + err = -EIO;
>> + break;
>> + }
>> +
>> + /* Wait for GuC to detect business and raise
>> + * requested frequency if necessary */
>> + delay_for_h2g();
>> +
>> + req_freq = intel_rps_read_punit_req_frequency(rps);
>> +
>> + /* GuC requests freq in multiples of 50/3 MHz */
>> + if (req_freq < (min_freq - 50/3)) {
>> + pr_err("SWReq is %d, should be at least %d", req_freq,
>> + min_freq - 50/3);
>> + igt_spinner_end(&spin);
>> + st_engine_heartbeat_enable(engine);
>> + err = -EINVAL;
>> + break;
>> + }
>> +
>> + act_freq = intel_rps_read_actual_frequency(rps);
>> + if (act_freq > max_act_freq)
>> + max_act_freq = act_freq;
>> +
>> + igt_spinner_end(&spin);
>> + st_engine_heartbeat_enable(engine);
>> + }
>> +
>> + pr_info("Max actual frequency for %s was %d",
>> + engine->name, max_act_freq);
>> +
>> + /* Actual frequency should rise above min */
>> + if (max_act_freq == slpc_min_freq) {
>> + pr_err("Actual freq did not rise above min");
>> + err = -EINVAL;
>> + }
>
> 2x missing \n
>
> and few more below
added.
>
>> +
>> + if (err)
>> + break;
>> + }
>> +
>> + /* Restore min/max frequencies */
>> + set_max_freq(slpc, slpc_max_freq);
>> + set_min_freq(slpc, slpc_min_freq);
>> +
>> + if (igt_flush_test(gt->i915))
>> + err = -EIO;
>> +
>> + intel_gt_pm_put(gt);
>> + igt_spinner_fini(&spin);
>> + intel_gt_pm_wait_for_idle(gt);
>> +
>> + return err;
>> +}
>> +
>> +int live_slpc_clamp_max(void *arg)
>> +{
>> + struct drm_i915_private *i915 = arg;
>> + struct intel_gt *gt = &i915->gt;
>> + struct intel_guc_slpc *slpc;
>> + struct intel_rps *rps;
>> + struct intel_engine_cs *engine;
>> + enum intel_engine_id id;
>> + struct igt_spinner spin;
>> + int err = 0;
>> + u32 slpc_min_freq, slpc_max_freq;
>> +
>> + slpc = >->uc.guc.slpc;
>> + rps = >->rps;
>> +
>> + if (!intel_uc_uses_guc_slpc(>->uc))
>> + return 0;
>> +
>> + if (igt_spinner_init(&spin, gt))
>> + return -ENOMEM;
>> +
>> + if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
>> + pr_err("Could not get SLPC max freq");
>> + return -EIO;
>> + }
>> +
>> + if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
>> + pr_err("Could not get SLPC min freq");
>> + return -EIO;
>> + }
>> +
>> + if (slpc_min_freq == slpc_max_freq) {
>> + pr_err("Min/Max are fused to the same value");
>> + return -EINVAL;
>> + }
>> +
>> + intel_gt_pm_wait_for_idle(gt);
>> + intel_gt_pm_get(gt);
>> + for_each_engine(engine, gt, id) {
>> + struct i915_request *rq;
>> + u32 max_freq, req_freq;
>> + u32 act_freq, max_act_freq;
>> + u32 step;
>> +
>> + if (!intel_engine_can_store_dword(engine))
>> + continue;
>> +
>> + /* Go from max to min in 5 steps */
>> + step = (slpc_max_freq - slpc_min_freq)/NUM_STEPS;
>> + max_act_freq = slpc_min_freq;
>> + for (max_freq = slpc_max_freq; max_freq > slpc_min_freq; max_freq-=step)
>> + {
>> + err = set_max_freq(slpc, max_freq);
>> + if (err)
>> + break;
>> +
>> + st_engine_heartbeat_disable(engine);
>> +
>> + rq = igt_spinner_create_request(&spin,
>> + engine->kernel_context,
>> + MI_NOOP);
>> + if (IS_ERR(rq)) {
>> + st_engine_heartbeat_enable(engine);
>> + err = PTR_ERR(rq);
>> + break;
>> + }
>> +
>> + i915_request_add(rq);
>> +
>> + if (!igt_wait_for_spinner(&spin, rq)) {
>> + pr_err("%s: SLPC spinner did not start\n",
>> + engine->name);
>> + igt_spinner_end(&spin);
>> + st_engine_heartbeat_enable(engine);
>> + intel_gt_set_wedged(engine->gt);
>> + err = -EIO;
>> + break;
>> + }
>> +
>> + delay_for_h2g();
>> +
>> + /* Verify that SWREQ indeed was set to specific value */
>> + req_freq = intel_rps_read_punit_req_frequency(rps);
>> +
>> + /* GuC requests freq in multiples of 50/3 MHz */
>> + if (req_freq > (max_freq + 50/3)) {
>> + pr_err("SWReq is %d, should be at most %d", req_freq,
>> + max_freq + 50/3);
>> + igt_spinner_end(&spin);
>> + st_engine_heartbeat_enable(engine);
>> + err = -EINVAL;
>> + break;
>> + }
>> +
>> + act_freq = intel_rps_read_actual_frequency(rps);
>> + if (act_freq > max_act_freq)
>> + max_act_freq = act_freq;
>> +
>> + st_engine_heartbeat_enable(engine);
>> + igt_spinner_end(&spin);
>> +
>> + if (err)
>> + break;
>> + }
>> +
>> + pr_info("Max actual frequency for %s was %d",
>> + engine->name, max_act_freq);
>> +
>> + /* Actual frequency should rise above min */
>> + if (max_act_freq == slpc_min_freq) {
>> + pr_err("Actual freq did not rise above min");
>> + err = -EINVAL;
>> + }
>> +
>> + if (igt_flush_test(gt->i915)) {
>> + err = -EIO;
>> + break;
>> + }
>> +
>> + if (err)
>> + break;
>> + }
>> +
>> + /* Restore min/max freq */
>> + set_max_freq(slpc, slpc_max_freq);
>> + set_min_freq(slpc, slpc_min_freq);
>> +
>> + intel_gt_pm_put(gt);
>> + igt_spinner_fini(&spin);
>> + intel_gt_pm_wait_for_idle(gt);
>> +
>> + return err;
>> +}
>> +
>> +int intel_slpc_live_selftests(struct drm_i915_private *i915)
>> +{
>> + static const struct i915_subtest tests[] = {
>> + SUBTEST(live_slpc_clamp_max),
>> + SUBTEST(live_slpc_clamp_min),
>> + };
>> +
>> + if (intel_gt_is_wedged(&i915->gt))
>> + return 0;
>> +
>> + return i915_live_subtests(tests, i915);
>> +}
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.h b/drivers/gpu/drm/i915/gt/selftest_slpc.h
>> new file mode 100644
>> index 000000000000..8dfb40916a8c
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.h
>> @@ -0,0 +1,12 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2020 Intel Corporation
>
> 2021
done.
Thanks,
Vinay.
>
> Michal
>
>> + */
>> +
>> +#ifndef SELFTEST_SLPC_H
>> +#define SELFTEST_SLPC_H
>> +
>> +int live_slpc_clamp_max(void *arg);
>> +int live_slpc_clamp_min(void *arg);
>> +
>> +#endif /* SELFTEST_SLPC_H */
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
>> index e2fd1b61af71..1746a56dda06 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
>> +++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
>> @@ -47,5 +47,6 @@ selftest(hangcheck, intel_hangcheck_live_selftests)
>> selftest(execlists, intel_execlists_live_selftests)
>> selftest(ring_submission, intel_ring_submission_live_selftests)
>> selftest(perf, i915_perf_live_selftests)
>> +selftest(slpc, intel_slpc_live_selftests)
>> /* Here be dragons: keep last to run last! */
>> selftest(late_gt_pm, intel_gt_pm_late_selftests)
>>
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next prev parent reply other threads:[~2021-07-21 1:07 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-10 1:20 [Intel-gfx] [PATCH 00/16] Enable GuC based power management features Vinay Belgaumkar
2021-07-10 1:20 ` [Intel-gfx] [PATCH 01/16] drm/i915/guc: Squashed patch - DO NOT REVIEW Vinay Belgaumkar
2021-07-10 1:20 ` [Intel-gfx] [PATCH 02/16] drm/i915/guc/slpc: Initial definitions for slpc Vinay Belgaumkar
2021-07-10 14:27 ` Michal Wajdeczko
2021-07-12 18:40 ` Belgaumkar, Vinay
2021-07-12 23:43 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 03/16] drm/i915/guc/slpc: Gate Host RPS when slpc is enabled Vinay Belgaumkar
2021-07-10 1:20 ` [Intel-gfx] [PATCH 04/16] drm/i915/guc/slpc: Lay out slpc init/enable/disable/fini Vinay Belgaumkar
2021-07-10 14:35 ` Michal Wajdeczko
2021-07-13 0:37 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 05/16] drm/i915/guc/slpc: Adding slpc communication interfaces Vinay Belgaumkar
2021-07-10 15:52 ` Michal Wajdeczko
2021-07-13 23:22 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 06/16] drm/i915/guc/slpc: Allocate, initialize and release slpc Vinay Belgaumkar
2021-07-10 16:05 ` Michal Wajdeczko
2021-07-14 1:40 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 07/16] drm/i915/guc/slpc: Enable slpc and add related H2G events Vinay Belgaumkar
2021-07-10 17:37 ` Michal Wajdeczko
2021-07-15 1:58 ` Belgaumkar, Vinay
2021-07-21 17:36 ` Michal Wajdeczko
2021-07-10 1:20 ` [Intel-gfx] [PATCH 08/16] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar
2021-07-10 3:07 ` kernel test robot
2021-07-10 5:17 ` kernel test robot
2021-07-10 17:47 ` Michal Wajdeczko
2021-07-16 18:00 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 09/16] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar
2021-07-10 17:52 ` Michal Wajdeczko
2021-07-20 22:08 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 10/16] drm/i915/guc/slpc: Add debugfs for slpc info Vinay Belgaumkar
2021-07-10 18:08 ` Michal Wajdeczko
2021-07-20 23:00 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 11/16] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar
2021-07-10 1:20 ` [Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc Vinay Belgaumkar
2021-07-10 18:15 ` Michal Wajdeczko
2021-07-17 19:30 ` Belgaumkar, Vinay
2021-07-20 23:05 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 13/16] drm/i915/guc/slpc: Update slpc to use platform min/max Vinay Belgaumkar
2021-07-10 1:20 ` [Intel-gfx] [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc Vinay Belgaumkar
2021-07-10 6:18 ` kernel test robot
2021-07-10 7:30 ` kernel test robot
2021-07-10 7:30 ` [Intel-gfx] [RFC PATCH] drm/i915/guc/slpc: intel_rps_read_punit_req() can be static kernel test robot
2021-07-10 13:54 ` [Intel-gfx] [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc kernel test robot
2021-07-10 18:20 ` Michal Wajdeczko
2021-07-20 23:38 ` Belgaumkar, Vinay
2021-07-10 1:20 ` [Intel-gfx] [PATCH 15/16] drm/i915/guc/slpc: slpc selftest Vinay Belgaumkar
2021-07-10 18:29 ` Michal Wajdeczko
2021-07-21 1:06 ` Belgaumkar, Vinay [this message]
2021-07-10 1:20 ` [Intel-gfx] [PATCH 16/16] drm/i915/guc/rc: Setup and enable GUCRC feature Vinay Belgaumkar
2021-07-10 18:41 ` Michal Wajdeczko
2021-07-21 1:11 ` Belgaumkar, Vinay
2021-07-10 1:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC based power management features Patchwork
2021-07-10 1:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-10 2:09 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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