[PATCH 0/2] pinctl: armada-37xx: fix for pins 32+

[PATCH 0/2] pinctl: armada-37xx: fix for pins 32+

[alpawi]

From: Patrick Williams <alpawi@amazon.com>

The 37xx GPIO config registers are only 32 bits long and
span 2 registers for the NB GPIO controller.  The function
to calculate the offset was missing the increase to the
config register.

I have tested both raw gpio access and interrupts using
libgpiod utilities on an Espressonbin.

The first patch is a simple rename of a function because
the original name implied it was doing IO itself ("update
reg").  This patch could be dropped if undesired.

The second patch contains the fix for GPIOs 32+.

Patrick Williams (2):
  pinctrl: armada-37xx: rename reg-offset function
  pinctrl: armada-37xx: fix control of pins 32 and up

 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

-- 
2.17.2 (Apple Git-113)


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[PATCH 1/2] pinctrl: armada-37xx: rename reg-offset function

[alpawi]

From: Patrick Williams <alpawi@amazon.com>

The previously named function 'armada_37xx_update_reg'
implies that it updates the hardware register, but it
only calculates a register offset.  Rename to match
functionality.

Signed-off-by: Patrick Williams <alpawi@amazon.com>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 6462d3ca7ceb..00598b6f5c2a 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -220,8 +220,8 @@ static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
 	.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
 };
 
-static inline void armada_37xx_update_reg(unsigned int *reg,
-					  unsigned int offset)
+static inline void armada_37xx_calc_reg_offset(unsigned int *reg,
+					       unsigned int offset)
 {
 	/* We never have more than 2 registers */
 	if (offset >= GPIO_PER_REG) {
@@ -376,7 +376,7 @@ static inline void armada_37xx_irq_update_reg(unsigned int *reg,
 {
 	int offset = irqd_to_hwirq(d);
 
-	armada_37xx_update_reg(reg, offset);
+	armada_37xx_calc_reg_offset(reg, offset);
 }
 
 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
@@ -386,7 +386,7 @@ static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 
 	return regmap_update_bits(info->regmap, reg, mask, 0);
@@ -399,7 +399,7 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int val, mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 	regmap_read(info->regmap, reg, &val);
 
@@ -413,7 +413,7 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask, val, ret;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 
 	ret = regmap_update_bits(info->regmap, reg, mask, mask);
@@ -434,7 +434,7 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
 	unsigned int reg = INPUT_VAL;
 	unsigned int val, mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 
 	regmap_read(info->regmap, reg, &val);
@@ -449,7 +449,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
 	unsigned int reg = OUTPUT_VAL;
 	unsigned int mask, val;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 	val = value ? mask : 0;
 
-- 
2.17.2 (Apple Git-113)


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[PATCH 2/2] pinctrl: armada-37xx: fix control of pins 32 and up

[alpawi]

From: Patrick Williams <alpawi@amazon.com>

The 37xx configuration registers are only 32 bits long, so
pins 32-35 spill over into the next register.  The calculation
for the register address was done, but the bitmask was not, so
any configuration to pin 32 or above resulted in a bitmask that
overflowed and performed no action.

Fix the register / offset calculation to also adjust the offset.

Signed-off-by: Patrick Williams <alpawi@amazon.com>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 00598b6f5c2a..82c980c5cccd 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -221,11 +221,11 @@ static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
 };
 
 static inline void armada_37xx_calc_reg_offset(unsigned int *reg,
-					       unsigned int offset)
+					       unsigned int *offset)
 {
 	/* We never have more than 2 registers */
-	if (offset >= GPIO_PER_REG) {
-		offset -= GPIO_PER_REG;
+	if (*offset >= GPIO_PER_REG) {
+		*offset -= GPIO_PER_REG;
 		*reg += sizeof(u32);
 	}
 }
@@ -376,7 +376,7 @@ static inline void armada_37xx_irq_update_reg(unsigned int *reg,
 {
 	int offset = irqd_to_hwirq(d);
 
-	armada_37xx_calc_reg_offset(reg, offset);
+	armada_37xx_calc_reg_offset(reg, &offset);
 }
 
 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
@@ -386,7 +386,7 @@ static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 
 	return regmap_update_bits(info->regmap, reg, mask, 0);
@@ -399,7 +399,7 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int val, mask;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 	regmap_read(info->regmap, reg, &val);
 
@@ -413,7 +413,7 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask, val, ret;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 
 	ret = regmap_update_bits(info->regmap, reg, mask, mask);
@@ -434,7 +434,7 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
 	unsigned int reg = INPUT_VAL;
 	unsigned int val, mask;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 
 	regmap_read(info->regmap, reg, &val);
@@ -449,7 +449,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
 	unsigned int reg = OUTPUT_VAL;
 	unsigned int mask, val;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 	val = value ? mask : 0;
 
-- 
2.17.2 (Apple Git-113)


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Re: [PATCH 0/2] pinctl: armada-37xx: fix for pins 32+

[Linus Walleij]

On Tue, Jun 18, 2019 at 6:01 PM <alpawi@amazon.com> wrote:

> From: Patrick Williams <alpawi@amazon.com>
>
> The 37xx GPIO config registers are only 32 bits long and
> span 2 registers for the NB GPIO controller.  The function
> to calculate the offset was missing the increase to the
> config register.
>
> I have tested both raw gpio access and interrupts using
> libgpiod utilities on an Espressonbin.
>
> The first patch is a simple rename of a function because
> the original name implied it was doing IO itself ("update
> reg").  This patch could be dropped if undesired.
>
> The second patch contains the fix for GPIOs 32+.

This looks good overall. I am waiting for a maintainer review.
If nothing happens in a week, poke me and I'll just apply
the patches.

Yours,
Linus Walleij

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Re: [PATCH 0/2] pinctl: armada-37xx: fix for pins 32+

[Gregory CLEMENT]

Hi,

> On Tue, Jun 18, 2019 at 6:01 PM <alpawi@amazon.com> wrote:
>
>> From: Patrick Williams <alpawi@amazon.com>
>>
>> The 37xx GPIO config registers are only 32 bits long and
>> span 2 registers for the NB GPIO controller.  The function
>> to calculate the offset was missing the increase to the
>> config register.
>>
>> I have tested both raw gpio access and interrupts using
>> libgpiod utilities on an Espressonbin.
>>
>> The first patch is a simple rename of a function because
>> the original name implied it was doing IO itself ("update
>> reg").  This patch could be dropped if undesired.
>>
>> The second patch contains the fix for GPIOs 32+.

First you can add my
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>

Then as the second patch is a fix, you should add the fix tag: "Fixes:
5715092a458c ("pinctrl: armada-37xx: Add gpio support") " as well as the
'CC: <stable@vger.kernel.org>" tags.

But your change in the first patch made this second patch more difficult
to backport.

Actually, when I wrote "_update_reg" I was thinking to the update of the
variable, whereas with a function named "_calculate_reg" I am expecting
having the result as a return of the function.

However I am not against your change, as I pointed my main concern is
about the backport of the patch to the stable branch.

Maybe you could change the order of those 2 patches?

Thanks,

Gregory

>
> This looks good overall. I am waiting for a maintainer review.
> If nothing happens in a week, poke me and I'll just apply
> the patches.
>
> Yours,
> Linus Walleij
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com

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Re: [PATCH 0/2] pinctl: armada-37xx: fix for pins 32+

[Patrick Williams]

On Tue, Jun 25, 2019 at 03:38:59PM +0200, Gregory CLEMENT wrote:
> First you can add my
> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>

Thanks for the review Gregory.

> Then as the second patch is a fix, you should add the fix tag: "Fixes:
> 5715092a458c ("pinctrl: armada-37xx: Add gpio support") " as well as the
> 'CC: <stable@vger.kernel.org>" tags.
>
> But your change in the first patch made this second patch more difficult
> to backport.
> ...
> Maybe you could change the order of those 2 patches?

Good points.  Will do both.

> Actually, when I wrote "_update_reg" I was thinking to the update of the
> variable, whereas with a function named "_calculate_reg" I am expecting
> having the result as a return of the function.

Understand.  I can see the ambiguity in both names.  How about
"_update_reg_offset"?

> Thanks,
> 
> Gregory
> 
-- 
- Patrick

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[PATCH v2] pinctrl: armada-37xx: fix control of pins 32 and up

[Patrick Williams]

The 37xx configuration registers are only 32 bits long, so
pins 32-35 spill over into the next register.  The calculation
for the register address was done, but the bitmask was not, so
any configuration to pin 32 or above resulted in a bitmask that
overflowed and performed no action.

Fix the register / offset calculation to also adjust the offset.

Fixes: 5715092a458c ("pinctrl: armada-37xx: Add gpio support")
Signed-off-by: Patrick Williams <alpawi@amazon.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: <stable@vger.kernel.org>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 6462d3ca7ceb..34c1fee52cbe 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -221,11 +221,11 @@ static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
 };
 
 static inline void armada_37xx_update_reg(unsigned int *reg,
-					  unsigned int offset)
+					  unsigned int *offset)
 {
 	/* We never have more than 2 registers */
-	if (offset >= GPIO_PER_REG) {
-		offset -= GPIO_PER_REG;
+	if (*offset >= GPIO_PER_REG) {
+		*offset -= GPIO_PER_REG;
 		*reg += sizeof(u32);
 	}
 }
@@ -376,7 +376,7 @@ static inline void armada_37xx_irq_update_reg(unsigned int *reg,
 {
 	int offset = irqd_to_hwirq(d);
 
-	armada_37xx_update_reg(reg, offset);
+	armada_37xx_update_reg(reg, &offset);
 }
 
 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
@@ -386,7 +386,7 @@ static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 
 	return regmap_update_bits(info->regmap, reg, mask, 0);
@@ -399,7 +399,7 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int val, mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 	regmap_read(info->regmap, reg, &val);
 
@@ -413,7 +413,7 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask, val, ret;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 
 	ret = regmap_update_bits(info->regmap, reg, mask, mask);
@@ -434,7 +434,7 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
 	unsigned int reg = INPUT_VAL;
 	unsigned int val, mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 
 	regmap_read(info->regmap, reg, &val);
@@ -449,7 +449,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
 	unsigned int reg = OUTPUT_VAL;
 	unsigned int mask, val;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 	val = value ? mask : 0;
 
-- 
2.17.2 (Apple Git-113)


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Re: [PATCH v2] pinctrl: armada-37xx: fix control of pins 32 and up

[Linus Walleij]

On Tue, Oct 1, 2019 at 5:49 PM Patrick Williams <alpawi@amazon.com> wrote:

> The 37xx configuration registers are only 32 bits long, so
> pins 32-35 spill over into the next register.  The calculation
> for the register address was done, but the bitmask was not, so
> any configuration to pin 32 or above resulted in a bitmask that
> overflowed and performed no action.
>
> Fix the register / offset calculation to also adjust the offset.
>
> Fixes: 5715092a458c ("pinctrl: armada-37xx: Add gpio support")
> Signed-off-by: Patrick Williams <alpawi@amazon.com>
> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> Cc: <stable@vger.kernel.org>

Patch applied for fixes.

Yours,
Linus Walleij

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