linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Joey Gouly <joey.gouly@arm.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com,
	james.morse@arm.com, maz@kernel.org, will@kernel.org, nd@arm.com
Subject: Re: [PATCH v2 07/19] arm64: entry: convert IRQ+FIQ handlers to C
Date: Fri, 21 May 2021 14:19:15 +0100	[thread overview]
Message-ID: <20210521131915.GC35816@e124191.cambridge.arm.com> (raw)
In-Reply-To: <20210519123902.2452-8-mark.rutland@arm.com>

Hi Mark,

On Wed, May 19, 2021 at 01:38:50PM +0100, Mark Rutland wrote:
> For various reasons we'd like to convert the bulk of arm64's exception
> triage logic to C. As a step towards that, this patch converts the EL1
> and EL0 IRQ+FIQ triage logic to C.
> 
> Separate C functions are added for the native and compat cases so that
> in subsequent patches we can handle native/compat differences in C.
> 
> Since the triage functions can now call arm64_apply_bp_hardening()
> directly, the do_el0_irq_bp_hardening() wrapper function is removed.
> 
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Will Deacon <will@kernel.org>
> ---
>  arch/arm64/include/asm/exception.h |  8 ++-
>  arch/arm64/include/asm/processor.h |  2 -
>  arch/arm64/kernel/entry-common.c   | 86 +++++++++++++++++++++++++++++++--
>  arch/arm64/kernel/entry.S          | 99 ++++++--------------------------------
>  arch/arm64/mm/fault.c              |  7 ---
>  5 files changed, 102 insertions(+), 100 deletions(-)

[..]

> 
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index 327a559679f7..eebc6e72125c 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -486,63 +486,12 @@ SYM_CODE_START_LOCAL(__swpan_exit_el0)
>  SYM_CODE_END(__swpan_exit_el0)
>  #endif
>  
> -	.macro	irq_stack_entry
> -	mov	x19, sp			// preserve the original sp
> -#ifdef CONFIG_SHADOW_CALL_STACK
> -	mov	x24, scs_sp		// preserve the original shadow stack
> -#endif
> -
> -	/*
> -	 * Compare sp with the base of the task stack.
> -	 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
> -	 * and should switch to the irq stack.
> -	 */
> -	ldr	x25, [tsk, TSK_STACK]
> -	eor	x25, x25, x19
> -	and	x25, x25, #~(THREAD_SIZE - 1)
> -	cbnz	x25, 9998f
> -
> -	ldr_this_cpu x25, irq_stack_ptr, x26
> -	mov	x26, #IRQ_STACK_SIZE
> -	add	x26, x25, x26
> -
> -	/* switch to the irq stack */
> -	mov	sp, x26
> -
> -#ifdef CONFIG_SHADOW_CALL_STACK
> -	/* also switch to the irq shadow stack */
> -	ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x26
> -#endif
> -
> -9998:
> -	.endm
> -
> -	/*
> -	 * The callee-saved regs (x19-x29) should be preserved between
> -	 * irq_stack_entry and irq_stack_exit, but note that kernel_entry
> -	 * uses x20-x23 to store data for later use.
> -	 */
> -	.macro	irq_stack_exit
> -	mov	sp, x19
> -#ifdef CONFIG_SHADOW_CALL_STACK
> -	mov	scs_sp, x24
> -#endif
> -	.endm
> -
>  /* GPRs used by entry code */
>  tsk	.req	x28		// current thread_info
>  
>  /*
>   * Interrupt handling.
>   */
> -	.macro	irq_handler, handler:req
> -	ldr_l	x1, \handler
> -	mov	x0, sp
> -	irq_stack_entry
> -	blr	x1
> -	irq_stack_exit
> -	.endm
> -
>  	.macro	gic_prio_kentry_setup, tmp:req
>  #ifdef CONFIG_ARM64_PSEUDO_NMI
>  	alternative_if ARM64_HAS_IRQ_PRIO_MASKING
> @@ -552,32 +501,6 @@ tsk	.req	x28		// current thread_info
>  #endif
>  	.endm
>  
> -	.macro el1_interrupt_handler, handler:req
> -	enable_da
> -
> -	mov	x0, sp
> -	bl	enter_el1_irq_or_nmi
> -
> -	irq_handler	\handler
> -
> -#ifdef CONFIG_PREEMPTION
> -	bl	arm64_preempt_schedule_irq	// irq en/disable is done inside
> -#endif
> -
> -	mov	x0, sp
> -	bl	exit_el1_irq_or_nmi
> -	.endm
> -
> -	.macro el0_interrupt_handler, handler:req
> -	user_exit_irqoff

Nothing is using the user_exit_irqoff macro anymore, it could be
removed?

> -	enable_da
> -
> -	tbz	x22, #55, 1f
> -	bl	do_el0_irq_bp_hardening
> -1:
> -	irq_handler	\handler
> -	.endm
> -

[..]

Reviewed-by: Joey Gouly <joey.gouly@arm.com>

Thanks,
Joey

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-05-21 13:21 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-19 12:38 [PATCH v2 00/19] arm64: entry: migrate more code " Mark Rutland
2021-05-19 12:38 ` [PATCH v2 01/19] arm64: remove redundant local_daif_mask() in bad_mode() Mark Rutland
2021-05-21 10:39   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 02/19] arm64: entry: unmask IRQ+FIQ after EL0 handling Mark Rutland
2021-05-25 16:45   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 03/19] arm64: entry: convert SError handlers to C Mark Rutland
2021-05-25 13:38   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 04/19] arm64: entry: move arm64_preempt_schedule_irq to entry-common.c Mark Rutland
2021-05-21 11:00   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 05/19] arm64: entry: move preempt logic to C Mark Rutland
2021-05-25 12:50   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 06/19] arm64: entry: add a call_on_irq_stack helper Mark Rutland
2021-05-19 14:46   ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 07/19] arm64: entry: convert IRQ+FIQ handlers to C Mark Rutland
2021-05-21 13:19   ` Joey Gouly [this message]
2021-05-21 15:23     ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 08/19] arm64: entry: organise entry handlers consistently Mark Rutland
2021-05-21 16:04   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 09/19] arm64: entry: organise entry vectors consistently Mark Rutland
2021-05-21 16:07   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 10/19] arm64: entry: consolidate EL1 exception returns Mark Rutland
2021-05-21 16:22   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 11/19] arm64: entry: move bad_mode() to entry-common.c Mark Rutland
2021-05-21 16:46   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 12/19] arm64: entry: improve bad_mode() Mark Rutland
2021-05-21 17:02   ` Joey Gouly
2021-05-21 17:10     ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 13/19] arm64: entry: template the entry asm functions Mark Rutland
2021-05-21 17:16   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 14/19] arm64: entry: handle all vectors with C Mark Rutland
2021-05-21 15:59   ` Joey Gouly
2021-05-21 16:41     ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 15/19] arm64: entry: split bad stack entry Mark Rutland
2021-05-25 11:25   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 16/19] arm64: entry: split SDEI entry Mark Rutland
2021-05-25 11:49   ` Joey Gouly
2021-05-19 12:39 ` [PATCH v2 17/19] arm64: entry: make NMI entry/exit functions static Mark Rutland
2021-05-21 17:21   ` Joey Gouly
2021-05-19 12:39 ` [PATCH v2 18/19] arm64: entry: don't instrument entry code with KCOV Mark Rutland
2021-05-19 12:39 ` [PATCH v2 19/19] arm64: idle: don't instrument idle " Mark Rutland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210521131915.GC35816@e124191.cambridge.arm.com \
    --to=joey.gouly@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=james.morse@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=mark.rutland@arm.com \
    --cc=maz@kernel.org \
    --cc=nd@arm.com \
    --cc=will@kernel.org \
    --subject='Re: [PATCH v2 07/19] arm64: entry: convert IRQ+FIQ handlers to C' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).