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From: Mark Rutland <mark.rutland@arm.com>
To: Joey Gouly <joey.gouly@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com,
	james.morse@arm.com, maz@kernel.org, will@kernel.org, nd@arm.com
Subject: Re: [PATCH v2 14/19] arm64: entry: handle all vectors with C
Date: Fri, 21 May 2021 17:41:05 +0100	[thread overview]
Message-ID: <20210521164105.GC9239@C02TD0UTHF1T.local> (raw)
In-Reply-To: <20210521155952.GD35816@e124191.cambridge.arm.com>

On Fri, May 21, 2021 at 04:59:52PM +0100, Joey Gouly wrote:
> Hi Mark,
> 
> I like these clean ups to entry.S!
> 
> On Wed, May 19, 2021 at 01:38:57PM +0100, Mark Rutland wrote:
> > We have 16 architectural exception vectors, and depending on kernel
> > configuration we handle 8 or 12 of these with C code, and we handle 8 or
> > 4 of these as sepcial cases in the entry assembly.
> > 
> > It would be nicer if the entry assembly were uniform for all exceptions,
> > and we deferred any specific handling of the exceptions to C code. This
> > way the entry assembly can be more easily templated without ifdeffery or
> > special cases, and it's easier to modify the handling of these cases in
> > future (e.g. to dump additional registers other context).
> > 
> > This patch reworks the entry code so that we always have a C handle for
> s/handle/handler/
> > every architectural exception vector, with the entry assembly being
> > completely uniform. We now have to handle exceptions from EL1t and EL1h,
> > and also have to handle exceptions from AArch32 even when the kernel is
> > built without CONFIG_COMPAT. To make this clear and to simplify
> > templating, we rename the top-level exception handlers with a consistent
> > naming scheme:
> > 
> >   asm: <el>_<regsize>_<type>
> >   c:   <el>_<regsize>_<type>_handler
> > 
> > .. where:
> > 
> >   <el> is `el1t`, `el1h`, or `el0`
> 
> Is there a reason against using `el0t`? `el0t` is used in the Arm ARM.
> It would get rid of the weird empty arguments in the `kernel_ventry`
> and `entry_handler` macros.

To be honest, I simply hadn't thought about it, as I'd only needed to
distingish EL1h and EL1t. Now that you say it, it does make sense to me
do use `el0t` for consistency, so I'll take a look at that.

> 
> >   <regsize> is `64` or `32`
> >   <type> is `sync`, `irq`, `fiq`, or `error`
> > 
> > ... e.g.
> > 
> >   asm: el1h_64_sync
> >   c:   el1h_64_sync_handler
> > 
> > ... with lower-level handlers simply using "el1" and "compat" as today.
> > 
> > For unexpected exceptions, this information is passed to
> > panic_unandled(), so it can report the specific vector an unexpected
> > exception was taken from, e.g.
> > 
> > | Unexpected 64-bit el1t sync exception
> > 
> > For vectors we never expect to enter legitimately, the C code is
> > gnerated using a macro to avoid code duplication.
> > 
> > The `kernel_ventry` and `entry_handler` assembly macros are update to
> s/update/updated/
> > handle the new naming scheme. In theory it should be possible to
> > generate the entry functions at the same time as the vectors using a
> > single table, but this will require reworking the linker script to split
> > the two into separate sections, so for now we duplicate the two.
> > 
> > Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: James Morse <james.morse@arm.com>
> > Cc: Marc Zyngier <maz@kernel.org>
> > Cc: Will Deacon <will@kernel.org>
> > ---
> >  arch/arm64/include/asm/exception.h |  31 +++++---
> >  arch/arm64/kernel/entry-common.c   |  51 +++++++------
> >  arch/arm64/kernel/entry.S          | 146 ++++++++++++-------------------------
> >  3 files changed, 92 insertions(+), 136 deletions(-)
> > 
> > diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h
> > index 4284ee57a9a5..40a3a20dca1c 100644
> > --- a/arch/arm64/include/asm/exception.h
> > +++ b/arch/arm64/include/asm/exception.h
> > @@ -31,18 +31,25 @@ static inline u32 disr_to_esr(u64 disr)
> >  	return esr;
> >  }
> >  
> > -asmlinkage void el1_sync_handler(struct pt_regs *regs);
> > -asmlinkage void el1_irq_handler(struct pt_regs *regs);
> > -asmlinkage void el1_fiq_handler(struct pt_regs *regs);
> > -asmlinkage void el1_error_handler(struct pt_regs *regs);
> > -asmlinkage void el0_sync_handler(struct pt_regs *regs);
> > -asmlinkage void el0_irq_handler(struct pt_regs *regs);
> > -asmlinkage void el0_fiq_handler(struct pt_regs *regs);
> > -asmlinkage void el0_error_handler(struct pt_regs *regs);
> > -asmlinkage void el0_sync_compat_handler(struct pt_regs *regs);
> > -asmlinkage void el0_irq_compat_handler(struct pt_regs *regs);
> > -asmlinkage void el0_fiq_compat_handler(struct pt_regs *regs);
> > -asmlinkage void el0_error_compat_handler(struct pt_regs *regs);
> > +asmlinkage void el1t_64_sync_handler(struct pt_regs *regs);
> > +asmlinkage void el1t_64_irq_handler(struct pt_regs *regs);
> > +asmlinkage void el1t_64_fiq_handler(struct pt_regs *regs);
> > +asmlinkage void el1t_64_error_handler(struct pt_regs *regs);
> > +
> > +asmlinkage void el1h_64_sync_handler(struct pt_regs *regs);
> > +asmlinkage void el1h_64_irq_handler(struct pt_regs *regs);
> > +asmlinkage void el1h_64_fiq_handler(struct pt_regs *regs);
> > +asmlinkage void el1h_64_error_handler(struct pt_regs *regs);
> > +
> > +asmlinkage void el0_64_sync_handler(struct pt_regs *regs);
> > +asmlinkage void el0_64_irq_handler(struct pt_regs *regs);
> > +asmlinkage void el0_64_fiq_handler(struct pt_regs *regs);
> > +asmlinkage void el0_64_error_handler(struct pt_regs *regs);
> > +
> > +asmlinkage void el0_32_sync_handler(struct pt_regs *regs);
> > +asmlinkage void el0_32_irq_handler(struct pt_regs *regs);
> > +asmlinkage void el0_32_fiq_handler(struct pt_regs *regs);
> > +asmlinkage void el0_32_error_handler(struct pt_regs *regs);
> >  
> >  asmlinkage void call_on_irq_stack(struct pt_regs *regs,
> >  				  void (*func)(struct pt_regs *));
> 
> Can you remove `bad_mode` from this header? (Further down, not shown here)
> 
> Also there is a reference to `bad_mode` in `traps.c`.

Sure; I'll rip both of those out.

> >  static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
> >  {
> >  	unsigned long far = read_sysreg(far_el1);
> > @@ -271,7 +271,7 @@ static void noinstr el1_inv(struct pt_regs *regs, unsigned long esr)
> >  {
> >  	enter_from_kernel_mode(regs);
> >  	local_daif_inherit(regs);
> > -	bad_mode(regs, 0, esr);
> > +	__panic_unhandled(regs, "el1h sync", esr);
> >  	local_daif_mask();
> >  	exit_to_kernel_mode(regs);
> 
> This is never going to actually exit to kernel mode, is it? The panic
> should stop that.

Correct.

Now that __panic_unhandled() does NMI entry work, we can remove
el1_inv() and have el1h_64_sync_handler() call __panic_unhandled()
directly.

I'll do that as a followup patch, since it's a slight (but deliberate)
behavioural change.

> Minor comments / questions, but otherwise:
> 
> Reviewed-by: Joey Gouly <joey.gouly@arm.com>

Thanks!

Mark.

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  reply	other threads:[~2021-05-21 16:43 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-19 12:38 [PATCH v2 00/19] arm64: entry: migrate more code to C Mark Rutland
2021-05-19 12:38 ` [PATCH v2 01/19] arm64: remove redundant local_daif_mask() in bad_mode() Mark Rutland
2021-05-21 10:39   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 02/19] arm64: entry: unmask IRQ+FIQ after EL0 handling Mark Rutland
2021-05-25 16:45   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 03/19] arm64: entry: convert SError handlers to C Mark Rutland
2021-05-25 13:38   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 04/19] arm64: entry: move arm64_preempt_schedule_irq to entry-common.c Mark Rutland
2021-05-21 11:00   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 05/19] arm64: entry: move preempt logic to C Mark Rutland
2021-05-25 12:50   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 06/19] arm64: entry: add a call_on_irq_stack helper Mark Rutland
2021-05-19 14:46   ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 07/19] arm64: entry: convert IRQ+FIQ handlers to C Mark Rutland
2021-05-21 13:19   ` Joey Gouly
2021-05-21 15:23     ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 08/19] arm64: entry: organise entry handlers consistently Mark Rutland
2021-05-21 16:04   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 09/19] arm64: entry: organise entry vectors consistently Mark Rutland
2021-05-21 16:07   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 10/19] arm64: entry: consolidate EL1 exception returns Mark Rutland
2021-05-21 16:22   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 11/19] arm64: entry: move bad_mode() to entry-common.c Mark Rutland
2021-05-21 16:46   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 12/19] arm64: entry: improve bad_mode() Mark Rutland
2021-05-21 17:02   ` Joey Gouly
2021-05-21 17:10     ` Mark Rutland
2021-05-19 12:38 ` [PATCH v2 13/19] arm64: entry: template the entry asm functions Mark Rutland
2021-05-21 17:16   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 14/19] arm64: entry: handle all vectors with C Mark Rutland
2021-05-21 15:59   ` Joey Gouly
2021-05-21 16:41     ` Mark Rutland [this message]
2021-05-19 12:38 ` [PATCH v2 15/19] arm64: entry: split bad stack entry Mark Rutland
2021-05-25 11:25   ` Joey Gouly
2021-05-19 12:38 ` [PATCH v2 16/19] arm64: entry: split SDEI entry Mark Rutland
2021-05-25 11:49   ` Joey Gouly
2021-05-19 12:39 ` [PATCH v2 17/19] arm64: entry: make NMI entry/exit functions static Mark Rutland
2021-05-21 17:21   ` Joey Gouly
2021-05-19 12:39 ` [PATCH v2 18/19] arm64: entry: don't instrument entry code with KCOV Mark Rutland
2021-05-19 12:39 ` [PATCH v2 19/19] arm64: idle: don't instrument idle " Mark Rutland

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