* [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
@ 2019-04-17 11:24 Paul Cercueil
2019-04-17 23:48 ` Stephen Boyd
2019-04-18 21:58 ` Stephen Boyd
0 siblings, 2 replies; 7+ messages in thread
From: Paul Cercueil @ 2019-04-17 11:24 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-kernel, Paul Cercueil, stable
The pixel clock is directly connected to the output of the PLL, and not
to the /2 divider.
Cc: stable@vger.kernel.org
Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/clk/ingenic/jz4725b-cgu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 8901ea0295b7..76793b3d2ef8 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -102,7 +102,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
[JZ4725B_CLK_LCD] = {
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
- .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
+ .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 9 },
},
--
2.21.0.593.g511ec345e18
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
2019-04-17 11:24 [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock Paul Cercueil
@ 2019-04-17 23:48 ` Stephen Boyd
2019-04-17 23:53 ` Paul Cercueil
2019-04-18 21:58 ` Stephen Boyd
1 sibling, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2019-04-17 23:48 UTC (permalink / raw)
To: Michael Turquette, Paul Cercueil
Cc: linux-clk, linux-kernel, Paul Cercueil, stable
Quoting Paul Cercueil (2019-04-17 04:24:20)
> The pixel clock is directly connected to the output of the PLL, and not
> to the /2 divider.
>
> Cc: stable@vger.kernel.org
> Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
Is this breaking something in 5.1-rc series? Or just found by
inspection? I'm trying to understand the priority of this patch.
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
2019-04-17 23:48 ` Stephen Boyd
@ 2019-04-17 23:53 ` Paul Cercueil
2019-04-18 20:32 ` Stephen Boyd
0 siblings, 1 reply; 7+ messages in thread
From: Paul Cercueil @ 2019-04-17 23:53 UTC (permalink / raw)
To: Stephen Boyd; +Cc: Michael Turquette, linux-clk, linux-kernel, stable
Hi Stephen,
Le jeu. 18 avril 2019 à 1:48, Stephen Boyd <sboyd@kernel.org> a écrit
:
> Quoting Paul Cercueil (2019-04-17 04:24:20)
>> The pixel clock is directly connected to the output of the PLL, and
>> not
>> to the /2 divider.
>>
>> Cc: stable@vger.kernel.org
>> Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
>> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
>> ---
>
> Is this breaking something in 5.1-rc series? Or just found by
> inspection? I'm trying to understand the priority of this patch.
I verified it with the hardware. It fixes a bug that has been present
since the introduction of this driver.
However until now nothing uses this particular clock so it can go to
5.2.
-Paul
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
2019-04-17 23:53 ` Paul Cercueil
@ 2019-04-18 20:32 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2019-04-18 20:32 UTC (permalink / raw)
To: Paul Cercueil; +Cc: Michael Turquette, linux-clk, linux-kernel, stable
Quoting Paul Cercueil (2019-04-17 16:53:53)
> Hi Stephen,
>
> Le jeu. 18 avril 2019 à 1:48, Stephen Boyd <sboyd@kernel.org> a écrit
> :
> > Quoting Paul Cercueil (2019-04-17 04:24:20)
> >> The pixel clock is directly connected to the output of the PLL, and
> >> not
> >> to the /2 divider.
> >>
> >> Cc: stable@vger.kernel.org
> >> Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> >> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> >> ---
> >
> > Is this breaking something in 5.1-rc series? Or just found by
> > inspection? I'm trying to understand the priority of this patch.
>
> I verified it with the hardware. It fixes a bug that has been present
> since the introduction of this driver.
>
> However until now nothing uses this particular clock so it can go to
> 5.2.
>
Great. Thanks for the background!
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
2019-04-17 11:24 [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock Paul Cercueil
2019-04-17 23:48 ` Stephen Boyd
@ 2019-04-18 21:58 ` Stephen Boyd
2019-04-29 20:53 ` Paul Cercueil
1 sibling, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2019-04-18 21:58 UTC (permalink / raw)
To: Michael Turquette, Paul Cercueil
Cc: linux-clk, linux-kernel, Paul Cercueil, stable
Quoting Paul Cercueil (2019-04-17 04:24:20)
> The pixel clock is directly connected to the output of the PLL, and not
> to the /2 divider.
>
> Cc: stable@vger.kernel.org
> Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
2019-04-18 21:58 ` Stephen Boyd
@ 2019-04-29 20:53 ` Paul Cercueil
2019-04-29 22:59 ` Stephen Boyd
0 siblings, 1 reply; 7+ messages in thread
From: Paul Cercueil @ 2019-04-29 20:53 UTC (permalink / raw)
To: Stephen Boyd; +Cc: Michael Turquette, linux-clk, linux-kernel, stable
Hi Stephen,
Le jeu. 18 avril 2019 à 23:58, Stephen Boyd <sboyd@kernel.org> a
écrit :
> Quoting Paul Cercueil (2019-04-17 04:24:20)
>> The pixel clock is directly connected to the output of the PLL, and
>> not
>> to the /2 divider.
>>
>> Cc: stable@vger.kernel.org
>> Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
>> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
>> ---
>
> Applied to clk-next
Could you drop this patch?
It turns out it is wrong and the pixel clock is really connected to the
"pll half"
clock. The real bug was elsewhere: the "pll half" clock does not report
the correct
rate. I will send a patch for this one later.
Thanks,
-Paul
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
2019-04-29 20:53 ` Paul Cercueil
@ 2019-04-29 22:59 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2019-04-29 22:59 UTC (permalink / raw)
To: Paul Cercueil; +Cc: Michael Turquette, linux-clk, linux-kernel, stable
Quoting Paul Cercueil (2019-04-29 13:53:11)
> Hi Stephen,
>
> Le jeu. 18 avril 2019 à 23:58, Stephen Boyd <sboyd@kernel.org> a
> écrit :
> > Quoting Paul Cercueil (2019-04-17 04:24:20)
> >> The pixel clock is directly connected to the output of the PLL, and
> >> not
> >> to the /2 divider.
> >>
> >> Cc: stable@vger.kernel.org
> >> Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> >> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> >> ---
> >
> > Applied to clk-next
>
> Could you drop this patch?
>
> It turns out it is wrong and the pixel clock is really connected to the
> "pll half"
> clock. The real bug was elsewhere: the "pll half" clock does not report
> the correct
> rate. I will send a patch for this one later.
>
Ok. No problem.
^ permalink raw reply [flat|nested] 7+ messages in thread
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2019-04-17 11:24 [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock Paul Cercueil
2019-04-17 23:48 ` Stephen Boyd
2019-04-17 23:53 ` Paul Cercueil
2019-04-18 20:32 ` Stephen Boyd
2019-04-18 21:58 ` Stephen Boyd
2019-04-29 20:53 ` Paul Cercueil
2019-04-29 22:59 ` Stephen Boyd
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