From: Thierry Reding <thierry.reding@gmail.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Jon Hunter <jonathanh@nvidia.com>,
Vidya Sagar <vidyas@nvidia.com>,
linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: [PATCH 2/9] gpio: tegra186: Add support for pin ranges
Date: Thu, 19 Mar 2020 13:27:30 +0100 [thread overview]
Message-ID: <20200319122737.3063291-3-thierry.reding@gmail.com> (raw)
In-Reply-To: <20200319122737.3063291-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Add support for Tegra SoC generations to specify a list of pin ranges
that map GPIOs to ranges of pins in the pin controller.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/gpio/gpio-tegra186.c | 56 ++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index de241263d4be..1086c1fcaf49 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -58,11 +58,20 @@ struct tegra_gpio_port {
unsigned int pins;
};
+struct tegra186_pin_range {
+ unsigned int offset;
+ const char *group;
+};
+
struct tegra_gpio_soc {
const struct tegra_gpio_port *ports;
unsigned int num_ports;
const char *name;
unsigned int instance;
+
+ const struct tegra186_pin_range *pin_ranges;
+ unsigned int num_pin_ranges;
+ const char *pinmux;
};
struct tegra_gpio {
@@ -254,6 +263,50 @@ static int tegra186_gpio_set_config(struct gpio_chip *chip,
return 0;
}
+static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
+{
+ struct tegra_gpio *gpio = gpiochip_get_data(chip);
+ struct pinctrl_dev *pctldev;
+ struct device_node *np;
+ unsigned int i, j;
+ int err;
+
+ if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
+ return 0;
+
+ np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
+ if (!np)
+ return -ENODEV;
+
+ pctldev = of_pinctrl_get(np);
+ of_node_put(np);
+ if (!pctldev)
+ return -EPROBE_DEFER;
+
+ for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
+ unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
+ const char *group = gpio->soc->pin_ranges[i].group;
+
+ port = pin / 8;
+ pin = pin % 8;
+
+ if (port >= gpio->soc->num_ports) {
+ dev_warn(chip->parent, "invalid port %u for %s\n",
+ port, group);
+ continue;
+ }
+
+ for (j = 0; j < port; j++)
+ pin += gpio->soc->ports[j].pins;
+
+ err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
const struct of_phandle_args *spec,
u32 *flags)
@@ -578,12 +631,15 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
gpio->gpio.label = gpio->soc->name;
gpio->gpio.parent = &pdev->dev;
+ gpio->gpio.request = gpiochip_generic_request;
+ gpio->gpio.free = gpiochip_generic_free;
gpio->gpio.get_direction = tegra186_gpio_get_direction;
gpio->gpio.direction_input = tegra186_gpio_direction_input;
gpio->gpio.direction_output = tegra186_gpio_direction_output;
gpio->gpio.get = tegra186_gpio_get,
gpio->gpio.set = tegra186_gpio_set;
gpio->gpio.set_config = tegra186_gpio_set_config;
+ gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
gpio->gpio.base = -1;
--
2.24.1
next prev parent reply other threads:[~2020-03-19 12:27 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-19 12:27 [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming Thierry Reding
2020-03-19 12:27 ` [PATCH 1/9] gpio: Support GPIO controllers without pin-ranges Thierry Reding
2020-03-19 17:05 ` Vidya Sagar
2020-03-27 10:37 ` Linus Walleij
2020-03-27 12:13 ` Thierry Reding
2020-03-19 12:27 ` Thierry Reding [this message]
2020-03-19 17:05 ` [PATCH 2/9] gpio: tegra186: Add support for pin ranges Vidya Sagar
2020-03-27 10:39 ` Linus Walleij
2020-03-31 20:53 ` Thierry Reding
2020-03-19 12:27 ` [PATCH 3/9] gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1 Thierry Reding
2020-03-19 17:06 ` Vidya Sagar
2020-03-27 10:39 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 4/9] pinctrl: tegra: Fix whitespace issues for improved readability Thierry Reding
2020-03-19 17:06 ` Vidya Sagar
2020-03-27 10:40 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 5/9] pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo Thierry Reding
2020-03-19 17:07 ` Vidya Sagar
2020-03-27 10:42 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 6/9] pinctrl: tegra: Pass struct tegra_pmx for pin range check Thierry Reding
2020-03-19 17:07 ` Vidya Sagar
2020-03-27 10:43 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 7/9] pinctrl: tegra: Do not add default pin range on Tegra194 Thierry Reding
2020-03-19 17:08 ` Vidya Sagar
2020-03-27 10:44 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins Thierry Reding
2020-03-19 17:08 ` Vidya Sagar
2020-03-27 10:45 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 9/9] pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 Thierry Reding
2020-03-19 17:08 ` Vidya Sagar
2020-03-27 10:46 ` Linus Walleij
2020-03-19 17:04 ` [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming Vidya Sagar
2020-03-20 19:37 ` Linus Walleij
2020-03-23 13:16 ` Thierry Reding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200319122737.3063291-3-thierry.reding@gmail.com \
--to=thierry.reding@gmail.com \
--cc=bgolaszewski@baylibre.com \
--cc=jonathanh@nvidia.com \
--cc=linus.walleij@linaro.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).