linux-gpio.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Vidya Sagar <vidyas@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Jon Hunter <jonathanh@nvidia.com>, <linux-gpio@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>
Subject: Re: [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming
Date: Thu, 19 Mar 2020 22:34:49 +0530	[thread overview]
Message-ID: <99368d3c-0a98-eb80-06a9-4deef402ce87@nvidia.com> (raw)
In-Reply-To: <20200319122737.3063291-1-thierry.reding@gmail.com>



On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
> 
> 
> From: Thierry Reding <treding@nvidia.com>
> 
> Hi,
> 
> NVIDIA Tegra186 and later have a bit in the pin controller that defines
> whether a pin is used in special function (SFIO) mode or in general
> purpose (GPIO) mode. On early Tegra SoC generations, this bit was part
> of the GPIO controller.
> 
> The pin configuration on Tegra186 and later (and partially on Tegra210)
> is typically static, so there is little need to reconfigure these pins.
> However, there's a special case on Tegra194 where the PCIe CLKREQ and
> RST pins for controller 5 may need to be reprogrammed in the kernel,
> depending on whether the controller runs in endpoint mode or in root
> port mode.
> 
> This series of patches establishes the mapping of these two pins to
> their GPIO equivalents and implements the code necessary to switch
> between SFIO and GPIO modes when the kernel requests or releases the
> GPIOs, respectively.
> 
> Thierry
> 
> Thierry Reding (9):
>    gpio: Support GPIO controllers without pin-ranges
>    gpio: tegra186: Add support for pin ranges
>    gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1
>    pinctrl: tegra: Fix whitespace issues for improved readability
>    pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
>    pinctrl: tegra: Pass struct tegra_pmx for pin range check
>    pinctrl: tegra: Do not add default pin range on Tegra194
>    pinctrl: tegra: Renumber the GG.0 and GG.1 pins
>    pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
> 
>   drivers/gpio/gpio-tegra186.c             | 64 ++++++++++++++++++++++++
>   drivers/gpio/gpiolib.c                   |  5 +-
>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 52 +++++++++++++++++--
>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +-
>   drivers/pinctrl/tegra/pinctrl-tegra194.c | 47 +++++++++--------
>   5 files changed, 144 insertions(+), 29 deletions(-)
> 
> --
> 2.24.1
> 
Tested-by: Vidya Sagar <vidyas@nvidia.com>

  parent reply	other threads:[~2020-03-19 17:04 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-19 12:27 [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming Thierry Reding
2020-03-19 12:27 ` [PATCH 1/9] gpio: Support GPIO controllers without pin-ranges Thierry Reding
2020-03-19 17:05   ` Vidya Sagar
2020-03-27 10:37   ` Linus Walleij
2020-03-27 12:13     ` Thierry Reding
2020-03-19 12:27 ` [PATCH 2/9] gpio: tegra186: Add support for pin ranges Thierry Reding
2020-03-19 17:05   ` Vidya Sagar
2020-03-27 10:39   ` Linus Walleij
2020-03-31 20:53     ` Thierry Reding
2020-03-19 12:27 ` [PATCH 3/9] gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1 Thierry Reding
2020-03-19 17:06   ` Vidya Sagar
2020-03-27 10:39   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 4/9] pinctrl: tegra: Fix whitespace issues for improved readability Thierry Reding
2020-03-19 17:06   ` Vidya Sagar
2020-03-27 10:40   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 5/9] pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo Thierry Reding
2020-03-19 17:07   ` Vidya Sagar
2020-03-27 10:42   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 6/9] pinctrl: tegra: Pass struct tegra_pmx for pin range check Thierry Reding
2020-03-19 17:07   ` Vidya Sagar
2020-03-27 10:43   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 7/9] pinctrl: tegra: Do not add default pin range on Tegra194 Thierry Reding
2020-03-19 17:08   ` Vidya Sagar
2020-03-27 10:44   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins Thierry Reding
2020-03-19 17:08   ` Vidya Sagar
2020-03-27 10:45   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 9/9] pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 Thierry Reding
2020-03-19 17:08   ` Vidya Sagar
2020-03-27 10:46   ` Linus Walleij
2020-03-19 17:04 ` Vidya Sagar [this message]
2020-03-20 19:37 ` [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming Linus Walleij
2020-03-23 13:16   ` Thierry Reding

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=99368d3c-0a98-eb80-06a9-4deef402ce87@nvidia.com \
    --to=vidyas@nvidia.com \
    --cc=bgolaszewski@baylibre.com \
    --cc=jonathanh@nvidia.com \
    --cc=linus.walleij@linaro.org \
    --cc=linux-gpio@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=thierry.reding@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).