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From: Thierry Reding <thierry.reding@gmail.com>
To: Linus Walleij <linus.walleij@linaro.org>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Jon Hunter <jonathanh@nvidia.com>,
	Vidya Sagar <vidyas@nvidia.com>,
	linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: [PATCH 8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins
Date: Thu, 19 Mar 2020 13:27:36 +0100	[thread overview]
Message-ID: <20200319122737.3063291-9-thierry.reding@gmail.com> (raw)
In-Reply-To: <20200319122737.3063291-1-thierry.reding@gmail.com>

From: Thierry Reding <treding@nvidia.com>

There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra194.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index 61fc7e680788..61afe5fe9dec 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -24,17 +24,14 @@
 
 /* Define unique ID for each pins */
 enum pin_id {
-	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256,
-	TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257,
-	TEGRA_PIN_NUM_GPIOS = 258,
+	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
+	TEGRA_PIN_PEX_L5_RST_N_PGG1,
 };
 
 /* Table for pin descriptor */
 static const struct pinctrl_pin_desc tegra194_pins[] = {
-	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
-		    "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"),
-	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1,
-		    "TEGRA_PIN_PEX_L5_RST_N_PGG1"),
+	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
+	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
 };
 
 static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
-- 
2.24.1


  parent reply	other threads:[~2020-03-19 12:28 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-19 12:27 [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming Thierry Reding
2020-03-19 12:27 ` [PATCH 1/9] gpio: Support GPIO controllers without pin-ranges Thierry Reding
2020-03-19 17:05   ` Vidya Sagar
2020-03-27 10:37   ` Linus Walleij
2020-03-27 12:13     ` Thierry Reding
2020-03-19 12:27 ` [PATCH 2/9] gpio: tegra186: Add support for pin ranges Thierry Reding
2020-03-19 17:05   ` Vidya Sagar
2020-03-27 10:39   ` Linus Walleij
2020-03-31 20:53     ` Thierry Reding
2020-03-19 12:27 ` [PATCH 3/9] gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1 Thierry Reding
2020-03-19 17:06   ` Vidya Sagar
2020-03-27 10:39   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 4/9] pinctrl: tegra: Fix whitespace issues for improved readability Thierry Reding
2020-03-19 17:06   ` Vidya Sagar
2020-03-27 10:40   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 5/9] pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo Thierry Reding
2020-03-19 17:07   ` Vidya Sagar
2020-03-27 10:42   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 6/9] pinctrl: tegra: Pass struct tegra_pmx for pin range check Thierry Reding
2020-03-19 17:07   ` Vidya Sagar
2020-03-27 10:43   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 7/9] pinctrl: tegra: Do not add default pin range on Tegra194 Thierry Reding
2020-03-19 17:08   ` Vidya Sagar
2020-03-27 10:44   ` Linus Walleij
2020-03-19 12:27 ` Thierry Reding [this message]
2020-03-19 17:08   ` [PATCH 8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins Vidya Sagar
2020-03-27 10:45   ` Linus Walleij
2020-03-19 12:27 ` [PATCH 9/9] pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 Thierry Reding
2020-03-19 17:08   ` Vidya Sagar
2020-03-27 10:46   ` Linus Walleij
2020-03-19 17:04 ` [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming Vidya Sagar
2020-03-20 19:37 ` Linus Walleij
2020-03-23 13:16   ` Thierry Reding

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