From: Vidya Sagar <vidyas@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Jon Hunter <jonathanh@nvidia.com>, <linux-gpio@vger.kernel.org>,
<linux-tegra@vger.kernel.org>
Subject: Re: [PATCH 9/9] pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
Date: Thu, 19 Mar 2020 22:38:57 +0530 [thread overview]
Message-ID: <66c5ab1d-e5c0-b4b1-08c6-da5db3d4d939@nvidia.com> (raw)
In-Reply-To: <20200319122737.3063291-10-thierry.reding@gmail.com>
On 3/19/2020 5:57 PM, Thierry Reding wrote:
> External email: Use caution opening links or attachments
>
>
> From: Thierry Reding <treding@nvidia.com>
>
> Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part
> of the GPIO controller's register programming. Starting with Tegra186, a
> pin is configured as GPIO or SFIO with a bit in a configuration register
> of the pin controller.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/pinctrl/tegra/pinctrl-tegra.c | 46 ++++++++++++++++++++++++
> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
> drivers/pinctrl/tegra/pinctrl-tegra194.c | 2 ++
> 3 files changed, 51 insertions(+)
>
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
> index 65511bf27d34..21661f6490d6 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
> @@ -275,11 +275,57 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
> return 0;
> }
>
> +static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
> + struct pinctrl_gpio_range *range,
> + unsigned int offset)
> +{
> + struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> + const struct tegra_pingroup *group;
> + u32 value;
> +
> + if (!pmx->soc->sfsel_in_mux)
> + return 0;
> +
> + group = &pmx->soc->groups[offset];
> +
> + if (group->mux_reg < 0 || group->sfsel_bit < 0)
> + return -EINVAL;
> +
> + value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
> + value &= ~BIT(group->sfsel_bit);
> + pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
> +
> + return 0;
> +}
> +
> +static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
> + struct pinctrl_gpio_range *range,
> + unsigned int offset)
> +{
> + struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> + const struct tegra_pingroup *group;
> + u32 value;
> +
> + if (!pmx->soc->sfsel_in_mux)
> + return;
> +
> + group = &pmx->soc->groups[offset];
> +
> + if (group->mux_reg < 0 || group->sfsel_bit < 0)
> + return;
> +
> + value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
> + value |= BIT(group->sfsel_bit);
> + pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
> +}
> +
> static const struct pinmux_ops tegra_pinmux_ops = {
> .get_functions_count = tegra_pinctrl_get_funcs_count,
> .get_function_name = tegra_pinctrl_get_func_name,
> .get_function_groups = tegra_pinctrl_get_func_groups,
> .set_mux = tegra_pinctrl_set_mux,
> + .gpio_request_enable = tegra_pinctrl_gpio_request_enable,
> + .gpio_disable_free = tegra_pinctrl_gpio_disable_free,
> };
>
> static int tegra_pinconf_reg(struct tegra_pmx *pmx,
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
> index 520865979d4a..fcad7f74c5a2 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
> @@ -107,6 +107,7 @@ struct tegra_function {
> * drvup, slwr, slwf, and drvtype parameters.
> * @drv_bank: Drive fields register bank.
> * @hsm_bit: High Speed Mode register bit.
> + * @sfsel_bit: GPIO/SFIO selection register bit.
> * @schmitt_bit: Schmitt register bit.
> * @lpmd_bit: Low Power Mode register bit.
> * @drvdn_bit: Drive Down register bit.
> @@ -153,6 +154,7 @@ struct tegra_pingroup {
> s32 ioreset_bit:6;
> s32 rcv_sel_bit:6;
> s32 hsm_bit:6;
> + s32 sfsel_bit:6;
> s32 schmitt_bit:6;
> s32 lpmd_bit:6;
> s32 drvdn_bit:6;
> @@ -192,6 +194,7 @@ struct tegra_pinctrl_soc_data {
> bool hsm_in_mux;
> bool schmitt_in_mux;
> bool drvtype_in_mux;
> + bool sfsel_in_mux;
> };
>
> extern const struct dev_pm_ops tegra_pinctrl_pm;
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> index 61afe5fe9dec..2e0b5f7bb095 100644
> --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
> +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
> @@ -95,6 +95,7 @@ static struct tegra_function tegra194_functions[] = {
> .tri_bit = 4, \
> .einput_bit = e_input, \
> .odrain_bit = e_od, \
> + .sfsel_bit = 10, \
> .schmitt_bit = schmitt_b, \
> .drvtype_bit = 13, \
> .drv_reg = -1, \
> @@ -140,6 +141,7 @@ static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
> .hsm_in_mux = true,
> .schmitt_in_mux = true,
> .drvtype_in_mux = true,
> + .sfsel_in_mux = true,
> };
>
> static int tegra194_pinctrl_probe(struct platform_device *pdev)
> --
> 2.24.1
>
Tested-by: Vidya Sagar <vidyas@nvidia.com>
next prev parent reply other threads:[~2020-03-19 17:09 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-19 12:27 [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming Thierry Reding
2020-03-19 12:27 ` [PATCH 1/9] gpio: Support GPIO controllers without pin-ranges Thierry Reding
2020-03-19 17:05 ` Vidya Sagar
2020-03-27 10:37 ` Linus Walleij
2020-03-27 12:13 ` Thierry Reding
2020-03-19 12:27 ` [PATCH 2/9] gpio: tegra186: Add support for pin ranges Thierry Reding
2020-03-19 17:05 ` Vidya Sagar
2020-03-27 10:39 ` Linus Walleij
2020-03-31 20:53 ` Thierry Reding
2020-03-19 12:27 ` [PATCH 3/9] gpio: tegra186: Add Tegra194 pin ranges for GG.0 and GG.1 Thierry Reding
2020-03-19 17:06 ` Vidya Sagar
2020-03-27 10:39 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 4/9] pinctrl: tegra: Fix whitespace issues for improved readability Thierry Reding
2020-03-19 17:06 ` Vidya Sagar
2020-03-27 10:40 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 5/9] pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo Thierry Reding
2020-03-19 17:07 ` Vidya Sagar
2020-03-27 10:42 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 6/9] pinctrl: tegra: Pass struct tegra_pmx for pin range check Thierry Reding
2020-03-19 17:07 ` Vidya Sagar
2020-03-27 10:43 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 7/9] pinctrl: tegra: Do not add default pin range on Tegra194 Thierry Reding
2020-03-19 17:08 ` Vidya Sagar
2020-03-27 10:44 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 8/9] pinctrl: tegra: Renumber the GG.0 and GG.1 pins Thierry Reding
2020-03-19 17:08 ` Vidya Sagar
2020-03-27 10:45 ` Linus Walleij
2020-03-19 12:27 ` [PATCH 9/9] pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 Thierry Reding
2020-03-19 17:08 ` Vidya Sagar [this message]
2020-03-27 10:46 ` Linus Walleij
2020-03-19 17:04 ` [PATCH 0/9] pinctrl: tegra: Support SFIO/GPIO programming Vidya Sagar
2020-03-20 19:37 ` Linus Walleij
2020-03-23 13:16 ` Thierry Reding
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