From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <thierry.reding@gmail.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>,
<vidyas@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH V6 08/27] PCI: tegra: Program UPHY electrical settings for Tegra210
Date: Tue, 18 Jun 2019 23:31:47 +0530 [thread overview]
Message-ID: <20190618180206.4908-9-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <20190618180206.4908-1-mmaddireddy@nvidia.com>
UPHY electrical programming guidelines are documented in Tegra210 TRM.
Program these electrical settings for proper eye diagram in Gen1 and Gen2
link speeds.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V6: No change
V5: No change
V4: No change
V3: No change
V2: Addressed coding style comments
drivers/pci/controller/pci-tegra.c | 107 +++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 39a8cbf6da24..c38a370ed853 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -177,6 +177,32 @@
#define AFI_PEXBIAS_CTRL_0 0x168
+#define RP_ECTL_2_R1 0x00000e84
+#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff
+
+#define RP_ECTL_4_R1 0x00000e8c
+#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK (0xffff << 16)
+#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT 16
+
+#define RP_ECTL_5_R1 0x00000e90
+#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK 0xffffffff
+
+#define RP_ECTL_6_R1 0x00000e94
+#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff
+
+#define RP_ECTL_2_R2 0x00000ea4
+#define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff
+
+#define RP_ECTL_4_R2 0x00000eac
+#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK (0xffff << 16)
+#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT 16
+
+#define RP_ECTL_5_R2 0x00000eb0
+#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK 0xffffffff
+
+#define RP_ECTL_6_R2 0x00000eb4
+#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff
+
#define RP_VEND_XP 0x00000f00
#define RP_VEND_XP_DL_UP (1 << 30)
@@ -266,6 +292,19 @@ struct tegra_pcie_soc {
bool has_gen2;
bool force_pca_enable;
bool program_uphy;
+ struct {
+ struct {
+ u32 rp_ectl_2_r1;
+ u32 rp_ectl_4_r1;
+ u32 rp_ectl_5_r1;
+ u32 rp_ectl_6_r1;
+ u32 rp_ectl_2_r2;
+ u32 rp_ectl_4_r2;
+ u32 rp_ectl_5_r2;
+ u32 rp_ectl_6_r2;
+ } regs;
+ bool enable;
+ } ectl;
};
static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -492,6 +531,54 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
writel(value, port->base + RP_VEND_CTL1);
}
+static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
+{
+ const struct tegra_pcie_soc *soc = port->pcie->soc;
+ u32 value;
+
+ value = readl(port->base + RP_ECTL_2_R1);
+ value &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK;
+ value |= soc->ectl.regs.rp_ectl_2_r1;
+ writel(value, port->base + RP_ECTL_2_R1);
+
+ value = readl(port->base + RP_ECTL_4_R1);
+ value &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK;
+ value |= soc->ectl.regs.rp_ectl_4_r1 <<
+ RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT;
+ writel(value, port->base + RP_ECTL_4_R1);
+
+ value = readl(port->base + RP_ECTL_5_R1);
+ value &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK;
+ value |= soc->ectl.regs.rp_ectl_5_r1;
+ writel(value, port->base + RP_ECTL_5_R1);
+
+ value = readl(port->base + RP_ECTL_6_R1);
+ value &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK;
+ value |= soc->ectl.regs.rp_ectl_6_r1;
+ writel(value, port->base + RP_ECTL_6_R1);
+
+ value = readl(port->base + RP_ECTL_2_R2);
+ value &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK;
+ value |= soc->ectl.regs.rp_ectl_2_r2;
+ writel(value, port->base + RP_ECTL_2_R2);
+
+ value = readl(port->base + RP_ECTL_4_R2);
+ value &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK;
+ value |= soc->ectl.regs.rp_ectl_4_r2 <<
+ RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT;
+ writel(value, port->base + RP_ECTL_4_R2);
+
+ value = readl(port->base + RP_ECTL_5_R2);
+ value &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK;
+ value |= soc->ectl.regs.rp_ectl_5_r2;
+ writel(value, port->base + RP_ECTL_5_R2);
+
+ value = readl(port->base + RP_ECTL_6_R2);
+ value &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK;
+ value |= soc->ectl.regs.rp_ectl_6_r2;
+ writel(value, port->base + RP_ECTL_6_R2);
+}
+
static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
{
unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
@@ -518,6 +605,9 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
}
tegra_pcie_enable_rp_features(port);
+
+ if (soc->ectl.enable)
+ tegra_pcie_program_ectl_settings(port);
}
static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
@@ -2223,6 +2313,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.has_gen2 = false,
.force_pca_enable = false,
.program_uphy = true,
+ .ectl.enable = false,
};
static const struct tegra_pcie_port_soc tegra30_pcie_ports[] = {
@@ -2246,6 +2337,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.has_gen2 = false,
.force_pca_enable = false,
.program_uphy = true,
+ .ectl.enable = false,
};
static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2262,6 +2354,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.has_gen2 = true,
.force_pca_enable = false,
.program_uphy = true,
+ .ectl.enable = false,
};
static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2278,6 +2371,19 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.has_gen2 = true,
.force_pca_enable = true,
.program_uphy = true,
+ .ectl = {
+ .regs = {
+ .rp_ectl_2_r1 = 0x0000000f,
+ .rp_ectl_4_r1 = 0x00000067,
+ .rp_ectl_5_r1 = 0x55010000,
+ .rp_ectl_6_r1 = 0x00000001,
+ .rp_ectl_2_r2 = 0x0000008f,
+ .rp_ectl_4_r2 = 0x000000c7,
+ .rp_ectl_5_r2 = 0x55010000,
+ .rp_ectl_6_r2 = 0x00000001,
+ },
+ .enable = true,
+ },
};
static const struct tegra_pcie_port_soc tegra186_pcie_ports[] = {
@@ -2301,6 +2407,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.has_gen2 = true,
.force_pca_enable = false,
.program_uphy = false,
+ .ectl.enable = false,
};
static const struct of_device_id tegra_pcie_of_match[] = {
--
2.17.1
next prev parent reply other threads:[~2019-06-18 18:02 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-18 18:01 [PATCH V6 00/27] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 01/27] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 02/27] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 03/27] PCI: tegra: Rearrange Tegra PCIe driver functions Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 04/27] PCI: tegra: Mask AFI_INTR in runtime suspend Manikanta Maddireddy
2019-06-20 14:27 ` Lorenzo Pieralisi
2019-06-20 14:46 ` Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 05/27] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 06/27] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-06-20 14:32 ` Lorenzo Pieralisi
2019-06-20 14:57 ` Manikanta Maddireddy
2019-06-20 15:22 ` Lorenzo Pieralisi
2019-06-18 18:01 ` [PATCH V6 07/27] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-06-18 18:01 ` Manikanta Maddireddy [this message]
2019-06-18 18:01 ` [PATCH V6 09/27] PCI: tegra: Enable opportunistic UpdateFC and ACK Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 10/27] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 11/27] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 12/27] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 13/27] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 14/27] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 15/27] PCI: tegra: Update flow control timer frequency in Tegra210 Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 16/27] PCI: tegra: Set target speed as Gen1 before starting LTSSM Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 17/27] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 18/27] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-06-20 16:26 ` Lorenzo Pieralisi
2019-06-20 16:35 ` Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 19/27] PCI: tegra: Change PRSNT_SENSE IRQ log to debug Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 20/27] PCI: tegra: Disable MSI for Tegra PCIe root port Manikanta Maddireddy
2019-06-18 19:48 ` Bjorn Helgaas
2019-06-19 3:55 ` Manikanta Maddireddy
2019-06-19 9:50 ` Lorenzo Pieralisi
2019-06-18 18:02 ` [PATCH V6 21/27] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 22/27] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 23/27] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-06-20 10:14 ` Thierry Reding
2019-06-18 18:02 ` [PATCH V6 24/27] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 25/27] PCI: Add DT binding for "reset-gpios" property Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 26/27] PCI: tegra: Add support for GPIO based PERST# Manikanta Maddireddy
2019-07-04 14:48 ` Jon Hunter
2019-07-04 15:29 ` Manikanta Maddireddy
2019-07-04 17:23 ` Jon Hunter
2019-06-18 18:02 ` [PATCH V6 27/27] PCI: tegra: Change link retry log level to debug Manikanta Maddireddy
2019-06-20 10:25 ` [PATCH V6 00/27] Enable Tegra PCIe root port features Thierry Reding
2019-06-20 10:53 ` Lorenzo Pieralisi
2019-06-20 11:14 ` Thierry Reding
2019-06-20 16:46 ` Lorenzo Pieralisi
2019-06-20 17:23 ` Manikanta Maddireddy
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