From: Naveen Naidu <naveennaidu479@gmail.com>
To: bhelgaas@google.com
Cc: Naveen Naidu <naveennaidu479@gmail.com>,
linux-kernel-mentees@lists.linuxfoundation.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 14/22] PCI/ERR: Use RESPONSE_IS_PCI_ERROR() to check read from hardware
Date: Mon, 11 Oct 2021 23:34:21 +0530 [thread overview]
Message-ID: <5117401f4ff1ff8b0d0ebad0ef5b7b7adfee201e.1633972263.git.naveennaidu479@gmail.com> (raw)
In-Reply-To: <cover.1633972263.git.naveennaidu479@gmail.com>
An MMIO read from a PCI device that doesn't exist or doesn't respond
causes a PCI error. There's no real data to return to satisfy the
CPU read, so most hardware fabricates ~0 data.
Use RESPONSE_IS_PCI_ERROR() to check the response we get when we read
data from hardware.
This unifies PCI error response checking and make error checks
consistent and easier to find.
Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
---
drivers/pci/pci.c | 10 +++++-----
drivers/pci/probe.c | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index ce2ab62b64cf..c1575364d1ce 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1077,7 +1077,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
return -EIO;
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
- if (pmcsr == (u16) ~0) {
+ if (RESPONSE_IS_PCI_ERROR(&pmcsr)) {
pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
pci_power_name(dev->current_state),
pci_power_name(state));
@@ -1239,16 +1239,16 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
* After reset, the device should not silently discard config
* requests, but it may still indicate that it needs more time by
* responding to them with CRS completions. The Root Port will
- * generally synthesize ~0 data to complete the read (except when
- * CRS SV is enabled and the read was for the Vendor ID; in that
- * case it synthesizes 0x0001 data).
+ * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
+ * the read (except when CRS SV is enabled and the read was for the
+ * Vendor ID; in that case it synthesizes 0x0001 data).
*
* Wait for the device to return a non-CRS completion. Read the
* Command register instead of Vendor ID so we don't have to
* contend with the CRS SV value.
*/
pci_read_config_dword(dev, PCI_COMMAND, &id);
- while (id == ~0) {
+ while (RESPONSE_IS_PCI_ERROR(&id)) {
if (delay > timeout) {
pci_warn(dev, "not ready %dms after %s; giving up\n",
delay - 1, reset_type);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index d9fc02a71baa..55b94d689eca 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -206,14 +206,14 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
* 1 must be clear.
*/
- if (sz == 0xffffffff)
+ if (RESPONSE_IS_PCI_ERROR(&sz))
sz = 0;
/*
* I don't know how l can have all bits set. Copied from old code.
* Maybe it fixes a bug on some ancient platform.
*/
- if (l == 0xffffffff)
+ if (RESPONSE_IS_PCI_ERROR(&l))
l = 0;
if (type == pci_bar_unknown) {
@@ -1660,7 +1660,7 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev)
if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
return PCI_CFG_SPACE_SIZE;
- if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
+ if (RESPONSE_IS_PCI_ERROR(&status) || pci_ext_cfg_is_aliased(dev))
return PCI_CFG_SPACE_SIZE;
return PCI_CFG_SPACE_EXP_SIZE;
@@ -2336,8 +2336,8 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
return false;
- /* Some broken boards return 0 or ~0 if a slot is empty: */
- if (*l == 0xffffffff || *l == 0x00000000 ||
+ /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
+ if (RESPONSE_IS_PCI_ERROR(l) || *l == 0x00000000 ||
*l == 0x0000ffff || *l == 0xffff0000)
return false;
--
2.25.1
next prev parent reply other threads:[~2021-10-11 18:04 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-11 17:35 [PATCH 00/22] PCI: Unify PCI error response checking Naveen Naidu
2021-10-11 17:37 ` [PATCH 01/22] PCI: Add PCI_ERROR_RESPONSE and it's related defintions Naveen Naidu
2021-10-11 17:38 ` [PATCH 02/22] PCI: Unify PCI error response checking Naveen Naidu
2021-10-11 22:05 ` Rob Herring
2021-10-12 16:21 ` Naveen Naidu
2021-10-12 18:02 ` Rob Herring
2021-10-12 22:52 ` Pali Rohár
2021-10-13 2:43 ` Bjorn Helgaas
2021-10-13 13:06 ` Rob Herring
2021-10-13 17:16 ` Naveen Naidu
2021-10-13 17:54 ` Pali Rohár
2021-10-13 18:48 ` Bjorn Helgaas
2021-10-13 21:47 ` Rob Herring
2021-10-13 22:03 ` Pali Rohár
2021-10-13 22:12 ` Bjorn Helgaas
2021-10-11 17:45 ` [PATCH 03/22] PCI: thunder: Use SET_PCI_ERROR_RESPONSE() when device not found Naveen Naidu
2021-10-11 17:46 ` [PATCH 04/22] PCI: iproc: " Naveen Naidu
2021-10-11 17:51 ` [PATCH 05/22] PCI: mediatek: " Naveen Naidu
2021-10-11 17:52 ` [PATCH 06/22] PCI: exynos: " Naveen Naidu
2021-10-11 17:53 ` [PATCH 07/22] PCI: histb: " Naveen Naidu
2021-10-11 17:55 ` [PATCH 08/22] PCI: kirin: " Naveen Naidu
2021-10-11 17:56 ` [PATCH 09/22] PCI: aardvark: " Naveen Naidu
2021-10-11 18:08 ` Pali Rohár
2021-10-11 18:28 ` Naveen Naidu
[not found] ` <20211011182526.kboaxqofdpd2jjrl@theprophet>
2021-10-11 18:41 ` Pali Rohár
2021-10-12 15:59 ` Naveen Naidu
2021-10-13 2:13 ` Bjorn Helgaas
2021-10-13 17:59 ` Pali Rohár
2021-10-11 18:00 ` [PATCH 10/22] PCI: mvebu: " Naveen Naidu
2021-10-11 18:00 ` [PATCH 11/22] PCI: altera: " Naveen Naidu
2021-10-11 18:02 ` [PATCH 12/22] PCI: rcar: " Naveen Naidu
2021-10-11 18:02 ` [PATCH 13/22] PCI: rockchip: " Naveen Naidu
2021-10-11 18:04 ` Naveen Naidu [this message]
2021-10-11 18:06 ` [PATCH 15/22] PCI: vmd: Use RESPONSE_IS_PCI_ERROR() to check read from hardware Naveen Naidu
2021-10-14 18:04 ` Jonathan Derrick
2021-10-11 18:07 ` [PATCH 16/22] PCI: pciehp: " Naveen Naidu
2021-10-11 19:47 ` Lukas Wunner
2021-10-12 16:05 ` Naveen Naidu
2021-10-12 23:12 ` Pali Rohár
2021-10-13 12:20 ` Lukas Wunner
2021-10-11 18:08 ` [PATCH 17/22] PCI/DPC: " Naveen Naidu
2021-10-11 18:10 ` [PATCH 18/22] PCI/PME: " Naveen Naidu
2021-10-11 18:11 ` [PATCH 19/22] PCI: cpqphp: " Naveen Naidu
2021-10-11 18:11 ` [PATCH 20/22] PCI: keystone: Use PCI_ERROR_RESPONSE to specify hardware error Naveen Naidu
2021-10-11 18:12 ` [PATCH 21/22] PCI: hv: Use PCI_ERROR_RESPONSE to specify hardware read error Naveen Naidu
2021-10-11 18:13 ` [PATCH 22/22] PCI: xgene: Use PCI_ERROR_RESPONSE to specify hardware error Naveen Naidu
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