From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: <bhelgaas@google.com>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <jonathanh@nvidia.com>,
<lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH 12/30] PCI: tegra: Add SW fixup for RAW violations
Date: Mon, 15 Apr 2019 20:32:05 +0530 [thread overview]
Message-ID: <93988f14-6776-0143-ccf3-4efbf5be8ada@nvidia.com> (raw)
In-Reply-To: <20190415114510.GN29254@ulmo>
On 15-Apr-19 5:15 PM, Thierry Reding wrote:
> On Thu, Apr 11, 2019 at 10:33:37PM +0530, Manikanta Maddireddy wrote:
>> The logic which blocks read requests till AFI gets ACK for all outstanding
>> MC writes does not behave correctly when number of outstanding write
>> becomes more than 32 in Tegra124 and 132.
>>
>> SW fixup to prevent this issue is to limit outstanding posted writes and
>> tweak updateFC timer threshold.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> drivers/pci/controller/pci-tegra.c | 34 ++++++++++++++++++++++++++++++
>> 1 file changed, 34 insertions(+)
>>
>> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
>> index 9e61da68cfae..b74408eeb367 100644
>> --- a/drivers/pci/controller/pci-tegra.c
>> +++ b/drivers/pci/controller/pci-tegra.c
>> @@ -178,6 +178,13 @@
>>
>> #define AFI_PEXBIAS_CTRL_0 0x168
>>
>> +#define RP_PRIV_XP_DL 0x00000494
>> +#define RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD (0x1ff << 1)
>> +
>> +#define RP_RX_HDR_LIMIT 0x00000e00
>> +#define RP_RX_HDR_LIMIT_PW_MASK (0xff << 8)
>> +#define RP_RX_HDR_LIMIT_PW (0x0e << 8)
>> +
>> #define RP_ECTL_2_R1 0x00000e84
>> #define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff
>>
>> @@ -208,6 +215,7 @@
>> #define RP_VEND_XP_DL_UP (1 << 30)
>> #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27)
>> #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28)
>> +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18)
>>
>> #define RP_VEND_CTL0 0x00000f44
>> #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12)
>> @@ -300,6 +308,7 @@ struct tegra_pcie_soc {
>> u32 tx_ref_sel;
>> u32 pads_refclk_cfg0;
>> u32 pads_refclk_cfg1;
>> + u32 update_fc_val;
> Shouldn't this be something like "update_fc_threshold" since the mask
> defined above is for a field named UPDATE_FC_THRESHOLD?
>
>> bool has_pex_clkreq_en;
>> bool has_pex_bias_ctrl;
>> bool has_intr_prsnt_sense;
>> @@ -309,6 +318,7 @@ struct tegra_pcie_soc {
>> bool program_uphy;
>> bool update_clamp_threshold;
>> bool program_deskew_time;
>> + bool raw_violation_fixup;
>> struct {
>> struct {
>> u32 rp_ectl_2_r1;
>> @@ -635,6 +645,23 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>> value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
>> writel(value, port->base + RP_VEND_CTL0);
>> }
>> +
>> + /* Fixup for read after write violation in T124 & T132 platforms */
> No need to mention the SoC generations here, it's already implied by the
> per-SoC flag.
>
> Thierry
I will take care of both the comments in V2
Manikanta
>
>> + if (soc->raw_violation_fixup) {
>> + value = readl(port->base + RP_RX_HDR_LIMIT);
>> + value &= ~RP_RX_HDR_LIMIT_PW_MASK;
>> + value |= RP_RX_HDR_LIMIT_PW;
>> + writel(value, port->base + RP_RX_HDR_LIMIT);
>> +
>> + value = readl(port->base + RP_PRIV_XP_DL);
>> + value |= RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD;
>> + writel(value, port->base + RP_PRIV_XP_DL);
>> +
>> + value = readl(port->base + RP_VEND_XP);
>> + value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
>> + value |= soc->update_fc_val;
>> + writel(value, port->base + RP_VEND_XP);
>> + }
>> }
>>
>> static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
>> @@ -2381,6 +2408,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
>> .program_uphy = true,
>> .update_clamp_threshold = false,
>> .program_deskew_time = false,
>> + .raw_violation_fixup = false,
>> .ectl.enable = false,
>> };
>>
>> @@ -2407,6 +2435,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
>> .program_uphy = true,
>> .update_clamp_threshold = false,
>> .program_deskew_time = false,
>> + .raw_violation_fixup = false,
>> .ectl.enable = false,
>> };
>>
>> @@ -2417,6 +2446,8 @@ static const struct tegra_pcie_soc tegra124_pcie = {
>> .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
>> .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
>> .pads_refclk_cfg0 = 0x44ac44ac,
>> + /* FC threshold is bit[25:18] */
>> + .update_fc_val = 0x03fc0000,
>
>
>> .has_pex_clkreq_en = true,
>> .has_pex_bias_ctrl = true,
>> .has_intr_prsnt_sense = true,
>> @@ -2426,6 +2457,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
>> .program_uphy = true,
>> .update_clamp_threshold = true,
>> .program_deskew_time = false,
>> + .raw_violation_fixup = true,
>> .ectl.enable = false,
>> };
>>
>> @@ -2445,6 +2477,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
>> .program_uphy = true,
>> .update_clamp_threshold = true,
>> .program_deskew_time = true,
>> + .raw_violation_fixup = false,
>> .ectl.regs.rp_ectl_2_r1 = 0x0000000f,
>> .ectl.regs.rp_ectl_4_r1 = 0x00000067,
>> .ectl.regs.rp_ectl_5_r1 = 0x55010000,
>> @@ -2479,6 +2512,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
>> .program_uphy = false,
>> .update_clamp_threshold = false,
>> .program_deskew_time = false,
>> + .raw_violation_fixup = false,
>> .ectl.enable = false,
>> };
>>
>> --
>> 2.17.1
>>
next prev parent reply other threads:[~2019-04-15 15:02 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-11 17:03 [PATCH 00/30] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 01/30] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 02/30] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-04-15 11:01 ` Thierry Reding
2019-04-15 14:11 ` Manikanta Maddireddy
2019-04-15 14:30 ` Thierry Reding
2019-04-15 18:14 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 03/30] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2019-04-15 11:06 ` Thierry Reding
2019-04-15 14:20 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 04/30] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-04-15 11:21 ` Thierry Reding
2019-04-15 14:47 ` Manikanta Maddireddy
2019-04-15 15:36 ` Thierry Reding
2019-04-15 15:53 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 05/30] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-04-15 11:23 ` Thierry Reding
2019-04-15 14:49 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 06/30] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy
2019-04-15 11:29 ` Thierry Reding
2019-04-15 14:55 ` Manikanta Maddireddy
2019-04-15 15:38 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 07/30] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
2019-04-15 11:30 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 08/30] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-04-15 11:32 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 09/30] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-04-15 11:33 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 10/30] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-04-15 11:37 ` Thierry Reding
2019-04-15 14:58 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 11/30] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-04-15 11:39 ` Thierry Reding
2019-04-15 14:58 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 12/30] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-04-11 20:01 ` Bjorn Helgaas
2019-04-12 5:59 ` Manikanta Maddireddy
2019-04-15 11:41 ` Thierry Reding
2019-04-15 11:45 ` Thierry Reding
2019-04-15 15:02 ` Manikanta Maddireddy [this message]
2019-04-11 17:03 ` [PATCH 13/30] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy
2019-04-15 11:47 ` Thierry Reding
2019-04-15 15:05 ` Manikanta Maddireddy
2019-04-23 9:27 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 14/30] PCI: tegra: Set target speed as Gen1 before link up Manikanta Maddireddy
2019-04-11 20:04 ` Bjorn Helgaas
2019-04-12 6:44 ` Manikanta Maddireddy
2019-04-12 14:35 ` Bjorn Helgaas
2019-04-15 10:43 ` Manikanta Maddireddy
2019-04-15 11:52 ` Thierry Reding
2019-04-15 15:12 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 15/30] PCI: tegra: Fix PLLE powerdown issue due to CLKREQ# signal Manikanta Maddireddy
2019-04-15 13:17 ` Thierry Reding
2019-04-15 15:14 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 16/30] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-04-15 13:20 ` Thierry Reding
2019-04-16 10:47 ` Manikanta Maddireddy
2019-04-16 16:11 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 17/30] PCI: tegra: Use switch statements in tegra_pcie_isr() Manikanta Maddireddy
2019-04-15 13:25 ` Thierry Reding
2019-04-15 15:25 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 18/30] PCI: tegra: Change PRSNT_SENSE irq log to debug Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 19/30] PCI: tegra: Use legacy irq for port service drivers Manikanta Maddireddy
2019-04-15 13:35 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 20/30] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy
2019-04-15 13:31 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 21/30] PCI: tegra: Add "pci" type check before parsing child device tree node Manikanta Maddireddy
2019-04-15 13:37 ` Thierry Reding
2019-04-15 15:30 ` Manikanta Maddireddy
2019-04-15 15:42 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 22/30] PCI: tegra: Access endpoint config only if PCIe link is up Manikanta Maddireddy
2019-04-11 20:15 ` Bjorn Helgaas
2019-04-12 7:00 ` Manikanta Maddireddy
2019-04-12 14:50 ` Bjorn Helgaas
2019-04-15 11:36 ` Manikanta Maddireddy
2019-04-15 13:45 ` Thierry Reding
2019-04-15 13:52 ` Thierry Reding
2019-04-15 14:04 ` Bjorn Helgaas
2019-04-15 15:43 ` Manikanta Maddireddy
2019-04-23 20:24 ` Bjorn Helgaas
2019-04-11 17:03 ` [PATCH 23/30] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-04-15 14:07 ` Thierry Reding
2019-04-15 15:48 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 24/30] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 25/30] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-04-15 14:11 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 26/30] dt-bindings: pci: tegra: Document nvidia,plat-gpios optional prop Manikanta Maddireddy
2019-04-11 20:18 ` Bjorn Helgaas
2019-04-12 7:01 ` Manikanta Maddireddy
2019-04-15 14:16 ` Thierry Reding
2019-04-15 17:58 ` Manikanta Maddireddy
2019-04-16 15:34 ` Thierry Reding
2019-04-17 11:22 ` Manikanta Maddireddy
2019-04-17 15:19 ` Thierry Reding
2019-04-17 18:26 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 27/30] PCI: tegra: Add support to configure platform GPIOs Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 28/30] dt-bindings: pci: tegra: Document nvidia,rst-gpio optional prop Manikanta Maddireddy
2019-04-15 14:20 ` Thierry Reding
2019-04-15 18:01 ` Manikanta Maddireddy
2019-04-29 18:33 ` Rob Herring
2019-04-11 17:03 ` [PATCH 29/30] PCI: tegra: Add support for GPIO based PCIe reset Manikanta Maddireddy
2019-04-15 14:20 ` Thierry Reding
2019-04-15 18:03 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 30/30] PCI: tegra: Change link retry log level to INFO Manikanta Maddireddy
2019-04-15 14:23 ` Thierry Reding
2019-04-15 18:05 ` Manikanta Maddireddy
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