From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: <bhelgaas@google.com>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <jonathanh@nvidia.com>,
<lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH 11/30] PCI: tegra: Increase the deskew retry time
Date: Mon, 15 Apr 2019 20:28:54 +0530 [thread overview]
Message-ID: <e7a8746e-484a-03b1-bec1-ee026d0651f0@nvidia.com> (raw)
In-Reply-To: <20190415113918.GL29254@ulmo>
On 15-Apr-19 5:09 PM, Thierry Reding wrote:
> On Thu, Apr 11, 2019 at 10:33:36PM +0530, Manikanta Maddireddy wrote:
>> Some times link speed change from Gen2 to Gen1 fails due to instability
> "Sometimes"
>
>> in deskew logic on lane-0 in Tegra210. Increase the deskew retry time
>> to resolve this issue.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> drivers/pci/controller/pci-tegra.c | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
>> index f785ecae2f6b..9e61da68cfae 100644
>> --- a/drivers/pci/controller/pci-tegra.c
>> +++ b/drivers/pci/controller/pci-tegra.c
>> @@ -209,6 +209,10 @@
>> #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27)
>> #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28)
>>
>> +#define RP_VEND_CTL0 0x00000f44
>> +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12)
>> +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12)
>> +
>> #define RP_VEND_CTL1 0x00000f48
>> #define RP_VEND_CTL1_ERPT (1 << 13)
>>
>> @@ -304,6 +308,7 @@ struct tegra_pcie_soc {
>> bool force_pca_enable;
>> bool program_uphy;
>> bool update_clamp_threshold;
>> + bool program_deskew_time;
>> struct {
>> struct {
>> u32 rp_ectl_2_r1;
>> @@ -615,6 +620,23 @@ static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
>> writel(val, port->base + RP_ECTL_6_R2);
>> }
>>
>> +static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>> +{
>> + const struct tegra_pcie_soc *soc = port->pcie->soc;
>> + u32 value;
>> +
>> + /*
>> + * Tune deskew retry time to take care of Gen2 -> Gen1
>> + * link speed change error in corner cases
>> + */
>> + if (soc->program_deskew_time) {
>> + value = readl(port->base + RP_VEND_CTL0);
>> + value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK;
>> + value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
>> + writel(value, port->base + RP_VEND_CTL0);
>> + }
>> +}
>> +
>> static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
>> {
>> unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
>> @@ -643,6 +665,7 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
>> tegra_pcie_enable_rp_features(port);
>> if (soc->ectl.enable)
>> tegra_pcie_program_ectl_settings(port);
>> + tegra_pcie_apply_sw_fixup(port);
> Blank line between the above two for readability.
>
> Thierry
I will take care of all the comments in V2
Manikanta
>
>> }
>>
>> static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
>> @@ -2357,6 +2380,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
>> .force_pca_enable = false,
>> .program_uphy = true,
>> .update_clamp_threshold = false,
>> + .program_deskew_time = false,
>> .ectl.enable = false,
>> };
>>
>> @@ -2382,6 +2406,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
>> .force_pca_enable = false,
>> .program_uphy = true,
>> .update_clamp_threshold = false,
>> + .program_deskew_time = false,
>> .ectl.enable = false,
>> };
>>
>> @@ -2400,6 +2425,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
>> .force_pca_enable = false,
>> .program_uphy = true,
>> .update_clamp_threshold = true,
>> + .program_deskew_time = false,
>> .ectl.enable = false,
>> };
>>
>> @@ -2418,6 +2444,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
>> .force_pca_enable = true,
>> .program_uphy = true,
>> .update_clamp_threshold = true,
>> + .program_deskew_time = true,
>> .ectl.regs.rp_ectl_2_r1 = 0x0000000f,
>> .ectl.regs.rp_ectl_4_r1 = 0x00000067,
>> .ectl.regs.rp_ectl_5_r1 = 0x55010000,
>> @@ -2451,6 +2478,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
>> .force_pca_enable = false,
>> .program_uphy = false,
>> .update_clamp_threshold = false,
>> + .program_deskew_time = false,
>> .ectl.enable = false,
>> };
>>
>> --
>> 2.17.1
>>
next prev parent reply other threads:[~2019-04-15 14:59 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-11 17:03 [PATCH 00/30] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 01/30] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 02/30] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-04-15 11:01 ` Thierry Reding
2019-04-15 14:11 ` Manikanta Maddireddy
2019-04-15 14:30 ` Thierry Reding
2019-04-15 18:14 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 03/30] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2019-04-15 11:06 ` Thierry Reding
2019-04-15 14:20 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 04/30] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-04-15 11:21 ` Thierry Reding
2019-04-15 14:47 ` Manikanta Maddireddy
2019-04-15 15:36 ` Thierry Reding
2019-04-15 15:53 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 05/30] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-04-15 11:23 ` Thierry Reding
2019-04-15 14:49 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 06/30] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy
2019-04-15 11:29 ` Thierry Reding
2019-04-15 14:55 ` Manikanta Maddireddy
2019-04-15 15:38 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 07/30] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
2019-04-15 11:30 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 08/30] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-04-15 11:32 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 09/30] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-04-15 11:33 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 10/30] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-04-15 11:37 ` Thierry Reding
2019-04-15 14:58 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 11/30] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-04-15 11:39 ` Thierry Reding
2019-04-15 14:58 ` Manikanta Maddireddy [this message]
2019-04-11 17:03 ` [PATCH 12/30] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-04-11 20:01 ` Bjorn Helgaas
2019-04-12 5:59 ` Manikanta Maddireddy
2019-04-15 11:41 ` Thierry Reding
2019-04-15 11:45 ` Thierry Reding
2019-04-15 15:02 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 13/30] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy
2019-04-15 11:47 ` Thierry Reding
2019-04-15 15:05 ` Manikanta Maddireddy
2019-04-23 9:27 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 14/30] PCI: tegra: Set target speed as Gen1 before link up Manikanta Maddireddy
2019-04-11 20:04 ` Bjorn Helgaas
2019-04-12 6:44 ` Manikanta Maddireddy
2019-04-12 14:35 ` Bjorn Helgaas
2019-04-15 10:43 ` Manikanta Maddireddy
2019-04-15 11:52 ` Thierry Reding
2019-04-15 15:12 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 15/30] PCI: tegra: Fix PLLE powerdown issue due to CLKREQ# signal Manikanta Maddireddy
2019-04-15 13:17 ` Thierry Reding
2019-04-15 15:14 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 16/30] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-04-15 13:20 ` Thierry Reding
2019-04-16 10:47 ` Manikanta Maddireddy
2019-04-16 16:11 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 17/30] PCI: tegra: Use switch statements in tegra_pcie_isr() Manikanta Maddireddy
2019-04-15 13:25 ` Thierry Reding
2019-04-15 15:25 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 18/30] PCI: tegra: Change PRSNT_SENSE irq log to debug Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 19/30] PCI: tegra: Use legacy irq for port service drivers Manikanta Maddireddy
2019-04-15 13:35 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 20/30] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy
2019-04-15 13:31 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 21/30] PCI: tegra: Add "pci" type check before parsing child device tree node Manikanta Maddireddy
2019-04-15 13:37 ` Thierry Reding
2019-04-15 15:30 ` Manikanta Maddireddy
2019-04-15 15:42 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 22/30] PCI: tegra: Access endpoint config only if PCIe link is up Manikanta Maddireddy
2019-04-11 20:15 ` Bjorn Helgaas
2019-04-12 7:00 ` Manikanta Maddireddy
2019-04-12 14:50 ` Bjorn Helgaas
2019-04-15 11:36 ` Manikanta Maddireddy
2019-04-15 13:45 ` Thierry Reding
2019-04-15 13:52 ` Thierry Reding
2019-04-15 14:04 ` Bjorn Helgaas
2019-04-15 15:43 ` Manikanta Maddireddy
2019-04-23 20:24 ` Bjorn Helgaas
2019-04-11 17:03 ` [PATCH 23/30] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-04-15 14:07 ` Thierry Reding
2019-04-15 15:48 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 24/30] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 25/30] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-04-15 14:11 ` Thierry Reding
2019-04-11 17:03 ` [PATCH 26/30] dt-bindings: pci: tegra: Document nvidia,plat-gpios optional prop Manikanta Maddireddy
2019-04-11 20:18 ` Bjorn Helgaas
2019-04-12 7:01 ` Manikanta Maddireddy
2019-04-15 14:16 ` Thierry Reding
2019-04-15 17:58 ` Manikanta Maddireddy
2019-04-16 15:34 ` Thierry Reding
2019-04-17 11:22 ` Manikanta Maddireddy
2019-04-17 15:19 ` Thierry Reding
2019-04-17 18:26 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 27/30] PCI: tegra: Add support to configure platform GPIOs Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 28/30] dt-bindings: pci: tegra: Document nvidia,rst-gpio optional prop Manikanta Maddireddy
2019-04-15 14:20 ` Thierry Reding
2019-04-15 18:01 ` Manikanta Maddireddy
2019-04-29 18:33 ` Rob Herring
2019-04-11 17:03 ` [PATCH 29/30] PCI: tegra: Add support for GPIO based PCIe reset Manikanta Maddireddy
2019-04-15 14:20 ` Thierry Reding
2019-04-15 18:03 ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 30/30] PCI: tegra: Change link retry log level to INFO Manikanta Maddireddy
2019-04-15 14:23 ` Thierry Reding
2019-04-15 18:05 ` Manikanta Maddireddy
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