[PATCH 00/17] Add more support for the RZ/G2E

[PATCH 00/17] Add more support for the RZ/G2E

[Fabrizio Castro]

Dear All,

this series adds more support to the RZ/G2E (a.k.a. r8a774c0)
SoC specific device tree on top of what added from series
(on which this series depends on):
https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg36692.html

Thanks,
Fab

Fabrizio Castro (17):
  arm64: dts: renesas: r8a774c0: Add SDHI nodes
  arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support
  arm64: dts: renesas: r8a774c0: Add IPMMU device nodes
  arm64: dts: renesas: r8a774c0: Add CAN nodes
  arm64: dts: renesas: r8a774c0: Add thermal support
  arm64: dts: renesas: r8a774c0: Add MSIOF nodes
  arm64: dts: renesas: r8a774c0: Add audio support
  arm64: dts: renesas: r8a774c0: Add PWM support
  arm64: dts: renesas: r8a774c0: Add display output support
  arm64: dts: renesas: r8a774c0: Add USB2.0 phy and host device nodes
  arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes
  arm64: dts: renesas: r8a774c0: Add USB3.0 device nodes
  arm64: dts: renesas: r8a774c0: Connect RZ/G2E SYS-DMAC to IPMMU
  arm64: dts: renesas: r8a774c0: Connect RZ/G2E AVB to IPMMU
  arm64: dts: renesas: r8a774c0: Connect RZ/G2E Audio-DMAC to IPMMU
  arm64: dts: renesas: r8a774c0: Add PCIe device node
  arm64: dts: renesas: r8a774c0: Add VIN and CSI-2 device nodes

 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1099 +++++++++++++++++++++++++++++
 1 file changed, 1099 insertions(+)

-- 
2.7.4

[PATCH 01/17] arm64: dts: renesas: r8a774c0: Add SDHI nodes

[Fabrizio Castro]

Add SDHI nodes to the DT of the r8a774c0 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 36 +++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 83db7c7..96a71e3 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -603,6 +603,42 @@
 			status = "disabled";
 		};
 
+		sdhi0: sd@ee100000 {
+			compatible = "renesas,sdhi-r8a774c0",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee100000 0 0x2000>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 314>;
+			status = "disabled";
+		};
+
+		sdhi1: sd@ee120000 {
+			compatible = "renesas,sdhi-r8a774c0",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee120000 0 0x2000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 313>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 313>;
+			status = "disabled";
+		};
+
+		sdhi3: sd@ee160000 {
+			compatible = "renesas,sdhi-r8a774c0",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee160000 0 0x2000>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 311>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@f1010000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
-- 
2.7.4

[PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support

[Fabrizio Castro]

Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774c0 device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 143 ++++++++++++++++++++++++++++++
 1 file changed, 143 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 96a71e3..bf08aba 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -271,6 +271,149 @@
 			resets = <&cpg 407>;
 		};
 
+		i2c0: i2c@e6500000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774c0",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6500000 0 0x40>;
+			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 931>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 931>;
+			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+			       <&dmac2 0x91>, <&dmac2 0x90>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@e6508000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774c0",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6508000 0 0x40>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 930>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 930>;
+			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+			       <&dmac2 0x93>, <&dmac2 0x92>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@e6510000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774c0",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6510000 0 0x40>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 929>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 929>;
+			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+			       <&dmac2 0x95>, <&dmac2 0x94>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@e66d0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774c0",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d0000 0 0x40>;
+			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 928>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 928>;
+			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@e66d8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774c0",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d8000 0 0x40>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 927>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 927>;
+			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@e66e0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774c0",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e0000 0 0x40>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 919>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 919>;
+			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@e66e8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774c0",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e8000 0 0x40>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 918>;
+			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@e6690000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774c0",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6690000 0 0x40>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1003>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 1003>;
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c_dvfs: i2c@e60b0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,iic-r8a774c0";
+			reg = <0 0xe60b0000 0 0x15>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 926>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 926>;
+			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
 		hscif0: serial@e6540000 {
 			compatible = "renesas,hscif-r8a774c0",
 				     "renesas,rcar-gen3-hscif",
-- 
2.7.4

[PATCH 03/17] arm64: dts: renesas: r8a774c0: Add IPMMU device nodes

[Fabrizio Castro]

Add r8a774c0 IPMMU nodes.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 73 +++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index bf08aba..042e26d 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -604,6 +604,79 @@
 			dma-channels = <16>;
 		};
 
+		ipmmu_ds0: mmu@e6740000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xe6740000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 0>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_ds1: mmu@e7740000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xe7740000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 1>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_hc: mmu@e6570000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xe6570000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 2>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mm: mmu@e67b0000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xe67b0000 0 0x1000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mp: mmu@ec670000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xec670000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 4>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_pv0: mmu@fd800000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xfd800000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 6>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vc0: mmu@fe6b0000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xfe6b0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 12>;
+			power-domains = <&sysc R8A774C0_PD_A3VC>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vi0: mmu@febd0000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xfebd0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 14>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vp0: mmu@fe990000 {
+			compatible = "renesas,ipmmu-r8a774c0";
+			reg = <0 0xfe990000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 16>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
 		avb: ethernet@e6800000 {
 			compatible = "renesas,etheravb-r8a774c0",
 				     "renesas,etheravb-rcar-gen3";
-- 
2.7.4

[PATCH 04/17] arm64: dts: renesas: r8a774c0: Add CAN nodes

[Fabrizio Castro]

Add the device nodes for both RZ/G2E CAN channels.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 042e26d..446cab1 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -722,6 +722,30 @@
 			status = "disabled";
 		};
 
+		can0: can@e6c30000 {
+			compatible = "renesas,can-r8a774c0",
+				     "renesas,rcar-gen3-can";
+			reg = <0 0xe6c30000 0 0x1000>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
+			clock-names = "clkp1", "can_clk";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 916>;
+			status = "disabled";
+		};
+
+		can1: can@e6c38000 {
+			compatible = "renesas,can-r8a774c0",
+				     "renesas,rcar-gen3-can";
+			reg = <0 0xe6c38000 0 0x1000>;
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
+			clock-names = "clkp1", "can_clk";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 915>;
+			status = "disabled";
+		};
+
 		scif0: serial@e6e60000 {
 			compatible = "renesas,scif-r8a774c0",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.7.4

[PATCH 05/17] arm64: dts: renesas: r8a774c0: Add thermal support

[Fabrizio Castro]

This patch adds the thermal device node and the thermal-zones
node to the SoC specific dtsi for the RZ/G2E.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 446cab1..9532d29 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -255,6 +255,18 @@
 			#power-domain-cells = <1>;
 		};
 
+		thermal: thermal@e6190000 {
+			compatible = "renesas,thermal-r8a774c0";
+			reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 522>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 522>;
+			#thermal-sensor-cells = <0>;
+		};
+
 		intc_ex: interrupt-controller@e61c0000 {
 			compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
 			#interrupt-cells = <2>;
@@ -902,6 +914,25 @@
 		};
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&thermal>;
+
+			trips {
+				cpu-crit {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-- 
2.7.4

[PATCH 06/17] arm64: dts: renesas: r8a774c0: Add MSIOF nodes

[Fabrizio Castro]

Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 9532d29..9bd66b1 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -855,6 +855,68 @@
 			status = "disabled";
 		};
 
+		msiof0: spi@e6e90000 {
+			compatible = "renesas,msiof-r8a774c0",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6e90000 0 0x0064>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 211>;
+			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+			       <&dmac2 0x41>, <&dmac2 0x40>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 211>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof1: spi@e6ea0000 {
+			compatible = "renesas,msiof-r8a774c0",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6ea0000 0 0x0064>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 210>;
+			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+			       <&dmac2 0x43>, <&dmac2 0x42>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 210>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof2: spi@e6c00000 {
+			compatible = "renesas,msiof-r8a774c0",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c00000 0 0x0064>;
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 209>;
+			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 209>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof3: spi@e6c10000 {
+			compatible = "renesas,msiof-r8a774c0",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c10000 0 0x0064>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 208>;
+			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 208>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		sdhi0: sd@ee100000 {
 			compatible = "renesas,sdhi-r8a774c0",
 				     "renesas,rcar-gen3-sdhi";
-- 
2.7.4

[PATCH 07/17] arm64: dts: renesas: r8a774c0: Add audio support

[Fabrizio Castro]

Add sound support for the RZ/G2E SoC (a.k.a. R8A774C0).

This work is based on similar work done on the R8A77990 SoC
by Yoshihiro Kaneko <ykaneko0929@gmail.com>.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 241 ++++++++++++++++++++++++++++++
 1 file changed, 241 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 9bd66b1..35b27b8 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -917,6 +917,247 @@
 			status = "disabled";
 		};
 
+		rcar_sound: sound@ec500000 {
+			/*
+			 * #sound-dai-cells is required
+			 *
+			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
+			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
+			 */
+			/*
+			 * #clock-cells is required for audio_clkout0/1/2/3
+			 *
+			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
+			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
+			 */
+			compatible = "renesas,rcar_sound-r8a774c0",
+				     "renesas,rcar_sound-gen3";
+			reg =	<0 0xec500000 0 0x1000>, /* SCU */
+				<0 0xec5a0000 0 0x100>,  /* ADG */
+				<0 0xec540000 0 0x1000>, /* SSIU */
+				<0 0xec541000 0 0x280>,  /* SSI */
+				<0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
+			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+			clocks = <&cpg CPG_MOD 1005>,
+				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+				 <&audio_clk_a>, <&audio_clk_b>,
+				 <&audio_clk_c>,
+				 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
+			clock-names = "ssi-all",
+				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+				      "ssi.1", "ssi.0",
+				      "src.9", "src.8", "src.7", "src.6",
+				      "src.5", "src.4", "src.3", "src.2",
+				      "src.1", "src.0",
+				      "mix.1", "mix.0",
+				      "ctu.1", "ctu.0",
+				      "dvc.0", "dvc.1",
+				      "clk_a", "clk_b", "clk_c", "clk_i";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 1005>,
+				 <&cpg 1006>, <&cpg 1007>,
+				 <&cpg 1008>, <&cpg 1009>,
+				 <&cpg 1010>, <&cpg 1011>,
+				 <&cpg 1012>, <&cpg 1013>,
+				 <&cpg 1014>, <&cpg 1015>;
+			reset-names = "ssi-all",
+				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+				      "ssi.1", "ssi.0";
+			status = "disabled";
+
+			rcar_sound,dvc {
+				dvc0: dvc-0 {
+					dmas = <&audma0 0xbc>;
+					dma-names = "tx";
+				};
+				dvc1: dvc-1 {
+					dmas = <&audma0 0xbe>;
+					dma-names = "tx";
+				};
+			};
+
+			rcar_sound,mix {
+				mix0: mix-0 { };
+				mix1: mix-1 { };
+			};
+
+			rcar_sound,ctu {
+				ctu00: ctu-0 { };
+				ctu01: ctu-1 { };
+				ctu02: ctu-2 { };
+				ctu03: ctu-3 { };
+				ctu10: ctu-4 { };
+				ctu11: ctu-5 { };
+				ctu12: ctu-6 { };
+				ctu13: ctu-7 { };
+			};
+
+			rcar_sound,src {
+				src0: src-0 {
+					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x85>, <&audma0 0x9a>;
+					dma-names = "rx", "tx";
+				};
+				src1: src-1 {
+					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x87>, <&audma0 0x9c>;
+					dma-names = "rx", "tx";
+				};
+				src2: src-2 {
+					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x89>, <&audma0 0x9e>;
+					dma-names = "rx", "tx";
+				};
+				src3: src-3 {
+					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+					dma-names = "rx", "tx";
+				};
+				src4: src-4 {
+					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+					dma-names = "rx", "tx";
+				};
+				src5: src-5 {
+					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+					dma-names = "rx", "tx";
+				};
+				src6: src-6 {
+					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x91>, <&audma0 0xb4>;
+					dma-names = "rx", "tx";
+				};
+				src7: src-7 {
+					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x93>, <&audma0 0xb6>;
+					dma-names = "rx", "tx";
+				};
+				src8: src-8 {
+					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x95>, <&audma0 0xb8>;
+					dma-names = "rx", "tx";
+				};
+				src9: src-9 {
+					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x97>, <&audma0 0xba>;
+					dma-names = "rx", "tx";
+				};
+			};
+
+			rcar_sound,ssi {
+				ssi0: ssi-0 {
+					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x01>, <&audma0 0x02>,
+					       <&audma0 0x15>, <&audma0 0x16>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi1: ssi-1 {
+					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x03>, <&audma0 0x04>,
+					       <&audma0 0x49>, <&audma0 0x4a>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi2: ssi-2 {
+					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x05>, <&audma0 0x06>,
+					       <&audma0 0x63>, <&audma0 0x64>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi3: ssi-3 {
+					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x07>, <&audma0 0x08>,
+					       <&audma0 0x6f>, <&audma0 0x70>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi4: ssi-4 {
+					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x09>, <&audma0 0x0a>,
+					       <&audma0 0x71>, <&audma0 0x72>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi5: ssi-5 {
+					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+					       <&audma0 0x73>, <&audma0 0x74>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi6: ssi-6 {
+					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+					       <&audma0 0x75>, <&audma0 0x76>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi7: ssi-7 {
+					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0f>, <&audma0 0x10>,
+					       <&audma0 0x79>, <&audma0 0x7a>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi8: ssi-8 {
+					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x11>, <&audma0 0x12>,
+					       <&audma0 0x7b>, <&audma0 0x7c>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi9: ssi-9 {
+					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x13>, <&audma0 0x14>,
+					       <&audma0 0x7d>, <&audma0 0x7e>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+			};
+		};
+
+		audma0: dma-controller@ec700000 {
+			compatible = "renesas,dmac-r8a774c0",
+				     "renesas,rcar-dmac";
+			reg = <0 0xec700000 0 0x10000>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 502>;
+			clock-names = "fck";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 502>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
 		sdhi0: sd@ee100000 {
 			compatible = "renesas,sdhi-r8a774c0",
 				     "renesas,rcar-gen3-sdhi";
-- 
2.7.4

[PATCH 08/17] arm64: dts: renesas: r8a774c0: Add PWM support

[Fabrizio Castro]

Add PWM support to the RZ/G2E (a.k.a. R8A774C0) SoC specific
device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 70 +++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 35b27b8..d876520 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -758,6 +758,76 @@
 			status = "disabled";
 		};
 
+		pwm0: pwm@e6e30000 {
+			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
+			reg = <0 0xe6e30000 0 0x8>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
+		pwm1: pwm@e6e31000 {
+			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
+			reg = <0 0xe6e31000 0 0x8>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
+		pwm2: pwm@e6e32000 {
+			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
+			reg = <0 0xe6e32000 0 0x8>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
+		pwm3: pwm@e6e33000 {
+			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
+			reg = <0 0xe6e33000 0 0x8>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
+		pwm4: pwm@e6e34000 {
+			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
+			reg = <0 0xe6e34000 0 0x8>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
+		pwm5: pwm@e6e35000 {
+			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
+			reg = <0 0xe6e35000 0 0x8>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
+		pwm6: pwm@e6e36000 {
+			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
+			reg = <0 0xe6e36000 0 0x8>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
 		scif0: serial@e6e60000 {
 			compatible = "renesas,scif-r8a774c0",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.7.4

[PATCH 09/17] arm64: dts: renesas: r8a774c0: Add display output support

[Fabrizio Castro]

The RZ/G2E (a.k.a. R8A774C0) has one RGB output and two LVDS
outputs connected to DU.
This patch add support for DU, LVDS encoders, VSP and FCP.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 167 ++++++++++++++++++++++++++++++
 1 file changed, 167 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index d876520..f3c4910 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1281,6 +1281,173 @@
 			resets = <&cpg 408>;
 		};
 
+		vspb0: vsp@fe960000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe960000 0 0x8000>;
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 626>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 626>;
+			renesas,fcp = <&fcpvb0>;
+		};
+
+		fcpvb0: fcp@fe96f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe96f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 607>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 607>;
+			iommus = <&ipmmu_vp0 5>;
+		};
+
+		vspi0: vsp@fe9a0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe9a0000 0 0x8000>;
+			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 631>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 631>;
+			renesas,fcp = <&fcpvi0>;
+		};
+
+		fcpvi0: fcp@fe9af000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe9af000 0 0x200>;
+			clocks = <&cpg CPG_MOD 611>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 611>;
+			iommus = <&ipmmu_vp0 8>;
+		};
+
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x7000>;
+			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 623>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 623>;
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		fcpvd0: fcp@fea27000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea27000 0 0x200>;
+			clocks = <&cpg CPG_MOD 603>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 603>;
+			iommus = <&ipmmu_vi0 8>;
+		};
+
+		vspd1: vsp@fea28000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea28000 0 0x7000>;
+			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 622>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 622>;
+			renesas,fcp = <&fcpvd1>;
+		};
+
+		fcpvd1: fcp@fea2f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea2f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 602>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 602>;
+			iommus = <&ipmmu_vi0 9>;
+		};
+
+		du: display@feb00000 {
+			compatible = "renesas,du-r8a774c0";
+			reg = <0 0xfeb00000 0 0x80000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 724>,
+				 <&cpg CPG_MOD 723>;
+			clock-names = "du.0", "du.1";
+			vsps = <&vspd0 0 &vspd1 0>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_rgb: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					du_out_lvds0: endpoint {
+						remote-endpoint = <&lvds0_in>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					du_out_lvds1: endpoint {
+						remote-endpoint = <&lvds1_in>;
+					};
+				};
+			};
+		};
+
+		lvds0: lvds-encoder@feb90000 {
+			compatible = "renesas,r8a774c0-lvds";
+			reg = <0 0xfeb90000 0 0x20>;
+			clocks = <&cpg CPG_MOD 727>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 727>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					lvds0_in: endpoint {
+						remote-endpoint = <&du_out_lvds0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					lvds0_out: endpoint {
+					};
+				};
+			};
+		};
+
+		lvds1: lvds-encoder@feb90100 {
+			compatible = "renesas,r8a774c0-lvds";
+			reg = <0 0xfeb90100 0 0x20>;
+			clocks = <&cpg CPG_MOD 727>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 726>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					lvds1_in: endpoint {
+						remote-endpoint = <&du_out_lvds1>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					lvds1_out: endpoint {
+					};
+				};
+			};
+		};
+
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;
-- 
2.7.4

[PATCH 10/17] arm64: dts: renesas: r8a774c0: Add USB2.0 phy and host device nodes

[Fabrizio Castro]

Add USB2.0 phy and host (EHCI/OHCI) device tree nodes to the RZ/G2E
SoC dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 37 +++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index f3c4910..0ab3aa6 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1228,6 +1228,43 @@
 			dma-channels = <16>;
 		};
 
+		ohci0: usb@ee080000 {
+			compatible = "generic-ohci";
+			reg = <0 0xee080000 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 703>, <&cpg 704>;
+			status = "disabled";
+		};
+
+		ehci0: usb@ee080100 {
+			compatible = "generic-ehci";
+			reg = <0 0xee080100 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			companion = <&ohci0>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 703>, <&cpg 704>;
+			status = "disabled";
+		};
+
+		usb2_phy0: usb-phy@ee080200 {
+			compatible = "renesas,usb2-phy-r8a774c0",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee080200 0 0x700>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 703>, <&cpg 704>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		sdhi0: sd@ee100000 {
 			compatible = "renesas,sdhi-r8a774c0",
 				     "renesas,rcar-gen3-sdhi";
-- 
2.7.4

[PATCH 11/17] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes

[Fabrizio Castro]

Add usb dmac and hsusb device nodes on RZ/G2E SoC dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 0ab3aa6..79cdaac 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -514,6 +514,51 @@
 			status = "disabled";
 		};
 
+		hsusb: usb@e6590000 {
+			compatible = "renesas,usbhs-r8a774c0",
+				     "renesas,rcar-gen3-usbhs";
+			reg = <0 0xe6590000 0 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
+			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+			dma-names = "ch0", "ch1", "ch2", "ch3";
+			renesas,buswait = <11>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 704>, <&cpg 703>;
+			status = "disabled";
+		};
+
+		usb_dmac0: dma-controller@e65a0000 {
+			compatible = "renesas,r8a774c0-usb-dmac",
+				     "renesas,usb-dmac";
+			reg = <0 0xe65a0000 0 0x100>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1";
+			clocks = <&cpg CPG_MOD 330>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 330>;
+			#dma-cells = <1>;
+			dma-channels = <2>;
+		};
+
+		usb_dmac1: dma-controller@e65b0000 {
+			compatible = "renesas,r8a774c0-usb-dmac",
+				     "renesas,usb-dmac";
+			reg = <0 0xe65b0000 0 0x100>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1";
+			clocks = <&cpg CPG_MOD 331>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 331>;
+			#dma-cells = <1>;
+			dma-channels = <2>;
+		};
+
 		dmac0: dma-controller@e6700000 {
 			compatible = "renesas,dmac-r8a774c0",
 				     "renesas,rcar-dmac";
-- 
2.7.4

[PATCH 12/17] arm64: dts: renesas: r8a774c0: Add USB3.0 device nodes

[Fabrizio Castro]

Add usb3.0 host and function device nodes to the RZ/G2E SoC dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 79cdaac..6491fdd 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1273,6 +1273,28 @@
 			dma-channels = <16>;
 		};
 
+		xhci0: usb@ee000000 {
+			compatible = "renesas,xhci-r8a774c0",
+				     "renesas,rcar-gen3-xhci";
+			reg = <0 0xee000000 0 0xc00>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 328>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 328>;
+			status = "disabled";
+		};
+
+		usb3_peri0: usb@ee020000 {
+			compatible = "renesas,r8a774c0-usb3-peri",
+				     "renesas,rcar-gen3-usb3-peri";
+			reg = <0 0xee020000 0 0x400>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 328>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 328>;
+			status = "disabled";
+		};
+
 		ohci0: usb@ee080000 {
 			compatible = "generic-ohci";
 			reg = <0 0xee080000 0 0x100>;
-- 
2.7.4

[PATCH 13/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E SYS-DMAC to IPMMU

[Fabrizio Castro]

Hook up SYS-DMAC0, SYS-DMAC1, and SYS-DMAC2 to IPMMU-DS0 and
IPMMU-DS1, according to what reported by the RZ/G2 User's manual.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 6491fdd..5186a1b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -591,6 +591,14 @@
 			resets = <&cpg 219>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
+			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
 		};
 
 		dmac1: dma-controller@e7300000 {
@@ -625,6 +633,14 @@
 			resets = <&cpg 218>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
+			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
 		};
 
 		dmac2: dma-controller@e7310000 {
@@ -659,6 +675,14 @@
 			resets = <&cpg 217>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
+			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
 		};
 
 		ipmmu_ds0: mmu@e6740000 {
-- 
2.7.4

[PATCH 14/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E AVB to IPMMU

[Fabrizio Castro]

Hook up the RZ/G2E AVB device to IPMMU-DS0 as stated by the
RZ/G2 User's manual.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 5186a1b..58d4c60 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -798,6 +798,7 @@
 			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
+			iommus = <&ipmmu_ds0 16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-- 
2.7.4

[PATCH 15/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E Audio-DMAC to IPMMU

[Fabrizio Castro]

Hook up the RZ/G2E Audio-DMAC device to IPMMU-MP as stated by the
RZ/G2 User's manual.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 58d4c60..6247ebc 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1296,6 +1296,14 @@
 			resets = <&cpg 502>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
+			iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
+				 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
+				 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
+				 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
+				 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
+				 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
+				 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
+				 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
 		};
 
 		xhci0: usb@ee000000 {
-- 
2.7.4

[PATCH 16/17] arm64: dts: renesas: r8a774c0: Add PCIe device node

[Fabrizio Castro]

This patch adds PCI express channel 0 device tree node to the
RZ/G2E (a.k.a. R8A774C0) SoC dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 6247ebc..c13c182 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1418,6 +1418,33 @@
 			resets = <&cpg 408>;
 		};
 
+		pciec0: pcie@fe000000 {
+			compatible = "renesas,pcie-r8a774c0",
+				     "renesas,pcie-rcar-gen3";
+			reg = <0 0xfe000000 0 0x80000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			bus-range = <0x00 0xff>;
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 319>;
+			status = "disabled";
+		};
+
 		vspb0: vsp@fe960000 {
 			compatible = "renesas,vsp2";
 			reg = <0 0xfe960000 0 0x8000>;
-- 
2.7.4

[PATCH 17/17] arm64: dts: renesas: r8a774c0: Add VIN and CSI-2 device nodes

[Fabrizio Castro]

Add device nodes for VIN4, VIN5 and CSI40 to RZ/G2E (a.k.a. R8A774C0)
SoC specific device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 88 +++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index c13c182..3970aaf 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1057,6 +1057,62 @@
 			status = "disabled";
 		};
 
+		vin4: video@e6ef4000 {
+			compatible = "renesas,vin-r8a774c0";
+			reg = <0 0xe6ef4000 0 0x1000>;
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 807>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 807>;
+			renesas,id = <4>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin4csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint= <&csi40vin4>;
+					};
+				};
+			};
+		};
+
+		vin5: video@e6ef5000 {
+			compatible = "renesas,vin-r8a774c0";
+			reg = <0 0xe6ef5000 0 0x1000>;
+			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 806>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 806>;
+			renesas,id = <5>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					vin5csi40: endpoint@2 {
+						reg = <2>;
+						remote-endpoint= <&csi40vin5>;
+					};
+				};
+			};
+		};
+
 		rcar_sound: sound@ec500000 {
 			/*
 			 * #sound-dai-cells is required
@@ -1521,6 +1577,38 @@
 			iommus = <&ipmmu_vi0 9>;
 		};
 
+		csi40: csi2@feaa0000 {
+			compatible = "renesas,r8a774c0-csi2",
+				     "renesas,rcar-gen3-csi2";
+			reg = <0 0xfeaa0000 0 0x10000>;
+			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 716>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			resets = <&cpg 716>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					reg = <1>;
+
+					csi40vin4: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&vin4csi40>;
+					};
+					csi40vin5: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vin5csi40>;
+					};
+				};
+			};
+		};
+
 		du: display@feb00000 {
 			compatible = "renesas,du-r8a774c0";
 			reg = <0 0xfeb00000 0 0x80000>;
-- 
2.7.4

Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:25AM +0000, Fabrizio Castro wrote:
> Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS)
> devices nodes to the r8a774c0 device tree.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks Fabrizo for this patch, it looks good to me with the exception of
one minor question I have below.

> ---
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 143 ++++++++++++++++++++++++++++++
>  1 file changed, 143 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> index 96a71e3..bf08aba 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> @@ -271,6 +271,149 @@
>  			resets = <&cpg 407>;
>  		};
>  
> +		i2c0: i2c@e6500000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,i2c-r8a774c0",
> +				     "renesas,rcar-gen3-i2c";
> +			reg = <0 0xe6500000 0 0x40>;
> +			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 931>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 931>;
> +			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
> +			       <&dmac2 0x91>, <&dmac2 0x90>;
> +			dma-names = "tx", "rx", "tx", "rx";
> +			i2c-scl-internal-delay-ns = <110>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@e6508000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,i2c-r8a774c0",
> +				     "renesas,rcar-gen3-i2c";
> +			reg = <0 0xe6508000 0 0x40>;
> +			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 930>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 930>;
> +			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
> +			       <&dmac2 0x93>, <&dmac2 0x92>;
> +			dma-names = "tx", "rx", "tx", "rx";
> +			i2c-scl-internal-delay-ns = <6>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c@e6510000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,i2c-r8a774c0",
> +				     "renesas,rcar-gen3-i2c";
> +			reg = <0 0xe6510000 0 0x40>;
> +			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 929>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 929>;
> +			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
> +			       <&dmac2 0x95>, <&dmac2 0x94>;
> +			dma-names = "tx", "rx", "tx", "rx";
> +			i2c-scl-internal-delay-ns = <6>;
> +			status = "disabled";
> +		};
> +
> +		i2c3: i2c@e66d0000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,i2c-r8a774c0",
> +				     "renesas,rcar-gen3-i2c";
> +			reg = <0 0xe66d0000 0 0x40>;
> +			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 928>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 928>;
> +			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
> +			dma-names = "tx", "rx";
> +			i2c-scl-internal-delay-ns = <110>;
> +			status = "disabled";
> +		};
> +
> +		i2c4: i2c@e66d8000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,i2c-r8a774c0",
> +				     "renesas,rcar-gen3-i2c";
> +			reg = <0 0xe66d8000 0 0x40>;
> +			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 927>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 927>;
> +			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
> +			dma-names = "tx", "rx";
> +			i2c-scl-internal-delay-ns = <6>;
> +			status = "disabled";
> +		};
> +
> +		i2c5: i2c@e66e0000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,i2c-r8a774c0",
> +				     "renesas,rcar-gen3-i2c";
> +			reg = <0 0xe66e0000 0 0x40>;
> +			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 919>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 919>;
> +			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
> +			dma-names = "tx", "rx";
> +			i2c-scl-internal-delay-ns = <6>;
> +			status = "disabled";
> +		};
> +
> +		i2c6: i2c@e66e8000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,i2c-r8a774c0",
> +				     "renesas,rcar-gen3-i2c";
> +			reg = <0 0xe66e8000 0 0x40>;
> +			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 918>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 918>;
> +			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
> +			dma-names = "tx", "rx";
> +			i2c-scl-internal-delay-ns = <6>;
> +			status = "disabled";
> +		};
> +
> +		i2c7: i2c@e6690000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,i2c-r8a774c0",
> +				     "renesas,rcar-gen3-i2c";
> +			reg = <0 0xe6690000 0 0x40>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 1003>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 1003>;
> +			i2c-scl-internal-delay-ns = <6>;
> +			status = "disabled";
> +		};
> +
> +		i2c_dvfs: i2c@e60b0000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,iic-r8a774c0";
> +			reg = <0 0xe60b0000 0 0x15>;

My reading of the documentation is that 0x31 would be a more appropriate
size for the register window.

> +			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 926>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 926>;
> +			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
> +			dma-names = "tx", "rx";
> +			status = "disabled";
> +		};
> +
>  		hscif0: serial@e6540000 {
>  			compatible = "renesas,hscif-r8a774c0",
>  				     "renesas,rcar-gen3-hscif",
> -- 
> 2.7.4
> 

Re: [PATCH 01/17] arm64: dts: renesas: r8a774c0: Add SDHI nodes

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:24AM +0000, Fabrizio Castro wrote:
> Add SDHI nodes to the DT of the r8a774c0 SoC.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> ---
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 36 +++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> index 83db7c7..96a71e3 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> @@ -603,6 +603,42 @@
>  			status = "disabled";
>  		};
>  
> +		sdhi0: sd@ee100000 {
> +			compatible = "renesas,sdhi-r8a774c0",
> +				     "renesas,rcar-gen3-sdhi";
> +			reg = <0 0xee100000 0 0x2000>;
> +			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 314>;
> +			max-frequency = <200000000>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 314>;
> +			status = "disabled";
> +		};
> +
> +		sdhi1: sd@ee120000 {
> +			compatible = "renesas,sdhi-r8a774c0",
> +				     "renesas,rcar-gen3-sdhi";
> +			reg = <0 0xee120000 0 0x2000>;
> +			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 313>;
> +			max-frequency = <200000000>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 313>;
> +			status = "disabled";
> +		};
> +
> +		sdhi3: sd@ee160000 {
> +			compatible = "renesas,sdhi-r8a774c0",
> +				     "renesas,rcar-gen3-sdhi";
> +			reg = <0 0xee160000 0 0x2000>;
> +			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 311>;
> +			max-frequency = <200000000>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 311>;
> +			status = "disabled";
> +		};
> +
>  		gic: interrupt-controller@f1010000 {
>  			compatible = "arm,gic-400";
>  			#interrupt-cells = <3>;
> -- 
> 2.7.4
> 

Re: [PATCH 03/17] arm64: dts: renesas: r8a774c0: Add IPMMU device nodes

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:26AM +0000, Fabrizio Castro wrote:
> Add r8a774c0 IPMMU nodes.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 04/17] arm64: dts: renesas: r8a774c0: Add CAN nodes

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:27AM +0000, Fabrizio Castro wrote:
> Add the device nodes for both RZ/G2E CAN channels.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 05/17] arm64: dts: renesas: r8a774c0: Add thermal support

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:28AM +0000, Fabrizio Castro wrote:
> This patch adds the thermal device node and the thermal-zones
> node to the SoC specific dtsi for the RZ/G2E.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 06/17] arm64: dts: renesas: r8a774c0: Add MSIOF nodes

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:29AM +0000, Fabrizio Castro wrote:
> Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 07/17] arm64: dts: renesas: r8a774c0: Add audio support

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:30AM +0000, Fabrizio Castro wrote:
> Add sound support for the RZ/G2E SoC (a.k.a. R8A774C0).
> 
> This work is based on similar work done on the R8A77990 SoC
> by Yoshihiro Kaneko <ykaneko0929@gmail.com>.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 241 ++++++++++++++++++++++++++++++
>  1 file changed, 241 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> index 9bd66b1..35b27b8 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> @@ -917,6 +917,247 @@
>  			status = "disabled";
>  		};
>  
> +		rcar_sound: sound@ec500000 {
> +			/*
> +			 * #sound-dai-cells is required
> +			 *
> +			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
> +			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
> +			 */
> +			/*
> +			 * #clock-cells is required for audio_clkout0/1/2/3
> +			 *
> +			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
> +			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
> +			 */
> +			compatible = "renesas,rcar_sound-r8a774c0",
> +				     "renesas,rcar_sound-gen3";
> +			reg =	<0 0xec500000 0 0x1000>, /* SCU */
> +				<0 0xec5a0000 0 0x100>,  /* ADG */
> +				<0 0xec540000 0 0x1000>, /* SSIU */
> +				<0 0xec541000 0 0x280>,  /* SSI */
> +				<0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
> +			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
> +
> +			clocks = <&cpg CPG_MOD 1005>,
> +				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
> +				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
> +				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
> +				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
> +				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
> +				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
> +				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
> +				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
> +				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
> +				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
> +				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> +				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> +				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
> +				 <&audio_clk_a>, <&audio_clk_b>,
> +				 <&audio_clk_c>,
> +				 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
> +			clock-names = "ssi-all",
> +				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
> +				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
> +				      "ssi.1", "ssi.0",
> +				      "src.9", "src.8", "src.7", "src.6",
> +				      "src.5", "src.4", "src.3", "src.2",
> +				      "src.1", "src.0",
> +				      "mix.1", "mix.0",
> +				      "ctu.1", "ctu.0",
> +				      "dvc.0", "dvc.1",
> +				      "clk_a", "clk_b", "clk_c", "clk_i";
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 1005>,
> +				 <&cpg 1006>, <&cpg 1007>,
> +				 <&cpg 1008>, <&cpg 1009>,
> +				 <&cpg 1010>, <&cpg 1011>,
> +				 <&cpg 1012>, <&cpg 1013>,
> +				 <&cpg 1014>, <&cpg 1015>;
> +			reset-names = "ssi-all",
> +				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
> +				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
> +				      "ssi.1", "ssi.0";
> +			status = "disabled";
> +
> +			rcar_sound,dvc {
> +				dvc0: dvc-0 {
> +					dmas = <&audma0 0xbc>;
> +					dma-names = "tx";
> +				};
> +				dvc1: dvc-1 {
> +					dmas = <&audma0 0xbe>;
> +					dma-names = "tx";
> +				};
> +			};
> +
> +			rcar_sound,mix {
> +				mix0: mix-0 { };
> +				mix1: mix-1 { };
> +			};
> +
> +			rcar_sound,ctu {
> +				ctu00: ctu-0 { };
> +				ctu01: ctu-1 { };
> +				ctu02: ctu-2 { };
> +				ctu03: ctu-3 { };
> +				ctu10: ctu-4 { };
> +				ctu11: ctu-5 { };
> +				ctu12: ctu-6 { };
> +				ctu13: ctu-7 { };
> +			};
> +
> +			rcar_sound,src {
> +				src0: src-0 {
> +					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x85>, <&audma0 0x9a>;
> +					dma-names = "rx", "tx";
> +				};

I am a little confused here as the table i48.4 of User's Manual: Hardware
v0.61 lists DMAR 0x85 and 0x9a as being unavailable on RZ/G2E. Likewise for
other DMARs used below. And likewise for the R-Car E3 but in that case the
documentation is corrected by an Errata dated 24th Aug 2018.  Is it safe to
assume that the RZ/G2E documentation is in error in this regards? 

Other than the above this patch looks good to me.

> +				src1: src-1 {
> +					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x87>, <&audma0 0x9c>;
> +					dma-names = "rx", "tx";
> +				};
> +				src2: src-2 {
> +					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x89>, <&audma0 0x9e>;
> +					dma-names = "rx", "tx";
> +				};
> +				src3: src-3 {
> +					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x8b>, <&audma0 0xa0>;
> +					dma-names = "rx", "tx";
> +				};
> +				src4: src-4 {
> +					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x8d>, <&audma0 0xb0>;
> +					dma-names = "rx", "tx";
> +				};
> +				src5: src-5 {
> +					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x8f>, <&audma0 0xb2>;
> +					dma-names = "rx", "tx";
> +				};
> +				src6: src-6 {
> +					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x91>, <&audma0 0xb4>;
> +					dma-names = "rx", "tx";
> +				};
> +				src7: src-7 {
> +					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x93>, <&audma0 0xb6>;
> +					dma-names = "rx", "tx";
> +				};
> +				src8: src-8 {
> +					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x95>, <&audma0 0xb8>;
> +					dma-names = "rx", "tx";
> +				};
> +				src9: src-9 {
> +					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x97>, <&audma0 0xba>;
> +					dma-names = "rx", "tx";
> +				};
> +			};
> +
> +			rcar_sound,ssi {
> +				ssi0: ssi-0 {
> +					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x01>, <&audma0 0x02>,
> +					       <&audma0 0x15>, <&audma0 0x16>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi1: ssi-1 {
> +					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x03>, <&audma0 0x04>,
> +					       <&audma0 0x49>, <&audma0 0x4a>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi2: ssi-2 {
> +					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x05>, <&audma0 0x06>,
> +					       <&audma0 0x63>, <&audma0 0x64>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi3: ssi-3 {
> +					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x07>, <&audma0 0x08>,
> +					       <&audma0 0x6f>, <&audma0 0x70>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi4: ssi-4 {
> +					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x09>, <&audma0 0x0a>,
> +					       <&audma0 0x71>, <&audma0 0x72>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi5: ssi-5 {
> +					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x0b>, <&audma0 0x0c>,
> +					       <&audma0 0x73>, <&audma0 0x74>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi6: ssi-6 {
> +					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x0d>, <&audma0 0x0e>,
> +					       <&audma0 0x75>, <&audma0 0x76>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi7: ssi-7 {
> +					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x0f>, <&audma0 0x10>,
> +					       <&audma0 0x79>, <&audma0 0x7a>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi8: ssi-8 {
> +					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x11>, <&audma0 0x12>,
> +					       <&audma0 0x7b>, <&audma0 0x7c>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +				ssi9: ssi-9 {
> +					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> +					dmas = <&audma0 0x13>, <&audma0 0x14>,
> +					       <&audma0 0x7d>, <&audma0 0x7e>;
> +					dma-names = "rx", "tx", "rxu", "txu";
> +				};
> +			};
> +		};
> +
> +		audma0: dma-controller@ec700000 {
> +			compatible = "renesas,dmac-r8a774c0",
> +				     "renesas,rcar-dmac";
> +			reg = <0 0xec700000 0 0x10000>;
> +			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "error",
> +					"ch0", "ch1", "ch2", "ch3",
> +					"ch4", "ch5", "ch6", "ch7",
> +					"ch8", "ch9", "ch10", "ch11",
> +					"ch12", "ch13", "ch14", "ch15";
> +			clocks = <&cpg CPG_MOD 502>;
> +			clock-names = "fck";
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 502>;
> +			#dma-cells = <1>;
> +			dma-channels = <16>;
> +		};
> +
>  		sdhi0: sd@ee100000 {
>  			compatible = "renesas,sdhi-r8a774c0",
>  				     "renesas,rcar-gen3-sdhi";
> -- 
> 2.7.4
> 

Re: [PATCH 08/17] arm64: dts: renesas: r8a774c0: Add PWM support

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:31AM +0000, Fabrizio Castro wrote:
> Add PWM support to the RZ/G2E (a.k.a. R8A774C0) SoC specific
> device tree.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 09/17] arm64: dts: renesas: r8a774c0: Add display output support

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:32AM +0000, Fabrizio Castro wrote:
> The RZ/G2E (a.k.a. R8A774C0) has one RGB output and two LVDS
> outputs connected to DU.
> This patch add support for DU, LVDS encoders, VSP and FCP.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 10/17] arm64: dts: renesas: r8a774c0: Add USB2.0 phy and host device nodes

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:33AM +0000, Fabrizio Castro wrote:
> Add USB2.0 phy and host (EHCI/OHCI) device tree nodes to the RZ/G2E
> SoC dtsi.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 11/17] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:34AM +0000, Fabrizio Castro wrote:
> Add usb dmac and hsusb device nodes on RZ/G2E SoC dtsi.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 45 +++++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> index 0ab3aa6..79cdaac 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> @@ -514,6 +514,51 @@
>  			status = "disabled";
>  		};
>  
> +		hsusb: usb@e6590000 {
> +			compatible = "renesas,usbhs-r8a774c0",
> +				     "renesas,rcar-gen3-usbhs";
> +			reg = <0 0xe6590000 0 0x200>;

The above looks good but while reviewing this patch I noticed
that the size of the hsusb register range on in the DT for r8a774a1
is 0x100, Is that correct?

As for this patch, it looks good to me but I will wait to see if there are
other reviews before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> +			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
> +			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
> +			       <&usb_dmac1 0>, <&usb_dmac1 1>;
> +			dma-names = "ch0", "ch1", "ch2", "ch3";
> +			renesas,buswait = <11>;
> +			phys = <&usb2_phy0>;
> +			phy-names = "usb";
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 704>, <&cpg 703>;
> +			status = "disabled";
> +		};
> +
> +		usb_dmac0: dma-controller@e65a0000 {
> +			compatible = "renesas,r8a774c0-usb-dmac",
> +				     "renesas,usb-dmac";
> +			reg = <0 0xe65a0000 0 0x100>;
> +			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "ch0", "ch1";
> +			clocks = <&cpg CPG_MOD 330>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 330>;
> +			#dma-cells = <1>;
> +			dma-channels = <2>;
> +		};
> +
> +		usb_dmac1: dma-controller@e65b0000 {
> +			compatible = "renesas,r8a774c0-usb-dmac",
> +				     "renesas,usb-dmac";
> +			reg = <0 0xe65b0000 0 0x100>;
> +			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
> +				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "ch0", "ch1";
> +			clocks = <&cpg CPG_MOD 331>;
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 331>;
> +			#dma-cells = <1>;
> +			dma-channels = <2>;
> +		};
> +
>  		dmac0: dma-controller@e6700000 {
>  			compatible = "renesas,dmac-r8a774c0",
>  				     "renesas,rcar-dmac";
> -- 
> 2.7.4
> 

Re: [PATCH 12/17] arm64: dts: renesas: r8a774c0: Add USB3.0 device nodes

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:35AM +0000, Fabrizio Castro wrote:
> Add usb3.0 host and function device nodes to the RZ/G2E SoC dtsi.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 13/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E SYS-DMAC to IPMMU

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:36AM +0000, Fabrizio Castro wrote:
> Hook up SYS-DMAC0, SYS-DMAC1, and SYS-DMAC2 to IPMMU-DS0 and
> IPMMU-DS1, according to what reported by the RZ/G2 User's manual.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 14/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E AVB to IPMMU

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:37AM +0000, Fabrizio Castro wrote:
> Hook up the RZ/G2E AVB device to IPMMU-DS0 as stated by the
> RZ/G2 User's manual.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 15/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E Audio-DMAC to IPMMU

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:38AM +0000, Fabrizio Castro wrote:
> Hook up the RZ/G2E Audio-DMAC device to IPMMU-MP as stated by the
> RZ/G2 User's manual.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 16/17] arm64: dts: renesas: r8a774c0: Add PCIe device node

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:39AM +0000, Fabrizio Castro wrote:
> This patch adds PCI express channel 0 device tree node to the
> RZ/G2E (a.k.a. R8A774C0) SoC dtsi.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks,

This looks fine to me but I will wait to see if there are other reviews
before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 17/17] arm64: dts: renesas: r8a774c0: Add VIN and CSI-2 device nodes

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:40AM +0000, Fabrizio Castro wrote:
> Add device nodes for VIN4, VIN5 and CSI40 to RZ/G2E (a.k.a. R8A774C0)
> SoC specific device tree.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

RE: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support

[Fabrizio Castro]

Hello Simon,

> From: Simon Horman <horms@verge.net.au>
> Sent: 16 December 2018 20:18
> Subject: Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support
>
> On Fri, Dec 14, 2018 at 09:37:25AM +0000, Fabrizio Castro wrote:
> > Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS)
> > devices nodes to the r8a774c0 device tree.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Thanks Fabrizo for this patch, it looks good to me with the exception of
> one minor question I have below.
>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 143 ++++++++++++++++++++++++++++++
> >  1 file changed, 143 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > index 96a71e3..bf08aba 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > @@ -271,6 +271,149 @@
> >  resets = <&cpg 407>;
> >  };
> >
> > +i2c0: i2c@e6500000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,i2c-r8a774c0",
> > +     "renesas,rcar-gen3-i2c";
> > +reg = <0 0xe6500000 0 0x40>;
> > +interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 931>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 931>;
> > +dmas = <&dmac1 0x91>, <&dmac1 0x90>,
> > +       <&dmac2 0x91>, <&dmac2 0x90>;
> > +dma-names = "tx", "rx", "tx", "rx";
> > +i2c-scl-internal-delay-ns = <110>;
> > +status = "disabled";
> > +};
> > +
> > +i2c1: i2c@e6508000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,i2c-r8a774c0",
> > +     "renesas,rcar-gen3-i2c";
> > +reg = <0 0xe6508000 0 0x40>;
> > +interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 930>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 930>;
> > +dmas = <&dmac1 0x93>, <&dmac1 0x92>,
> > +       <&dmac2 0x93>, <&dmac2 0x92>;
> > +dma-names = "tx", "rx", "tx", "rx";
> > +i2c-scl-internal-delay-ns = <6>;
> > +status = "disabled";
> > +};
> > +
> > +i2c2: i2c@e6510000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,i2c-r8a774c0",
> > +     "renesas,rcar-gen3-i2c";
> > +reg = <0 0xe6510000 0 0x40>;
> > +interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 929>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 929>;
> > +dmas = <&dmac1 0x95>, <&dmac1 0x94>,
> > +       <&dmac2 0x95>, <&dmac2 0x94>;
> > +dma-names = "tx", "rx", "tx", "rx";
> > +i2c-scl-internal-delay-ns = <6>;
> > +status = "disabled";
> > +};
> > +
> > +i2c3: i2c@e66d0000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,i2c-r8a774c0",
> > +     "renesas,rcar-gen3-i2c";
> > +reg = <0 0xe66d0000 0 0x40>;
> > +interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 928>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 928>;
> > +dmas = <&dmac0 0x97>, <&dmac0 0x96>;
> > +dma-names = "tx", "rx";
> > +i2c-scl-internal-delay-ns = <110>;
> > +status = "disabled";
> > +};
> > +
> > +i2c4: i2c@e66d8000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,i2c-r8a774c0",
> > +     "renesas,rcar-gen3-i2c";
> > +reg = <0 0xe66d8000 0 0x40>;
> > +interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 927>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 927>;
> > +dmas = <&dmac0 0x99>, <&dmac0 0x98>;
> > +dma-names = "tx", "rx";
> > +i2c-scl-internal-delay-ns = <6>;
> > +status = "disabled";
> > +};
> > +
> > +i2c5: i2c@e66e0000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,i2c-r8a774c0",
> > +     "renesas,rcar-gen3-i2c";
> > +reg = <0 0xe66e0000 0 0x40>;
> > +interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 919>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 919>;
> > +dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
> > +dma-names = "tx", "rx";
> > +i2c-scl-internal-delay-ns = <6>;
> > +status = "disabled";
> > +};
> > +
> > +i2c6: i2c@e66e8000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,i2c-r8a774c0",
> > +     "renesas,rcar-gen3-i2c";
> > +reg = <0 0xe66e8000 0 0x40>;
> > +interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 918>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 918>;
> > +dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
> > +dma-names = "tx", "rx";
> > +i2c-scl-internal-delay-ns = <6>;
> > +status = "disabled";
> > +};
> > +
> > +i2c7: i2c@e6690000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,i2c-r8a774c0",
> > +     "renesas,rcar-gen3-i2c";
> > +reg = <0 0xe6690000 0 0x40>;
> > +interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 1003>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 1003>;
> > +i2c-scl-internal-delay-ns = <6>;
> > +status = "disabled";
> > +};
> > +
> > +i2c_dvfs: i2c@e60b0000 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +compatible = "renesas,iic-r8a774c0";
> > +reg = <0 0xe60b0000 0 0x15>;
>
> My reading of the documentation is that 0x31 would be a more appropriate
> size for the register window.

Thank you for looking into this. RZ/G2 documentation about this seems a bit incomplete
at the moment, and we weren't too sure about what to do here. Our expectation is
that the IP should be the same as the one found in R-Car E3, and we thought they
finally wanted to document some previously undocumented registers with the RZ/G2
User's manual. We are waiting for some answers from Japan, and since the driver
doesn't support the "new" registers we thought there was no harm in using the same
memory region used for R-Car E3. I can see the following options:
* use 0x31 as you recommended
* keep 0x15 and change it later on to the right figure once the driver actually supports all
of the documented registers (and maybe updated r8a77990.dtsi as well in case the IP is the
same?)
* drop i2c_dvfs from this patch, and send it with a new patch once we get some answers
from Japan

What's best option?

Thanks,
Fab

>
> > +interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 926>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 926>;
> > +dmas = <&dmac0 0x11>, <&dmac0 0x10>;
> > +dma-names = "tx", "rx";
> > +status = "disabled";
> > +};
> > +
> >  hscif0: serial@e6540000 {
> >  compatible = "renesas,hscif-r8a774c0",
> >       "renesas,rcar-gen3-hscif",
> > --
> > 2.7.4
> >


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RE: [PATCH 07/17] arm64: dts: renesas: r8a774c0: Add audio support

[Fabrizio Castro]

Hello Simon,

Thank you for your feedback!

> From: Simon Horman <horms@verge.net.au>
> Sent: 17 December 2018 10:22
> To: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 07/17] arm64: dts: renesas: r8a774c0: Add audio support
>
> On Fri, Dec 14, 2018 at 09:37:30AM +0000, Fabrizio Castro wrote:
> > Add sound support for the RZ/G2E SoC (a.k.a. R8A774C0).
> >
> > This work is based on similar work done on the R8A77990 SoC
> > by Yoshihiro Kaneko <ykaneko0929@gmail.com>.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 241 ++++++++++++++++++++++++++++++
> >  1 file changed, 241 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > index 9bd66b1..35b27b8 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > @@ -917,6 +917,247 @@
> >  status = "disabled";
> >  };
> >
> > +rcar_sound: sound@ec500000 {
> > +/*
> > + * #sound-dai-cells is required
> > + *
> > + * Single DAI : #sound-dai-cells = <0>;<&rcar_sound>;
> > + * Multi  DAI : #sound-dai-cells = <1>;<&rcar_sound N>;
> > + */
> > +/*
> > + * #clock-cells is required for audio_clkout0/1/2/3
> > + *
> > + * clkout: #clock-cells = <0>;<&rcar_sound>;
> > + * clkout0/1/2/3: #clock-cells = <1>;<&rcar_sound N>;
> > + */
> > +compatible = "renesas,rcar_sound-r8a774c0",
> > +     "renesas,rcar_sound-gen3";
> > +reg =<0 0xec500000 0 0x1000>, /* SCU */
> > +<0 0xec5a0000 0 0x100>,  /* ADG */
> > +<0 0xec540000 0 0x1000>, /* SSIU */
> > +<0 0xec541000 0 0x280>,  /* SSI */
> > +<0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
> > +reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
> > +
> > +clocks = <&cpg CPG_MOD 1005>,
> > + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
> > + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
> > + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
> > + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
> > + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
> > + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
> > + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
> > + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
> > + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
> > + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
> > + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> > + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> > + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
> > + <&audio_clk_a>, <&audio_clk_b>,
> > + <&audio_clk_c>,
> > + <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
> > +clock-names = "ssi-all",
> > +      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
> > +      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
> > +      "ssi.1", "ssi.0",
> > +      "src.9", "src.8", "src.7", "src.6",
> > +      "src.5", "src.4", "src.3", "src.2",
> > +      "src.1", "src.0",
> > +      "mix.1", "mix.0",
> > +      "ctu.1", "ctu.0",
> > +      "dvc.0", "dvc.1",
> > +      "clk_a", "clk_b", "clk_c", "clk_i";
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 1005>,
> > + <&cpg 1006>, <&cpg 1007>,
> > + <&cpg 1008>, <&cpg 1009>,
> > + <&cpg 1010>, <&cpg 1011>,
> > + <&cpg 1012>, <&cpg 1013>,
> > + <&cpg 1014>, <&cpg 1015>;
> > +reset-names = "ssi-all",
> > +      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
> > +      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
> > +      "ssi.1", "ssi.0";
> > +status = "disabled";
> > +
> > +rcar_sound,dvc {
> > +dvc0: dvc-0 {
> > +dmas = <&audma0 0xbc>;
> > +dma-names = "tx";
> > +};
> > +dvc1: dvc-1 {
> > +dmas = <&audma0 0xbe>;
> > +dma-names = "tx";
> > +};
> > +};
> > +
> > +rcar_sound,mix {
> > +mix0: mix-0 { };
> > +mix1: mix-1 { };
> > +};
> > +
> > +rcar_sound,ctu {
> > +ctu00: ctu-0 { };
> > +ctu01: ctu-1 { };
> > +ctu02: ctu-2 { };
> > +ctu03: ctu-3 { };
> > +ctu10: ctu-4 { };
> > +ctu11: ctu-5 { };
> > +ctu12: ctu-6 { };
> > +ctu13: ctu-7 { };
> > +};
> > +
> > +rcar_sound,src {
> > +src0: src-0 {
> > +interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x85>, <&audma0 0x9a>;
> > +dma-names = "rx", "tx";
> > +};
>
> I am a little confused here as the table i48.4 of User's Manual: Hardware
> v0.61 lists DMAR 0x85 and 0x9a as being unavailable on RZ/G2E. Likewise for
> other DMARs used below. And likewise for the R-Car E3 but in that case the
> documentation is corrected by an Errata dated 24th Aug 2018.  Is it safe to
> assume that the RZ/G2E documentation is in error in this regards?

Yeah, the current version of chapter 48 was based on top of R-Car Gen 3 manual, version 1.00.
The new version will be based on version 1.50 of the R-Car Gen3 manual, and therefore they
should rectify this.

Thanks,
Fab

>
> Other than the above this patch looks good to me.
>
> > +src1: src-1 {
> > +interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x87>, <&audma0 0x9c>;
> > +dma-names = "rx", "tx";
> > +};
> > +src2: src-2 {
> > +interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x89>, <&audma0 0x9e>;
> > +dma-names = "rx", "tx";
> > +};
> > +src3: src-3 {
> > +interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x8b>, <&audma0 0xa0>;
> > +dma-names = "rx", "tx";
> > +};
> > +src4: src-4 {
> > +interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x8d>, <&audma0 0xb0>;
> > +dma-names = "rx", "tx";
> > +};
> > +src5: src-5 {
> > +interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x8f>, <&audma0 0xb2>;
> > +dma-names = "rx", "tx";
> > +};
> > +src6: src-6 {
> > +interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x91>, <&audma0 0xb4>;
> > +dma-names = "rx", "tx";
> > +};
> > +src7: src-7 {
> > +interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x93>, <&audma0 0xb6>;
> > +dma-names = "rx", "tx";
> > +};
> > +src8: src-8 {
> > +interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x95>, <&audma0 0xb8>;
> > +dma-names = "rx", "tx";
> > +};
> > +src9: src-9 {
> > +interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x97>, <&audma0 0xba>;
> > +dma-names = "rx", "tx";
> > +};
> > +};
> > +
> > +rcar_sound,ssi {
> > +ssi0: ssi-0 {
> > +interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x01>, <&audma0 0x02>,
> > +       <&audma0 0x15>, <&audma0 0x16>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi1: ssi-1 {
> > +interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x03>, <&audma0 0x04>,
> > +       <&audma0 0x49>, <&audma0 0x4a>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi2: ssi-2 {
> > +interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x05>, <&audma0 0x06>,
> > +       <&audma0 0x63>, <&audma0 0x64>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi3: ssi-3 {
> > +interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x07>, <&audma0 0x08>,
> > +       <&audma0 0x6f>, <&audma0 0x70>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi4: ssi-4 {
> > +interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x09>, <&audma0 0x0a>,
> > +       <&audma0 0x71>, <&audma0 0x72>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi5: ssi-5 {
> > +interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x0b>, <&audma0 0x0c>,
> > +       <&audma0 0x73>, <&audma0 0x74>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi6: ssi-6 {
> > +interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x0d>, <&audma0 0x0e>,
> > +       <&audma0 0x75>, <&audma0 0x76>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi7: ssi-7 {
> > +interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x0f>, <&audma0 0x10>,
> > +       <&audma0 0x79>, <&audma0 0x7a>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi8: ssi-8 {
> > +interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x11>, <&audma0 0x12>,
> > +       <&audma0 0x7b>, <&audma0 0x7c>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +ssi9: ssi-9 {
> > +interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> > +dmas = <&audma0 0x13>, <&audma0 0x14>,
> > +       <&audma0 0x7d>, <&audma0 0x7e>;
> > +dma-names = "rx", "tx", "rxu", "txu";
> > +};
> > +};
> > +};
> > +
> > +audma0: dma-controller@ec700000 {
> > +compatible = "renesas,dmac-r8a774c0",
> > +     "renesas,rcar-dmac";
> > +reg = <0 0xec700000 0 0x10000>;
> > +interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
> > +interrupt-names = "error",
> > +"ch0", "ch1", "ch2", "ch3",
> > +"ch4", "ch5", "ch6", "ch7",
> > +"ch8", "ch9", "ch10", "ch11",
> > +"ch12", "ch13", "ch14", "ch15";
> > +clocks = <&cpg CPG_MOD 502>;
> > +clock-names = "fck";
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 502>;
> > +#dma-cells = <1>;
> > +dma-channels = <16>;
> > +};
> > +
> >  sdhi0: sd@ee100000 {
> >  compatible = "renesas,sdhi-r8a774c0",
> >       "renesas,rcar-gen3-sdhi";
> > --
> > 2.7.4
> >


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Re: [PATCH 07/17] arm64: dts: renesas: r8a774c0: Add audio support

[Simon Horman]

On Mon, Dec 17, 2018 at 11:38:07AM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> Thank you for your feedback!
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 17 December 2018 10:22
> > To: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Subject: Re: [PATCH 07/17] arm64: dts: renesas: r8a774c0: Add audio support
> >
> > On Fri, Dec 14, 2018 at 09:37:30AM +0000, Fabrizio Castro wrote:
> > > Add sound support for the RZ/G2E SoC (a.k.a. R8A774C0).
> > >
> > > This work is based on similar work done on the R8A77990 SoC
> > > by Yoshihiro Kaneko <ykaneko0929@gmail.com>.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > ---
> > >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 241 ++++++++++++++++++++++++++++++
> > >  1 file changed, 241 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > index 9bd66b1..35b27b8 100644
> > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > @@ -917,6 +917,247 @@
> > >  status = "disabled";
> > >  };
> > >
> > > +rcar_sound: sound@ec500000 {
> > > +/*
> > > + * #sound-dai-cells is required
> > > + *
> > > + * Single DAI : #sound-dai-cells = <0>;<&rcar_sound>;
> > > + * Multi  DAI : #sound-dai-cells = <1>;<&rcar_sound N>;
> > > + */
> > > +/*
> > > + * #clock-cells is required for audio_clkout0/1/2/3
> > > + *
> > > + * clkout: #clock-cells = <0>;<&rcar_sound>;
> > > + * clkout0/1/2/3: #clock-cells = <1>;<&rcar_sound N>;
> > > + */
> > > +compatible = "renesas,rcar_sound-r8a774c0",
> > > +     "renesas,rcar_sound-gen3";
> > > +reg =<0 0xec500000 0 0x1000>, /* SCU */
> > > +<0 0xec5a0000 0 0x100>,  /* ADG */
> > > +<0 0xec540000 0 0x1000>, /* SSIU */
> > > +<0 0xec541000 0 0x280>,  /* SSI */
> > > +<0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
> > > +reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
> > > +
> > > +clocks = <&cpg CPG_MOD 1005>,
> > > + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
> > > + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
> > > + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
> > > + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
> > > + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
> > > + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
> > > + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
> > > + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
> > > + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
> > > + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
> > > + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> > > + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
> > > + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
> > > + <&audio_clk_a>, <&audio_clk_b>,
> > > + <&audio_clk_c>,
> > > + <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
> > > +clock-names = "ssi-all",
> > > +      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
> > > +      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
> > > +      "ssi.1", "ssi.0",
> > > +      "src.9", "src.8", "src.7", "src.6",
> > > +      "src.5", "src.4", "src.3", "src.2",
> > > +      "src.1", "src.0",
> > > +      "mix.1", "mix.0",
> > > +      "ctu.1", "ctu.0",
> > > +      "dvc.0", "dvc.1",
> > > +      "clk_a", "clk_b", "clk_c", "clk_i";
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 1005>,
> > > + <&cpg 1006>, <&cpg 1007>,
> > > + <&cpg 1008>, <&cpg 1009>,
> > > + <&cpg 1010>, <&cpg 1011>,
> > > + <&cpg 1012>, <&cpg 1013>,
> > > + <&cpg 1014>, <&cpg 1015>;
> > > +reset-names = "ssi-all",
> > > +      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
> > > +      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
> > > +      "ssi.1", "ssi.0";
> > > +status = "disabled";
> > > +
> > > +rcar_sound,dvc {
> > > +dvc0: dvc-0 {
> > > +dmas = <&audma0 0xbc>;
> > > +dma-names = "tx";
> > > +};
> > > +dvc1: dvc-1 {
> > > +dmas = <&audma0 0xbe>;
> > > +dma-names = "tx";
> > > +};
> > > +};
> > > +
> > > +rcar_sound,mix {
> > > +mix0: mix-0 { };
> > > +mix1: mix-1 { };
> > > +};
> > > +
> > > +rcar_sound,ctu {
> > > +ctu00: ctu-0 { };
> > > +ctu01: ctu-1 { };
> > > +ctu02: ctu-2 { };
> > > +ctu03: ctu-3 { };
> > > +ctu10: ctu-4 { };
> > > +ctu11: ctu-5 { };
> > > +ctu12: ctu-6 { };
> > > +ctu13: ctu-7 { };
> > > +};
> > > +
> > > +rcar_sound,src {
> > > +src0: src-0 {
> > > +interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
> > > +dmas = <&audma0 0x85>, <&audma0 0x9a>;
> > > +dma-names = "rx", "tx";
> > > +};
> >
> > I am a little confused here as the table i48.4 of User's Manual: Hardware
> > v0.61 lists DMAR 0x85 and 0x9a as being unavailable on RZ/G2E. Likewise for
> > other DMARs used below. And likewise for the R-Car E3 but in that case the
> > documentation is corrected by an Errata dated 24th Aug 2018.  Is it safe to
> > assume that the RZ/G2E documentation is in error in this regards?
> 
> Yeah, the current version of chapter 48 was based on top of R-Car Gen 3 manual, version 1.00.
> The new version will be based on version 1.50 of the R-Car Gen3 manual, and therefore they
> should rectify this.

Thanks, in that case looks good to me but I will wait to see if there are
other reviews before applying.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support

[Simon Horman]

On Mon, Dec 17, 2018 at 11:24:39AM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 16 December 2018 20:18
> > Subject: Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support
> >
> > On Fri, Dec 14, 2018 at 09:37:25AM +0000, Fabrizio Castro wrote:
> > > Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS)
> > > devices nodes to the r8a774c0 device tree.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Thanks Fabrizo for this patch, it looks good to me with the exception of
> > one minor question I have below.
> >
> > > ---
> > >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 143 ++++++++++++++++++++++++++++++
> > >  1 file changed, 143 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > index 96a71e3..bf08aba 100644
> > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > @@ -271,6 +271,149 @@
> > >  resets = <&cpg 407>;
> > >  };
> > >
> > > +i2c0: i2c@e6500000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,i2c-r8a774c0",
> > > +     "renesas,rcar-gen3-i2c";
> > > +reg = <0 0xe6500000 0 0x40>;
> > > +interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 931>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 931>;
> > > +dmas = <&dmac1 0x91>, <&dmac1 0x90>,
> > > +       <&dmac2 0x91>, <&dmac2 0x90>;
> > > +dma-names = "tx", "rx", "tx", "rx";
> > > +i2c-scl-internal-delay-ns = <110>;
> > > +status = "disabled";
> > > +};
> > > +
> > > +i2c1: i2c@e6508000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,i2c-r8a774c0",
> > > +     "renesas,rcar-gen3-i2c";
> > > +reg = <0 0xe6508000 0 0x40>;
> > > +interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 930>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 930>;
> > > +dmas = <&dmac1 0x93>, <&dmac1 0x92>,
> > > +       <&dmac2 0x93>, <&dmac2 0x92>;
> > > +dma-names = "tx", "rx", "tx", "rx";
> > > +i2c-scl-internal-delay-ns = <6>;
> > > +status = "disabled";
> > > +};
> > > +
> > > +i2c2: i2c@e6510000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,i2c-r8a774c0",
> > > +     "renesas,rcar-gen3-i2c";
> > > +reg = <0 0xe6510000 0 0x40>;
> > > +interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 929>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 929>;
> > > +dmas = <&dmac1 0x95>, <&dmac1 0x94>,
> > > +       <&dmac2 0x95>, <&dmac2 0x94>;
> > > +dma-names = "tx", "rx", "tx", "rx";
> > > +i2c-scl-internal-delay-ns = <6>;
> > > +status = "disabled";
> > > +};
> > > +
> > > +i2c3: i2c@e66d0000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,i2c-r8a774c0",
> > > +     "renesas,rcar-gen3-i2c";
> > > +reg = <0 0xe66d0000 0 0x40>;
> > > +interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 928>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 928>;
> > > +dmas = <&dmac0 0x97>, <&dmac0 0x96>;
> > > +dma-names = "tx", "rx";
> > > +i2c-scl-internal-delay-ns = <110>;
> > > +status = "disabled";
> > > +};
> > > +
> > > +i2c4: i2c@e66d8000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,i2c-r8a774c0",
> > > +     "renesas,rcar-gen3-i2c";
> > > +reg = <0 0xe66d8000 0 0x40>;
> > > +interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 927>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 927>;
> > > +dmas = <&dmac0 0x99>, <&dmac0 0x98>;
> > > +dma-names = "tx", "rx";
> > > +i2c-scl-internal-delay-ns = <6>;
> > > +status = "disabled";
> > > +};
> > > +
> > > +i2c5: i2c@e66e0000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,i2c-r8a774c0",
> > > +     "renesas,rcar-gen3-i2c";
> > > +reg = <0 0xe66e0000 0 0x40>;
> > > +interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 919>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 919>;
> > > +dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
> > > +dma-names = "tx", "rx";
> > > +i2c-scl-internal-delay-ns = <6>;
> > > +status = "disabled";
> > > +};
> > > +
> > > +i2c6: i2c@e66e8000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,i2c-r8a774c0",
> > > +     "renesas,rcar-gen3-i2c";
> > > +reg = <0 0xe66e8000 0 0x40>;
> > > +interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 918>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 918>;
> > > +dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
> > > +dma-names = "tx", "rx";
> > > +i2c-scl-internal-delay-ns = <6>;
> > > +status = "disabled";
> > > +};
> > > +
> > > +i2c7: i2c@e6690000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,i2c-r8a774c0",
> > > +     "renesas,rcar-gen3-i2c";
> > > +reg = <0 0xe6690000 0 0x40>;
> > > +interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 1003>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 1003>;
> > > +i2c-scl-internal-delay-ns = <6>;
> > > +status = "disabled";
> > > +};
> > > +
> > > +i2c_dvfs: i2c@e60b0000 {
> > > +#address-cells = <1>;
> > > +#size-cells = <0>;
> > > +compatible = "renesas,iic-r8a774c0";
> > > +reg = <0 0xe60b0000 0 0x15>;
> >
> > My reading of the documentation is that 0x31 would be a more appropriate
> > size for the register window.
> 
> Thank you for looking into this. RZ/G2 documentation about this seems a bit incomplete
> at the moment, and we weren't too sure about what to do here. Our expectation is
> that the IP should be the same as the one found in R-Car E3, and we thought they
> finally wanted to document some previously undocumented registers with the RZ/G2
> User's manual. We are waiting for some answers from Japan, and since the driver
> doesn't support the "new" registers we thought there was no harm in using the same
> memory region used for R-Car E3. I can see the following options:
> * use 0x31 as you recommended
> * keep 0x15 and change it later on to the right figure once the driver actually supports all
> of the documented registers (and maybe updated r8a77990.dtsi as well in case the IP is the
> same?)
> * drop i2c_dvfs from this patch, and send it with a new patch once we get some answers
> from Japan
> 
> What's best option?

If you think 0x15 is correct then lets just use that and follow-up
with a fix if necessary.

I'm now happy with this patch but would like to give others a chance to
review it.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> Thanks,
> Fab
> 
> >
> > > +interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> > > +clocks = <&cpg CPG_MOD 926>;
> > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > +resets = <&cpg 926>;
> > > +dmas = <&dmac0 0x11>, <&dmac0 0x10>;
> > > +dma-names = "tx", "rx";
> > > +status = "disabled";
> > > +};
> > > +
> > >  hscif0: serial@e6540000 {
> > >  compatible = "renesas,hscif-r8a774c0",
> > >       "renesas,rcar-gen3-hscif",
> > > --
> > > 2.7.4
> > >
> 
> 
> [https://www2.renesas.eu/media/email/unicef.jpg]
> 
> This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
> We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.
> 
> 
> 
> Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
> 

RE: [PATCH 11/17] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes

[Fabrizio Castro]

Hello Simon,

Thank you for your feedback!

> From: Simon Horman <horms@verge.net.au>
> Sent: 17 December 2018 10:55
> To: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 11/17] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes
>
> On Fri, Dec 14, 2018 at 09:37:34AM +0000, Fabrizio Castro wrote:
> > Add usb dmac and hsusb device nodes on RZ/G2E SoC dtsi.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 45 +++++++++++++++++++++++++++++++
> >  1 file changed, 45 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > index 0ab3aa6..79cdaac 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > @@ -514,6 +514,51 @@
> >  status = "disabled";
> >  };
> >
> > +hsusb: usb@e6590000 {
> > +compatible = "renesas,usbhs-r8a774c0",
> > +     "renesas,rcar-gen3-usbhs";
> > +reg = <0 0xe6590000 0 0x200>;
>
> The above looks good but while reviewing this patch I noticed
> that the size of the hsusb register range on in the DT for r8a774a1
> is 0x100, Is that correct?

That is a good catch! No, I don't think it's correct, I'll send a patch to fix that.

Thanks,
Fab

>
> As for this patch, it looks good to me but I will wait to see if there are
> other reviews before applying.
>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
>
> > +interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
> > +dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
> > +       <&usb_dmac1 0>, <&usb_dmac1 1>;
> > +dma-names = "ch0", "ch1", "ch2", "ch3";
> > +renesas,buswait = <11>;
> > +phys = <&usb2_phy0>;
> > +phy-names = "usb";
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 704>, <&cpg 703>;
> > +status = "disabled";
> > +};
> > +
> > +usb_dmac0: dma-controller@e65a0000 {
> > +compatible = "renesas,r8a774c0-usb-dmac",
> > +     "renesas,usb-dmac";
> > +reg = <0 0xe65a0000 0 0x100>;
> > +interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > +interrupt-names = "ch0", "ch1";
> > +clocks = <&cpg CPG_MOD 330>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 330>;
> > +#dma-cells = <1>;
> > +dma-channels = <2>;
> > +};
> > +
> > +usb_dmac1: dma-controller@e65b0000 {
> > +compatible = "renesas,r8a774c0-usb-dmac",
> > +     "renesas,usb-dmac";
> > +reg = <0 0xe65b0000 0 0x100>;
> > +interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
> > +      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> > +interrupt-names = "ch0", "ch1";
> > +clocks = <&cpg CPG_MOD 331>;
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 331>;
> > +#dma-cells = <1>;
> > +dma-channels = <2>;
> > +};
> > +
> >  dmac0: dma-controller@e6700000 {
> >  compatible = "renesas,dmac-r8a774c0",
> >       "renesas,rcar-dmac";
> > --
> > 2.7.4
> >


[https://www2.renesas.eu/media/email/unicef.jpg]

This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support

[Fabrizio Castro]

Hello Simon,

Thank you for your feedback!

> From: Simon Horman <horms@verge.net.au>
> Sent: 17 December 2018 11:50
> To: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support
>
> On Mon, Dec 17, 2018 at 11:24:39AM +0000, Fabrizio Castro wrote:
> > Hello Simon,
> >
> > > From: Simon Horman <horms@verge.net.au>
> > > Sent: 16 December 2018 20:18
> > > Subject: Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support
> > >
> > > On Fri, Dec 14, 2018 at 09:37:25AM +0000, Fabrizio Castro wrote:
> > > > Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS)
> > > > devices nodes to the r8a774c0 device tree.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > Thanks Fabrizo for this patch, it looks good to me with the exception of
> > > one minor question I have below.
> > >
> > > > ---
> > > >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 143 ++++++++++++++++++++++++++++++
> > > >  1 file changed, 143 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > > index 96a71e3..bf08aba 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > > @@ -271,6 +271,149 @@
> > > >  resets = <&cpg 407>;
> > > >  };
> > > >
> > > > +i2c0: i2c@e6500000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,i2c-r8a774c0",
> > > > +     "renesas,rcar-gen3-i2c";
> > > > +reg = <0 0xe6500000 0 0x40>;
> > > > +interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 931>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 931>;
> > > > +dmas = <&dmac1 0x91>, <&dmac1 0x90>,
> > > > +       <&dmac2 0x91>, <&dmac2 0x90>;
> > > > +dma-names = "tx", "rx", "tx", "rx";
> > > > +i2c-scl-internal-delay-ns = <110>;
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > > +i2c1: i2c@e6508000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,i2c-r8a774c0",
> > > > +     "renesas,rcar-gen3-i2c";
> > > > +reg = <0 0xe6508000 0 0x40>;
> > > > +interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 930>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 930>;
> > > > +dmas = <&dmac1 0x93>, <&dmac1 0x92>,
> > > > +       <&dmac2 0x93>, <&dmac2 0x92>;
> > > > +dma-names = "tx", "rx", "tx", "rx";
> > > > +i2c-scl-internal-delay-ns = <6>;
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > > +i2c2: i2c@e6510000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,i2c-r8a774c0",
> > > > +     "renesas,rcar-gen3-i2c";
> > > > +reg = <0 0xe6510000 0 0x40>;
> > > > +interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 929>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 929>;
> > > > +dmas = <&dmac1 0x95>, <&dmac1 0x94>,
> > > > +       <&dmac2 0x95>, <&dmac2 0x94>;
> > > > +dma-names = "tx", "rx", "tx", "rx";
> > > > +i2c-scl-internal-delay-ns = <6>;
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > > +i2c3: i2c@e66d0000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,i2c-r8a774c0",
> > > > +     "renesas,rcar-gen3-i2c";
> > > > +reg = <0 0xe66d0000 0 0x40>;
> > > > +interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 928>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 928>;
> > > > +dmas = <&dmac0 0x97>, <&dmac0 0x96>;
> > > > +dma-names = "tx", "rx";
> > > > +i2c-scl-internal-delay-ns = <110>;
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > > +i2c4: i2c@e66d8000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,i2c-r8a774c0",
> > > > +     "renesas,rcar-gen3-i2c";
> > > > +reg = <0 0xe66d8000 0 0x40>;
> > > > +interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 927>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 927>;
> > > > +dmas = <&dmac0 0x99>, <&dmac0 0x98>;
> > > > +dma-names = "tx", "rx";
> > > > +i2c-scl-internal-delay-ns = <6>;
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > > +i2c5: i2c@e66e0000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,i2c-r8a774c0",
> > > > +     "renesas,rcar-gen3-i2c";
> > > > +reg = <0 0xe66e0000 0 0x40>;
> > > > +interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 919>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 919>;
> > > > +dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
> > > > +dma-names = "tx", "rx";
> > > > +i2c-scl-internal-delay-ns = <6>;
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > > +i2c6: i2c@e66e8000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,i2c-r8a774c0",
> > > > +     "renesas,rcar-gen3-i2c";
> > > > +reg = <0 0xe66e8000 0 0x40>;
> > > > +interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 918>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 918>;
> > > > +dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
> > > > +dma-names = "tx", "rx";
> > > > +i2c-scl-internal-delay-ns = <6>;
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > > +i2c7: i2c@e6690000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,i2c-r8a774c0",
> > > > +     "renesas,rcar-gen3-i2c";
> > > > +reg = <0 0xe6690000 0 0x40>;
> > > > +interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 1003>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 1003>;
> > > > +i2c-scl-internal-delay-ns = <6>;
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > > +i2c_dvfs: i2c@e60b0000 {
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +compatible = "renesas,iic-r8a774c0";
> > > > +reg = <0 0xe60b0000 0 0x15>;
> > >
> > > My reading of the documentation is that 0x31 would be a more appropriate
> > > size for the register window.
> >
> > Thank you for looking into this. RZ/G2 documentation about this seems a bit incomplete
> > at the moment, and we weren't too sure about what to do here. Our expectation is
> > that the IP should be the same as the one found in R-Car E3, and we thought they
> > finally wanted to document some previously undocumented registers with the RZ/G2
> > User's manual. We are waiting for some answers from Japan, and since the driver
> > doesn't support the "new" registers we thought there was no harm in using the same
> > memory region used for R-Car E3. I can see the following options:
> > * use 0x31 as you recommended
> > * keep 0x15 and change it later on to the right figure once the driver actually supports all
> > of the documented registers (and maybe updated r8a77990.dtsi as well in case the IP is the
> > same?)
> > * drop i2c_dvfs from this patch, and send it with a new patch once we get some answers
> > from Japan
> >
> > What's best option?
>
> If you think 0x15 is correct then lets just use that and follow-up
> with a fix if necessary.

Thank you for this.

Cheers,
Fab

>
> I'm now happy with this patch but would like to give others a chance to
> review it.
>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
>
> > Thanks,
> > Fab
> >
> > >
> > > > +interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> > > > +clocks = <&cpg CPG_MOD 926>;
> > > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > > +resets = <&cpg 926>;
> > > > +dmas = <&dmac0 0x11>, <&dmac0 0x10>;
> > > > +dma-names = "tx", "rx";
> > > > +status = "disabled";
> > > > +};
> > > > +
> > > >  hscif0: serial@e6540000 {
> > > >  compatible = "renesas,hscif-r8a774c0",
> > > >       "renesas,rcar-gen3-hscif",
> > > > --
> > > > 2.7.4
> > > >
> >
> >
> > [https://www2.renesas.eu/media/email/unicef.jpg]
> >
> > This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further
> details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
> > We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.
> >
> >
> >
> > Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England
> & Wales under Registered No. 04586709.
> >


[https://www2.renesas.eu/media/email/unicef.jpg]

This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH 11/17] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes

[Simon Horman]

On Mon, Dec 17, 2018 at 12:17:12PM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> Thank you for your feedback!
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 17 December 2018 10:55
> > To: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Subject: Re: [PATCH 11/17] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes
> >
> > On Fri, Dec 14, 2018 at 09:37:34AM +0000, Fabrizio Castro wrote:
> > > Add usb dmac and hsusb device nodes on RZ/G2E SoC dtsi.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > ---
> > >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 45 +++++++++++++++++++++++++++++++
> > >  1 file changed, 45 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > index 0ab3aa6..79cdaac 100644
> > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > @@ -514,6 +514,51 @@
> > >  status = "disabled";
> > >  };
> > >
> > > +hsusb: usb@e6590000 {
> > > +compatible = "renesas,usbhs-r8a774c0",
> > > +     "renesas,rcar-gen3-usbhs";
> > > +reg = <0 0xe6590000 0 0x200>;
> >
> > The above looks good but while reviewing this patch I noticed
> > that the size of the hsusb register range on in the DT for r8a774a1
> > is 0x100, Is that correct?
> 
> That is a good catch! No, I don't think it's correct, I'll send a patch to fix that.

Great, thanks!

Re: [PATCH 01/17] arm64: dts: renesas: r8a774c0: Add SDHI nodes

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:37 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add SDHI nodes to the DT of the r8a774c0 SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:37 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS)
> devices nodes to the r8a774c0 device tree.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

The register size for IICDVFS can be enlarged later, as the mapping
includes the full PAGE_SIZE block anyway.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 03/17] arm64: dts: renesas: r8a774c0: Add IPMMU device nodes

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:37 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add r8a774c0 IPMMU nodes.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 04/17] arm64: dts: renesas: r8a774c0: Add CAN nodes

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:37 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add the device nodes for both RZ/G2E CAN channels.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 05/17] arm64: dts: renesas: r8a774c0: Add thermal support

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> This patch adds the thermal device node and the thermal-zones
> node to the SoC specific dtsi for the RZ/G2E.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 06/17] arm64: dts: renesas: r8a774c0: Add MSIOF nodes

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 08/17] arm64: dts: renesas: r8a774c0: Add PWM support

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add PWM support to the RZ/G2E (a.k.a. R8A774C0) SoC specific
> device tree.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 10/17] arm64: dts: renesas: r8a774c0: Add USB2.0 phy and host device nodes

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add USB2.0 phy and host (EHCI/OHCI) device tree nodes to the RZ/G2E
> SoC dtsi.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 11/17] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add usb dmac and hsusb device nodes on RZ/G2E SoC dtsi.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 12/17] arm64: dts: renesas: r8a774c0: Add USB3.0 device nodes

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add usb3.0 host and function device nodes to the RZ/G2E SoC dtsi.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support

[Fabrizio Castro]

Hello Geert, hello Simon

I have just received word from Japan, apparently they are going to drop ICTR, ICRR, ICTA, ICTB, ICTC, ICTD, ICSF, and ICVCON from the RZ/G2 documentation.

Thanks,
Fab

> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 17 December 2018 16:12
> To: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Geert Uytterhoeven <geert+renesas@glider.be>; Simon Horman <horms@verge.net.au>;
> Mark Rutland <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>; Linux-Renesas <linux-renesas-
> soc@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; Chris
> Paterson <Chris.Paterson2@renesas.com>; Biju Das <biju.das@bp.renesas.com>
> Subject: Re: [PATCH 02/17] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support
>
> On Fri, Dec 14, 2018 at 10:37 AM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS)
> > devices nodes to the r8a774c0 device tree.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> The register size for IICDVFS can be enlarged later, as the mapping
> includes the full PAGE_SIZE block anyway.
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds


[https://www2.renesas.eu/media/email/unicef.jpg]

This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH 13/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E SYS-DMAC to IPMMU

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Hook up SYS-DMAC0, SYS-DMAC1, and SYS-DMAC2 to IPMMU-DS0 and
> IPMMU-DS1, according to what reported by the RZ/G2 User's manual.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 14/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E AVB to IPMMU

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Hook up the RZ/G2E AVB device to IPMMU-DS0 as stated by the
> RZ/G2 User's manual.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 15/17] arm64: dts: renesas: r8a774c0: Connect RZ/G2E Audio-DMAC to IPMMU

[Geert Uytterhoeven]

On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Hook up the RZ/G2E Audio-DMAC device to IPMMU-MP as stated by the
> RZ/G2 User's manual.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 06/17] arm64: dts: renesas: r8a774c0: Add MSIOF nodes

[Sergei Shtylyov]

Hello!

On 12/14/2018 12:37 PM, Fabrizio Castro wrote:

> Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> index 9532d29..9bd66b1 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> @@ -855,6 +855,68 @@
>  			status = "disabled";
>  		};
>  
> +		msiof0: spi@e6e90000 {
> +			compatible = "renesas,msiof-r8a774c0",
> +				     "renesas,rcar-gen3-msiof";
> +			reg = <0 0xe6e90000 0 0x0064>;

   Do we really need the leading zeros in the size cells?

> +			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 211>;
> +			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
> +			       <&dmac2 0x41>, <&dmac2 0x40>;
> +			dma-names = "tx", "rx", "tx", "rx";
> +			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> +			resets = <&cpg 211>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
[...]

   Same question for the other instances of MSIOF.

MBR, Sergei

RE: [PATCH 06/17] arm64: dts: renesas: r8a774c0: Add MSIOF nodes

[Fabrizio Castro]

Hello Sergei,

Thank you for your feedback!

> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Sent: 17 December 2018 16:27
> To: Fabrizio Castro <fabrizio.castro@bp.renesas.com>; Rob Herring <robh+dt@kernel.org>; Geert Uytterhoeven
> Subject: Re: [PATCH 06/17] arm64: dts: renesas: r8a774c0: Add MSIOF nodes
>
> Hello!
>
> On 12/14/2018 12:37 PM, Fabrizio Castro wrote:
>
> > Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++++++++++
> >  1 file changed, 62 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > index 9532d29..9bd66b1 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > @@ -855,6 +855,68 @@
> >  status = "disabled";
> >  };
> >
> > +msiof0: spi@e6e90000 {
> > +compatible = "renesas,msiof-r8a774c0",
> > +     "renesas,rcar-gen3-msiof";
> > +reg = <0 0xe6e90000 0 0x0064>;
>
>    Do we really need the leading zeros in the size cells?

We don't, I just kept it consistent with the same definitions for the other platforms.
Do you want me to send a v2 for this?

>
> > +interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 211>;
> > +dmas = <&dmac1 0x41>, <&dmac1 0x40>,
> > +       <&dmac2 0x41>, <&dmac2 0x40>;
> > +dma-names = "tx", "rx", "tx", "rx";
> > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > +resets = <&cpg 211>;
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +status = "disabled";
> > +};
> [...]
>
>    Same question for the other instances of MSIOF.

Same answer applies for the other instances.

Thanks,
Fab

>
> MBR, Sergei


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Re: [PATCH 06/17] arm64: dts: renesas: r8a774c0: Add MSIOF nodes

[Sergei Shtylyov]

On 12/17/2018 07:36 PM, Fabrizio Castro wrote:

[...]
>>> Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC.
>>>
>>> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>>> ---
>>>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++++++++++
>>>  1 file changed, 62 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
>>> index 9532d29..9bd66b1 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
>>> @@ -855,6 +855,68 @@
>>>  status = "disabled";
>>>  };
>>>
>>> +msiof0: spi@e6e90000 {
>>> +compatible = "renesas,msiof-r8a774c0",
>>> +     "renesas,rcar-gen3-msiof";
>>> +reg = <0 0xe6e90000 0 0x0064>;
>>
>>    Do we really need the leading zeros in the size cells?
> 
> We don't, I just kept it consistent with the same definitions for the other platforms.
> Do you want me to send a v2 for this?

   Ah, consistency is good. Keep it then. :-)

MBR, Sergei

Re: [PATCH 00/17] Add more support for the RZ/G2E

[Simon Horman]

On Fri, Dec 14, 2018 at 09:37:23AM +0000, Fabrizio Castro wrote:
> Dear All,
> 
> this series adds more support to the RZ/G2E (a.k.a. r8a774c0)
> SoC specific device tree on top of what added from series
> (on which this series depends on):
> https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg36692.html
> 
> Thanks,
> Fab

Thanks, applied for v4.22.