From: Hal Feng <hal.feng@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Rob Herring" <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Ben Dooks <ben.dooks@sifive.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
Linus Walleij <linus.walleij@linaro.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Hal Feng <hal.feng@starfivetech.com>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
Date: Tue, 20 Dec 2022 09:12:40 +0800 [thread overview]
Message-ID: <20221220011247.35560-1-hal.feng@starfivetech.com> (raw)
This patch series adds basic device tree support for StarFive JH7110 SoC.
This patch series depends on series [1] and [2]. You can simply get or
review the patches at the link [3].
[1]: https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/
[2]: https://lore.kernel.org/all/20221220005529.34744-1-hal.feng@starfivetech.com/
[3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
Changes since v2:
- Rebased on tag v6.1.
- Dropped patch 8 because it was merged.
Patch 1:
- Made the links into "Link:" tags. (by Conor)
- Corrected the board name to "VisionFive 2" instead of
"VisionFive V2" and added compatibles for version A and
version B of VisionFive 2. (by Emil)
Patch 4:
- Used "sifive,ccache0" compatible string to match. (by Conor)
Patch 5:
- Dropped "select SIFIVE_CCACHE" in config SOC_STARFIVE. (by Conor)
- Dropped "starfive,jh7110-ccache" compatible in
drivers/soc/sifive/sifive_ccache.c.
Patch 6:
- Removed all "clock-frequency = <0>". (by Conor)
- Sorted the nodes after their addresses. (by Emil)
- Renamed "clk_rtc" to "rtc_osc".
- Added "sifive,ccache0" compatible in the cache-controller node.
- Renamed "JH7110_SYSCLK_APB_BUS_FUNC" to "JH7110_SYSCLK_APB_BUS" and
renamed "apb_bus_func" to "apb_bus".
Renamed "JH7110_SYSCLK_IOMUX" to "JH7110_SYSCLK_IOMUX_APB".
Renamed "JH7110_SYSRST_IOMUX" to "JH7110_SYSRST_IOMUX_APB".
Renamed "JH7110_AONRST_AON_IOMUX" to "JH7110_AONRST_IOMUX".
- Removed "reg-names" in gpio nodes.
Patch 7:
- Corrected the board name to "VisionFive 2" instead of "VisionFive V2".
- Renamed jh7110-starfive-visionfive-v2.dts to
jh7110-starfive-visionfive-2.dtsi.
- Added dts for VisionFive 2 version A and version B boards.
- In the chosen node, deleted "linux,initrd-start" and "linux,initrd-end"
and changed the value of "stdout-path" to "serial0:115200n8".
- Changed the bias of uart0 "rx-pins" to
"bias-disable; /* external pull-up */".
- Renamed "clk_rtc" to "rtc_osc".
- Moved the gpio node behind the uart0 node.
v2: https://lore.kernel.org/all/20221118011714.70877-1-hal.feng@starfivetech.com/
Changes since v1:
- Rebased on tag v6.1-rc5.
- Added blank line in patch 1. (by Krzysztof)
- Rebased patch 4 and 6 on the newest code. (by Conor)
- Dropped patch 5. (by Conor)
- Removed the quirk of JH7100 in patch 6, considering this patch series
should only add support for JH7110.
- For patch 27, added Co-developed-by tag for Jianlong and me. Renamed
cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style
of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts.
Rewrote clock-controller nodes and deleted reset-controller nodes for
using auxiliary bus. Rewrote gpio nodes following generic pinctrl
bindings. Removed the redundant second reset entry of uart nodes.
- For patch 28, added Co-developed-by tag for Jianlong and me. Added a
chosen node. Removed reserved-memory node. Added fixed frequency clock
nodes for overriding the "clock-frequency" properties. Rewrote the gpio
nodes following generic pinctrl bindings.
- Dropped patch 30. (by Conor)
- Reworded the commit messages.
v1: https://lore.kernel.org/all/20220929143225.17907-1-hal.feng@linux.starfivetech.com/
Emil Renner Berthing (7):
dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
soc: sifive: ccache: Add StarFive JH7110 support
riscv: dts: starfive: Add initial StarFive JH7110 device tree
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
tree
.../sifive,plic-1.0.0.yaml | 1 +
.../bindings/riscv/sifive,ccache0.yaml | 9 +-
.../devicetree/bindings/riscv/starfive.yaml | 6 +
.../bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../jh7110-starfive-visionfive-2-va.dts | 13 +
.../jh7110-starfive-visionfive-2-vb.dts | 13 +
.../jh7110-starfive-visionfive-2.dtsi | 111 +++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 ++++++++++++++++++
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
11 files changed, 567 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
base-commit: 830b3c68c1fb1e9176028d02ef86f3cf76aa2476
prerequisite-patch-id: 4dc515731ce237184553c1606ffb3afaeb51c3d8
prerequisite-patch-id: 09c98554df52d17ba5fd604125f8cdd62cbe80d1
prerequisite-patch-id: a798370d170dc2bcc79ed86f741c21c1e6d87c78
prerequisite-patch-id: bd9fd8b5cb2376dc7a5e08e1a1fbb969cf475926
prerequisite-patch-id: c57ebb83bc43ccd2a8366ff166eb499da1e1d2cf
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: 94860423c7acc9025249d4bb36652a585bd0a797
prerequisite-patch-id: b5084253283929d9a6d0e66c350400c7c85d034d
prerequisite-patch-id: 6e369dbe9dca2785e4ea7d0b80e525e227a90a6e
prerequisite-patch-id: e08806183c152714c563f3a21c6d7b2f539c4d6e
prerequisite-patch-id: 79db8036abdc48fd36da227652ec62627a6b548b
prerequisite-patch-id: 06971b8e6bddc0e87e63bfdb0ce8bfb653bd73aa
prerequisite-patch-id: 16309a0e23811a2c55d2e56886de3e8eccc51554
prerequisite-patch-id: bf4f7ab0b6cfa90b6e49e66c7d75ed2eaaebbe78
prerequisite-patch-id: 38468d532e87867990055d3320679f18c5f52278
prerequisite-patch-id: 4710f2ac22dca0bdd9ff5d744d2c37cab3c74515
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2022-12-20 1:13 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-20 1:12 Hal Feng [this message]
2022-12-20 1:12 ` [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board Hal Feng
2022-12-20 10:05 ` Krzysztof Kozlowski
2022-12-23 2:05 ` Hal Feng
2022-12-20 20:58 ` Conor Dooley
2022-12-23 2:15 ` Hal Feng
2022-12-20 1:12 ` [PATCH v3 2/7] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2022-12-20 1:12 ` [PATCH v3 3/7] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2022-12-20 1:12 ` [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC Hal Feng
2022-12-20 20:21 ` Rob Herring
2022-12-20 1:12 ` [PATCH v3 5/7] soc: sifive: ccache: Add StarFive JH7110 support Hal Feng
2022-12-20 21:14 ` Conor Dooley
2022-12-20 1:12 ` [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2022-12-20 10:10 ` Krzysztof Kozlowski
2022-12-25 10:31 ` Hal Feng
2022-12-25 11:56 ` Krzysztof Kozlowski
2022-12-20 21:31 ` Conor Dooley
2022-12-25 14:31 ` Hal Feng
2022-12-27 20:58 ` Conor Dooley
2022-12-28 22:48 ` Conor Dooley
2022-12-29 5:25 ` Icenowy Zheng
2022-12-29 9:02 ` Conor Dooley
2023-02-01 7:53 ` Hal Feng
2023-02-01 7:31 ` Hal Feng
2023-02-01 7:21 ` Hal Feng
2023-02-01 8:21 ` Conor Dooley
2023-02-02 18:56 ` Hal Feng
2023-02-02 19:41 ` Conor Dooley
2023-02-09 11:11 ` Conor Dooley
2023-02-13 9:41 ` Hal Feng
2023-02-13 10:07 ` Conor Dooley
2023-02-14 2:37 ` Hal Feng
2023-02-15 3:07 ` Hal Feng
2023-02-15 7:42 ` Conor Dooley
2023-02-15 7:59 ` Conor Dooley
2023-01-31 2:00 ` Hal Feng
2023-01-31 6:17 ` Conor Dooley
2023-02-02 2:42 ` Hal Feng
2023-02-02 6:19 ` Conor Dooley
2022-12-20 1:12 ` [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board " Hal Feng
2022-12-20 21:26 ` Conor Dooley
2022-12-23 3:12 ` Hal Feng
2022-12-28 22:49 ` Conor Dooley
2023-01-10 17:59 ` Conor Dooley
2023-01-18 23:43 ` Conor Dooley
2023-02-14 9:53 ` Emil Renner Berthing
2023-02-15 14:03 ` Hal Feng
2023-02-16 9:27 ` Emil Renner Berthing
2023-02-16 9:50 ` Conor Dooley
2023-02-16 10:09 ` Conor Dooley
2023-02-16 10:32 ` Emil Renner Berthing
2023-02-16 12:27 ` Hal Feng
2023-02-16 13:02 ` Conor Dooley
2022-12-26 23:01 ` [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC Conor Dooley
2022-12-27 7:58 ` Krzysztof Kozlowski
2022-12-27 14:20 ` Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221220011247.35560-1-hal.feng@starfivetech.com \
--to=hal.feng@starfivetech.com \
--cc=aou@eecs.berkeley.edu \
--cc=ben.dooks@sifive.com \
--cc=conor@kernel.org \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=emil.renner.berthing@canonical.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linus.walleij@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).