Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

From: <Conor.Dooley@microchip.com>
To: <geert@linux-m68k.org>, <Conor.Dooley@microchip.com>
Cc: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<geert+renesas@glider.be>, <anup@brainfault.org>,
	<linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<prabhakar.csengg@gmail.com>, <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Date: Sat, 20 Aug 2022 08:49:11 +0000	[thread overview]
Message-ID: <47cec683-dc17-7aa2-3511-b0244020d571@microchip.com> (raw)
In-Reply-To: <CAMuHMdUGttswcSGeOdrJLeoZLmoeKhm7R82L-3wLJnagmZ4dBA@mail.gmail.com>

On 20/08/2022 09:45, Geert Uytterhoeven wrote:
> Hi Conor,
> 
> On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote:
>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
>>> Single).
>>>
>>> Below is the list of IP blocks added in the initial SoC DTSI which can be
>>> used to boot via initramfs on RZ/Five SMARC EVK:
>>> - AX45MP CPU
>>> - CPG
>>> - PINCTRL
>>> - PLIC
>>> - SCIF0
>>> - SYSC
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> v1->v2
>>> * Dropped including makefile change
>>> * Updated ndev count
>>> ---
>>>  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>>>  1 file changed, 121 insertions(+)
>>>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>>
>>> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>> new file mode 100644
>>> index 000000000000..b288d2607796
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>>> @@ -0,0 +1,121 @@
>>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +/*
>>> + * Device Tree Source for the RZ/Five SoC
>>> + *
>>> + * Copyright (C) 2022 Renesas Electronics Corp.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/clock/r9a07g043-cpg.h>
>>> +
>>> +/ {
>>> +     compatible = "renesas,r9a07g043";
>>> +     #address-cells = <2>;
>>> +     #size-cells = <2>;
>>> +
>>> +     /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
>>> +     extal_clk: extal-clk {
>>> +             compatible = "fixed-clock";
>>> +             #clock-cells = <0>;
>>> +             /* This value must be overridden by the board */
>>> +             clock-frequency = <0>;
>>
>> What's the value in having the clock-frequency here if the board .dtsi
>> overwrites it? dtbs_check will complain if someone forgets to fill it
>> IIUC & what the missing frequency means is also kinda obvious, no?
> 
> Some external clocks may be optional. Hence "dtbs_check" will complain
> if no "clock-frequency" is missing.

Right, seems reasonable enough.

> 
>>
>> That aside, by convention so far we have put things like extals or
>> reference clocks below the /cpus node. Could you do the same here too
>> please?
> 
> Really? We've been putting them at the root node for a long time,
> since the separate "clocks" grouping subnode was deprecated.
> The extal-clk is not even part of the SoC, so it should definitely
> not be under the /cpus node.

Under may have been a confusing choice of words, I meant "physically"
under it in the file. Maybe after would have been a better choice of
words? I wasn't suggesting you put it inside the CPUs node.
Does that make more sense?
Conor.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv