Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC

From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Conor.Dooley@microchip.com
Cc: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	 Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	 Anup Patel <anup@brainfault.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	 LKML <linux-kernel@vger.kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC
Date: Mon, 15 Aug 2022 20:44:53 +0100	[thread overview]
Message-ID: <CA+V-a8s=RoZmMvDqnBpYZTR2uotv6srumeoRn2=828zhAbOQZA@mail.gmail.com> (raw)
In-Reply-To: <ca555430-055c-debb-fdb4-fa7f78129780@microchip.com>

Hi Conor,

Thank you for the review.

On Mon, Aug 15, 2022 at 7:52 PM <Conor.Dooley@microchip.com> wrote:
>
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > upstream kernel to boot on RZ/Five SMARC EVK board.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * New patch
> > ---
> >  arch/riscv/configs/defconfig | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index aed332a9d4ea..de0ccf816c08 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -26,6 +26,7 @@ CONFIG_EXPERT=y
> >  # CONFIG_SYSFS_SYSCALL is not set
> >  CONFIG_PROFILING=y
> >  CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > +CONFIG_SOC_RENESAS_RZFIVE=y
> >  CONFIG_SOC_SIFIVE=y
> >  CONFIG_SOC_STARFIVE=y
> >  CONFIG_SOC_VIRT=y
> > @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y
> >  CONFIG_SERIAL_8250=y
> >  CONFIG_SERIAL_8250_CONSOLE=y
> >  CONFIG_SERIAL_OF_PLATFORM=y
> > +CONFIG_SERIAL_SH_SCI=y
>
> What's this? The patch text makes this look like an accidental
> inclusion, but I figure it is required for boot?
This enables the serial driver used by the RZ/Five SoC. SInce the
intention was to have a bootable board with default defconfig. I'll
update the commit message.

Cheers,
Prabhakar

> Thanks,
> Conor.
>
> >  CONFIG_VIRTIO_CONSOLE=y
> >  CONFIG_HW_RANDOM=y
> >  CONFIG_HW_RANDOM_VIRTIO=y
> > --
> > 2.25.1
> >
>

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