Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

["Lad, Prabhakar" <prabhakar.csengg@gmail.com>]

Hi Geert,

On Fri, Aug 19, 2022 at 9:05 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhalar,
>
> On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
>
> My first thought was:
>
>     This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi,
>      including the common r9a07g043.dtsi, shared by
>      arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi.
>
> Then I realized this is harder than it sounds, due:
>
Indeed, my initial thought after the comments from Conor was we could
share the SoC dtsi, but that would be to messey due to PLIC.

Cheers,
Prabhakar

> > +       soc: soc {
> > +               compatible = "simple-bus";
> > +               interrupt-parent = <&plic>;
>
> vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly
> due to
>
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges;
> > +
> > +               scif0: serial@1004b800 {
> > +                       compatible = "renesas,scif-r9a07g043",
> > +                                    "renesas,scif-r9a07g044";
> > +                       reg = <0 0x1004b800 0 0x400>;
> > +                       interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <414 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <415 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <413 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <416 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <416 IRQ_TYPE_LEVEL_HIGH>;
>
> vs. "interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH> ..." on
> r9a07g043u11.
> Interestingly, the actual hardware interrupt numbers are the same,
> but the GIC DT bindings abstracts the offset of 32 by using a second
> cell and GIC_SPI.  Unfortunately this cannot be handled by some CPP
> magic, as dtc does not support arithmetic operations yet.
>
> I expect this or similar issues to pop up everywhere, when more
> RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs.
>
> Ignoring this issue, which we probably can solve only later:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>
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