From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Conor Dooley <Conor.Dooley@microchip.com>
Cc: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Anup Patel <anup@brainfault.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Prabhakar Lad <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Date: Sat, 20 Aug 2022 10:45:56 +0200 [thread overview]
Message-ID: <CAMuHMdUGttswcSGeOdrJLeoZLmoeKhm7R82L-3wLJnagmZ4dBA@mail.gmail.com> (raw)
In-Reply-To: <e9b00bb5-bb78-091f-9c10-96c156690469@microchip.com>
Hi Conor,
On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote:
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * Dropped including makefile change
> > * Updated ndev count
> > ---
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> > 1 file changed, 121 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > new file mode 100644
> > index 000000000000..b288d2607796
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/clock/r9a07g043-cpg.h>
> > +
> > +/ {
> > + compatible = "renesas,r9a07g043";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
>
> What's the value in having the clock-frequency here if the board .dtsi
> overwrites it? dtbs_check will complain if someone forgets to fill it
> IIUC & what the missing frequency means is also kinda obvious, no?
Some external clocks may be optional. Hence "dtbs_check" will complain
if no "clock-frequency" is missing.
>
> That aside, by convention so far we have put things like extals or
> reference clocks below the /cpus node. Could you do the same here too
> please?
Really? We've been putting them at the root node for a long time,
since the separate "clocks" grouping subnode was deprecated.
The extal-clk is not even part of the SoC, so it should definitely
not be under the /cpus node.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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next prev parent reply other threads:[~2022-08-20 8:46 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14 ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-08-15 19:11 ` Conor.Dooley
2022-08-18 13:00 ` Geert Uytterhoeven
2022-08-18 13:00 ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-08-18 14:55 ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 19:14 ` Conor.Dooley
2022-08-15 19:40 ` Lad, Prabhakar
2022-08-15 19:42 ` Conor.Dooley
2022-08-16 7:52 ` Krzysztof Kozlowski
2022-08-18 15:00 ` Geert Uytterhoeven
2022-08-18 18:14 ` Lad, Prabhakar
2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-08-15 19:10 ` Conor.Dooley
2022-08-15 19:57 ` Lad, Prabhakar
2022-08-15 20:05 ` Conor.Dooley
2022-08-15 21:44 ` Lad, Prabhakar
2022-08-18 15:16 ` Geert Uytterhoeven
2022-08-18 18:19 ` Lad, Prabhakar
2022-08-18 18:53 ` Conor.Dooley
2022-08-19 7:35 ` Geert Uytterhoeven
2022-08-19 7:59 ` Conor.Dooley
2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-08-19 8:04 ` Geert Uytterhoeven
2022-08-19 11:42 ` Lad, Prabhakar
2022-08-19 18:40 ` Conor.Dooley
2022-08-20 8:45 ` Geert Uytterhoeven [this message]
2022-08-20 8:49 ` Conor.Dooley
2022-08-20 12:07 ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2022-08-15 19:00 ` Conor.Dooley
2022-08-15 20:16 ` Lad, Prabhakar
2022-08-19 8:25 ` Geert Uytterhoeven
2022-08-19 11:39 ` Lad, Prabhakar
2022-08-19 18:15 ` Conor.Dooley
2022-08-19 8:11 ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar
2022-08-19 8:42 ` Geert Uytterhoeven
2022-08-19 9:08 ` Lad, Prabhakar
2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 18:52 ` Conor.Dooley
2022-08-15 19:44 ` Lad, Prabhakar
2022-08-15 19:49 ` Conor.Dooley
2022-08-19 8:46 ` Geert Uytterhoeven
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