From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Conor.Dooley@microchip.com
Cc: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Anup Patel <anup@brainfault.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
Date: Mon, 15 Aug 2022 21:16:13 +0100 [thread overview]
Message-ID: <CA+V-a8uNRr+WPX=YC+UMT4ch4S5XwsatHCzUoSt+hTk4C=cheA@mail.gmail.com> (raw)
In-Reply-To: <07342070-d96c-59fc-f9dd-b65cd742d97a@microchip.com>
Hi Conor,
On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote:
>
> On 15/08/2022 16:14, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Enable the minimal blocks required for booting the Renesas RZ/Five
> > SMARC EVK with initramfs.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * New patch
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/renesas/Makefile | 2 ++
> > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++
> > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++
> > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
> > 5 files changed, 73 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
>
> Just to sort out some of my own confusion here - is the smarc EVK
> shared between your arm boards and the riscv ones? Or just the
> peripherals etc on the soc?
>
RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL
SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC
SoM and still be used.
> If it is the forver, does the approach suggested here for the
> allwinner stuff make sense to also use for risc-v stuff with
> shared parts of devicetrees?
> https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/
>
it does make sense. But I wonder where we would place the common
shared dtsi that can be used by two arch's.
> Would at least be interesting in hearing more opinions from the dt
> people, Geert & Palmer. We have some SOM based stuff too with carriers
> so I am interested in seeing how the cross platform part of that works
> out.
>
Yep, that would be interesting.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-15 20:17 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 15:14 ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-08-15 19:11 ` Conor.Dooley
2022-08-18 13:00 ` Geert Uytterhoeven
2022-08-18 13:00 ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-08-18 14:55 ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 19:14 ` Conor.Dooley
2022-08-15 19:40 ` Lad, Prabhakar
2022-08-15 19:42 ` Conor.Dooley
2022-08-16 7:52 ` Krzysztof Kozlowski
2022-08-18 15:00 ` Geert Uytterhoeven
2022-08-18 18:14 ` Lad, Prabhakar
2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-08-15 19:10 ` Conor.Dooley
2022-08-15 19:57 ` Lad, Prabhakar
2022-08-15 20:05 ` Conor.Dooley
2022-08-15 21:44 ` Lad, Prabhakar
2022-08-18 15:16 ` Geert Uytterhoeven
2022-08-18 18:19 ` Lad, Prabhakar
2022-08-18 18:53 ` Conor.Dooley
2022-08-19 7:35 ` Geert Uytterhoeven
2022-08-19 7:59 ` Conor.Dooley
2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-08-19 8:04 ` Geert Uytterhoeven
2022-08-19 11:42 ` Lad, Prabhakar
2022-08-19 18:40 ` Conor.Dooley
2022-08-20 8:45 ` Geert Uytterhoeven
2022-08-20 8:49 ` Conor.Dooley
2022-08-20 12:07 ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2022-08-15 19:00 ` Conor.Dooley
2022-08-15 20:16 ` Lad, Prabhakar [this message]
2022-08-19 8:25 ` Geert Uytterhoeven
2022-08-19 11:39 ` Lad, Prabhakar
2022-08-19 18:15 ` Conor.Dooley
2022-08-19 8:11 ` Geert Uytterhoeven
2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar
2022-08-19 8:42 ` Geert Uytterhoeven
2022-08-19 9:08 ` Lad, Prabhakar
2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar
2022-08-15 18:52 ` Conor.Dooley
2022-08-15 19:44 ` Lad, Prabhakar
2022-08-15 19:49 ` Conor.Dooley
2022-08-19 8:46 ` Geert Uytterhoeven
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CA+V-a8uNRr+WPX=YC+UMT4ch4S5XwsatHCzUoSt+hTk4C=cheA@mail.gmail.com' \
--to=prabhakar.csengg@gmail.com \
--cc=Conor.Dooley@microchip.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=biju.das.jz@bp.renesas.com \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).