* [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes @ 2023-06-21 13:43 Sumit Gupta 2023-06-21 13:43 ` [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Sumit Gupta ` (4 more replies) 0 siblings, 5 replies; 15+ messages in thread From: Sumit Gupta @ 2023-06-21 13:43 UTC (permalink / raw) To: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra Cc: bbasu, talho, sumitg This patch set adds VIC, NVDEC, NVENC, NVJPG, NVDISPLAY clients of Memory Controller to the Tegra234 MC clients table. It also improves error handling when some MRQ's are not supported by a platform. For Example: - Avoid "tegra186_emc_probe" failure if the "MRQ_EMC_DVFS_LATENCY" is not supported. - Avoid Error returned by icc_set_bw() in the MC client drivers if the "MRQ_BWMGR_INT" is not supported. Sumit Gupta (4): memory: tegra: sort tegra234_mc_clients table as per register offsets memory: tegra: Add clients used by DRM in Tegra234 memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported memory: tegra: make icc_set_bw return zero if BWMGR not supported drivers/memory/tegra/tegra186-emc.c | 136 ++++--- drivers/memory/tegra/tegra234.c | 604 +++++++++++++++++----------- 2 files changed, 435 insertions(+), 305 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets 2023-06-21 13:43 [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Sumit Gupta @ 2023-06-21 13:43 ` Sumit Gupta 2023-07-10 10:08 ` Krzysztof Kozlowski 2023-07-13 15:00 ` Thierry Reding 2023-06-21 13:43 ` [Patch RESEND 2/4] memory: tegra: Add clients used by DRM in Tegra234 Sumit Gupta ` (3 subsequent siblings) 4 siblings, 2 replies; 15+ messages in thread From: Sumit Gupta @ 2023-06-21 13:43 UTC (permalink / raw) To: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra Cc: bbasu, talho, sumitg Sort the MC client entries in "tegra234_mc_clients" table as per the override and security register offsets. This will help to avoid creating duplicate entries. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> --- drivers/memory/tegra/tegra234.c | 514 ++++++++++++++++---------------- 1 file changed, 259 insertions(+), 255 deletions(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 8e873a7bc34f..3e44efe4541e 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -12,6 +12,10 @@ #include <soc/tegra/bpmp.h> #include "mc.h" +/* + * MC Client entries are sorted in the increasing order of the + * override and security register offsets. + */ static const struct tegra_mc_client tegra234_mc_clients[] = { { .id = TEGRA234_MEMORY_CLIENT_HDAR, @@ -25,6 +29,106 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0xac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, + .name = "pcie6ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x140, + .security = 0x144, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AW, + .name = "pcie6aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x148, + .security = 0x14c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR, + .name = "pcie7ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x150, + .security = 0x154, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, + .name = "dla0rdb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x160, + .security = 0x164, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1, + .name = "dla0rdb1", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x168, + .security = 0x16c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0WRB, + .name = "dla0wrb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x170, + .security = 0x174, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDB, + .name = "dla0rdb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x178, + .security = 0x17c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AW, + .name = "pcie7aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x180, + .security = 0x184, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AR, + .name = "pcie8ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x190, + .security = 0x194, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_HDAW, .name = "hdaw", @@ -37,6 +141,102 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x1ac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AW, + .name = "pcie8aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x1d8, + .security = 0x1dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AR, + .name = "pcie9ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1e0, + .security = 0x1e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1, + .name = "pcie6ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AW, + .name = "pcie9aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1f0, + .security = 0x1f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR, + .name = "pcie10ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x1f8, + .security = 0x1fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AW, + .name = "pcie10aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x200, + .security = 0x204, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1, + .name = "pcie10ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x240, + .security = 0x244, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1, + .name = "pcie7ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x248, + .security = 0x24c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_MGBEARD, .name = "mgbeard", @@ -157,6 +357,26 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x33c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, + .name = "dla0rdb1", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x370, + .security = 0x374, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1WRB, + .name = "dla0wrb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x378, + .security = 0x37c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_VI2W, .name = "vi2w", @@ -181,18 +401,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x38c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_VI2FALW, - .name = "vi2falw", - .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, - .type = TEGRA_ICC_ISO_VIFAL, - .sid = TEGRA234_SID_ISO_VI2FALC, - .regs = { - .sid = { - .override = 0x3e0, - .security = 0x3e4, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_APER, .name = "aper", @@ -218,27 +426,27 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, }, }, { - .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, - .name = "nvdisplayr", - .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, - .type = TEGRA_ICC_ISO_DISPLAY, - .sid = TEGRA234_SID_ISO_NVDISPLAY, + .id = TEGRA234_MEMORY_CLIENT_VI2FALW, + .name = "vi2falw", + .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, + .type = TEGRA_ICC_ISO_VIFAL, + .sid = TEGRA234_SID_ISO_VI2FALC, .regs = { .sid = { - .override = 0x490, - .security = 0x494, + .override = 0x3e0, + .security = 0x3e4, }, }, }, { - .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, - .name = "nvdisplayr1", + .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, + .name = "nvdisplayr", .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, .type = TEGRA_ICC_ISO_DISPLAY, .sid = TEGRA234_SID_ISO_NVDISPLAY, .regs = { .sid = { - .override = 0x508, - .security = 0x50c, + .override = 0x490, + .security = 0x494, }, }, }, { @@ -305,6 +513,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x504, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name = "nvdisplayr1", + .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, + .type = TEGRA_ICC_ISO_DISPLAY, + .sid = TEGRA234_SID_ISO_NVDISPLAY, + .regs = { + .sid = { + .override = 0x508, + .security = 0x50c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0RDA, .name = "dla0rda", @@ -335,26 +555,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x604, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, - .name = "dla0rdb", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x160, - .security = 0x164, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1, - .name = "dla0rda1", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x748, - .security = 0x74c, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB, .name = "dla0falwrb", @@ -365,26 +565,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x60c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1, - .name = "dla0rdb1", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x168, - .security = 0x16c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0WRB, - .name = "dla0wrb", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x170, - .security = 0x174, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1RDA, .name = "dla0rda", @@ -415,26 +595,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x624, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDB, - .name = "dla0rdb", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x178, - .security = 0x17c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1, - .name = "dla0rda1", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x750, - .security = 0x754, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB, .name = "dla0falwrb", @@ -445,26 +605,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x62c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, - .name = "dla0rdb1", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x370, - .security = 0x374, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1WRB, - .name = "dla0wrb", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x378, - .security = 0x37c, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_PCIE0R, .name = "pcie0r", @@ -610,171 +750,35 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, }, }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE5R1, - .name = "pcie5r1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_5, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE5, - .regs = { - .sid = { - .override = 0x778, - .security = 0x77c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, - .name = "pcie6ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x140, - .security = 0x144, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AW, - .name = "pcie6aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x148, - .security = 0x14c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1, - .name = "pcie6ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x1e8, - .security = 0x1ec, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AR, - .name = "pcie7ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x150, - .security = 0x154, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AW, - .name = "pcie7aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x180, - .security = 0x184, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1, - .name = "pcie7ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x248, - .security = 0x24c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE8AR, - .name = "pcie8ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE8, - .regs = { - .sid = { - .override = 0x190, - .security = 0x194, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE8AW, - .name = "pcie8aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE8, - .regs = { - .sid = { - .override = 0x1d8, - .security = 0x1dc, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE9AR, - .name = "pcie9ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE9, - .regs = { - .sid = { - .override = 0x1e0, - .security = 0x1e4, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE9AW, - .name = "pcie9aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE9, - .regs = { - .sid = { - .override = 0x1f0, - .security = 0x1f4, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AR, - .name = "pcie10ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, + .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1, + .name = "dla0rda1", + .sid = TEGRA234_SID_NVDLA0, .regs = { .sid = { - .override = 0x1f8, - .security = 0x1fc, + .override = 0x748, + .security = 0x74c, }, }, }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AW, - .name = "pcie10aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, + .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1, + .name = "dla0rda1", + .sid = TEGRA234_SID_NVDLA1, .regs = { .sid = { - .override = 0x200, - .security = 0x204, + .override = 0x750, + .security = 0x754, }, }, }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1, - .name = "pcie10ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .id = TEGRA234_MEMORY_CLIENT_PCIE5R1, + .name = "pcie5r1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_5, .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, + .sid = TEGRA234_SID_PCIE5, .regs = { .sid = { - .override = 0x240, - .security = 0x244, + .override = 0x778, + .security = 0x77c, }, }, }, { -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets 2023-06-21 13:43 ` [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Sumit Gupta @ 2023-07-10 10:08 ` Krzysztof Kozlowski 2023-07-10 16:48 ` Sumit Gupta 2023-07-13 15:00 ` Thierry Reding 1 sibling, 1 reply; 15+ messages in thread From: Krzysztof Kozlowski @ 2023-07-10 10:08 UTC (permalink / raw) To: Sumit Gupta, treding, jonathanh, linux-kernel, linux-tegra; +Cc: bbasu, talho On 21/06/2023 15:43, Sumit Gupta wrote: > Sort the MC client entries in "tegra234_mc_clients" table as per the > override and security register offsets. This will help to avoid > creating duplicate entries. If person cannot search for existing symbol before adding new entry, I doubt that sorting would solve it. OTOH, this patch makes backporting changes trickier, so I don't think this is good approach. Are all other Tegra files ordered in this matter? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets 2023-07-10 10:08 ` Krzysztof Kozlowski @ 2023-07-10 16:48 ` Sumit Gupta 2023-07-12 19:40 ` Krzysztof Kozlowski 0 siblings, 1 reply; 15+ messages in thread From: Sumit Gupta @ 2023-07-10 16:48 UTC (permalink / raw) To: Krzysztof Kozlowski, treding, jonathanh, linux-kernel, linux-tegra Cc: bbasu, talho On 10/07/23 15:38, Krzysztof Kozlowski wrote: > External email: Use caution opening links or attachments > > > On 21/06/2023 15:43, Sumit Gupta wrote: >> Sort the MC client entries in "tegra234_mc_clients" table as per the >> override and security register offsets. This will help to avoid >> creating duplicate entries. > > If person cannot search for existing symbol before adding new entry, I > doubt that sorting would solve it. OTOH, this patch makes backporting > changes trickier, so I don't think this is good approach. Are all other > Tegra files ordered in this matter? > > > Best regards, > Krzysztof > They are in order for previous T194 SoC. For T234 also, initially the entries were in order. Thank you, Sumit Gupta ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets 2023-07-10 16:48 ` Sumit Gupta @ 2023-07-12 19:40 ` Krzysztof Kozlowski 0 siblings, 0 replies; 15+ messages in thread From: Krzysztof Kozlowski @ 2023-07-12 19:40 UTC (permalink / raw) To: Sumit Gupta, treding, jonathanh, linux-kernel, linux-tegra Cc: bbasu, talho, Dmitry Osipenko, Ashish Mhetre On 10/07/2023 18:48, Sumit Gupta wrote: > > > On 10/07/23 15:38, Krzysztof Kozlowski wrote: >> External email: Use caution opening links or attachments >> >> >> On 21/06/2023 15:43, Sumit Gupta wrote: >>> Sort the MC client entries in "tegra234_mc_clients" table as per the >>> override and security register offsets. This will help to avoid >>> creating duplicate entries. >> >> If person cannot search for existing symbol before adding new entry, I >> doubt that sorting would solve it. OTOH, this patch makes backporting >> changes trickier, so I don't think this is good approach. Are all other >> Tegra files ordered in this matter? >> >> >> Best regards, >> Krzysztof >> > > They are in order for previous T194 SoC. > For T234 also, initially the entries were in order. OK. This has an impact on backports, thus I would be happy to see some acks or reviews from other developers of this code, that this change actually helps them by making code more readable and maintainable. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets 2023-06-21 13:43 ` [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Sumit Gupta 2023-07-10 10:08 ` Krzysztof Kozlowski @ 2023-07-13 15:00 ` Thierry Reding 1 sibling, 0 replies; 15+ messages in thread From: Thierry Reding @ 2023-07-13 15:00 UTC (permalink / raw) To: Sumit Gupta Cc: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra, bbasu, talho [-- Attachment #1: Type: text/plain, Size: 646 bytes --] On Wed, Jun 21, 2023 at 07:13:57PM +0530, Sumit Gupta wrote: > Sort the MC client entries in "tegra234_mc_clients" table as per the > override and security register offsets. This will help to avoid > creating duplicate entries. > > Signed-off-by: Sumit Gupta <sumitg@nvidia.com> > --- > drivers/memory/tegra/tegra234.c | 514 ++++++++++++++++---------------- > 1 file changed, 259 insertions(+), 255 deletions(-) I'm not sure if there's a good way to check that these are ordered correctly, so I'll keep an eye on future patches and manually make sure that they keep the ordering. Acked-by: Thierry Reding <treding@nvidia.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Patch RESEND 2/4] memory: tegra: Add clients used by DRM in Tegra234 2023-06-21 13:43 [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Sumit Gupta 2023-06-21 13:43 ` [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Sumit Gupta @ 2023-06-21 13:43 ` Sumit Gupta 2023-07-13 15:01 ` Thierry Reding 2023-06-21 13:43 ` [Patch RESEND 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Sumit Gupta ` (2 subsequent siblings) 4 siblings, 1 reply; 15+ messages in thread From: Sumit Gupta @ 2023-06-21 13:43 UTC (permalink / raw) To: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra Cc: bbasu, talho, sumitg, Johnny Liu Add entries for VIC, NVDEC, NVENC, NVJPG memory controller clients into the 'tegra_234_mc_clients' table. Signed-off-by: Johnny Liu <johnliu@nvidia.com> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> --- drivers/memory/tegra/tegra234.c | 120 ++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 3e44efe4541e..bc73be7fe143 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -29,6 +29,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0xac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVENCSRD, + .name = "nvencsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVENC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVENC, + .regs = { + .sid = { + .override = 0xe0, + .security = 0xe4, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, .name = "pcie6ar", @@ -65,6 +77,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x154, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVENCSWR, + .name = "nvencswr", + .bpmp_id = TEGRA_ICC_BPMP_NVENC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVENC, + .regs = { + .sid = { + .override = 0x158, + .security = 0x15c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, .name = "dla0rdb", @@ -357,6 +381,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x33c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VICSRD, + .name = "vicsrd", + .bpmp_id = TEGRA_ICC_BPMP_VIC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_VIC, + .regs = { + .sid = { + .override = 0x360, + .security = 0x364, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VICSWR, + .name = "vicswr", + .bpmp_id = TEGRA_ICC_BPMP_VIC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_VIC, + .regs = { + .sid = { + .override = 0x368, + .security = 0x36c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, .name = "dla0rdb1", @@ -401,6 +449,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x38c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDECSRD, + .name = "nvdecsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVDEC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVDEC, + .regs = { + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDECSWR, + .name = "nvdecswr", + .bpmp_id = TEGRA_ICC_BPMP_NVDEC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVDEC, + .regs = { + .sid = { + .override = 0x3c8, + .security = 0x3cc, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_APER, .name = "aper", @@ -437,6 +509,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x3e4, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPGSRD, + .name = "nvjpgsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG, + .regs = { + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPGSWR, + .name = "nvjpgswr", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG, + .regs = { + .sid = { + .override = 0x3f8, + .security = 0x3fc, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, .name = "nvdisplayr", @@ -781,6 +877,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x77c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD, + .name = "nvjpg1srd", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG1, + .regs = { + .sid = { + .override = 0x918, + .security = 0x91c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR, + .name = "nvjpg1swr", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG1, + .regs = { + .sid = { + .override = 0x920, + .security = 0x924, + }, + }, }, { .id = TEGRA_ICC_MC_CPU_CLUSTER0, .name = "sw_cluster0", -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 2/4] memory: tegra: Add clients used by DRM in Tegra234 2023-06-21 13:43 ` [Patch RESEND 2/4] memory: tegra: Add clients used by DRM in Tegra234 Sumit Gupta @ 2023-07-13 15:01 ` Thierry Reding 0 siblings, 0 replies; 15+ messages in thread From: Thierry Reding @ 2023-07-13 15:01 UTC (permalink / raw) To: Sumit Gupta Cc: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra, bbasu, talho, Johnny Liu [-- Attachment #1: Type: text/plain, Size: 447 bytes --] On Wed, Jun 21, 2023 at 07:13:58PM +0530, Sumit Gupta wrote: > Add entries for VIC, NVDEC, NVENC, NVJPG memory controller > clients into the 'tegra_234_mc_clients' table. > > Signed-off-by: Johnny Liu <johnliu@nvidia.com> > Signed-off-by: Sumit Gupta <sumitg@nvidia.com> > --- > drivers/memory/tegra/tegra234.c | 120 ++++++++++++++++++++++++++++++++ > 1 file changed, 120 insertions(+) Acked-by: Thierry Reding <treding@nvidia.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Patch RESEND 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported 2023-06-21 13:43 [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Sumit Gupta 2023-06-21 13:43 ` [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Sumit Gupta 2023-06-21 13:43 ` [Patch RESEND 2/4] memory: tegra: Add clients used by DRM in Tegra234 Sumit Gupta @ 2023-06-21 13:43 ` Sumit Gupta 2023-07-13 15:02 ` Thierry Reding 2023-06-21 13:44 ` [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported Sumit Gupta 2023-07-14 4:10 ` [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Krzysztof Kozlowski 4 siblings, 1 reply; 15+ messages in thread From: Sumit Gupta @ 2023-06-21 13:43 UTC (permalink / raw) To: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra Cc: bbasu, talho, sumitg Add check to ensure that "MRQ_EMC_DVFS_LATENCY" is supported by the BPMP-FW before making the MRQ request. Currently, if the BPMP-FW doesn't support this MRQ, then the "tegra186_emc_probe" fails. Due to this the Memory Interconnect initialization also doesn't happen. Memory Interconnect is not dependent on this MRQ and can initialize even when this MRQ is not supported in any platform. The check ensures that the MRQ is called only when it is supported by the BPMP-FW and Interconnect initializes independent of this MRQ. Also, moved the code to new function for better readability. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> --- drivers/memory/tegra/tegra186-emc.c | 136 +++++++++++++++------------- 1 file changed, 71 insertions(+), 65 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 6ad8a4023dd7..83981ae3ea86 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -155,6 +155,73 @@ DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, tegra186_emc_debug_max_rate_get, tegra186_emc_debug_max_rate_set, "%llu\n"); +static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc) +{ + struct mrq_emc_dvfs_latency_response response; + struct tegra_bpmp_message msg; + unsigned int i; + int err; + + memset(&msg, 0, sizeof(msg)); + msg.mrq = MRQ_EMC_DVFS_LATENCY; + msg.tx.data = NULL; + msg.tx.size = 0; + msg.rx.data = &response; + msg.rx.size = sizeof(response); + + err = tegra_bpmp_transfer(emc->bpmp, &msg); + if (err < 0) { + dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err); + return err; + } + if (msg.rx.ret < 0) { + dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret); + return -EINVAL; + } + + emc->debugfs.min_rate = ULONG_MAX; + emc->debugfs.max_rate = 0; + + emc->num_dvfs = response.num_pairs; + + emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL); + if (!emc->dvfs) + return -ENOMEM; + + dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs); + + for (i = 0; i < emc->num_dvfs; i++) { + emc->dvfs[i].rate = response.pairs[i].freq * 1000; + emc->dvfs[i].latency = response.pairs[i].latency; + + if (emc->dvfs[i].rate < emc->debugfs.min_rate) + emc->debugfs.min_rate = emc->dvfs[i].rate; + + if (emc->dvfs[i].rate > emc->debugfs.max_rate) + emc->debugfs.max_rate = emc->dvfs[i].rate; + + dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i, + emc->dvfs[i].rate, emc->dvfs[i].latency); + } + + err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate); + if (err < 0) { + dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n", + emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk); + return err; + } + + emc->debugfs.root = debugfs_create_dir("emc", NULL); + debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, + emc, &tegra186_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_max_rate_fops); + + return 0; +} + /* * tegra_emc_icc_set_bw() - Set BW api for EMC provider * @src: ICC node for External Memory Controller (EMC) @@ -251,10 +318,7 @@ static int tegra_emc_interconnect_init(struct tegra186_emc *emc) static int tegra186_emc_probe(struct platform_device *pdev) { struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); - struct mrq_emc_dvfs_latency_response response; - struct tegra_bpmp_message msg; struct tegra186_emc *emc; - unsigned int i; int err; emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); @@ -275,70 +339,12 @@ static int tegra186_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); emc->dev = &pdev->dev; - memset(&msg, 0, sizeof(msg)); - msg.mrq = MRQ_EMC_DVFS_LATENCY; - msg.tx.data = NULL; - msg.tx.size = 0; - msg.rx.data = &response; - msg.rx.size = sizeof(response); - - err = tegra_bpmp_transfer(emc->bpmp, &msg); - if (err < 0) { - dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err); - goto put_bpmp; - } - if (msg.rx.ret < 0) { - err = -EINVAL; - dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret); - goto put_bpmp; - } - - emc->debugfs.min_rate = ULONG_MAX; - emc->debugfs.max_rate = 0; - - emc->num_dvfs = response.num_pairs; - - emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs, - sizeof(*emc->dvfs), GFP_KERNEL); - if (!emc->dvfs) { - err = -ENOMEM; - goto put_bpmp; - } - - dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs); - - for (i = 0; i < emc->num_dvfs; i++) { - emc->dvfs[i].rate = response.pairs[i].freq * 1000; - emc->dvfs[i].latency = response.pairs[i].latency; - - if (emc->dvfs[i].rate < emc->debugfs.min_rate) - emc->debugfs.min_rate = emc->dvfs[i].rate; - - if (emc->dvfs[i].rate > emc->debugfs.max_rate) - emc->debugfs.max_rate = emc->dvfs[i].rate; - - dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i, - emc->dvfs[i].rate, emc->dvfs[i].latency); - } - - err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, - emc->debugfs.max_rate); - if (err < 0) { - dev_err(&pdev->dev, - "failed to set rate range [%lu-%lu] for %pC\n", - emc->debugfs.min_rate, emc->debugfs.max_rate, - emc->clk); - goto put_bpmp; + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) { + err = tegra186_emc_get_emc_dvfs_latency(emc); + if (err) + goto put_bpmp; } - emc->debugfs.root = debugfs_create_dir("emc", NULL); - debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, - emc, &tegra186_emc_debug_available_rates_fops); - debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_min_rate_fops); - debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_max_rate_fops); - if (mc && mc->soc->icc_ops) { if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { mc->bwmgr_mrq_supported = true; -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported 2023-06-21 13:43 ` [Patch RESEND 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Sumit Gupta @ 2023-07-13 15:02 ` Thierry Reding 0 siblings, 0 replies; 15+ messages in thread From: Thierry Reding @ 2023-07-13 15:02 UTC (permalink / raw) To: Sumit Gupta Cc: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra, bbasu, talho [-- Attachment #1: Type: text/plain, Size: 914 bytes --] On Wed, Jun 21, 2023 at 07:13:59PM +0530, Sumit Gupta wrote: > Add check to ensure that "MRQ_EMC_DVFS_LATENCY" is supported by the > BPMP-FW before making the MRQ request. Currently, if the BPMP-FW > doesn't support this MRQ, then the "tegra186_emc_probe" fails. > Due to this the Memory Interconnect initialization also doesn't > happen. Memory Interconnect is not dependent on this MRQ and can > initialize even when this MRQ is not supported in any platform. > The check ensures that the MRQ is called only when it is supported > by the BPMP-FW and Interconnect initializes independent of this MRQ. > Also, moved the code to new function for better readability. > > Signed-off-by: Sumit Gupta <sumitg@nvidia.com> > --- > drivers/memory/tegra/tegra186-emc.c | 136 +++++++++++++++------------- > 1 file changed, 71 insertions(+), 65 deletions(-) Acked-by: Thierry Reding <treding@nvidia.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported 2023-06-21 13:43 [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Sumit Gupta ` (2 preceding siblings ...) 2023-06-21 13:43 ` [Patch RESEND 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Sumit Gupta @ 2023-06-21 13:44 ` Sumit Gupta 2023-07-13 15:03 ` Thierry Reding 2023-07-25 18:29 ` Jon Hunter 2023-07-14 4:10 ` [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Krzysztof Kozlowski 4 siblings, 2 replies; 15+ messages in thread From: Sumit Gupta @ 2023-06-21 13:44 UTC (permalink / raw) To: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra Cc: bbasu, talho, sumitg Return zero from icc_set_bw() to MC client driver if MRQ_BWMGR_INT is not supported by the BPMP-FW. Currently, 'EINVAL' is returned which causes error message in client drivers even when the platform doesn't support scaling. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> --- drivers/memory/tegra/tegra234.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index bc73be7fe143..07aba301a173 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -951,7 +951,7 @@ static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst) return 0; if (!mc->bwmgr_mrq_supported) - return -EINVAL; + return 0; if (!mc->bpmp) { dev_err(mc->dev, "BPMP reference NULL\n"); @@ -998,7 +998,7 @@ static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, struct tegra_mc *mc = icc_provider_to_tegra_mc(p); if (!mc->bwmgr_mrq_supported) - return -EINVAL; + return 0; if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported 2023-06-21 13:44 ` [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported Sumit Gupta @ 2023-07-13 15:03 ` Thierry Reding 2023-07-25 18:29 ` Jon Hunter 1 sibling, 0 replies; 15+ messages in thread From: Thierry Reding @ 2023-07-13 15:03 UTC (permalink / raw) To: Sumit Gupta Cc: krzysztof.kozlowski, treding, jonathanh, linux-kernel, linux-tegra, bbasu, talho [-- Attachment #1: Type: text/plain, Size: 506 bytes --] On Wed, Jun 21, 2023 at 07:14:00PM +0530, Sumit Gupta wrote: > Return zero from icc_set_bw() to MC client driver if MRQ_BWMGR_INT > is not supported by the BPMP-FW. Currently, 'EINVAL' is returned > which causes error message in client drivers even when the platform > doesn't support scaling. > > Signed-off-by: Sumit Gupta <sumitg@nvidia.com> > --- > drivers/memory/tegra/tegra234.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Acked-by: Thierry Reding <treding@nvidia.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported 2023-06-21 13:44 ` [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported Sumit Gupta 2023-07-13 15:03 ` Thierry Reding @ 2023-07-25 18:29 ` Jon Hunter 2023-07-25 20:11 ` Krzysztof Kozlowski 1 sibling, 1 reply; 15+ messages in thread From: Jon Hunter @ 2023-07-25 18:29 UTC (permalink / raw) To: Sumit Gupta, krzysztof.kozlowski, treding, linux-kernel, linux-tegra Cc: bbasu, talho Hi Krzysztof, On 21/06/2023 14:44, Sumit Gupta wrote: > Return zero from icc_set_bw() to MC client driver if MRQ_BWMGR_INT > is not supported by the BPMP-FW. Currently, 'EINVAL' is returned > which causes error message in client drivers even when the platform > doesn't support scaling. > > Signed-off-by: Sumit Gupta <sumitg@nvidia.com> > --- > drivers/memory/tegra/tegra234.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c > index bc73be7fe143..07aba301a173 100644 > --- a/drivers/memory/tegra/tegra234.c > +++ b/drivers/memory/tegra/tegra234.c > @@ -951,7 +951,7 @@ static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst) > return 0; > > if (!mc->bwmgr_mrq_supported) > - return -EINVAL; > + return 0; > > if (!mc->bpmp) { > dev_err(mc->dev, "BPMP reference NULL\n"); > @@ -998,7 +998,7 @@ static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, > struct tegra_mc *mc = icc_provider_to_tegra_mc(p); > > if (!mc->bwmgr_mrq_supported) > - return -EINVAL; > + return 0; > > if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || > node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || I have also found that this change is needed for Linux v6.5 in order to work with current BPMP firmware. Without this patch PCIe does not work on Tegra234. We should probably also add the following fixes tag for this patch ... Fixes: 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234") Thanks Jon -- nvpublic ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported 2023-07-25 18:29 ` Jon Hunter @ 2023-07-25 20:11 ` Krzysztof Kozlowski 0 siblings, 0 replies; 15+ messages in thread From: Krzysztof Kozlowski @ 2023-07-25 20:11 UTC (permalink / raw) To: Jon Hunter, Sumit Gupta, treding, linux-kernel, linux-tegra; +Cc: bbasu, talho On 25/07/2023 20:29, Jon Hunter wrote: > Hi Krzysztof, > > On 21/06/2023 14:44, Sumit Gupta wrote: >> Return zero from icc_set_bw() to MC client driver if MRQ_BWMGR_INT >> is not supported by the BPMP-FW. Currently, 'EINVAL' is returned >> which causes error message in client drivers even when the platform >> doesn't support scaling. >> >> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> >> --- >> drivers/memory/tegra/tegra234.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c >> index bc73be7fe143..07aba301a173 100644 >> --- a/drivers/memory/tegra/tegra234.c >> +++ b/drivers/memory/tegra/tegra234.c >> @@ -951,7 +951,7 @@ static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst) >> return 0; >> >> if (!mc->bwmgr_mrq_supported) >> - return -EINVAL; >> + return 0; >> >> if (!mc->bpmp) { >> dev_err(mc->dev, "BPMP reference NULL\n"); >> @@ -998,7 +998,7 @@ static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, >> struct tegra_mc *mc = icc_provider_to_tegra_mc(p); >> >> if (!mc->bwmgr_mrq_supported) >> - return -EINVAL; >> + return 0; >> >> if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || >> node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || > > > I have also found that this change is needed for Linux v6.5 in order to > work with current BPMP firmware. Without this patch PCIe does not work > on Tegra234. We should probably also add the following fixes tag for > this patch ... > > Fixes: 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234") Thank you, I moved the commit to fixes branch. I hope other patches do not depend on the order (it was part of the patchset as 3/4 commit). Since I re-shuffled everything, I will send pull for current RC tomorrow, not today. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes 2023-06-21 13:43 [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Sumit Gupta ` (3 preceding siblings ...) 2023-06-21 13:44 ` [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported Sumit Gupta @ 2023-07-14 4:10 ` Krzysztof Kozlowski 4 siblings, 0 replies; 15+ messages in thread From: Krzysztof Kozlowski @ 2023-07-14 4:10 UTC (permalink / raw) To: treding, jonathanh, linux-kernel, linux-tegra, Sumit Gupta Cc: Krzysztof Kozlowski, bbasu, talho On Wed, 21 Jun 2023 19:13:56 +0530, Sumit Gupta wrote: > This patch set adds VIC, NVDEC, NVENC, NVJPG, NVDISPLAY clients > of Memory Controller to the Tegra234 MC clients table. It also > improves error handling when some MRQ's are not supported by a > platform. For Example: > - Avoid "tegra186_emc_probe" failure if the "MRQ_EMC_DVFS_LATENCY" > is not supported. > - Avoid Error returned by icc_set_bw() in the MC client drivers if > the "MRQ_BWMGR_INT" is not supported. > > [...] Applied, thanks! [1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets https://git.kernel.org/krzk/linux-mem-ctrl/c/01c70c8e52c5579de0c3fff81f81778a570a8643 [2/4] memory: tegra: Add clients used by DRM in Tegra234 https://git.kernel.org/krzk/linux-mem-ctrl/c/9d0bd0e535953886cd1a1335941c5afbe4d7df32 [3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported https://git.kernel.org/krzk/linux-mem-ctrl/c/8fda1018ca68e7b8fa860087e3069c3be476148f Checkpatch errors (I guess expected due to code move): WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. #86: FILE: drivers/memory/tegra/tegra186-emc.c:215: + debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, WARNING: Symbolic permissions 'S_IRUGO | S_IWUSR' are not preferred. Consider using octal permissions '0644'. #88: FILE: drivers/memory/tegra/tegra186-emc.c:217: + debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, WARNING: Symbolic permissions 'S_IRUGO | S_IWUSR' are not preferred. Consider using octal permissions '0644'. #90: FILE: drivers/memory/tegra/tegra186-emc.c:219: + debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, [4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported https://git.kernel.org/krzk/linux-mem-ctrl/c/3d7cfb8d6142c1d681eb70eae7fb1950b59fc0dc Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-07-25 20:11 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-06-21 13:43 [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Sumit Gupta 2023-06-21 13:43 ` [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Sumit Gupta 2023-07-10 10:08 ` Krzysztof Kozlowski 2023-07-10 16:48 ` Sumit Gupta 2023-07-12 19:40 ` Krzysztof Kozlowski 2023-07-13 15:00 ` Thierry Reding 2023-06-21 13:43 ` [Patch RESEND 2/4] memory: tegra: Add clients used by DRM in Tegra234 Sumit Gupta 2023-07-13 15:01 ` Thierry Reding 2023-06-21 13:43 ` [Patch RESEND 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Sumit Gupta 2023-07-13 15:02 ` Thierry Reding 2023-06-21 13:44 ` [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported Sumit Gupta 2023-07-13 15:03 ` Thierry Reding 2023-07-25 18:29 ` Jon Hunter 2023-07-25 20:11 ` Krzysztof Kozlowski 2023-07-14 4:10 ` [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Krzysztof Kozlowski
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