[PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This series officializes the device tree bindings for the embedded
Ethernet switch on NXP LS1028A (and for the reference design board).
The driver has been in the tree since v5.4-rc6.

As per feedback received in v1, I've changed the DT bindings for the
internal ports from "gmii" to "internal". So I would like the entire
series to be merged through a single tree, be it net-next or devicetree.
If this happens, I would like the other maintainer to acknowledge this
fact and the patches themselves. Thanks.

Claudiu Manoil (2):
  arm64: dts: fsl: ls1028a: add node for Felix switch
  arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

Vladimir Oltean (3):
  arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC
    RCIE
  net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII
  dt-bindings: net: dsa: ocelot: document the vsc9959 core

 .../devicetree/bindings/net/dsa/ocelot.txt    | 96 +++++++++++++++++++
 .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 51 ++++++++++
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 85 +++++++++++++++-
 drivers/net/dsa/ocelot/felix.c                |  3 +-
 drivers/net/dsa/ocelot/felix_vsc9959.c        |  3 +-
 5 files changed, 232 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt

-- 
2.17.1

[PATCH v2 net-next/devicetree 1/5] arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC RCIE

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This specifier overrides the interrupt specifier with 3 cells from gic
(/interrupt-controller@6000000), but in fact ENETC is not an interrupt
controller, so the property is bogus.

Interrupts used by the children of the ENETC RCIE must use the full
3-cell specifier required by the GIC.

The issue has no functional consequence so there is no real reason to
port the patch to stable trees.

Fixes: 927d7f857542 ("arm64: dts: fsl: ls1028a: Add PCI IERC node and ENETC endpoints")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Changes in v2:
None.

 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 0bf375ec959b..dfead691e509 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -683,7 +683,6 @@
 			reg = <0x01 0xf0000000 0x0 0x100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-			#interrupt-cells = <1>;
 			msi-parent = <&its>;
 			device_type = "pci";
 			bus-range = <0x0 0x0>;
-- 
2.17.1

Re: [PATCH v2 net-next/devicetree 1/5] arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC RCIE

[Shawn Guo]

On Wed, Feb 19, 2020 at 05:12:55PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> This specifier overrides the interrupt specifier with 3 cells from gic
> (/interrupt-controller@6000000), but in fact ENETC is not an interrupt
> controller, so the property is bogus.
> 
> Interrupts used by the children of the ENETC RCIE must use the full
> 3-cell specifier required by the GIC.
> 
> The issue has no functional consequence so there is no real reason to
> port the patch to stable trees.
> 
> Fixes: 927d7f857542 ("arm64: dts: fsl: ls1028a: Add PCI IERC node and ENETC endpoints")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Prefix 'arm64: dts: ls1028a: ...' should be already clear enough.

Shawn

[PATCH v2 net-next/devicetree 2/5] net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

phy-mode = "gmii" is confusing because it may mean that the port
supports the 8-bit-wide parallel data interface pinout, which it
doesn't.

It may also be confusing because one of the "gmii" internal ports is
actually overclocked to run at 2.5Gbps (even though, yes, as far as the
switch MAC is concerned, it still thinks it's gigabit).

So use the phy-mode = "internal" property to describe the internal ports
inside the NXP LS1028A chip (the ones facing the ENETC). The change
should be fine, because the device tree bindings document is yet to be
introduced, and there are no stable DT blobs in use.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Changes in v2:
Patch is new.

 drivers/net/dsa/ocelot/felix.c         | 3 +--
 drivers/net/dsa/ocelot/felix_vsc9959.c | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c
index 3257962c147e..35124ef7e75b 100644
--- a/drivers/net/dsa/ocelot/felix.c
+++ b/drivers/net/dsa/ocelot/felix.c
@@ -176,8 +176,7 @@ static void felix_phylink_validate(struct dsa_switch *ds, int port,
 	phylink_set(mask, 100baseT_Full);
 	phylink_set(mask, 1000baseT_Full);
 
-	/* The internal ports that run at 2.5G are overclocked GMII */
-	if (state->interface == PHY_INTERFACE_MODE_GMII ||
+	if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
 	    state->interface == PHY_INTERFACE_MODE_2500BASEX ||
 	    state->interface == PHY_INTERFACE_MODE_USXGMII) {
 		phylink_set(mask, 2500baseT_Full);
diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c
index 2c812b481778..93800e81cdd4 100644
--- a/drivers/net/dsa/ocelot/felix_vsc9959.c
+++ b/drivers/net/dsa/ocelot/felix_vsc9959.c
@@ -955,8 +955,7 @@ static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port,
 					phy_interface_t phy_mode)
 {
 	switch (phy_mode) {
-	case PHY_INTERFACE_MODE_GMII:
-		/* Only supported on internal to-CPU ports */
+	case PHY_INTERFACE_MODE_INTERNAL:
 		if (port != 4 && port != 5)
 			return -ENOTSUPP;
 		return 0;
-- 
2.17.1

Re: [PATCH v2 net-next/devicetree 2/5] net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII

[Andrew Lunn]

On Wed, Feb 19, 2020 at 05:12:56PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> phy-mode = "gmii" is confusing because it may mean that the port
> supports the 8-bit-wide parallel data interface pinout, which it
> doesn't.
> 
> It may also be confusing because one of the "gmii" internal ports is
> actually overclocked to run at 2.5Gbps (even though, yes, as far as the
> switch MAC is concerned, it still thinks it's gigabit).
> 
> So use the phy-mode = "internal" property to describe the internal ports
> inside the NXP LS1028A chip (the ones facing the ENETC). The change
> should be fine, because the device tree bindings document is yet to be
> introduced, and there are no stable DT blobs in use.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

[PATCH v2 net-next/devicetree 3/5] dt-bindings: net: dsa: ocelot: document the vsc9959 core

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This patch adds the required documentation for the embedded L2 switch
inside the NXP LS1028A chip.

I've submitted it in the legacy format instead of yaml schema, because
DSA itself has not yet been converted to yaml, and this driver defines
no custom bindings.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Changes in v2:
Adapted phy-mode = "gmii" to phy-mode = "internal".

 .../devicetree/bindings/net/dsa/ocelot.txt    | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt

diff --git a/Documentation/devicetree/bindings/net/dsa/ocelot.txt b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
new file mode 100644
index 000000000000..a9d86e09dafa
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
@@ -0,0 +1,96 @@
+Microchip Ocelot switch driver family
+=====================================
+
+Felix
+-----
+
+The VSC9959 core is currently the only switch supported by the driver, and is
+found in the NXP LS1028A. It is a PCI device, part of the larger ENETC root
+complex. As a result, the ethernet-switch node is a sub-node of the PCIe root
+complex node and its "reg" property conforms to the parent node bindings:
+
+* reg: Specifies PCIe Device Number and Function Number of the endpoint device,
+  in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).
+
+It does not require a "compatible" string.
+
+The interrupt line is used to signal availability of PTP TX timestamps and for
+TSN frame preemption.
+
+For the external switch ports, depending on board configuration, "phy-mode" and
+"phy-handle" are populated by board specific device tree instances. Ports 4 and
+5 are fixed as internal ports in the NXP LS1028A instantiation.
+
+Any port can be disabled, but the CPU port should be kept enabled.
+
+The CPU port property ("ethernet"), which is assigned by default to the 2.5Gbps
+port@4, can be moved to the 1Gbps port@5, depending on the specific use case.
+DSA tagging is supported on a single port at a time.
+
+For the rest of the device tree binding definitions, which are standard DSA and
+PCI, refer to the following documents:
+
+Documentation/devicetree/bindings/net/dsa/dsa.txt
+Documentation/devicetree/bindings/pci/pci.txt
+
+Example:
+
+&soc {
+	pcie@1f0000000 { /* Integrated Endpoint Root Complex */
+		ethernet-switch@0,5 {
+			reg = <0x000500 0 0 0 0>;
+			/* IEP INT_B */
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* External ports */
+				port@0 {
+					reg = <0>;
+					label = "swp0";
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "swp1";
+				};
+
+				port@2 {
+					reg = <2>;
+					label = "swp2";
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "swp3";
+				};
+
+				/* Tagging CPU port */
+				port@4 {
+					reg = <4>;
+					ethernet = <&enetc_port2>;
+					phy-mode = "internal";
+
+					fixed-link {
+						speed = <2500>;
+						full-duplex;
+					};
+				};
+
+				/* Non-tagging CPU port */
+				port@5 {
+					reg = <5>;
+					phy-mode = "internal";
+					status = "disabled";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+	};
+};
-- 
2.17.1

Re: [PATCH v2 net-next/devicetree 3/5] dt-bindings: net: dsa: ocelot: document the vsc9959 core

[Andrew Lunn]

On Wed, Feb 19, 2020 at 05:12:57PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> This patch adds the required documentation for the embedded L2 switch
> inside the NXP LS1028A chip.
> 
> I've submitted it in the legacy format instead of yaml schema, because
> DSA itself has not yet been converted to yaml, and this driver defines
> no custom bindings.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH v2 net-next/devicetree 3/5] dt-bindings: net: dsa: ocelot: document the vsc9959 core

[Michael Walle]

> This patch adds the required documentation for the embedded L2 switch
> inside the NXP LS1028A chip.
> 
> I've submitted it in the legacy format instead of yaml schema, because
> DSA itself has not yet been converted to yaml, and this driver defines
> no custom bindings.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Changes in v2:
> Adapted phy-mode = "gmii" to phy-mode = "internal".
> 
>  .../devicetree/bindings/net/dsa/ocelot.txt    | 96 +++++++++++++++++++
>  1 file changed, 96 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/dsa/ocelot.txt b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
> new file mode 100644
> index 000000000000..a9d86e09dafa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
> @@ -0,0 +1,96 @@
> +Microchip Ocelot switch driver family
> +=====================================
> +
> +Felix
> +-----
> +
> +The VSC9959 core is currently the only switch supported by the driver, and is
> +found in the NXP LS1028A. It is a PCI device, part of the larger ENETC root
> +complex. As a result, the ethernet-switch node is a sub-node of the PCIe root
> +complex node and its "reg" property conforms to the parent node bindings:
> +
> +* reg: Specifies PCIe Device Number and Function Number of the endpoint device,
> +  in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).
> +
> +It does not require a "compatible" string.
> +
> +The interrupt line is used to signal availability of PTP TX timestamps and for
> +TSN frame preemption.
> +
> +For the external switch ports, depending on board configuration, "phy-mode" and
> +"phy-handle" are populated by board specific device tree instances. Ports 4 and
> +5 are fixed as internal ports in the NXP LS1028A instantiation.
> +
> +Any port can be disabled, but the CPU port should be kept enabled.

What is the reason for this? Do you mean if you actually want to use it? In
fact, I'd would like to see it disabled by default in the .dtsi file. It
doesn't make sense to just have the CPU port enabled, but not any of the
outgoing ports. It'd just confuse the user if there is an additional
network port which cannot be used.

-michael

> +
> +The CPU port property ("ethernet"), which is assigned by default to the 2.5Gbps
> +port@4, can be moved to the 1Gbps port@5, depending on the specific use case.
> +DSA tagging is supported on a single port at a time.
> +
> +For the rest of the device tree binding definitions, which are standard DSA and
> +PCI, refer to the following documents:
> +
> +Documentation/devicetree/bindings/net/dsa/dsa.txt
> +Documentation/devicetree/bindings/pci/pci.txt
> +
> +Example:
> +
> +&soc {
> +	pcie@1f0000000 { /* Integrated Endpoint Root Complex */
> +		ethernet-switch@0,5 {
> +			reg = <0x000500 0 0 0 0>;
> +			/* IEP INT_B */
> +			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				/* External ports */
> +				port@0 {
> +					reg = <0>;
> +					label = "swp0";
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +					label = "swp1";
> +				};
> +
> +				port@2 {
> +					reg = <2>;
> +					label = "swp2";
> +				};
> +
> +				port@3 {
> +					reg = <3>;
> +					label = "swp3";
> +				};
> +
> +				/* Tagging CPU port */
> +				port@4 {
> +					reg = <4>;
> +					ethernet = <&enetc_port2>;
> +					phy-mode = "internal";
> +
> +					fixed-link {
> +						speed = <2500>;
> +						full-duplex;
> +					};
> +				};
> +
> +				/* Non-tagging CPU port */
> +				port@5 {
> +					reg = <5>;
> +					phy-mode = "internal";
> +					status = "disabled";
> +
> +					fixed-link {
> +						speed = <1000>;
> +						full-duplex;
> +					};
> +				};
> +			};
> +		};
> +	};
> +};
> -- 
> 2.17.1

Re: [PATCH v2 net-next/devicetree 3/5] dt-bindings: net: dsa: ocelot: document the vsc9959 core

[Vladimir Oltean]

Hi Michael,

On Sat, 22 Feb 2020 at 13:28, Michael Walle <michael@walle.cc> wrote:
>
> > +Any port can be disabled, but the CPU port should be kept enabled.
>
> What is the reason for this? Do you mean if you actually want to use it? In
> fact, I'd would like to see it disabled by default in the .dtsi file. It
> doesn't make sense to just have the CPU port enabled, but not any of the
> outgoing ports. It'd just confuse the user if there is an additional
> network port which cannot be used.
>
> -michael
>

I can disable all internal ports by default, but there is one
configuration which will not work: enabling only eno3 and switch port
5. This is because the switch PCS registers belong to eno2, and if
that is disabled, the memory accesses will be invalid. So providing a
configuration with eno2 disabled by default is more likely to produce
confusion. But I'll try to clarify better next time.

> > --
> > 2.17.1
>
>

Thanks,
-Vladimir

[PATCH v2 net-next/devicetree 4/5] arm64: dts: fsl: ls1028a: add node for Felix switch

[Vladimir Oltean]

From: Claudiu Manoil <claudiu.manoil@nxp.com>

Add the switch device node, available on PF5, so that the switch port
sub-nodes (net devices) can be linked to corresponding board specific
phy nodes (external ports) or have their link mode defined (internal
ports).

The switch device features 6 ports, 4 with external links and 2
internally facing to the LS1028A SoC and connected via fixed links to 2
internal ENETC Ethernet controller ports.

Add the corresponding ENETC host port device nodes, mapped to PF2 and
PF6 PCIe functions. Since the switch only supports tagging on one CPU
port, only one port pair (swp4, eno2) is enabled by default and the
other, lower speed, port pair is disabled to prevent the PCI core from
probing them. If enabled, swp5 will be a fixed-link slave port.

DSA tagging can also be moved from the swp4-eno2 2.5G port pair to the
1G swp5-eno3 pair by changing the ethernet = <&enetc_port2> phandle to
<&enetc_port3> and moving it under port5, but in that case enetc_port2
should not be disabled, because it is the hardware owner of the Felix
PCS and disabling its memory would result in access faults in the Felix
DSA driver.

All ports are disabled by default, except one CPU port.

The switch's INTB interrupt line signals:
- PTP timestamp ready in timestamp FIFO
- TSN Frame Preemption

And don't forget to enable the 4MB BAR4 in the root complex ECAM space,
where the switch registers are mapped.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Changes in v2:
Adapted phy-mode = "gmii" to phy-mode = "internal".

 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 84 ++++++++++++++++++-
 1 file changed, 83 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index dfead691e509..a6b9c6d1eb5e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -700,7 +700,9 @@
 				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */
 				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
 				  /* PF1: VF0-1 BAR2 - prefetchable memory */
-				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000>;
+				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000
+				  /* BAR4 (PF5) - non-prefetchable memory */
+				  0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000>;
 
 			enetc_port0: ethernet@0,0 {
 				compatible = "fsl,enetc";
@@ -710,6 +712,18 @@
 				compatible = "fsl,enetc";
 				reg = <0x000100 0 0 0 0>;
 			};
+
+			enetc_port2: ethernet@0,2 {
+				compatible = "fsl,enetc";
+				reg = <0x000200 0 0 0 0>;
+				phy-mode = "gmii";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
 			enetc_mdio_pf3: mdio@0,3 {
 				compatible = "fsl,enetc-mdio";
 				reg = <0x000300 0 0 0 0>;
@@ -722,6 +736,74 @@
 				clocks = <&clockgen 4 0>;
 				little-endian;
 			};
+
+			ethernet-switch@0,5 {
+				reg = <0x000500 0 0 0 0>;
+				/* IEP INT_B */
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					/* external ports */
+					mscc_felix_port0: port@0 {
+						reg = <0>;
+						status = "disabled";
+					};
+
+					mscc_felix_port1: port@1 {
+						reg = <1>;
+						status = "disabled";
+					};
+
+					mscc_felix_port2: port@2 {
+						reg = <2>;
+						status = "disabled";
+					};
+
+					mscc_felix_port3: port@3 {
+						reg = <3>;
+						status = "disabled";
+					};
+
+					/* Internal port with DSA tagging */
+					mscc_felix_port4: port@4 {
+						reg = <4>;
+						phy-mode = "internal";
+						ethernet = <&enetc_port2>;
+
+						fixed-link {
+							speed = <2500>;
+							full-duplex;
+						};
+					};
+
+					/* Internal port without DSA tagging */
+					mscc_felix_port5: port@5 {
+						reg = <5>;
+						phy-mode = "internal";
+						status = "disabled";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+
+			enetc_port3: ethernet@0,6 {
+				compatible = "fsl,enetc";
+				reg = <0x000600 0 0 0 0>;
+				status = "disabled";
+				phy-mode = "gmii";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
 		};
 	};
 
-- 
2.17.1

Re: [PATCH v2 net-next/devicetree 4/5] arm64: dts: fsl: ls1028a: add node for Felix switch

[Michael Walle]

Hi,

> Add the switch device node, available on PF5, so that the switch port
> sub-nodes (net devices) can be linked to corresponding board specific
> phy nodes (external ports) or have their link mode defined (internal
> ports).
> 
> The switch device features 6 ports, 4 with external links and 2
> internally facing to the LS1028A SoC and connected via fixed links to 2
> internal ENETC Ethernet controller ports.
> 
> Add the corresponding ENETC host port device nodes, mapped to PF2 and
> PF6 PCIe functions. Since the switch only supports tagging on one CPU
> port, only one port pair (swp4, eno2) is enabled by default and the
> other, lower speed, port pair is disabled to prevent the PCI core from
> probing them. If enabled, swp5 will be a fixed-link slave port.
> 
> DSA tagging can also be moved from the swp4-eno2 2.5G port pair to the
> 1G swp5-eno3 pair by changing the ethernet = <&enetc_port2> phandle to
> <&enetc_port3> and moving it under port5, but in that case enetc_port2
> should not be disabled, because it is the hardware owner of the Felix
> PCS and disabling its memory would result in access faults in the Felix
> DSA driver.
> 
> All ports are disabled by default, except one CPU port.
> 
> The switch's INTB interrupt line signals:
> - PTP timestamp ready in timestamp FIFO
> - TSN Frame Preemption
> 
> And don't forget to enable the 4MB BAR4 in the root complex ECAM space,
> where the switch registers are mapped.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Changes in v2:
> Adapted phy-mode = "gmii" to phy-mode = "internal".
> 
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 84 ++++++++++++++++++-
>  1 file changed, 83 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index dfead691e509..a6b9c6d1eb5e 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -700,7 +700,9 @@
>  				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */
>  				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
>  				  /* PF1: VF0-1 BAR2 - prefetchable memory */
> -				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000>;
> +				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000
> +				  /* BAR4 (PF5) - non-prefetchable memory */
> +				  0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000>;
>  
>  			enetc_port0: ethernet@0,0 {
>  				compatible = "fsl,enetc";
> @@ -710,6 +712,18 @@
>  				compatible = "fsl,enetc";
>  				reg = <0x000100 0 0 0 0>;
>  			};
> +
> +			enetc_port2: ethernet@0,2 {
> +				compatible = "fsl,enetc";
> +				reg = <0x000200 0 0 0 0>;
> +				phy-mode = "gmii";
Can we disable this port by default in this dtsi? As mentioned in the other
mail, I'd prefer to have all ports disabled because it doesn't make sense
to have this port while having all the external ports disabled.

> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
> +
>  			enetc_mdio_pf3: mdio@0,3 {
>  				compatible = "fsl,enetc-mdio";
>  				reg = <0x000300 0 0 0 0>;
> @@ -722,6 +736,74 @@
>  				clocks = <&clockgen 4 0>;
>  				little-endian;
>  			};
> +
> +			ethernet-switch@0,5 {
> +				reg = <0x000500 0 0 0 0>;
> +				/* IEP INT_B */
> +				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					/* external ports */
> +					mscc_felix_port0: port@0 {
> +						reg = <0>;
> +						status = "disabled";
> +					};
> +
> +					mscc_felix_port1: port@1 {
> +						reg = <1>;
> +						status = "disabled";
> +					};
> +
> +					mscc_felix_port2: port@2 {
> +						reg = <2>;
> +						status = "disabled";
> +					};
> +
> +					mscc_felix_port3: port@3 {
> +						reg = <3>;
> +						status = "disabled";
> +					};
> +
> +					/* Internal port with DSA tagging */
> +					mscc_felix_port4: port@4 {
> +						reg = <4>;
> +						phy-mode = "internal";
> +						ethernet = <&enetc_port2>;
Likewise, I'd prefer to have this disabled.

> +
> +						fixed-link {
> +							speed = <2500>;
> +							full-duplex;
> +						};
> +					};
> +
> +					/* Internal port without DSA tagging */
> +					mscc_felix_port5: port@5 {
> +						reg = <5>;
> +						phy-mode = "internal";
> +						status = "disabled";
> +
> +						fixed-link {
> +							speed = <1000>;
> +							full-duplex;
> +						};
> +					};
> +				};
> +			};
> +
> +			enetc_port3: ethernet@0,6 {
> +				compatible = "fsl,enetc";
> +				reg = <0x000600 0 0 0 0>;
> +				status = "disabled";
> +				phy-mode = "gmii";
shouldn't the status be after the phy-mode property?

-michael

> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
>  		};
>  	};
>  
> -- 
> 2.17.1

Re: [PATCH v2 net-next/devicetree 4/5] arm64: dts: fsl: ls1028a: add node for Felix switch

[Vladimir Oltean]

Hi Michael,

On Sat, 22 Feb 2020 at 13:38, Michael Walle <michael@walle.cc> wrote:
>
> Hi,
>

> > +
> > +                     enetc_port2: ethernet@0,2 {
> > +                             compatible = "fsl,enetc";
> > +                             reg = <0x000200 0 0 0 0>;
> > +                             phy-mode = "gmii";
> Can we disable this port by default in this dtsi? As mentioned in the other
> mail, I'd prefer to have all ports disabled because it doesn't make sense
> to have this port while having all the external ports disabled.
>

Ok. What would you want to happen with the "ethernet" property? Do you
want the board dts to set that too?

> > +                                     /* Internal port with DSA tagging */
> > +                                     mscc_felix_port4: port@4 {
> > +                                             reg = <4>;
> > +                                             phy-mode = "internal";
> > +                                             ethernet = <&enetc_port2>;
> Likewise, I'd prefer to have this disabled.
>

Ok.

> > +                     enetc_port3: ethernet@0,6 {
> > +                             compatible = "fsl,enetc";
> > +                             reg = <0x000600 0 0 0 0>;
> > +                             status = "disabled";
> > +                             phy-mode = "gmii";
> shouldn't the status be after the phy-mode property?

Why?

>
> -michael
>

Regards,
-Vladimir

Re: [PATCH v2 net-next/devicetree 4/5] arm64: dts: fsl: ls1028a: add node for Felix switch

[Michael Walle]

Hi Vladimir,

Am 2020-02-22 13:25, schrieb Vladimir Oltean:
> Hi Michael,
> 
> On Sat, 22 Feb 2020 at 13:38, Michael Walle <michael@walle.cc> wrote:
>> 
>> Hi,
>> 
> 
>> > +
>> > +                     enetc_port2: ethernet@0,2 {
>> > +                             compatible = "fsl,enetc";
>> > +                             reg = <0x000200 0 0 0 0>;
>> > +                             phy-mode = "gmii";
>> Can we disable this port by default in this dtsi? As mentioned in the 
>> other
>> mail, I'd prefer to have all ports disabled because it doesn't make 
>> sense
>> to have this port while having all the external ports disabled.
>> 
> 
> Ok. What would you want to happen with the "ethernet" property? Do you
> want the board dts to set that too?

That's something I've also thought about. And now that you've mention
this, I think it makes more sense to have that in the board too. Because
if you have the freedom to use either eno2/swp4 or eno3/swp5, then if I
choose the second one I'd have to delete the ethernet property from the
first, correct? I actually thought about adding the ethernet property
to both; but (1) I don't know if that is even possible (given that one
is always disabled) and (2) if one want to use the second port as an
additional link to the switch you'd have to remove the ethernet property
on that port. correct?


>> > +                                     /* Internal port with DSA tagging */
>> > +                                     mscc_felix_port4: port@4 {
>> > +                                             reg = <4>;
>> > +                                             phy-mode = "internal";
>> > +                                             ethernet = <&enetc_port2>;
>> Likewise, I'd prefer to have this disabled.
>> 
> 
> Ok.
> 
>> > +                     enetc_port3: ethernet@0,6 {
>> > +                             compatible = "fsl,enetc";
>> > +                             reg = <0x000600 0 0 0 0>;
>> > +                             status = "disabled";
>> > +                             phy-mode = "gmii";
>> shouldn't the status be after the phy-mode property?
> 
> Why?

I thought that would be a rule. I just had a quick look on some other 
device
trees before and they all has the status property as the last property 
(before
any subnodes). I might be mistaken. If so, you could do it for 
consistency
reasons ;) all status property in the ls1028a.dtsi are the last ones.

-michael

Re: [PATCH v2 net-next/devicetree 4/5] arm64: dts: fsl: ls1028a: add node for Felix switch

[Shawn Guo]

On Wed, Feb 19, 2020 at 05:12:58PM +0200, Vladimir Oltean wrote:
> From: Claudiu Manoil <claudiu.manoil@nxp.com>
> 
> Add the switch device node, available on PF5, so that the switch port
> sub-nodes (net devices) can be linked to corresponding board specific
> phy nodes (external ports) or have their link mode defined (internal
> ports).
> 
> The switch device features 6 ports, 4 with external links and 2
> internally facing to the LS1028A SoC and connected via fixed links to 2
> internal ENETC Ethernet controller ports.
> 
> Add the corresponding ENETC host port device nodes, mapped to PF2 and
> PF6 PCIe functions. Since the switch only supports tagging on one CPU
> port, only one port pair (swp4, eno2) is enabled by default and the
> other, lower speed, port pair is disabled to prevent the PCI core from
> probing them. If enabled, swp5 will be a fixed-link slave port.
> 
> DSA tagging can also be moved from the swp4-eno2 2.5G port pair to the
> 1G swp5-eno3 pair by changing the ethernet = <&enetc_port2> phandle to
> <&enetc_port3> and moving it under port5, but in that case enetc_port2
> should not be disabled, because it is the hardware owner of the Felix
> PCS and disabling its memory would result in access faults in the Felix
> DSA driver.
> 
> All ports are disabled by default, except one CPU port.
> 
> The switch's INTB interrupt line signals:
> - PTP timestamp ready in timestamp FIFO
> - TSN Frame Preemption
> 
> And don't forget to enable the 4MB BAR4 in the root complex ECAM space,
> where the switch registers are mapped.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Changes in v2:
> Adapted phy-mode = "gmii" to phy-mode = "internal".
> 
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 84 ++++++++++++++++++-
>  1 file changed, 83 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index dfead691e509..a6b9c6d1eb5e 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -700,7 +700,9 @@
>  				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */
>  				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
>  				  /* PF1: VF0-1 BAR2 - prefetchable memory */
> -				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000>;
> +				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000
> +				  /* BAR4 (PF5) - non-prefetchable memory */
> +				  0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000>;
>  
>  			enetc_port0: ethernet@0,0 {
>  				compatible = "fsl,enetc";
> @@ -710,6 +712,18 @@
>  				compatible = "fsl,enetc";
>  				reg = <0x000100 0 0 0 0>;
>  			};
> +
> +			enetc_port2: ethernet@0,2 {
> +				compatible = "fsl,enetc";
> +				reg = <0x000200 0 0 0 0>;
> +				phy-mode = "gmii";
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
> +
>  			enetc_mdio_pf3: mdio@0,3 {
>  				compatible = "fsl,enetc-mdio";
>  				reg = <0x000300 0 0 0 0>;
> @@ -722,6 +736,74 @@
>  				clocks = <&clockgen 4 0>;
>  				little-endian;
>  			};
> +
> +			ethernet-switch@0,5 {
> +				reg = <0x000500 0 0 0 0>;
> +				/* IEP INT_B */
> +				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					/* external ports */
> +					mscc_felix_port0: port@0 {
> +						reg = <0>;
> +						status = "disabled";
> +					};
> +
> +					mscc_felix_port1: port@1 {
> +						reg = <1>;
> +						status = "disabled";
> +					};
> +
> +					mscc_felix_port2: port@2 {
> +						reg = <2>;
> +						status = "disabled";
> +					};
> +
> +					mscc_felix_port3: port@3 {
> +						reg = <3>;
> +						status = "disabled";
> +					};
> +
> +					/* Internal port with DSA tagging */
> +					mscc_felix_port4: port@4 {
> +						reg = <4>;
> +						phy-mode = "internal";
> +						ethernet = <&enetc_port2>;
> +
> +						fixed-link {
> +							speed = <2500>;
> +							full-duplex;
> +						};
> +					};
> +
> +					/* Internal port without DSA tagging */
> +					mscc_felix_port5: port@5 {
> +						reg = <5>;
> +						phy-mode = "internal";
> +						status = "disabled";
> +
> +						fixed-link {
> +							speed = <1000>;
> +							full-duplex;
> +						};
> +					};
> +				};
> +			};
> +
> +			enetc_port3: ethernet@0,6 {
> +				compatible = "fsl,enetc";
> +				reg = <0x000600 0 0 0 0>;
> +				status = "disabled";

Please have 'status' at bottom of the property list.

Shawn

> +				phy-mode = "gmii";
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
>  		};
>  	};
>  
> -- 
> 2.17.1
> 

[PATCH v2 net-next/devicetree 5/5] arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

[Vladimir Oltean]

From: Claudiu Manoil <claudiu.manoil@nxp.com>

Link the switch PHY nodes to the central MDIO controller PCIe endpoint
node on LS1028A (implemented as PF3) so that PHYs are accessible via
MDIO.

Enable SGMII AN on the Felix PCS by telling PHYLINK that the VSC8514
quad PHY is capable of in-band-status.

The PHYs are used in poll mode due to an issue with the interrupt line
on current revisions of the LS1028A-RDB board.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v2:
None.

 .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 51 +++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index afb55653850d..9353c00e46a7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -194,6 +194,57 @@
 	status = "disabled";
 };
 
+&enetc_mdio_pf3 {
+	/* VSC8514 QSGMII quad PHY */
+	qsgmii_phy0: ethernet-phy@10 {
+		reg = <0x10>;
+	};
+
+	qsgmii_phy1: ethernet-phy@11 {
+		reg = <0x11>;
+	};
+
+	qsgmii_phy2: ethernet-phy@12 {
+		reg = <0x12>;
+	};
+
+	qsgmii_phy3: ethernet-phy@13 {
+		reg = <0x13>;
+	};
+};
+
+&mscc_felix_port0 {
+	status = "okay";
+	label = "swp0";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy0>;
+	phy-mode = "qsgmii";
+};
+
+&mscc_felix_port1 {
+	status = "okay";
+	label = "swp1";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy1>;
+	phy-mode = "qsgmii";
+};
+
+&mscc_felix_port2 {
+	status = "okay";
+	label = "swp2";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy2>;
+	phy-mode = "qsgmii";
+};
+
+&mscc_felix_port3 {
+	status = "okay";
+	label = "swp3";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy3>;
+	phy-mode = "qsgmii";
+};
+
 &sai4 {
 	status = "okay";
 };
-- 
2.17.1

Re: [PATCH v2 net-next/devicetree 5/5] arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

[Michael Walle]

Hi,

> Link the switch PHY nodes to the central MDIO controller PCIe endpoint
> node on LS1028A (implemented as PF3) so that PHYs are accessible via
> MDIO.
> 
> Enable SGMII AN on the Felix PCS by telling PHYLINK that the VSC8514
> quad PHY is capable of in-band-status.
> 
> The PHYs are used in poll mode due to an issue with the interrupt line
> on current revisions of the LS1028A-RDB board.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> ---
> Changes in v2:
> None.
> 
>  .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> index afb55653850d..9353c00e46a7 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> @@ -194,6 +194,57 @@
>  	status = "disabled";
>  };
>  
> +&enetc_mdio_pf3 {
> +	/* VSC8514 QSGMII quad PHY */
> +	qsgmii_phy0: ethernet-phy@10 {
> +		reg = <0x10>;
> +	};
> +
> +	qsgmii_phy1: ethernet-phy@11 {
> +		reg = <0x11>;
> +	};
> +
> +	qsgmii_phy2: ethernet-phy@12 {
> +		reg = <0x12>;
> +	};
> +
> +	qsgmii_phy3: ethernet-phy@13 {
> +		reg = <0x13>;
> +	};
> +};
> +
> +&mscc_felix_port0 {
> +	status = "okay";
status should be the last property, correct?

-michael

> +	label = "swp0";
> +	managed = "in-band-status";
> +	phy-handle = <&qsgmii_phy0>;
> +	phy-mode = "qsgmii";
> +};
> +
> +&mscc_felix_port1 {
> +	status = "okay";
> +	label = "swp1";
> +	managed = "in-band-status";
> +	phy-handle = <&qsgmii_phy1>;
> +	phy-mode = "qsgmii";
> +};
> +
> +&mscc_felix_port2 {
> +	status = "okay";
> +	label = "swp2";
> +	managed = "in-band-status";
> +	phy-handle = <&qsgmii_phy2>;
> +	phy-mode = "qsgmii";
> +};
> +
> +&mscc_felix_port3 {
> +	status = "okay";
> +	label = "swp3";
> +	managed = "in-band-status";
> +	phy-handle = <&qsgmii_phy3>;
> +	phy-mode = "qsgmii";
> +};
> +
>  &sai4 {
>  	status = "okay";
>  };
> -- 
> 2.17.1

Re: [PATCH v2 net-next/devicetree 5/5] arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

[Vladimir Oltean]

Hi Michael,

On Sat, 22 Feb 2020 at 13:41, Michael Walle <michael@walle.cc> wrote:
>
> Hi,
>
> status should be the last property, correct?
>
> -michael

I know of no such convention to exist.

-Vladimir

Re: [PATCH v2 net-next/devicetree 5/5] arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

[Shawn Guo]

On Sat, Feb 22, 2020 at 02:17:54PM +0200, Vladimir Oltean wrote:
> Hi Michael,
> 
> On Sat, 22 Feb 2020 at 13:41, Michael Walle <michael@walle.cc> wrote:
> >
> > Hi,
> >
> > status should be the last property, correct?
> >
> > -michael
> 
> I know of no such convention to exist.

Hmm, it's a convention for DTS files that I'm looking after.

Shawn

Re: [PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[David Miller]

From: Vladimir Oltean <olteanv@gmail.com>
Date: Wed, 19 Feb 2020 17:12:54 +0200

> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> This series officializes the device tree bindings for the embedded
> Ethernet switch on NXP LS1028A (and for the reference design board).
> The driver has been in the tree since v5.4-rc6.
> 
> As per feedback received in v1, I've changed the DT bindings for the
> internal ports from "gmii" to "internal". So I would like the entire
> series to be merged through a single tree, be it net-next or devicetree.
> If this happens, I would like the other maintainer to acknowledge this
> fact and the patches themselves. Thanks.

I'm fine with this going through the devicetree tree.

Acked-by: David S. Miller <davem@davemloft.net>

Re: [PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[Michael Walle]

> This series officializes the device tree bindings for the embedded
> Ethernet switch on NXP LS1028A (and for the reference design board).
> The driver has been in the tree since v5.4-rc6.
> 
> As per feedback received in v1, I've changed the DT bindings for the
> internal ports from "gmii" to "internal". So I would like the entire
> series to be merged through a single tree, be it net-next or devicetree.
> If this happens, I would like the other maintainer to acknowledge this
> fact and the patches themselves. Thanks.
> 
> Claudiu Manoil (2):
>   arm64: dts: fsl: ls1028a: add node for Felix switch
>   arm64: dts: fsl: ls1028a: enable switch PHYs on RDB
> 
> Vladimir Oltean (3):
>   arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC
>     RCIE
>   net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII
>   dt-bindings: net: dsa: ocelot: document the vsc9959 core

For all patches except 5/5 (because it was tested on a custom board) and
with patch from [1] applied:

Tested-by: Michael Walle <michael@walle.cc>

-michael

[1] https://patchwork.ozlabs.org/patch/1239296/

> 
>  .../devicetree/bindings/net/dsa/ocelot.txt    | 96 +++++++++++++++++++
>  .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 51 ++++++++++
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 85 +++++++++++++++-
>  drivers/net/dsa/ocelot/felix.c                |  3 +-
>  drivers/net/dsa/ocelot/felix_vsc9959.c        |  3 +-
>  5 files changed, 232 insertions(+), 6 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt

-- 
2.17.1

Re: [PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[Shawn Guo]

On Wed, Feb 19, 2020 at 05:12:54PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> This series officializes the device tree bindings for the embedded
> Ethernet switch on NXP LS1028A (and for the reference design board).
> The driver has been in the tree since v5.4-rc6.
> 
> As per feedback received in v1, I've changed the DT bindings for the
> internal ports from "gmii" to "internal". So I would like the entire
> series to be merged through a single tree, be it net-next or devicetree.

Will applying the patches via different trees as normal cause any
issue like build breakage or regression on either tree?  Otherwise, I do
not see the series needs to go in through a single tree.

Shawn

> If this happens, I would like the other maintainer to acknowledge this
> fact and the patches themselves. Thanks.
> 
> Claudiu Manoil (2):
>   arm64: dts: fsl: ls1028a: add node for Felix switch
>   arm64: dts: fsl: ls1028a: enable switch PHYs on RDB
> 
> Vladimir Oltean (3):
>   arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC
>     RCIE
>   net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII
>   dt-bindings: net: dsa: ocelot: document the vsc9959 core
> 
>  .../devicetree/bindings/net/dsa/ocelot.txt    | 96 +++++++++++++++++++
>  .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 51 ++++++++++
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 85 +++++++++++++++-
>  drivers/net/dsa/ocelot/felix.c                |  3 +-
>  drivers/net/dsa/ocelot/felix_vsc9959.c        |  3 +-
>  5 files changed, 232 insertions(+), 6 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt
> 
> -- 
> 2.17.1
> 

Re: [PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[Vladimir Oltean]

Hi Shawn,

On Mon, 24 Feb 2020 at 08:32, Shawn Guo <shawnguo@kernel.org> wrote:
>
> On Wed, Feb 19, 2020 at 05:12:54PM +0200, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > As per feedback received in v1, I've changed the DT bindings for the
> > internal ports from "gmii" to "internal". So I would like the entire
> > series to be merged through a single tree, be it net-next or devicetree.
>
> Will applying the patches via different trees as normal cause any
> issue like build breakage or regression on either tree?  Otherwise, I do
> not see the series needs to go in through a single tree.
>
> Shawn
>

No, the point is that I've made some changes in the device tree
bindings validation in the driver, which make the driver without those
changes incompatible with the bindings themselves that I'm
introducing. So I would like the driver to be operational on the
actual commit that introduces the bindings, at least in your tree. I
don't expect merge conflicts to occur in that area of the code.

Thanks,
-Vladimir

Re: [PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[Shawn Guo]

On Mon, Feb 24, 2020 at 09:59:53AM +0200, Vladimir Oltean wrote:
> Hi Shawn,
> 
> On Mon, 24 Feb 2020 at 08:32, Shawn Guo <shawnguo@kernel.org> wrote:
> >
> > On Wed, Feb 19, 2020 at 05:12:54PM +0200, Vladimir Oltean wrote:
> > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > >
> > > As per feedback received in v1, I've changed the DT bindings for the
> > > internal ports from "gmii" to "internal". So I would like the entire
> > > series to be merged through a single tree, be it net-next or devicetree.
> >
> > Will applying the patches via different trees as normal cause any
> > issue like build breakage or regression on either tree?  Otherwise, I do
> > not see the series needs to go in through a single tree.
> >
> > Shawn
> >
> 
> No, the point is that I've made some changes in the device tree
> bindings validation in the driver, which make the driver without those
> changes incompatible with the bindings themselves that I'm
> introducing. So I would like the driver to be operational on the
> actual commit that introduces the bindings, at least in your tree. I
> don't expect merge conflicts to occur in that area of the code.

The dt-bindings patch is supposed to go through subsystem tree together
with driver changes by nature.  That said, patch #1 and #2 are for
David, and I will pick up the rest (DTS ones).

Shawn

Re: [PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[Vladimir Oltean]

On Mon, 24 Feb 2020 at 10:48, Shawn Guo <shawnguo@kernel.org> wrote:
>
> On Mon, Feb 24, 2020 at 09:59:53AM +0200, Vladimir Oltean wrote:
> > Hi Shawn,
> >
> > On Mon, 24 Feb 2020 at 08:32, Shawn Guo <shawnguo@kernel.org> wrote:
> > >
> > > On Wed, Feb 19, 2020 at 05:12:54PM +0200, Vladimir Oltean wrote:
> > > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > > >
> > > > As per feedback received in v1, I've changed the DT bindings for the
> > > > internal ports from "gmii" to "internal". So I would like the entire
> > > > series to be merged through a single tree, be it net-next or devicetree.
> > >
> > > Will applying the patches via different trees as normal cause any
> > > issue like build breakage or regression on either tree?  Otherwise, I do
> > > not see the series needs to go in through a single tree.
> > >
> > > Shawn
> > >
> >
> > No, the point is that I've made some changes in the device tree
> > bindings validation in the driver, which make the driver without those
> > changes incompatible with the bindings themselves that I'm
> > introducing. So I would like the driver to be operational on the
> > actual commit that introduces the bindings, at least in your tree. I
> > don't expect merge conflicts to occur in that area of the code.
>
> The dt-bindings patch is supposed to go through subsystem tree together
> with driver changes by nature.  That said, patch #1 and #2 are for
> David, and I will pick up the rest (DTS ones).
>
> Shawn

Ok, any further comments on the series or should I respin after your
feedback regarding the commit message prefix and the status =
"disabled" ordering?

-Vladimir

Re: [PATCH v2 net-next/devicetree 0/5] DT bindings for Felix DSA switch on LS1028A

[Vladimir Oltean]

On Mon, 24 Feb 2020 at 10:50, Vladimir Oltean <olteanv@gmail.com> wrote:
>
> On Mon, 24 Feb 2020 at 10:48, Shawn Guo <shawnguo@kernel.org> wrote:
> >
> > On Mon, Feb 24, 2020 at 09:59:53AM +0200, Vladimir Oltean wrote:
> > > Hi Shawn,
> > >
> > > On Mon, 24 Feb 2020 at 08:32, Shawn Guo <shawnguo@kernel.org> wrote:
> > > >
> > > > On Wed, Feb 19, 2020 at 05:12:54PM +0200, Vladimir Oltean wrote:
> > > > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > > > >
> > > > > As per feedback received in v1, I've changed the DT bindings for the
> > > > > internal ports from "gmii" to "internal". So I would like the entire
> > > > > series to be merged through a single tree, be it net-next or devicetree.
> > > >
> > > > Will applying the patches via different trees as normal cause any
> > > > issue like build breakage or regression on either tree?  Otherwise, I do
> > > > not see the series needs to go in through a single tree.
> > > >
> > > > Shawn
> > > >
> > >
> > > No, the point is that I've made some changes in the device tree
> > > bindings validation in the driver, which make the driver without those
> > > changes incompatible with the bindings themselves that I'm
> > > introducing. So I would like the driver to be operational on the
> > > actual commit that introduces the bindings, at least in your tree. I
> > > don't expect merge conflicts to occur in that area of the code.
> >
> > The dt-bindings patch is supposed to go through subsystem tree together
> > with driver changes by nature.  That said, patch #1 and #2 are for
> > David, and I will pick up the rest (DTS ones).
> >
> > Shawn
>
> Ok, any further comments on the series or should I respin after your
> feedback regarding the commit message prefix and the status =
> "disabled" ordering?
>
> -Vladimir

By the way all your comments have been on v2 and I've sent v3 already.
So this series is superseded.

Regards,
-Vladimir