* [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC @ 2023-12-01 12:14 Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng ` (6 more replies) 0 siblings, 7 replies; 26+ messages in thread From: Sia Jee Heng @ 2023-12-01 12:14 UTC (permalink / raw) To: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan StarFive JH8100 SoC consists of 4 RISC-V performance Cores (Dubhe-90) and 2 RISC-V energy efficient cores (Dubhe-80). It also features various interfaces such as DDR4, Gbit-Ether, CAN, USB 3.2, SD/MMC, etc., making it ideal for high-performance computing scenarios. This patch series introduces initial SoC DTSI support for the StarFive JH8100 SoC. The relevant dt-binding documentation has been updated accordingly. Below is the list of IP blocks added in the initial SoC DTSI, which can be used for booting via initramfs on FPGA: - StarFive Dubhe-80 CPU - StarFive Dubhe-90 CPU - PLIC - CLINT - UART The primary goal is to include foundational patches so that additional drivers can be built on top of this framework. Changes since v2: - Resolved CI build error (dtb_warn_rv64.sh) in patch 6. - Introduced a new line in patch 6 to distinguish between platforms. - Reordered the CPU sequence in patch 1. - Corrected a line deletion in patch 2. - Removed the description and rearranged the sequence of items in patch 5. - Added 'Acked-by' from Conor for patches 1, 2, 3 and 4. Changes since v1: - Dropped patch 5. - Moved timebase-frequency from .dts to .dtsi. - Moved soc node from .dts to .dtsi. - Revised the title for the dt-binding document by removing Xilinx wording. - Added a full stop to the end of the commit messages. - Removed extra blank lines. - Used hyphen for a node name. - Added more recipients to the mailing list. Sia Jee Heng (6): dt-bindings: riscv: Add StarFive Dubhe compatibles dt-bindings: riscv: Add StarFive JH8100 SoC dt-bindings: timer: Add StarFive JH8100 clint dt-bindings: interrupt-controller: Add StarFive JH8100 plic dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART riscv: dts: starfive: Add initial StarFive JH8100 device tree .../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/cpus.yaml | 2 + .../devicetree/bindings/riscv/starfive.yaml | 4 + .../devicetree/bindings/serial/cdns,uart.yaml | 3 + .../bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/starfive/Makefile | 2 + arch/riscv/boot/dts/starfive/jh8100-evb.dts | 28 ++ arch/riscv/boot/dts/starfive/jh8100.dtsi | 378 ++++++++++++++++++ 8 files changed, 419 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi base-commit: 994d5c58e50e91bb02c7be4a91d5186292a895c8 -- 2.34.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles 2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng @ 2023-12-01 12:14 ` Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC Sia Jee Heng ` (5 subsequent siblings) 6 siblings, 0 replies; 26+ messages in thread From: Sia Jee Heng @ 2023-12-01 12:14 UTC (permalink / raw) To: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan, Conor Dooley Add new compatible strings for Dubhe-80 and Dubhe-90. These are RISC-V cpu core from StarFive Technology and are used in StarFive JH8100 SoC. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f392e367d673..0dd2d2ce4fcd 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -45,6 +45,8 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - starfive,dubhe-80 + - starfive,dubhe-90 - thead,c906 - thead,c910 - thead,c920 -- 2.34.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng @ 2023-12-01 12:14 ` Sia Jee Heng 2023-12-13 12:43 ` Conor Dooley 2023-12-01 12:14 ` [PATCH v3 3/6] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng ` (4 subsequent siblings) 6 siblings, 1 reply; 26+ messages in thread From: Sia Jee Heng @ 2023-12-01 12:14 UTC (permalink / raw) To: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan, Conor Dooley Add device tree bindings for the StarFive JH8100 RISC-V SoC. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index cc4d92f0a1bf..12d7844232b8 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -30,6 +30,10 @@ properties: - starfive,visionfive-2-v1.3b - const: starfive,jh7110 + - items: + - enum: + - starfive,jh8100-evb + - const: starfive,jh8100 additionalProperties: true ... -- 2.34.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-12-01 12:14 ` [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC Sia Jee Heng @ 2023-12-13 12:43 ` Conor Dooley 2023-12-13 13:24 ` Leyfoon Tan 2023-12-14 0:36 ` JeeHeng Sia 0 siblings, 2 replies; 26+ messages in thread From: Conor Dooley @ 2023-12-13 12:43 UTC (permalink / raw) To: Sia Jee Heng Cc: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew, devicetree, linux-riscv, linux-kernel, leyfoon.tan, Conor Dooley [-- Attachment #1: Type: text/plain, Size: 1554 bytes --] On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote: > Add device tree bindings for the StarFive JH8100 RISC-V SoC. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml > index cc4d92f0a1bf..12d7844232b8 100644 > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml > @@ -30,6 +30,10 @@ properties: > - starfive,visionfive-2-v1.3b > - const: starfive,jh7110 > > + - items: > + - enum: > + - starfive,jh8100-evb Hmm, reading some of the other threads it appears that the evaluation platform that you guys have is actually just an FPGA? Could you please provide more information as to what this "evb" actually is? If it is just an FPGA-based evaluation platform I don't think that we want to merge patches for the platform. I'm fine with patches adding peripheral support, but the soc/board dts files and things like pinctrl or clock drivers I am not keen on. Perhaps Emil also has an opinion on this. Thanks, Conor. > + - const: starfive,jh8100 > additionalProperties: true > > ... > -- > 2.34.1 > > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-12-13 12:43 ` Conor Dooley @ 2023-12-13 13:24 ` Leyfoon Tan 2023-12-14 0:36 ` JeeHeng Sia 1 sibling, 0 replies; 26+ messages in thread From: Leyfoon Tan @ 2023-12-13 13:24 UTC (permalink / raw) To: Conor Dooley, JeeHeng Sia Cc: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, anup, gregkh, jirislaby, michal.simek, Michael Zhu, drew, devicetree, linux-riscv, linux-kernel, Conor Dooley > -----Original Message----- > From: Conor Dooley <conor@kernel.org> > Sent: Wednesday, December 13, 2023 8:43 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; > palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; > tglx@linutronix.de; anup@brainfault.org; gregkh@linuxfoundation.org; > jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > <michael.zhu@starfivetech.com>; drew@beagleboard.org; > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Conor > Dooley <conor.dooley@microchip.com> > Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC > > On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote: > > Add device tree bindings for the StarFive JH8100 RISC-V SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml > > b/Documentation/devicetree/bindings/riscv/starfive.yaml > > index cc4d92f0a1bf..12d7844232b8 100644 > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml > > @@ -30,6 +30,10 @@ properties: > > - starfive,visionfive-2-v1.3b > > - const: starfive,jh7110 > > > > + - items: > > + - enum: > > + - starfive,jh8100-evb > > Hmm, reading some of the other threads it appears that the evaluation > platform that you guys have is actually just an FPGA? Could you please provide > more information as to what this "evb" actually is? > > If it is just an FPGA-based evaluation platform I don't think that we want to > merge patches for the platform. I'm fine with patches adding peripheral > support, but the soc/board dts files and things like pinctrl or clock drivers I am > not keen on. > Perhaps Emil also has an opinion on this. > > Thanks, > Conor. We have been testing on the FPGA/emulator for pre-silicon validation. It will have real silicon SoC next year. Regards Ley Foon ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-12-13 12:43 ` Conor Dooley 2023-12-13 13:24 ` Leyfoon Tan @ 2023-12-14 0:36 ` JeeHeng Sia 2023-12-14 16:22 ` Conor Dooley 1 sibling, 1 reply; 26+ messages in thread From: JeeHeng Sia @ 2023-12-14 0:36 UTC (permalink / raw) To: Conor Dooley Cc: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, anup, gregkh, jirislaby, michal.simek, Michael Zhu, drew, devicetree, linux-riscv, linux-kernel, Leyfoon Tan, Conor Dooley > -----Original Message----- > From: Conor Dooley <conor@kernel.org> > Sent: Wednesday, December 13, 2023 8:43 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > <michael.zhu@starfivetech.com>; drew@beagleboard.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Conor Dooley <conor.dooley@microchip.com> > Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC > > On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote: > > Add device tree bindings for the StarFive JH8100 RISC-V SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml > > index cc4d92f0a1bf..12d7844232b8 100644 > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml > > @@ -30,6 +30,10 @@ properties: > > - starfive,visionfive-2-v1.3b > > - const: starfive,jh7110 > > > > + - items: > > + - enum: > > + - starfive,jh8100-evb > > Hmm, reading some of the other threads it appears that the evaluation > platform that you guys have is actually just an FPGA? Could you please > provide more information as to what this "evb" actually is? > > If it is just an FPGA-based evaluation platform I don't think that we > want to merge patches for the platform. I'm fine with patches adding > peripheral support, but the soc/board dts files and things like pinctrl > or clock drivers I am not keen on. > Perhaps Emil also has an opinion on this. Eco the same reply here. I am not sure what you mean. We verified on FPGA & Emulator, and the logic is pretty much close to the real silicon. I did mention that in the cover letter as well. I am new to Linux, so I am wondering if there is a Linux upstream guideline mentioning that pre-silicon software is not allowed to upstream? Hope there is an updated Linux upstream guideline that benefit other vendors. > > Thanks, > Conor. > > > + - const: starfive,jh8100 > > additionalProperties: true > > > > ... > > -- > > 2.34.1 > > > > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-12-14 0:36 ` JeeHeng Sia @ 2023-12-14 16:22 ` Conor Dooley 2023-12-14 17:20 ` Palmer Dabbelt 0 siblings, 1 reply; 26+ messages in thread From: Conor Dooley @ 2023-12-14 16:22 UTC (permalink / raw) To: JeeHeng Sia Cc: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, anup, gregkh, jirislaby, michal.simek, Michael Zhu, drew, devicetree, linux-riscv, linux-kernel, Leyfoon Tan, Conor Dooley [-- Attachment #1: Type: text/plain, Size: 4374 bytes --] On Thu, Dec 14, 2023 at 12:36:57AM +0000, JeeHeng Sia wrote: > > > > -----Original Message----- > > From: Conor Dooley <conor@kernel.org> > > Sent: Wednesday, December 13, 2023 8:43 PM > > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; > > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; > > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > > <michael.zhu@starfivetech.com>; drew@beagleboard.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux- > > kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Conor Dooley <conor.dooley@microchip.com> > > Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC > > > > On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote: > > > Add device tree bindings for the StarFive JH8100 RISC-V SoC. > > > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > > > --- > > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ > > > 1 file changed, 4 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml > > > index cc4d92f0a1bf..12d7844232b8 100644 > > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml > > > @@ -30,6 +30,10 @@ properties: > > > - starfive,visionfive-2-v1.3b > > > - const: starfive,jh7110 > > > > > > + - items: > > > + - enum: > > > + - starfive,jh8100-evb > > > > Hmm, reading some of the other threads it appears that the evaluation > > platform that you guys have is actually just an FPGA? Could you please > > provide more information as to what this "evb" actually is? > > > > If it is just an FPGA-based evaluation platform I don't think that we > > want to merge patches for the platform. I'm fine with patches adding > > peripheral support, but the soc/board dts files and things like pinctrl > > or clock drivers I am not keen on. > > Perhaps Emil also has an opinion on this. > Eco the same reply here. I am not sure what you mean. We verified on FPGA & Emulator, > and the logic is pretty much close to the real silicon. "Pretty much close" That doesn't give me confidence. The compatible should uniquely identify an SoC, but if it is used for both the actual SoC and for something "pretty much close" to the actual SoC then that does not hold. > I did mention that in the cover letter as well. Ah apologies for missing that. I try to read cover letters but the volume of mail gets to me at times. > I am new to Linux, so I am wondering if there is a Linux upstream guideline mentioning > that pre-silicon software is not allowed to upstream? I wouldn't say that this is the case, but things like clock and pinctrl drivers are the sort of things that are likely to vary in your "pretty much close" as that is the kind of thing that change for your final integration, versus a more "standalone" peripheral. For dts stuff, in RISC-V at least, we've been operating so far on the basis that systems implemented entirely on an FPGA are not suitable for inclusion in mainline. I would say that this can probably be relaxed to allow systems where there are publicly available, versioned, designs or bitstreams that are widely used that these devicetrees correspond to. This would suit something like if AMD published a bitstream using one of their new MicroblazeV cpu cores as a sort of "reference design". > Hope there is an updated Linux > upstream guideline that benefit other vendors. I have no idea if there is one or not. I think it generally varies on individual maintainers etc, and for something like a dts it comes down to the platform maintainer (Emil) I suppose. Sending stuff out before your SoC has been produced is really great though, so it is a fine line to avoid discouraging something we really like to see. Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-12-14 16:22 ` Conor Dooley @ 2023-12-14 17:20 ` Palmer Dabbelt 2023-12-15 1:49 ` JeeHeng Sia 0 siblings, 1 reply; 26+ messages in thread From: Palmer Dabbelt @ 2023-12-14 17:20 UTC (permalink / raw) To: Conor Dooley Cc: jeeheng.sia, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, Paul Walmsley, aou, daniel.lezcano, tglx, anup, Greg KH, jirislaby, michal.simek, michael.zhu, drew, devicetree, linux-riscv, linux-kernel, leyfoon.tan, Conor Dooley On Thu, 14 Dec 2023 08:22:29 PST (-0800), Conor Dooley wrote: > On Thu, Dec 14, 2023 at 12:36:57AM +0000, JeeHeng Sia wrote: >> >> >> > -----Original Message----- >> > From: Conor Dooley <conor@kernel.org> >> > Sent: Wednesday, December 13, 2023 8:43 PM >> > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> >> > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; >> > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; >> > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu >> > <michael.zhu@starfivetech.com>; drew@beagleboard.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux- >> > kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Conor Dooley <conor.dooley@microchip.com> >> > Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC >> > >> > On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote: >> > > Add device tree bindings for the StarFive JH8100 RISC-V SoC. >> > > >> > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> >> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> >> > > Acked-by: Conor Dooley <conor.dooley@microchip.com> >> > > --- >> > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ >> > > 1 file changed, 4 insertions(+) >> > > >> > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml >> > > index cc4d92f0a1bf..12d7844232b8 100644 >> > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml >> > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml >> > > @@ -30,6 +30,10 @@ properties: >> > > - starfive,visionfive-2-v1.3b >> > > - const: starfive,jh7110 >> > > >> > > + - items: >> > > + - enum: >> > > + - starfive,jh8100-evb >> > >> > Hmm, reading some of the other threads it appears that the evaluation >> > platform that you guys have is actually just an FPGA? Could you please >> > provide more information as to what this "evb" actually is? >> > >> > If it is just an FPGA-based evaluation platform I don't think that we >> > want to merge patches for the platform. I'm fine with patches adding >> > peripheral support, but the soc/board dts files and things like pinctrl >> > or clock drivers I am not keen on. >> > Perhaps Emil also has an opinion on this. >> Eco the same reply here. I am not sure what you mean. We verified on FPGA & Emulator, >> and the logic is pretty much close to the real silicon. > > "Pretty much close" That doesn't give me confidence. The compatible > should uniquely identify an SoC, but if it is used for both the actual > SoC and for something "pretty much close" to the actual SoC then that > does not hold. Ya, trying to have some pre-silicon FPGA-based platform alias with the real chip is a repice for disaster. >> I did mention that in the cover letter as well. > > Ah apologies for missing that. I try to read cover letters but the > volume of mail gets to me at times. > >> I am new to Linux, so I am wondering if there is a Linux upstream guideline mentioning >> that pre-silicon software is not allowed to upstream? > > I wouldn't say that this is the case, but things like clock and pinctrl > drivers are the sort of things that are likely to vary in your "pretty > much close" as that is the kind of thing that change for your final > integration, versus a more "standalone" peripheral. Yep, and since integration issues in the ASIC blocks can end up manifesting as SW-visible behavior in nearby blocks it's hard to just pull out the peripherals -- we sort of try by getting the DT topology to match the SOC, but there's always some mismatches. > For dts stuff, in RISC-V at least, we've been operating so far on the > basis that systems implemented entirely on an FPGA are not suitable for > inclusion in mainline. I would say that this can probably be relaxed to > allow systems where there are publicly available, versioned, designs or > bitstreams that are widely used that these devicetrees correspond to. > This would suit something like if AMD published a bitstream using one > of their new MicroblazeV cpu cores as a sort of "reference design". FPGAs are definately in a grey area, but that's been my mindset as well. For me it's less about FPGA vs ASIC (or any other manufacturing technology in between) and more about whether something is being used publicly. Specifically: is the FPGA used for internal pre-silicon work or is it some publicly availiable system? The versioning stuff is also important, but we need that for ASICs as well since they can be re-spun. >> Hope there is an updated Linux >> upstream guideline that benefit other vendors. > > I have no idea if there is one or not. I think it generally varies on > individual maintainers etc, and for something like a dts it comes down > to the platform maintainer (Emil) I suppose. Sending stuff out before > your SoC has been produced is really great though, so it is a fine line > to avoid discouraging something we really like to see. IIRC we've got some stuff written for arch/riscv somewhere in Documentation, but the hardest part here is that each subsystem is going to have different policies so it's kind of hard to try and come up with a general rule. > Cheers, > Conor. ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-12-14 17:20 ` Palmer Dabbelt @ 2023-12-15 1:49 ` JeeHeng Sia 2023-12-16 12:06 ` Conor Dooley 0 siblings, 1 reply; 26+ messages in thread From: JeeHeng Sia @ 2023-12-15 1:49 UTC (permalink / raw) To: Palmer Dabbelt, Conor Dooley Cc: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, Paul Walmsley, aou, daniel.lezcano, tglx, anup, Greg KH, jirislaby, michal.simek, Michael Zhu, drew, devicetree, linux-riscv, linux-kernel, Leyfoon Tan, Conor Dooley > -----Original Message----- > From: Palmer Dabbelt <palmer@dabbelt.com> > Sent: Friday, December 15, 2023 1:21 AM > To: Conor Dooley <conor@kernel.org> > Cc: JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > krzk@kernel.org; conor+dt@kernel.org; Paul Walmsley <paul.walmsley@sifive.com>; aou@eecs.berkeley.edu; > daniel.lezcano@linaro.org; tglx@linutronix.de; anup@brainfault.org; Greg KH <gregkh@linuxfoundation.org>; jirislaby@kernel.org; > michal.simek@amd.com; Michael Zhu <michael.zhu@starfivetech.com>; drew@beagleboard.org; devicetree@vger.kernel.org; linux- > riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Conor Dooley > <conor.dooley@microchip.com> > Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC > > On Thu, 14 Dec 2023 08:22:29 PST (-0800), Conor Dooley wrote: > > On Thu, Dec 14, 2023 at 12:36:57AM +0000, JeeHeng Sia wrote: > >> > >> > >> > -----Original Message----- > >> > From: Conor Dooley <conor@kernel.org> > >> > Sent: Wednesday, December 13, 2023 8:43 PM > >> > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > >> > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; > >> > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; > >> > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > >> > <michael.zhu@starfivetech.com>; drew@beagleboard.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux- > >> > kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Conor Dooley <conor.dooley@microchip.com> > >> > Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC > >> > > >> > On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote: > >> > > Add device tree bindings for the StarFive JH8100 RISC-V SoC. > >> > > > >> > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > >> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > >> > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > >> > > --- > >> > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++ > >> > > 1 file changed, 4 insertions(+) > >> > > > >> > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml > >> > > index cc4d92f0a1bf..12d7844232b8 100644 > >> > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml > >> > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml > >> > > @@ -30,6 +30,10 @@ properties: > >> > > - starfive,visionfive-2-v1.3b > >> > > - const: starfive,jh7110 > >> > > > >> > > + - items: > >> > > + - enum: > >> > > + - starfive,jh8100-evb > >> > > >> > Hmm, reading some of the other threads it appears that the evaluation > >> > platform that you guys have is actually just an FPGA? Could you please > >> > provide more information as to what this "evb" actually is? > >> > > >> > If it is just an FPGA-based evaluation platform I don't think that we > >> > want to merge patches for the platform. I'm fine with patches adding > >> > peripheral support, but the soc/board dts files and things like pinctrl > >> > or clock drivers I am not keen on. > >> > Perhaps Emil also has an opinion on this. > >> Eco the same reply here. I am not sure what you mean. We verified on FPGA & Emulator, > >> and the logic is pretty much close to the real silicon. > > > > "Pretty much close" That doesn't give me confidence. The compatible > > should uniquely identify an SoC, but if it is used for both the actual > > SoC and for something "pretty much close" to the actual SoC then that > > does not hold. > > Ya, trying to have some pre-silicon FPGA-based platform alias with the > real chip is a repice for disaster. > > >> I did mention that in the cover letter as well. > > > > Ah apologies for missing that. I try to read cover letters but the > > volume of mail gets to me at times. > > > >> I am new to Linux, so I am wondering if there is a Linux upstream guideline mentioning > >> that pre-silicon software is not allowed to upstream? > > > > I wouldn't say that this is the case, but things like clock and pinctrl > > drivers are the sort of things that are likely to vary in your "pretty > > much close" as that is the kind of thing that change for your final > > integration, versus a more "standalone" peripheral. > > Yep, and since integration issues in the ASIC blocks can end up > manifesting as SW-visible behavior in nearby blocks it's hard to just > pull out the peripherals -- we sort of try by getting the DT topology to > match the SOC, but there's always some mismatches. Thank you everyone. I think I get your point. Is it possible to send "RFC" patches for things like DT, clk&reset, and pinctrl? Please note that these have been tested on FPGA/Emulator. > > > For dts stuff, in RISC-V at least, we've been operating so far on the > > basis that systems implemented entirely on an FPGA are not suitable for > > inclusion in mainline. I would say that this can probably be relaxed to > > allow systems where there are publicly available, versioned, designs or > > bitstreams that are widely used that these devicetrees correspond to. > > This would suit something like if AMD published a bitstream using one > > of their new MicroblazeV cpu cores as a sort of "reference design". > > FPGAs are definately in a grey area, but that's been my mindset as well. > For me it's less about FPGA vs ASIC (or any other manufacturing > technology in between) and more about whether something is being used > publicly. Specifically: is the FPGA used for internal pre-silicon work > or is it some publicly availiable system? It is internal. > > The versioning stuff is also important, but we need that for ASICs as > well since they can be re-spun. > > >> Hope there is an updated Linux > >> upstream guideline that benefit other vendors. > > > > I have no idea if there is one or not. I think it generally varies on > > individual maintainers etc, and for something like a dts it comes down > > to the platform maintainer (Emil) I suppose. Sending stuff out before > > your SoC has been produced is really great though, so it is a fine line > > to avoid discouraging something we really like to see. > > IIRC we've got some stuff written for arch/riscv somewhere in > Documentation, but the hardest part here is that each subsystem is going > to have different policies so it's kind of hard to try and come up with > a general rule. > > > Cheers, > > Conor. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC 2023-12-15 1:49 ` JeeHeng Sia @ 2023-12-16 12:06 ` Conor Dooley 0 siblings, 0 replies; 26+ messages in thread From: Conor Dooley @ 2023-12-16 12:06 UTC (permalink / raw) To: JeeHeng Sia Cc: Palmer Dabbelt, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, Paul Walmsley, aou, daniel.lezcano, tglx, anup, Greg KH, jirislaby, michal.simek, Michael Zhu, drew, devicetree, linux-riscv, linux-kernel, Leyfoon Tan, Conor Dooley [-- Attachment #1: Type: text/plain, Size: 293 bytes --] On Fri, Dec 15, 2023 at 01:49:02AM +0000, JeeHeng Sia wrote: > Thank you everyone. I think I get your point. Is it possible to send "RFC" > patches for things like DT, clk&reset, and pinctrl? Please note that > these have been tested on FPGA/Emulator. For sure you can send them as RFC, yes. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 3/6] dt-bindings: timer: Add StarFive JH8100 clint 2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC Sia Jee Heng @ 2023-12-01 12:14 ` Sia Jee Heng 2023-12-04 17:36 ` Daniel Lezcano 2024-01-18 19:23 ` [tip: timers/core] " tip-bot2 for Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 4/6] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng ` (3 subsequent siblings) 6 siblings, 2 replies; 26+ messages in thread From: Sia Jee Heng @ 2023-12-01 12:14 UTC (permalink / raw) To: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan, Conor Dooley Add compatible string for the StarFive JH8100 clint. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index e8be6c470364..01254261e156 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - sifive,fu540-c000-clint # SiFive FU540 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 + - starfive,jh8100-clint # StarFive JH8100 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - enum: -- 2.34.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v3 3/6] dt-bindings: timer: Add StarFive JH8100 clint 2023-12-01 12:14 ` [PATCH v3 3/6] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng @ 2023-12-04 17:36 ` Daniel Lezcano 2024-01-18 19:23 ` [tip: timers/core] " tip-bot2 for Sia Jee Heng 1 sibling, 0 replies; 26+ messages in thread From: Daniel Lezcano @ 2023-12-04 17:36 UTC (permalink / raw) To: Sia Jee Heng, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, leyfoon.tan, Conor Dooley On 01/12/2023 13:14, Sia Jee Heng wrote: > Add compatible string for the StarFive JH8100 clint. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- Applied 3/6, thanks -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog ^ permalink raw reply [flat|nested] 26+ messages in thread
* [tip: timers/core] dt-bindings: timer: Add StarFive JH8100 clint 2023-12-01 12:14 ` [PATCH v3 3/6] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng 2023-12-04 17:36 ` Daniel Lezcano @ 2024-01-18 19:23 ` tip-bot2 for Sia Jee Heng 1 sibling, 0 replies; 26+ messages in thread From: tip-bot2 for Sia Jee Heng @ 2024-01-18 19:23 UTC (permalink / raw) To: linux-tip-commits Cc: Sia Jee Heng, Ley Foon Tan, Conor Dooley, Daniel Lezcano, x86, linux-kernel The following commit has been merged into the timers/core branch of tip: Commit-ID: e0cf60151e6317c654c42ba0e8b1fb6ff477489a Gitweb: https://git.kernel.org/tip/e0cf60151e6317c654c42ba0e8b1fb6ff477489a Author: Sia Jee Heng <jeeheng.sia@starfivetech.com> AuthorDate: Fri, 01 Dec 2023 20:14:07 +08:00 Committer: Daniel Lezcano <daniel.lezcano@linaro.org> CommitterDate: Wed, 27 Dec 2023 15:37:11 +01:00 dt-bindings: timer: Add StarFive JH8100 clint Add compatible string for the StarFive JH8100 clint. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20231201121410.95298-4-jeeheng.sia@starfivetech.com --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index e8be6c4..0125426 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - sifive,fu540-c000-clint # SiFive FU540 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 + - starfive,jh8100-clint # StarFive JH8100 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - enum: ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 4/6] dt-bindings: interrupt-controller: Add StarFive JH8100 plic 2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng ` (2 preceding siblings ...) 2023-12-01 12:14 ` [PATCH v3 3/6] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng @ 2023-12-01 12:14 ` Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 5/6] dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART Sia Jee Heng ` (2 subsequent siblings) 6 siblings, 0 replies; 26+ messages in thread From: Sia Jee Heng @ 2023-12-01 12:14 UTC (permalink / raw) To: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan, Conor Dooley Add compatible string for StarFive JH8100 plic. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 0c07e8dda445..8f5c6044cef7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -61,6 +61,7 @@ properties: - sifive,fu540-c000-plic - starfive,jh7100-plic - starfive,jh7110-plic + - starfive,jh8100-plic - const: sifive,plic-1.0.0 - items: - enum: -- 2.34.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 5/6] dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART 2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng ` (3 preceding siblings ...) 2023-12-01 12:14 ` [PATCH v3 4/6] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng @ 2023-12-01 12:14 ` Sia Jee Heng 2023-12-01 15:46 ` Conor Dooley 2023-12-01 12:14 ` [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng 2023-12-06 16:45 ` [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Conor Dooley 6 siblings, 1 reply; 26+ messages in thread From: Sia Jee Heng @ 2023-12-01 12:14 UTC (permalink / raw) To: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan Add new compatible string for UART in the StarFive JH8100 SoC. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- Documentation/devicetree/bindings/serial/cdns,uart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index e35ad1109efc..07732ae60007 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -12,6 +12,9 @@ maintainers: properties: compatible: oneOf: + - items: + - const: starfive,jh8100-uart + - const: cdns,uart-r1p8 - description: UART controller for Zynq-7xxx SoC items: - const: xlnx,xuartps -- 2.34.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v3 5/6] dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART 2023-12-01 12:14 ` [PATCH v3 5/6] dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART Sia Jee Heng @ 2023-12-01 15:46 ` Conor Dooley 0 siblings, 0 replies; 26+ messages in thread From: Conor Dooley @ 2023-12-01 15:46 UTC (permalink / raw) To: Sia Jee Heng Cc: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew, devicetree, linux-riscv, linux-kernel, leyfoon.tan [-- Attachment #1: Type: text/plain, Size: 1068 bytes --] On Fri, Dec 01, 2023 at 08:14:09PM +0800, Sia Jee Heng wrote: > Add new compatible string for UART in the StarFive JH8100 SoC. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor. > --- > Documentation/devicetree/bindings/serial/cdns,uart.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml > index e35ad1109efc..07732ae60007 100644 > --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml > +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml > @@ -12,6 +12,9 @@ maintainers: > properties: > compatible: > oneOf: > + - items: > + - const: starfive,jh8100-uart > + - const: cdns,uart-r1p8 > - description: UART controller for Zynq-7xxx SoC > items: > - const: xlnx,xuartps > -- > 2.34.1 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng ` (4 preceding siblings ...) 2023-12-01 12:14 ` [PATCH v3 5/6] dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART Sia Jee Heng @ 2023-12-01 12:14 ` Sia Jee Heng 2023-12-08 12:08 ` Shengyu Qu 2023-12-08 16:05 ` Emil Renner Berthing 2023-12-06 16:45 ` [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Conor Dooley 6 siblings, 2 replies; 26+ messages in thread From: Sia Jee Heng @ 2023-12-01 12:14 UTC (permalink / raw) To: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, jeeheng.sia, leyfoon.tan Add initial device tree for the StarFive JH8100 RISC-V SoC. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- arch/riscv/boot/dts/starfive/Makefile | 2 + arch/riscv/boot/dts/starfive/jh8100-evb.dts | 28 ++ arch/riscv/boot/dts/starfive/jh8100.dtsi | 378 ++++++++++++++++++++ 3 files changed, 408 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 0141504c0f5c..ef5c7331c7ec 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb + +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts new file mode 100644 index 000000000000..c16bc25d8988 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +#include "jh8100.dtsi" + +/ { + model = "StarFive JH8100 EVB"; + compatible = "starfive,jh8100-evb", "starfive,jh8100"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x2 0x00000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi new file mode 100644 index 000000000000..f26aff5c1ddf --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +/dts-v1/; + +/ { + compatible = "starfive,jh8100"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <4000000>; + + cpu0: cpu@0 { + compatible = "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz = <768>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c0>; + reg = <0x0>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu1: cpu@1 { + compatible = "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz = <768>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c1>; + reg = <0x1>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu2: cpu@2 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x2>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu3: cpu@3 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x3>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu4: cpu@4 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x4>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu5: cpu@5 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x5>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu1>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + + core2 { + cpu = <&cpu4>; + }; + + core3 { + cpu = <&cpu5>; + }; + }; + }; + + l2c0: cache-controller-0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2c1: cache-controller-1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2c2: cache-controller-2{ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <4096>; + cache-size = <0x200000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: cache-controller-3 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + }; + }; + + clk_uart: clk-uart { + compatible = "fixed-clock"; /* Initial clock handler for UART */ + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: clint@2000000 { + compatible = "starfive,jh8100-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "starfive,jh8100-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x0c000000 0x0 0x4000000>; + riscv,ndev = <200>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>; + }; + + uart0: serial@12160000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x12160000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <67>; + status = "disabled"; + }; + + uart1: serial@12170000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x12170000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <68>; + status = "disabled"; + }; + + uart2: serial@12180000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x12180000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <69>; + status = "disabled"; + }; + + uart3: serial@12190000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x12190000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <70>; + status = "disabled"; + }; + + uart4: serial@121a0000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x121a0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <71>; + status = "disabled"; + }; + + uart5: serial@127d0000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x127d0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <72>; + status = "disabled"; + }; + + uart6: serial@127e0000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x127e0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <73>; + status = "disabled"; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-01 12:14 ` [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng @ 2023-12-08 12:08 ` Shengyu Qu 2023-12-11 1:38 ` JeeHeng Sia 2023-12-08 16:05 ` Emil Renner Berthing 1 sibling, 1 reply; 26+ messages in thread From: Shengyu Qu @ 2023-12-08 12:08 UTC (permalink / raw) To: Sia Jee Heng, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: wiagn233, devicetree, linux-riscv, linux-kernel, leyfoon.tan Hello Sia, Does the dubhe-80 cores actually support vector? Or vector support doesn't exist on actual silicon? Best regards, Shengyu > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/Makefile | 2 + > arch/riscv/boot/dts/starfive/jh8100-evb.dts | 28 ++ > arch/riscv/boot/dts/starfive/jh8100.dtsi | 378 ++++++++++++++++++++ > 3 files changed, 408 insertions(+) > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts > create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi > > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile > index 0141504c0f5c..ef5c7331c7ec 100644 > --- a/arch/riscv/boot/dts/starfive/Makefile > +++ b/arch/riscv/boot/dts/starfive/Makefile > @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb > + > +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb > diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > new file mode 100644 > index 000000000000..c16bc25d8988 > --- /dev/null > +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > @@ -0,0 +1,28 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > + */ > + > +#include "jh8100.dtsi" > + > +/ { > + model = "StarFive JH8100 EVB"; > + compatible = "starfive,jh8100-evb", "starfive,jh8100"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0x0 0x40000000 0x2 0x00000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi > new file mode 100644 > index 000000000000..f26aff5c1ddf > --- /dev/null > +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi > @@ -0,0 +1,378 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > + */ > + > +/dts-v1/; > + > +/ { > + compatible = "starfive,jh8100"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <4000000>; > + > + cpu0: cpu@0 { > + compatible = "starfive,dubhe-80", "riscv"; > + capacity-dmips-mhz = <768>; > + d-cache-block-size = <64>; > + d-cache-sets = <512>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <512>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c0>; > + reg = <0x0>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu1: cpu@1 { > + compatible = "starfive,dubhe-80", "riscv"; > + capacity-dmips-mhz = <768>; > + d-cache-block-size = <64>; > + d-cache-sets = <512>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <512>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c1>; > + reg = <0x1>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu1_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu2: cpu@2 { > + compatible = "starfive,dubhe-90", "riscv"; > + capacity-dmips-mhz = <1024>; > + d-cache-block-size = <64>; > + d-cache-sets = <1024>; > + d-cache-size = <65536>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <1024>; > + i-cache-size = <65536>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c2>; > + reg = <0x2>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu2_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu3: cpu@3 { > + compatible = "starfive,dubhe-90", "riscv"; > + capacity-dmips-mhz = <1024>; > + d-cache-block-size = <64>; > + d-cache-sets = <1024>; > + d-cache-size = <65536>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <1024>; > + i-cache-size = <65536>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c2>; > + reg = <0x3>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu3_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu4: cpu@4 { > + compatible = "starfive,dubhe-90", "riscv"; > + capacity-dmips-mhz = <1024>; > + d-cache-block-size = <64>; > + d-cache-sets = <1024>; > + d-cache-size = <65536>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <1024>; > + i-cache-size = <65536>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c2>; > + reg = <0x4>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu4_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu5: cpu@5 { > + compatible = "starfive,dubhe-90", "riscv"; > + capacity-dmips-mhz = <1024>; > + d-cache-block-size = <64>; > + d-cache-sets = <1024>; > + d-cache-size = <65536>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <1024>; > + i-cache-size = <65536>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c2>; > + reg = <0x5>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu5_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu1>; > + }; > + }; > + > + cluster2 { > + core0 { > + cpu = <&cpu2>; > + }; > + > + core1 { > + cpu = <&cpu3>; > + }; > + > + core2 { > + cpu = <&cpu4>; > + }; > + > + core3 { > + cpu = <&cpu5>; > + }; > + }; > + }; > + > + l2c0: cache-controller-0 { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <512>; > + cache-size = <0x40000>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l2c1: cache-controller-1 { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <512>; > + cache-size = <0x40000>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l2c2: cache-controller-2{ > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <4096>; > + cache-size = <0x200000>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l3_cache: cache-controller-3 { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <3>; > + cache-sets = <8192>; > + cache-size = <0x400000>; > + cache-unified; > + }; > + }; > + > + clk_uart: clk-uart { > + compatible = "fixed-clock"; /* Initial clock handler for UART */ > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clint: clint@2000000 { > + compatible = "starfive,jh8100-clint", "sifive,clint0"; > + reg = <0x0 0x2000000 0x0 0x10000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > + <&cpu1_intc 3>, <&cpu1_intc 7>, > + <&cpu2_intc 3>, <&cpu2_intc 7>, > + <&cpu3_intc 3>, <&cpu3_intc 7>, > + <&cpu4_intc 3>, <&cpu4_intc 7>, > + <&cpu5_intc 3>, <&cpu5_intc 7>; > + }; > + > + plic: interrupt-controller@c000000 { > + #interrupt-cells = <1>; > + #address-cells = <0>; > + compatible = "starfive,jh8100-plic", "sifive,plic-1.0.0"; > + reg = <0x0 0x0c000000 0x0 0x4000000>; > + riscv,ndev = <200>; > + interrupt-controller; > + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, > + <&cpu0_intc 9>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu3_intc 11>, > + <&cpu4_intc 11>, <&cpu5_intc 11>, > + <&cpu2_intc 9>, <&cpu3_intc 9>, > + <&cpu4_intc 9>, <&cpu5_intc 9>; > + }; > + > + uart0: serial@12160000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x12160000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <67>; > + status = "disabled"; > + }; > + > + uart1: serial@12170000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x12170000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <68>; > + status = "disabled"; > + }; > + > + uart2: serial@12180000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x12180000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <69>; > + status = "disabled"; > + }; > + > + uart3: serial@12190000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x12190000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <70>; > + status = "disabled"; > + }; > + > + uart4: serial@121a0000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x121a0000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <71>; > + status = "disabled"; > + }; > + > + uart5: serial@127d0000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x127d0000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <72>; > + status = "disabled"; > + }; > + > + uart6: serial@127e0000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x127e0000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <73>; > + status = "disabled"; > + }; > + }; > +}; ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-08 12:08 ` Shengyu Qu @ 2023-12-11 1:38 ` JeeHeng Sia 2023-12-11 7:58 ` Conor Dooley 0 siblings, 1 reply; 26+ messages in thread From: JeeHeng Sia @ 2023-12-11 1:38 UTC (permalink / raw) To: Shengyu Qu, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, Michael Zhu, drew Cc: devicetree, linux-riscv, linux-kernel, Leyfoon Tan > -----Original Message----- > From: Shengyu Qu <wiagn233@outlook.com> > Sent: Friday, December 8, 2023 8:09 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; anup@brainfault.org; gregkh@linuxfoundation.org; > jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu <michael.zhu@starfivetech.com>; drew@beagleboard.org > Cc: wiagn233@outlook.com; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > Hello Sia, Hi Shengyu > > Does the dubhe-80 cores actually support vector? Or vector support > > doesn't exist on actual silicon? We don't have a use case for vector application in JH8100 > > Best regards, > > Shengyu > > > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > --- > > arch/riscv/boot/dts/starfive/Makefile | 2 + > > arch/riscv/boot/dts/starfive/jh8100-evb.dts | 28 ++ > > arch/riscv/boot/dts/starfive/jh8100.dtsi | 378 ++++++++++++++++++++ > > 3 files changed, 408 insertions(+) > > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts > > create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi > > > > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile > > index 0141504c0f5c..ef5c7331c7ec 100644 > > --- a/arch/riscv/boot/dts/starfive/Makefile > > +++ b/arch/riscv/boot/dts/starfive/Makefile > > @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb > > > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb > > + > > +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb > > diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > > new file mode 100644 > > index 000000000000..c16bc25d8988 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > > @@ -0,0 +1,28 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > +/* > > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > > + */ > > + > > +#include "jh8100.dtsi" > > + > > +/ { > > + model = "StarFive JH8100 EVB"; > > + compatible = "starfive,jh8100-evb", "starfive,jh8100"; > > + > > + aliases { > > + serial0 = &uart0; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@40000000 { > > + device_type = "memory"; > > + reg = <0x0 0x40000000 0x2 0x00000000>; > > + }; > > +}; > > + > > +&uart0 { > > + status = "okay"; > > +}; > > diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi > > new file mode 100644 > > index 000000000000..f26aff5c1ddf > > --- /dev/null > > +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi > > @@ -0,0 +1,378 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > +/* > > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > > + */ > > + > > +/dts-v1/; > > + > > +/ { > > + compatible = "starfive,jh8100"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + timebase-frequency = <4000000>; > > + > > + cpu0: cpu@0 { > > + compatible = "starfive,dubhe-80", "riscv"; > > + capacity-dmips-mhz = <768>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <512>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <512>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c0>; > > + reg = <0x0>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu1: cpu@1 { > > + compatible = "starfive,dubhe-80", "riscv"; > > + capacity-dmips-mhz = <768>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <512>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <512>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c1>; > > + reg = <0x1>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu1_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu2: cpu@2 { > > + compatible = "starfive,dubhe-90", "riscv"; > > + capacity-dmips-mhz = <1024>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <1024>; > > + d-cache-size = <65536>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <1024>; > > + i-cache-size = <65536>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c2>; > > + reg = <0x2>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu2_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu3: cpu@3 { > > + compatible = "starfive,dubhe-90", "riscv"; > > + capacity-dmips-mhz = <1024>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <1024>; > > + d-cache-size = <65536>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <1024>; > > + i-cache-size = <65536>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c2>; > > + reg = <0x3>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu3_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu4: cpu@4 { > > + compatible = "starfive,dubhe-90", "riscv"; > > + capacity-dmips-mhz = <1024>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <1024>; > > + d-cache-size = <65536>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <1024>; > > + i-cache-size = <65536>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c2>; > > + reg = <0x4>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu4_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu5: cpu@5 { > > + compatible = "starfive,dubhe-90", "riscv"; > > + capacity-dmips-mhz = <1024>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <1024>; > > + d-cache-size = <65536>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <1024>; > > + i-cache-size = <65536>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c2>; > > + reg = <0x5>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu5_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&cpu0>; > > + }; > > + }; > > + > > + cluster1 { > > + core0 { > > + cpu = <&cpu1>; > > + }; > > + }; > > + > > + cluster2 { > > + core0 { > > + cpu = <&cpu2>; > > + }; > > + > > + core1 { > > + cpu = <&cpu3>; > > + }; > > + > > + core2 { > > + cpu = <&cpu4>; > > + }; > > + > > + core3 { > > + cpu = <&cpu5>; > > + }; > > + }; > > + }; > > + > > + l2c0: cache-controller-0 { > > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <512>; > > + cache-size = <0x40000>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l2c1: cache-controller-1 { > > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <512>; > > + cache-size = <0x40000>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l2c2: cache-controller-2{ > > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <4096>; > > + cache-size = <0x200000>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l3_cache: cache-controller-3 { > > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <3>; > > + cache-sets = <8192>; > > + cache-size = <0x400000>; > > + cache-unified; > > + }; > > + }; > > + > > + clk_uart: clk-uart { > > + compatible = "fixed-clock"; /* Initial clock handler for UART */ > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + interrupt-parent = <&plic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + clint: clint@2000000 { > > + compatible = "starfive,jh8100-clint", "sifive,clint0"; > > + reg = <0x0 0x2000000 0x0 0x10000>; > > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > > + <&cpu1_intc 3>, <&cpu1_intc 7>, > > + <&cpu2_intc 3>, <&cpu2_intc 7>, > > + <&cpu3_intc 3>, <&cpu3_intc 7>, > > + <&cpu4_intc 3>, <&cpu4_intc 7>, > > + <&cpu5_intc 3>, <&cpu5_intc 7>; > > + }; > > + > > + plic: interrupt-controller@c000000 { > > + #interrupt-cells = <1>; > > + #address-cells = <0>; > > + compatible = "starfive,jh8100-plic", "sifive,plic-1.0.0"; > > + reg = <0x0 0x0c000000 0x0 0x4000000>; > > + riscv,ndev = <200>; > > + interrupt-controller; > > + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, > > + <&cpu0_intc 9>, <&cpu1_intc 9>, > > + <&cpu2_intc 11>, <&cpu3_intc 11>, > > + <&cpu4_intc 11>, <&cpu5_intc 11>, > > + <&cpu2_intc 9>, <&cpu3_intc 9>, > > + <&cpu4_intc 9>, <&cpu5_intc 9>; > > + }; > > + > > + uart0: serial@12160000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x12160000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <67>; > > + status = "disabled"; > > + }; > > + > > + uart1: serial@12170000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x12170000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <68>; > > + status = "disabled"; > > + }; > > + > > + uart2: serial@12180000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x12180000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <69>; > > + status = "disabled"; > > + }; > > + > > + uart3: serial@12190000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x12190000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <70>; > > + status = "disabled"; > > + }; > > + > > + uart4: serial@121a0000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x121a0000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <71>; > > + status = "disabled"; > > + }; > > + > > + uart5: serial@127d0000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x127d0000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <72>; > > + status = "disabled"; > > + }; > > + > > + uart6: serial@127e0000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x127e0000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <73>; > > + status = "disabled"; > > + }; > > + }; > > +}; ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-11 1:38 ` JeeHeng Sia @ 2023-12-11 7:58 ` Conor Dooley 2023-12-11 9:38 ` JeeHeng Sia 0 siblings, 1 reply; 26+ messages in thread From: Conor Dooley @ 2023-12-11 7:58 UTC (permalink / raw) To: JeeHeng Sia Cc: Shengyu Qu, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, Michael Zhu, drew, devicetree, linux-riscv, linux-kernel, Leyfoon Tan [-- Attachment #1: Type: text/plain, Size: 440 bytes --] On Mon, Dec 11, 2023 at 01:38:06AM +0000, JeeHeng Sia wrote: > > > From: Shengyu Qu <wiagn233@outlook.com> > > Sent: Friday, December 8, 2023 8:09 PM > > Does the dubhe-80 cores actually support vector? Or vector support > > > > doesn't exist on actual silicon? > We don't have a use case for vector application in JH8100 I am sorry, but I am not clear on what this means. Do the CPUs on the JH8100 support vector or not? [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-11 7:58 ` Conor Dooley @ 2023-12-11 9:38 ` JeeHeng Sia 2023-12-11 17:43 ` Conor Dooley 0 siblings, 1 reply; 26+ messages in thread From: JeeHeng Sia @ 2023-12-11 9:38 UTC (permalink / raw) To: Conor Dooley Cc: Shengyu Qu, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, Michael Zhu, drew, devicetree, linux-riscv, linux-kernel, Leyfoon Tan > -----Original Message----- > From: Conor Dooley <conor.dooley@microchip.com> > Sent: Monday, December 11, 2023 3:59 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > Cc: Shengyu Qu <wiagn233@outlook.com>; kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; anup@brainfault.org; gregkh@linuxfoundation.org; > jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu <michael.zhu@starfivetech.com>; drew@beagleboard.org; > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > On Mon, Dec 11, 2023 at 01:38:06AM +0000, JeeHeng Sia wrote: > > > > > From: Shengyu Qu <wiagn233@outlook.com> > > > Sent: Friday, December 8, 2023 8:09 PM > > > > Does the dubhe-80 cores actually support vector? Or vector support > > > > > > doesn't exist on actual silicon? > > > We don't have a use case for vector application in JH8100 > > I am sorry, but I am not clear on what this means. Do the CPUs on > the JH8100 support vector or not? The JH8100 CPU does not support vector operation. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-11 9:38 ` JeeHeng Sia @ 2023-12-11 17:43 ` Conor Dooley 0 siblings, 0 replies; 26+ messages in thread From: Conor Dooley @ 2023-12-11 17:43 UTC (permalink / raw) To: JeeHeng Sia Cc: Conor Dooley, Shengyu Qu, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, anup, gregkh, jirislaby, michal.simek, Michael Zhu, drew, devicetree, linux-riscv, linux-kernel, Leyfoon Tan [-- Attachment #1: Type: text/plain, Size: 1529 bytes --] On Mon, Dec 11, 2023 at 09:38:03AM +0000, JeeHeng Sia wrote: > > > > -----Original Message----- > > From: Conor Dooley <conor.dooley@microchip.com> > > Sent: Monday, December 11, 2023 3:59 PM > > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > > Cc: Shengyu Qu <wiagn233@outlook.com>; kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > > krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > > daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; anup@brainfault.org; gregkh@linuxfoundation.org; > > jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu <michael.zhu@starfivetech.com>; drew@beagleboard.org; > > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > > <leyfoon.tan@starfivetech.com> > > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > > > On Mon, Dec 11, 2023 at 01:38:06AM +0000, JeeHeng Sia wrote: > > > > > > > From: Shengyu Qu <wiagn233@outlook.com> > > > > Sent: Friday, December 8, 2023 8:09 PM > > > > > > Does the dubhe-80 cores actually support vector? Or vector support > > > > > > > > doesn't exist on actual silicon? > > > > > We don't have a use case for vector application in JH8100 > > > > I am sorry, but I am not clear on what this means. Do the CPUs on > > the JH8100 support vector or not? > The JH8100 CPU does not support vector operation. Thanks for clarifiying. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-01 12:14 ` [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng 2023-12-08 12:08 ` Shengyu Qu @ 2023-12-08 16:05 ` Emil Renner Berthing 2023-12-13 12:39 ` Emil Renner Berthing 1 sibling, 1 reply; 26+ messages in thread From: Emil Renner Berthing @ 2023-12-08 16:05 UTC (permalink / raw) To: Sia Jee Heng, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, leyfoon.tan Sia Jee Heng wrote: > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Looks good to me, thanks. Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-08 16:05 ` Emil Renner Berthing @ 2023-12-13 12:39 ` Emil Renner Berthing 2023-12-14 0:34 ` JeeHeng Sia 0 siblings, 1 reply; 26+ messages in thread From: Emil Renner Berthing @ 2023-12-13 12:39 UTC (permalink / raw) To: Emil Renner Berthing, Sia Jee Heng, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew Cc: devicetree, linux-riscv, linux-kernel, leyfoon.tan Emil Renner Berthing wrote: > Sia Jee Heng wrote: > > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > Looks good to me, thanks. > > Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> I just learned that this JH8100 is not actually a real SoC yet but just an FPGA implementation, and no indication that that's actually a product that will be mass produced. Hence a lot of details may change before it becomes a real SoC/product people can buy, so let's not add this device tree yet before everything is set in silicon. Please consider my Acked-by abeve revoked. Sia Jee Heng: With that said I still think it's super awesome that you're beginning upstreaming support for your new SoCs early. I wish more SoC vendors would follow your example. /Emil ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree 2023-12-13 12:39 ` Emil Renner Berthing @ 2023-12-14 0:34 ` JeeHeng Sia 0 siblings, 0 replies; 26+ messages in thread From: JeeHeng Sia @ 2023-12-14 0:34 UTC (permalink / raw) To: Emil Renner Berthing, kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, conor, anup, gregkh, jirislaby, michal.simek, Michael Zhu, drew Cc: devicetree, linux-riscv, linux-kernel, Leyfoon Tan > -----Original Message----- > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Sent: Wednesday, December 13, 2023 8:39 PM > To: Emil Renner Berthing <emil.renner.berthing@canonical.com>; JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; > robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; > palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > <michael.zhu@starfivetech.com>; drew@beagleboard.org > Cc: devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > Emil Renner Berthing wrote: > > Sia Jee Heng wrote: > > > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > > > Looks good to me, thanks. > > > > Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > I just learned that this JH8100 is not actually a real SoC yet but just an FPGA > implementation, and no indication that that's actually a product that will be > mass produced. Hence a lot of details may change before it becomes a real > SoC/product people can buy, so let's not add this device tree yet before > everything is set in silicon. > > Please consider my Acked-by abeve revoked. > > Sia Jee Heng: With that said I still think it's super awesome that you're > beginning upstreaming support for your new SoCs early. I wish more SoC vendors > would follow your example. Hi Emil, I am not sure what you mean. We verified on FPGA & Emulator, and the logic is pretty much close to the real silicon. I did mention that in the cover letter as well. I am new to Linux, so I am wondering if there is a Linux upstream guideline mentioning that pre-silicon software is not allowed to upstream? Hope there is an updated Linux upstream guideline that benefit other vendors. > > /Emil ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC 2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng ` (5 preceding siblings ...) 2023-12-01 12:14 ` [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng @ 2023-12-06 16:45 ` Conor Dooley 6 siblings, 0 replies; 26+ messages in thread From: Conor Dooley @ 2023-12-06 16:45 UTC (permalink / raw) To: Sia Jee Heng Cc: kernel, robh+dt, krzysztof.kozlowski+dt, krzk, conor+dt, paul.walmsley, palmer, aou, daniel.lezcano, tglx, anup, gregkh, jirislaby, michal.simek, michael.zhu, drew, devicetree, linux-riscv, linux-kernel, leyfoon.tan [-- Attachment #1: Type: text/plain, Size: 734 bytes --] On Fri, Dec 01, 2023 at 08:14:04PM +0800, Sia Jee Heng wrote: > StarFive JH8100 SoC consists of 4 RISC-V performance Cores (Dubhe-90) and > 2 RISC-V energy efficient cores (Dubhe-80). It also features various > interfaces such as DDR4, Gbit-Ether, CAN, USB 3.2, SD/MMC, etc., making it > ideal for high-performance computing scenarios. > > This patch series introduces initial SoC DTSI support for the StarFive > JH8100 SoC. The relevant dt-binding documentation has been updated > accordingly. Below is the list of IP blocks added in the initial SoC DTSI, > which can be used for booting via initramfs on FPGA: This all seems okay to me. I'll need an ack from Emil though before I can pick it up. Thanks, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2024-01-18 19:24 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC Sia Jee Heng 2023-12-13 12:43 ` Conor Dooley 2023-12-13 13:24 ` Leyfoon Tan 2023-12-14 0:36 ` JeeHeng Sia 2023-12-14 16:22 ` Conor Dooley 2023-12-14 17:20 ` Palmer Dabbelt 2023-12-15 1:49 ` JeeHeng Sia 2023-12-16 12:06 ` Conor Dooley 2023-12-01 12:14 ` [PATCH v3 3/6] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng 2023-12-04 17:36 ` Daniel Lezcano 2024-01-18 19:23 ` [tip: timers/core] " tip-bot2 for Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 4/6] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng 2023-12-01 12:14 ` [PATCH v3 5/6] dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART Sia Jee Heng 2023-12-01 15:46 ` Conor Dooley 2023-12-01 12:14 ` [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng 2023-12-08 12:08 ` Shengyu Qu 2023-12-11 1:38 ` JeeHeng Sia 2023-12-11 7:58 ` Conor Dooley 2023-12-11 9:38 ` JeeHeng Sia 2023-12-11 17:43 ` Conor Dooley 2023-12-08 16:05 ` Emil Renner Berthing 2023-12-13 12:39 ` Emil Renner Berthing 2023-12-14 0:34 ` JeeHeng Sia 2023-12-06 16:45 ` [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Conor Dooley
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