[PATCH net-next 00/12] DSA driver for Vitesse Felix switch

[PATCH net-next 00/12] DSA driver for Vitesse Felix switch

[Vladimir Oltean]

This series builds upon the previous "Accomodate DSA front-end into
Ocelot" topic and does the following:

- Reworks the Ocelot (VSC7514) driver to support one more switching core
  (VSC9959), used in NPI mode. Some code which was thought to be
  SoC-specific (ocelot_board.c) wasn't, and vice versa, so it is being
  accordingly moved.
- Exports ocelot driver structures and functions to include/soc/mscc.
- Adds a DSA ocelot front-end for VSC9959, which is a PCI device and
  uses the exported ocelot functionality for hardware configuration.
- Adds a tagger driver for the Vitesse injection/extraction DSA headers.
  This is known to be compatible with at least Ocelot and Felix.

Claudiu Manoil (2):
  net: mscc: ocelot: move resource ioremap and regmap init to common
    code
  net: mscc: ocelot: filter out ocelot SoC specific PCS config from
    common path

Vladimir Oltean (10):
  net: mscc: ocelot: move invariant configs out of adjust_link
  net: mscc: ocelot: create a helper for changing the port MTU
  net: mscc: ocelot: export a constant for the tag length in bytes
  net: mscc: ocelot: adjust MTU on the CPU port in NPI mode
  net: mscc: ocelot: separate the implementation of switch reset
  net: mscc: ocelot: publish structure definitions to
    include/soc/mscc/ocelot.h
  net: mscc: ocelot: publish ocelot_sys.h to include/soc/mscc
  net: dsa: vitesse: move vsc73xx driver to a separate folder
  net: dsa: vitesse: add basic Felix switch driver
  net: dsa: vitesse: add tagger for Ocelot/Felix switches

 MAINTAINERS                                   |   8 +
 drivers/net/dsa/Kconfig                       |  31 +-
 drivers/net/dsa/Makefile                      |   4 +-
 drivers/net/dsa/vitesse/Kconfig               |  44 ++
 drivers/net/dsa/vitesse/Makefile              |  10 +
 drivers/net/dsa/vitesse/felix-regs.c          | 647 ++++++++++++++++
 drivers/net/dsa/vitesse/felix.c               | 358 +++++++++
 drivers/net/dsa/vitesse/felix.h               |  36 +
 .../vsc73xx-core.c}                           |   2 +-
 .../vsc73xx-platform.c}                       |   2 +-
 .../vsc73xx-spi.c}                            |   2 +-
 .../{vitesse-vsc73xx.h => vitesse/vsc73xx.h}  |   0
 drivers/net/ethernet/mscc/ocelot.c            | 205 ++---
 drivers/net/ethernet/mscc/ocelot.h            | 479 +-----------
 drivers/net/ethernet/mscc/ocelot_board.c      |  85 ++-
 drivers/net/ethernet/mscc/ocelot_io.c         |  14 +-
 drivers/net/ethernet/mscc/ocelot_regs.c       |   4 +-
 include/net/dsa.h                             |   2 +
 include/soc/mscc/ocelot.h                     | 698 ++++++++++++++++++
 .../soc}/mscc/ocelot_sys.h                    |   0
 net/dsa/Kconfig                               |   7 +
 net/dsa/Makefile                              |   1 +
 net/dsa/tag_ocelot.c                          | 229 ++++++
 23 files changed, 2231 insertions(+), 637 deletions(-)
 create mode 100644 drivers/net/dsa/vitesse/Kconfig
 create mode 100644 drivers/net/dsa/vitesse/Makefile
 create mode 100644 drivers/net/dsa/vitesse/felix-regs.c
 create mode 100644 drivers/net/dsa/vitesse/felix.c
 create mode 100644 drivers/net/dsa/vitesse/felix.h
 rename drivers/net/dsa/{vitesse-vsc73xx-core.c => vitesse/vsc73xx-core.c} (99%)
 rename drivers/net/dsa/{vitesse-vsc73xx-platform.c => vitesse/vsc73xx-platform.c} (99%)
 rename drivers/net/dsa/{vitesse-vsc73xx-spi.c => vitesse/vsc73xx-spi.c} (99%)
 rename drivers/net/dsa/{vitesse-vsc73xx.h => vitesse/vsc73xx.h} (100%)
 create mode 100644 include/soc/mscc/ocelot.h
 rename {drivers/net/ethernet => include/soc}/mscc/ocelot_sys.h (100%)
 create mode 100644 net/dsa/tag_ocelot.c

-- 
2.17.1

[PATCH net-next 01/12] net: mscc: ocelot: move resource ioremap and regmap init to common code

[Vladimir Oltean]

From: Claudiu Manoil <claudiu.manoil@nxp.com>

Let's make this ioremap and regmap init code common.  It should not
be platform dependent as it should be usable by PCI devices too.
Use better names where necessary to avoid clashes.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.h       |  4 +---
 drivers/net/ethernet/mscc/ocelot_board.c | 17 ++++++++++-------
 drivers/net/ethernet/mscc/ocelot_io.c    | 14 +++++---------
 3 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
index 4d8e769ccad9..b5802cea7cc4 100644
--- a/drivers/net/ethernet/mscc/ocelot.h
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -546,9 +546,7 @@ void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
 
 int ocelot_regfields_init(struct ocelot *ocelot,
 			  const struct reg_field *const regfields);
-struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
-				       struct platform_device *pdev,
-				       const char *name);
+struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
 
 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c
index 811599f32910..ddb34f17fa52 100644
--- a/drivers/net/ethernet/mscc/ocelot_board.c
+++ b/drivers/net/ethernet/mscc/ocelot_board.c
@@ -268,7 +268,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
 		enum ocelot_target id;
 		char *name;
 		u8 optional:1;
-	} res[] = {
+	} io_target[] = {
 		{ SYS, "sys" },
 		{ REW, "rew" },
 		{ QSYS, "qsys" },
@@ -288,20 +288,23 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, ocelot);
 	ocelot->dev = &pdev->dev;
 
-	for (i = 0; i < ARRAY_SIZE(res); i++) {
+	for (i = 0; i < ARRAY_SIZE(io_target); i++) {
 		struct regmap *target;
+		struct resource *res;
+
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+						   io_target[i].name);
 
-		target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
+		target = ocelot_regmap_init(ocelot, res);
 		if (IS_ERR(target)) {
-			if (res[i].optional) {
-				ocelot->targets[res[i].id] = NULL;
+			if (io_target[i].optional) {
+				ocelot->targets[io_target[i].id] = NULL;
 				continue;
 			}
-
 			return PTR_ERR(target);
 		}
 
-		ocelot->targets[res[i].id] = target;
+		ocelot->targets[io_target[i].id] = target;
 	}
 
 	hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
diff --git a/drivers/net/ethernet/mscc/ocelot_io.c b/drivers/net/ethernet/mscc/ocelot_io.c
index c6db8ad31fdf..b229b1cb68ef 100644
--- a/drivers/net/ethernet/mscc/ocelot_io.c
+++ b/drivers/net/ethernet/mscc/ocelot_io.c
@@ -97,20 +97,16 @@ static struct regmap_config ocelot_regmap_config = {
 	.reg_stride	= 4,
 };
 
-struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
-				       struct platform_device *pdev,
-				       const char *name)
+struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res)
 {
-	struct resource *res;
 	void __iomem *regs;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 	regs = devm_ioremap_resource(ocelot->dev, res);
 	if (IS_ERR(regs))
 		return ERR_CAST(regs);
 
-	ocelot_regmap_config.name = name;
-	return devm_regmap_init_mmio(ocelot->dev, regs,
-				     &ocelot_regmap_config);
+	ocelot_regmap_config.name = res->name;
+
+	return devm_regmap_init_mmio(ocelot->dev, regs, &ocelot_regmap_config);
 }
-EXPORT_SYMBOL(ocelot_io_platform_init);
+EXPORT_SYMBOL(ocelot_regmap_init);
-- 
2.17.1

[PATCH net-next 02/12] net: mscc: ocelot: filter out ocelot SoC specific PCS config from common path

[Vladimir Oltean]

From: Claudiu Manoil <claudiu.manoil@nxp.com>

The adjust_link routine should be generic enough to be (re)used by
any SoC that integrates a switch core compatible with the Ocelot
core switch driver.  Currently all configurations are generic except
for the PCS settings that are SoC specific.  Move these out to the
Ocelot SoC/board instance.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.c       | 19 ++--------------
 drivers/net/ethernet/mscc/ocelot.h       |  8 ++++++-
 drivers/net/ethernet/mscc/ocelot_board.c | 29 +++++++++++++++++++++++-
 drivers/net/ethernet/mscc/ocelot_regs.c  |  4 ++--
 4 files changed, 39 insertions(+), 21 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 3e7a2796c37d..2b6792ab0eda 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -455,23 +455,8 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
 	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
 			   DEV_MAC_HDX_CFG);
 
-	/* Disable HDX fast control */
-	ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
-			   DEV_PORT_MISC);
-
-	/* SGMII only for now */
-	ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
-			   PCS1G_MODE_CFG);
-	ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
-
-	/* Enable PCS */
-	ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
-
-	/* No aneg on SGMII */
-	ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
-
-	/* No loopback */
-	ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
+	if (ocelot->ops->pcs_init)
+		ocelot->ops->pcs_init(ocelot, port);
 
 	/* Set Max Length and maximum tags allowed */
 	ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
index b5802cea7cc4..7e28434c22c1 100644
--- a/drivers/net/ethernet/mscc/ocelot.h
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -435,13 +435,19 @@ enum ocelot_tag_prefix {
 };
 
 struct ocelot_port;
+struct ocelot;
 
 struct ocelot_stat_layout {
 	u32 offset;
 	char name[ETH_GSTRING_LEN];
 };
 
+struct ocelot_ops {
+	void (*pcs_init)(struct ocelot *ocelot, int port);
+};
+
 struct ocelot {
+	const struct ocelot_ops *ops;
 	struct device *dev;
 
 	struct regmap *targets[TARGET_MAX];
@@ -553,7 +559,7 @@ struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
 
 int ocelot_init(struct ocelot *ocelot);
 void ocelot_deinit(struct ocelot *ocelot);
-int ocelot_chip_init(struct ocelot *ocelot);
+int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops);
 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
 		      void __iomem *regs,
 		      struct phy_device *phy);
diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c
index ddb34f17fa52..de2da6d33d43 100644
--- a/drivers/net/ethernet/mscc/ocelot_board.c
+++ b/drivers/net/ethernet/mscc/ocelot_board.c
@@ -254,6 +254,33 @@ static const struct of_device_id mscc_ocelot_match[] = {
 };
 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
 
+static void ocelot_port_pcs_init(struct ocelot *ocelot, int port)
+{
+	struct ocelot_port *ocelot_port = ocelot->ports[port];
+
+	/* Disable HDX fast control */
+	ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
+			   DEV_PORT_MISC);
+
+	/* SGMII only for now */
+	ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
+			   PCS1G_MODE_CFG);
+	ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
+
+	/* Enable PCS */
+	ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
+
+	/* No aneg on SGMII */
+	ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
+
+	/* No loopback */
+	ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
+}
+
+static const struct ocelot_ops ocelot_ops = {
+	.pcs_init		= ocelot_port_pcs_init,
+};
+
 static int mscc_ocelot_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -315,7 +342,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
 
 	ocelot->targets[HSIO] = hsio;
 
-	err = ocelot_chip_init(ocelot);
+	err = ocelot_chip_init(ocelot, &ocelot_ops);
 	if (err)
 		return err;
 
diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c b/drivers/net/ethernet/mscc/ocelot_regs.c
index e59977d20400..d715a924108b 100644
--- a/drivers/net/ethernet/mscc/ocelot_regs.c
+++ b/drivers/net/ethernet/mscc/ocelot_regs.c
@@ -423,7 +423,7 @@ static void ocelot_pll5_init(struct ocelot *ocelot)
 		     HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
 }
 
-int ocelot_chip_init(struct ocelot *ocelot)
+int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops)
 {
 	int ret;
 
@@ -431,6 +431,7 @@ int ocelot_chip_init(struct ocelot *ocelot)
 	ocelot->stats_layout = ocelot_stats_layout;
 	ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout);
 	ocelot->shared_queue_sz = 224 * 1024;
+	ocelot->ops = ops;
 
 	ret = ocelot_regfields_init(ocelot, ocelot_regfields);
 	if (ret)
@@ -443,4 +444,3 @@ int ocelot_chip_init(struct ocelot *ocelot)
 
 	return 0;
 }
-EXPORT_SYMBOL(ocelot_chip_init);
-- 
2.17.1

Re: [PATCH net-next 02/12] net: mscc: ocelot: filter out ocelot SoC specific PCS config from common path

[Andrew Lunn]

On Tue, Nov 12, 2019 at 02:44:10PM +0200, Vladimir Oltean wrote:
> From: Claudiu Manoil <claudiu.manoil@nxp.com>
> 
> The adjust_link routine should be generic enough to be (re)used by
> any SoC that integrates a switch core compatible with the Ocelot
> core switch driver.  Currently all configurations are generic except
> for the PCS settings that are SoC specific.  Move these out to the
> Ocelot SoC/board instance.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next 02/12] net: mscc: ocelot: filter out ocelot SoC specific PCS config from common path

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Claudiu Manoil <claudiu.manoil@nxp.com>
> 
> The adjust_link routine should be generic enough to be (re)used by
> any SoC that integrates a switch core compatible with the Ocelot
> core switch driver.  Currently all configurations are generic except
> for the PCS settings that are SoC specific.  Move these out to the
> Ocelot SoC/board instance.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH net-next 02/12] net: mscc: ocelot: filter out ocelot SoC specific PCS config from common path

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1479 bytes --]

Hi Vladimir,

I love your patch! Yet something to improve:

[auto build test ERROR on net-next/master]
[cannot apply to v5.4-rc7 next-20191111]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vladimir-Oltean/DSA-driver-for-Vitesse-Felix-switch/20191113-100022
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git e0580b50d9d4b61d6c56085acdc2bb01c040aca9
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 7.4.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.4.0 make.cross ARCH=ia64 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> ERROR: "ocelot_chip_init" [drivers/net/ethernet/mscc/ocelot_board.ko] undefined!
   ERROR: "ia64_delay_loop" [drivers/net/phy/mdio-cavium.ko] undefined!
   ERROR: "ia64_delay_loop" [drivers/spi/spi-thunderx.ko] undefined!

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 54944 bytes --]

[PATCH net-next 03/12] net: mscc: ocelot: move invariant configs out of adjust_link

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

It doesn't make sense to rewrite all these registers every time the PHY
library notifies us about a link state change.

In a future patch we will customize the MTU for the CPU port, and since
the MTU was previously configured from adjust_link, if we don't make
this change, its value would have got overridden.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.c | 85 +++++++++++++++---------------
 1 file changed, 43 insertions(+), 42 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 2b6792ab0eda..4558c09e2e8a 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -408,7 +408,7 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
 			       struct phy_device *phydev)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
-	int speed, atop_wm, mode = 0;
+	int speed, mode = 0;
 
 	switch (phydev->speed) {
 	case SPEED_10:
@@ -440,32 +440,9 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
 	ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
 			   mode, DEV_MAC_MODE_CFG);
 
-	/* Set MAC IFG Gaps
-	 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
-	 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
-	 */
-	ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
-			   DEV_MAC_IFG_CFG);
-
-	/* Load seed (0) and set MAC HDX late collision  */
-	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
-			   DEV_MAC_HDX_CFG_SEED_LOAD,
-			   DEV_MAC_HDX_CFG);
-	mdelay(1);
-	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
-			   DEV_MAC_HDX_CFG);
-
 	if (ocelot->ops->pcs_init)
 		ocelot->ops->pcs_init(ocelot, port);
 
-	/* Set Max Length and maximum tags allowed */
-	ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
-			   DEV_MAC_MAXLEN_CFG);
-	ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
-			   DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
-			   DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
-			   DEV_MAC_TAGS_CFG);
-
 	/* Enable MAC module */
 	ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
 			   DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
@@ -475,22 +452,10 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
 	ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
 			   DEV_CLOCK_CFG);
 
-	/* Set SMAC of Pause frame (00:00:00:00:00:00) */
-	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
-	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
-
 	/* No PFC */
 	ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
 			 ANA_PFC_PFC_CFG, port);
 
-	/* Set Pause WM hysteresis
-	 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
-	 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
-	 */
-	ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
-			 SYS_PAUSE_CFG_PAUSE_STOP(101) |
-			 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
-
 	/* Core: Enable port for frame transfer */
 	ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
 			 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
@@ -505,12 +470,6 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
 			 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
 			 SYS_MAC_FC_CFG, port);
 	ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
-
-	/* Tail dropping watermark */
-	atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
-	ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
-			 SYS_ATOP, port);
-	ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
 }
 
 static void ocelot_port_adjust_link(struct net_device *dev)
@@ -2141,11 +2100,53 @@ static int ocelot_init_timestamp(struct ocelot *ocelot)
 static void ocelot_init_port(struct ocelot *ocelot, int port)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
+	int atop_wm;
 
 	INIT_LIST_HEAD(&ocelot_port->skbs);
 
 	/* Basic L2 initialization */
 
+	/* Set MAC IFG Gaps
+	 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
+	 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
+	 */
+	ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
+			   DEV_MAC_IFG_CFG);
+
+	/* Load seed (0) and set MAC HDX late collision  */
+	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
+			   DEV_MAC_HDX_CFG_SEED_LOAD,
+			   DEV_MAC_HDX_CFG);
+	mdelay(1);
+	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
+			   DEV_MAC_HDX_CFG);
+
+	/* Set Max Length and maximum tags allowed */
+	ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
+			   DEV_MAC_MAXLEN_CFG);
+	ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
+			   DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
+			   DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
+			   DEV_MAC_TAGS_CFG);
+
+	/* Set SMAC of Pause frame (00:00:00:00:00:00) */
+	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
+	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
+
+	/* Set Pause WM hysteresis
+	 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
+	 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
+	 */
+	ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
+			 SYS_PAUSE_CFG_PAUSE_STOP(101) |
+			 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
+
+	/* Tail dropping watermark */
+	atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
+	ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
+			 SYS_ATOP, port);
+	ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
+
 	/* Drop frames with multicast source address */
 	ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
 		       ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
-- 
2.17.1

Re: [PATCH net-next 03/12] net: mscc: ocelot: move invariant configs out of adjust_link

[Andrew Lunn]

On Tue, Nov 12, 2019 at 02:44:11PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> It doesn't make sense to rewrite all these registers every time the PHY
> library notifies us about a link state change.
> 
> In a future patch we will customize the MTU for the CPU port, and since
> the MTU was previously configured from adjust_link, if we don't make
> this change, its value would have got overridden.

This is also a good change in preparation of PHYLINK.  When you do
that conversion, ocelot_adjust_link() is likely to become
ocelot_mac_config(). It should only change hardware state when there
actually is a change in link state. This is something drivers often
get wrong.

> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew



> ---
>  drivers/net/ethernet/mscc/ocelot.c | 85 +++++++++++++++---------------
>  1 file changed, 43 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
> index 2b6792ab0eda..4558c09e2e8a 100644
> --- a/drivers/net/ethernet/mscc/ocelot.c
> +++ b/drivers/net/ethernet/mscc/ocelot.c
> @@ -408,7 +408,7 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
>  			       struct phy_device *phydev)
>  {
>  	struct ocelot_port *ocelot_port = ocelot->ports[port];
> -	int speed, atop_wm, mode = 0;
> +	int speed, mode = 0;
>  
>  	switch (phydev->speed) {
>  	case SPEED_10:
> @@ -440,32 +440,9 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
>  	ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
>  			   mode, DEV_MAC_MODE_CFG);
>  
> -	/* Set MAC IFG Gaps
> -	 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
> -	 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
> -	 */
> -	ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
> -			   DEV_MAC_IFG_CFG);
> -
> -	/* Load seed (0) and set MAC HDX late collision  */
> -	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
> -			   DEV_MAC_HDX_CFG_SEED_LOAD,
> -			   DEV_MAC_HDX_CFG);
> -	mdelay(1);
> -	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
> -			   DEV_MAC_HDX_CFG);
> -
>  	if (ocelot->ops->pcs_init)
>  		ocelot->ops->pcs_init(ocelot, port);
>  
> -	/* Set Max Length and maximum tags allowed */
> -	ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
> -			   DEV_MAC_MAXLEN_CFG);
> -	ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
> -			   DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
> -			   DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
> -			   DEV_MAC_TAGS_CFG);
> -
>  	/* Enable MAC module */
>  	ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
>  			   DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
> @@ -475,22 +452,10 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
>  	ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
>  			   DEV_CLOCK_CFG);
>  
> -	/* Set SMAC of Pause frame (00:00:00:00:00:00) */
> -	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
> -	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
> -
>  	/* No PFC */
>  	ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
>  			 ANA_PFC_PFC_CFG, port);
>  
> -	/* Set Pause WM hysteresis
> -	 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
> -	 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
> -	 */
> -	ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
> -			 SYS_PAUSE_CFG_PAUSE_STOP(101) |
> -			 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
> -
>  	/* Core: Enable port for frame transfer */
>  	ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
>  			 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
> @@ -505,12 +470,6 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
>  			 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
>  			 SYS_MAC_FC_CFG, port);
>  	ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
> -
> -	/* Tail dropping watermark */
> -	atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
> -	ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
> -			 SYS_ATOP, port);
> -	ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
>  }
>  
>  static void ocelot_port_adjust_link(struct net_device *dev)
> @@ -2141,11 +2100,53 @@ static int ocelot_init_timestamp(struct ocelot *ocelot)
>  static void ocelot_init_port(struct ocelot *ocelot, int port)
>  {
>  	struct ocelot_port *ocelot_port = ocelot->ports[port];
> +	int atop_wm;
>  
>  	INIT_LIST_HEAD(&ocelot_port->skbs);
>  
>  	/* Basic L2 initialization */
>  
> +	/* Set MAC IFG Gaps
> +	 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
> +	 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
> +	 */
> +	ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
> +			   DEV_MAC_IFG_CFG);
> +
> +	/* Load seed (0) and set MAC HDX late collision  */
> +	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
> +			   DEV_MAC_HDX_CFG_SEED_LOAD,
> +			   DEV_MAC_HDX_CFG);
> +	mdelay(1);
> +	ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
> +			   DEV_MAC_HDX_CFG);
> +
> +	/* Set Max Length and maximum tags allowed */
> +	ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
> +			   DEV_MAC_MAXLEN_CFG);
> +	ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
> +			   DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
> +			   DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
> +			   DEV_MAC_TAGS_CFG);
> +
> +	/* Set SMAC of Pause frame (00:00:00:00:00:00) */
> +	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
> +	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
> +
> +	/* Set Pause WM hysteresis
> +	 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
> +	 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
> +	 */
> +	ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
> +			 SYS_PAUSE_CFG_PAUSE_STOP(101) |
> +			 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
> +
> +	/* Tail dropping watermark */
> +	atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
> +	ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
> +			 SYS_ATOP, port);
> +	ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
> +
>  	/* Drop frames with multicast source address */
>  	ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
>  		       ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
> -- 
> 2.17.1
> 

Re: [PATCH net-next 03/12] net: mscc: ocelot: move invariant configs out of adjust_link

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:35, Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Tue, Nov 12, 2019 at 02:44:11PM +0200, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > It doesn't make sense to rewrite all these registers every time the PHY
> > library notifies us about a link state change.
> >
> > In a future patch we will customize the MTU for the CPU port, and since
> > the MTU was previously configured from adjust_link, if we don't make
> > this change, its value would have got overridden.
>
> This is also a good change in preparation of PHYLINK.  When you do
> that conversion, ocelot_adjust_link() is likely to become
> ocelot_mac_config(). It should only change hardware state when there
> actually is a change in link state. This is something drivers often
> get wrong.
>

Yes. We'll need PHYLINK because the CPU port is 2.5G fixed-link, which
is something PHYLIB can't describe. One at a time, though.

> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>
>     Andrew
>
>

[snip]

Re: [PATCH net-next 03/12] net: mscc: ocelot: move invariant configs out of adjust_link

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> It doesn't make sense to rewrite all these registers every time the PHY
> library notifies us about a link state change.
> 
> In a future patch we will customize the MTU for the CPU port, and since
> the MTU was previously configured from adjust_link, if we don't make
> this change, its value would have got overridden.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

[PATCH net-next 04/12] net: mscc: ocelot: create a helper for changing the port MTU

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Since in an NPI/DSA setup, not all ports will have the same MTU, we need
to make sure the watermarks for pause frames and/or tail dropping logic
that existed in the driver is still coherent for the new MTU values.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.c | 40 +++++++++++++++++-------------
 1 file changed, 23 insertions(+), 17 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 4558c09e2e8a..8ede8ad902c9 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -2097,11 +2097,32 @@ static int ocelot_init_timestamp(struct ocelot *ocelot)
 	return 0;
 }
 
-static void ocelot_init_port(struct ocelot *ocelot, int port)
+static void ocelot_port_set_mtu(struct ocelot *ocelot, int port, size_t mtu)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
 	int atop_wm;
 
+	ocelot_port_writel(ocelot_port, mtu, DEV_MAC_MAXLEN_CFG);
+
+	/* Set Pause WM hysteresis
+	 * 152 = 6 * mtu / OCELOT_BUFFER_CELL_SZ
+	 * 101 = 4 * mtu / OCELOT_BUFFER_CELL_SZ
+	 */
+	ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
+			 SYS_PAUSE_CFG_PAUSE_STOP(101) |
+			 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
+
+	/* Tail dropping watermark */
+	atop_wm = (ocelot->shared_queue_sz - 9 * mtu) / OCELOT_BUFFER_CELL_SZ;
+	ocelot_write_rix(ocelot, ocelot_wm_enc(9 * mtu),
+			 SYS_ATOP, port);
+	ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
+}
+
+static void ocelot_init_port(struct ocelot *ocelot, int port)
+{
+	struct ocelot_port *ocelot_port = ocelot->ports[port];
+
 	INIT_LIST_HEAD(&ocelot_port->skbs);
 
 	/* Basic L2 initialization */
@@ -2122,8 +2143,7 @@ static void ocelot_init_port(struct ocelot *ocelot, int port)
 			   DEV_MAC_HDX_CFG);
 
 	/* Set Max Length and maximum tags allowed */
-	ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
-			   DEV_MAC_MAXLEN_CFG);
+	ocelot_port_set_mtu(ocelot, port, VLAN_ETH_FRAME_LEN);
 	ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
 			   DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
 			   DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
@@ -2133,20 +2153,6 @@ static void ocelot_init_port(struct ocelot *ocelot, int port)
 	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
 	ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
 
-	/* Set Pause WM hysteresis
-	 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
-	 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
-	 */
-	ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
-			 SYS_PAUSE_CFG_PAUSE_STOP(101) |
-			 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
-
-	/* Tail dropping watermark */
-	atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
-	ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
-			 SYS_ATOP, port);
-	ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
-
 	/* Drop frames with multicast source address */
 	ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
 		       ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
-- 
2.17.1

Re: [PATCH net-next 04/12] net: mscc: ocelot: create a helper for changing the port MTU

[Andrew Lunn]

On Tue, Nov 12, 2019 at 02:44:12PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> Since in an NPI/DSA setup, not all ports will have the same MTU

By this, do you mean that the CPU port needs a bigger MTU because of
the extra header?

    Andrew

Re: [PATCH net-next 04/12] net: mscc: ocelot: create a helper for changing the port MTU

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:40, Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Tue, Nov 12, 2019 at 02:44:12PM +0200, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > Since in an NPI/DSA setup, not all ports will have the same MTU
>
> By this, do you mean that the CPU port needs a bigger MTU because of
> the extra header?

Yes, see the next patch.

>
>     Andrew

Re: [PATCH net-next 04/12] net: mscc: ocelot: create a helper for changing the port MTU

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> Since in an NPI/DSA setup, not all ports will have the same MTU, we need
> to make sure the watermarks for pause frames and/or tail dropping logic
> that existed in the driver is still coherent for the new MTU values.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

[PATCH net-next 05/12] net: mscc: ocelot: export a constant for the tag length in bytes

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This constant will be used in a future patch to increase the MTU on NPI
ports, and will also be used in the tagger driver for Felix.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.c       | 4 ++--
 drivers/net/ethernet/mscc/ocelot.h       | 4 ++--
 drivers/net/ethernet/mscc/ocelot_board.c | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 8ede8ad902c9..8b73d760dfa5 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -576,11 +576,11 @@ static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
 	struct skb_shared_info *shinfo = skb_shinfo(skb);
 	struct ocelot_port *ocelot_port = &priv->port;
 	struct ocelot *ocelot = ocelot_port->ocelot;
+	u32 val, ifh[OCELOT_TAG_LEN / 4];
 	struct frame_info info = {};
 	u8 grp = 0; /* Send everything on CPU group 0 */
 	unsigned int i, count, last;
 	int port = priv->chip_port;
-	u32 val, ifh[IFH_LEN];
 
 	val = ocelot_read(ocelot, QS_INJ_STATUS);
 	if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
@@ -603,7 +603,7 @@ static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
 
 	ocelot_gen_ifh(ifh, &info);
 
-	for (i = 0; i < IFH_LEN; i++)
+	for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
 		ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
 				 QS_INJ_WR, grp);
 
diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
index 7e28434c22c1..9159b0adf1e7 100644
--- a/drivers/net/ethernet/mscc/ocelot.h
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -43,8 +43,6 @@
 
 #define OCELOT_PTP_QUEUE_SZ	128
 
-#define IFH_LEN 4
-
 struct frame_info {
 	u32 len;
 	u16 port;
@@ -66,6 +64,8 @@ struct frame_info {
 #define IFH_REW_OP_TWO_STEP_PTP		0x3
 #define IFH_REW_OP_ORIGIN_PTP		0x5
 
+#define OCELOT_TAG_LEN			16
+
 #define OCELOT_SPEED_2500 0
 #define OCELOT_SPEED_1000 1
 #define OCELOT_SPEED_100  2
diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c
index de2da6d33d43..32aafd951483 100644
--- a/drivers/net/ethernet/mscc/ocelot_board.c
+++ b/drivers/net/ethernet/mscc/ocelot_board.c
@@ -105,7 +105,7 @@ static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
 		int sz, len, buf_len;
 		struct sk_buff *skb;
 
-		for (i = 0; i < IFH_LEN; i++) {
+		for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
 			err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]);
 			if (err != 4)
 				break;
-- 
2.17.1

Re: [PATCH net-next 05/12] net: mscc: ocelot: export a constant for the tag length in bytes

[Andrew Lunn]

On Tue, Nov 12, 2019 at 02:44:13PM +0200, Vladimir Oltean wrote:
65;5800;1c> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> This constant will be used in a future patch to increase the MTU on NPI
> ports, and will also be used in the tagger driver for Felix.

Another example of the next patch explaining the previous patch :-)

Maybe this indicates the 'why' is missing from the commit messages?

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next 05/12] net: mscc: ocelot: export a constant for the tag length in bytes

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> This constant will be used in a future patch to increase the MTU on NPI
> ports, and will also be used in the tagger driver for Felix.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

[PATCH net-next 06/12] net: mscc: ocelot: adjust MTU on the CPU port in NPI mode

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

When using the NPI port, the DSA tag is passed through Ethernet, so the
switch's MAC needs to accept it as it comes from the DSA master. Increase
the MTU on the external CPU port to account for the length of the
injection header.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.c | 9 +++++++++
 drivers/net/ethernet/mscc/ocelot.h | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 8b73d760dfa5..42da193a8240 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -2230,9 +2230,18 @@ void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
 	 * Only one port can be an NPI at the same time.
 	 */
 	if (cpu < ocelot->num_phys_ports) {
+		int mtu = VLAN_ETH_FRAME_LEN + OCELOT_TAG_LEN;
+
 		ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
 			     QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu),
 			     QSYS_EXT_CPU_CFG);
+
+		if (injection == OCELOT_TAG_PREFIX_SHORT)
+			mtu += OCELOT_SHORT_PREFIX_LEN;
+		else if (injection == OCELOT_TAG_PREFIX_LONG)
+			mtu += OCELOT_LONG_PREFIX_LEN;
+
+		ocelot_port_set_mtu(ocelot, cpu, mtu);
 	}
 
 	/* CPU port Injection/Extraction configuration */
diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
index 9159b0adf1e7..bdc9b1d34b81 100644
--- a/drivers/net/ethernet/mscc/ocelot.h
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -65,6 +65,8 @@ struct frame_info {
 #define IFH_REW_OP_ORIGIN_PTP		0x5
 
 #define OCELOT_TAG_LEN			16
+#define OCELOT_SHORT_PREFIX_LEN		4
+#define OCELOT_LONG_PREFIX_LEN		16
 
 #define OCELOT_SPEED_2500 0
 #define OCELOT_SPEED_1000 1
-- 
2.17.1

Re: [PATCH net-next 06/12] net: mscc: ocelot: adjust MTU on the CPU port in NPI mode

[Andrew Lunn]

On Tue, Nov 12, 2019 at 02:44:14PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> When using the NPI port, the DSA tag is passed through Ethernet, so the
> switch's MAC needs to accept it as it comes from the DSA master. Increase
> the MTU on the external CPU port to account for the length of the
> injection header.

I think this is the only DSA driver which needs to do this. Generally,
the port knows it is adding/removing the extra header, and so
magically accepts bigger frames.

Where i have seen issues is the other end, the host interface. It
sometimes drops 'full MTU' frames because the DSA header makes the
frame too big.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next 06/12] net: mscc: ocelot: adjust MTU on the CPU port in NPI mode

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:51, Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Tue, Nov 12, 2019 at 02:44:14PM +0200, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > When using the NPI port, the DSA tag is passed through Ethernet, so the
> > switch's MAC needs to accept it as it comes from the DSA master. Increase
> > the MTU on the external CPU port to account for the length of the
> > injection header.
>
> I think this is the only DSA driver which needs to do this. Generally,
> the port knows it is adding/removing the extra header, and so
> magically accepts bigger frames.
>
> Where i have seen issues is the other end, the host interface. It
> sometimes drops 'full MTU' frames because the DSA header makes the
> frame too big.
>

No, that worked out of the box because DSA adjusts the MTU of the
master interface by the amount of bytes specified in the overhead of
the tagger.

> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>
>     Andrew

Re: [PATCH net-next 06/12] net: mscc: ocelot: adjust MTU on the CPU port in NPI mode

[Andrew Lunn]

On Tue, Nov 12, 2019 at 03:52:51PM +0200, Vladimir Oltean wrote:
> On Tue, 12 Nov 2019 at 15:51, Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > On Tue, Nov 12, 2019 at 02:44:14PM +0200, Vladimir Oltean wrote:
> > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > >
> > > When using the NPI port, the DSA tag is passed through Ethernet, so the
> > > switch's MAC needs to accept it as it comes from the DSA master. Increase
> > > the MTU on the external CPU port to account for the length of the
> > > injection header.
> >
> > I think this is the only DSA driver which needs to do this. Generally,
> > the port knows it is adding/removing the extra header, and so
> > magically accepts bigger frames.
> >
> > Where i have seen issues is the other end, the host interface. It
> > sometimes drops 'full MTU' frames because the DSA header makes the
> > frame too big.
> >
> 
> No, that worked out of the box because DSA adjusts the MTU of the
> master interface by the amount of bytes specified in the overhead of
> the tagger.

Yes, i added that code, after having to modify too many MAC drivers!

     Andrew

Re: [PATCH net-next 06/12] net: mscc: ocelot: adjust MTU on the CPU port in NPI mode

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> When using the NPI port, the DSA tag is passed through Ethernet, so the
> switch's MAC needs to accept it as it comes from the DSA master. Increase
> the MTU on the external CPU port to account for the length of the
> injection header.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

[PATCH net-next 07/12] net: mscc: ocelot: separate the implementation of switch reset

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

The Felix switch has a different reset procedure, so a function pointer
needs to be created and added to the ocelot_ops structure.

The reset procedure has been moved into ocelot_init.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.c       |  3 ++
 drivers/net/ethernet/mscc/ocelot.h       |  1 +
 drivers/net/ethernet/mscc/ocelot_board.c | 37 +++++++++++++++---------
 3 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 42da193a8240..0fe928026e61 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -2294,6 +2294,9 @@ int ocelot_init(struct ocelot *ocelot)
 	ocelot_vlan_init(ocelot);
 	ocelot_ace_init(ocelot);
 
+	if (ocelot->ops->reset)
+		ocelot->ops->reset(ocelot);
+
 	for (port = 0; port < ocelot->num_phys_ports; port++) {
 		/* Clear all counters (5 groups) */
 		ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
index bdc9b1d34b81..199ca2d6ea32 100644
--- a/drivers/net/ethernet/mscc/ocelot.h
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -446,6 +446,7 @@ struct ocelot_stat_layout {
 
 struct ocelot_ops {
 	void (*pcs_init)(struct ocelot *ocelot, int port);
+	int (*reset)(struct ocelot *ocelot);
 };
 
 struct ocelot {
diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c
index 32aafd951483..5581b3b0165c 100644
--- a/drivers/net/ethernet/mscc/ocelot_board.c
+++ b/drivers/net/ethernet/mscc/ocelot_board.c
@@ -277,8 +277,32 @@ static void ocelot_port_pcs_init(struct ocelot *ocelot, int port)
 	ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
 }
 
+static int ocelot_reset(struct ocelot *ocelot)
+{
+	int retries = 100;
+	u32 val;
+
+	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
+	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
+
+	do {
+		msleep(1);
+		regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
+				  &val);
+	} while (val && --retries);
+
+	if (!retries)
+		return -ETIMEDOUT;
+
+	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
+	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
+
+	return 0;
+}
+
 static const struct ocelot_ops ocelot_ops = {
 	.pcs_init		= ocelot_port_pcs_init,
+	.reset			= ocelot_reset,
 };
 
 static int mscc_ocelot_probe(struct platform_device *pdev)
@@ -289,7 +313,6 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
 	struct ocelot *ocelot;
 	struct regmap *hsio;
 	unsigned int i;
-	u32 val;
 
 	struct {
 		enum ocelot_target id;
@@ -369,18 +392,6 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
 		ocelot->ptp = 1;
 	}
 
-	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
-	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
-
-	do {
-		msleep(1);
-		regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
-				  &val);
-	} while (val);
-
-	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
-	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
-
 	ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */
 
 	ports = of_get_child_by_name(np, "ethernet-ports");
-- 
2.17.1

Re: [PATCH net-next 07/12] net: mscc: ocelot: separate the implementation of switch reset

[Andrew Lunn]

On Tue, Nov 12, 2019 at 02:44:15PM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> The Felix switch has a different reset procedure, so a function pointer
> needs to be created and added to the ocelot_ops structure.
> 
> The reset procedure has been moved into ocelot_init.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
>  drivers/net/ethernet/mscc/ocelot.c       |  3 ++
>  drivers/net/ethernet/mscc/ocelot.h       |  1 +
>  drivers/net/ethernet/mscc/ocelot_board.c | 37 +++++++++++++++---------

I'm wondering about the name board. So far, the code you have moved
into ocelot_board has nothing to do with the board as such. This is
not a GPIO used to reset the switch, it is not a regulator, etc. It is
all internal to the device, but just differs per family. Maybe you can
think of a better name?

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next 07/12] net: mscc: ocelot: separate the implementation of switch reset

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:56, Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Tue, Nov 12, 2019 at 02:44:15PM +0200, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > The Felix switch has a different reset procedure, so a function pointer
> > needs to be created and added to the ocelot_ops structure.
> >
> > The reset procedure has been moved into ocelot_init.
> >
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > ---
> >  drivers/net/ethernet/mscc/ocelot.c       |  3 ++
> >  drivers/net/ethernet/mscc/ocelot.h       |  1 +
> >  drivers/net/ethernet/mscc/ocelot_board.c | 37 +++++++++++++++---------
>
> I'm wondering about the name board. So far, the code you have moved
> into ocelot_board has nothing to do with the board as such. This is
> not a GPIO used to reset the switch, it is not a regulator, etc. It is
> all internal to the device, but just differs per family. Maybe you can
> think of a better name?
>

Alexandre, what do you think? I agree "ocelot_board" is a bit strange.

> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>
>     Andrew

Re: [PATCH net-next 07/12] net: mscc: ocelot: separate the implementation of switch reset

[Alexandre Belloni]

On 12/11/2019 15:59:37+0200, Vladimir Oltean wrote:
> On Tue, 12 Nov 2019 at 15:56, Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > On Tue, Nov 12, 2019 at 02:44:15PM +0200, Vladimir Oltean wrote:
> > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > >
> > > The Felix switch has a different reset procedure, so a function pointer
> > > needs to be created and added to the ocelot_ops structure.
> > >
> > > The reset procedure has been moved into ocelot_init.
> > >
> > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > > ---
> > >  drivers/net/ethernet/mscc/ocelot.c       |  3 ++
> > >  drivers/net/ethernet/mscc/ocelot.h       |  1 +
> > >  drivers/net/ethernet/mscc/ocelot_board.c | 37 +++++++++++++++---------
> >
> > I'm wondering about the name board. So far, the code you have moved
> > into ocelot_board has nothing to do with the board as such. This is
> > not a GPIO used to reset the switch, it is not a regulator, etc. It is
> > all internal to the device, but just differs per family. Maybe you can
> > think of a better name?
> >
> 
> Alexandre, what do you think? I agree "ocelot_board" is a bit strange.
> 

The name was coming from mscc, Allan agreed to rename it to
ocelot_vsc7514.c which would make sense.


-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH net-next 07/12] net: mscc: ocelot: separate the implementation of switch reset

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> The Felix switch has a different reset procedure, so a function pointer
> needs to be created and added to the ocelot_ops structure.
> 
> The reset procedure has been moved into ocelot_init.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
>  drivers/net/ethernet/mscc/ocelot.c       |  3 ++
>  drivers/net/ethernet/mscc/ocelot.h       |  1 +
>  drivers/net/ethernet/mscc/ocelot_board.c | 37 +++++++++++++++---------
>  3 files changed, 28 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
> index 42da193a8240..0fe928026e61 100644
> --- a/drivers/net/ethernet/mscc/ocelot.c
> +++ b/drivers/net/ethernet/mscc/ocelot.c
> @@ -2294,6 +2294,9 @@ int ocelot_init(struct ocelot *ocelot)
>  	ocelot_vlan_init(ocelot);
>  	ocelot_ace_init(ocelot);
>  
> +	if (ocelot->ops->reset)
> +		ocelot->ops->reset(ocelot);

We were not checking doing any error code checking, but arguably we know
should, any reason not to propagate the error code?
-- 
Florian

[PATCH net-next 08/12] net: mscc: ocelot: publish structure definitions to include/soc/mscc/ocelot.h

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

We will be registering another switch driver based on ocelot, which
lives under drivers/net/dsa.

Make sure the Felix DSA front-end has the necessary abstractions to
implement a new Ocelot driver instantiation. This includes the function
prototypes for implementing DSA callbacks.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.c |  79 ++--
 drivers/net/ethernet/mscc/ocelot.h | 482 +-------------------
 include/soc/mscc/ocelot.h          | 698 +++++++++++++++++++++++++++++
 3 files changed, 747 insertions(+), 512 deletions(-)
 create mode 100644 include/soc/mscc/ocelot.h

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 0fe928026e61..96f8d2d82570 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -21,7 +21,6 @@
 #include <net/netevent.h>
 #include <net/rtnetlink.h>
 #include <net/switchdev.h>
-#include <net/dsa.h>
 
 #include "ocelot.h"
 #include "ocelot_ace.h"
@@ -184,8 +183,8 @@ static void ocelot_vlan_mode(struct ocelot *ocelot, int port,
 	ocelot_write(ocelot, val, ANA_VLANMASK);
 }
 
-static void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
-				       bool vlan_aware)
+void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
+				bool vlan_aware)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
 	u32 val;
@@ -230,6 +229,7 @@ static void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
 		       REW_TAG_CFG_TAG_CFG_M,
 		       REW_TAG_CFG, port);
 }
+EXPORT_SYMBOL(ocelot_port_vlan_filtering);
 
 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
 				       u16 vid)
@@ -267,8 +267,8 @@ static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid)
 	ocelot_port->pvid = pvid;
 }
 
-static int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
-			   bool untagged)
+int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
+		    bool untagged)
 {
 	int ret;
 
@@ -291,6 +291,7 @@ static int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
 
 	return 0;
 }
+EXPORT_SYMBOL(ocelot_vlan_add);
 
 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
 			       bool untagged)
@@ -312,7 +313,7 @@ static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
 	return 0;
 }
 
-static int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
+int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
 	int ret;
@@ -333,6 +334,7 @@ static int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
 
 	return 0;
 }
+EXPORT_SYMBOL(ocelot_vlan_del);
 
 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
 {
@@ -404,8 +406,8 @@ static u16 ocelot_wm_enc(u16 value)
 	return value;
 }
 
-static void ocelot_adjust_link(struct ocelot *ocelot, int port,
-			       struct phy_device *phydev)
+void ocelot_adjust_link(struct ocelot *ocelot, int port,
+			struct phy_device *phydev)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
 	int speed, mode = 0;
@@ -471,6 +473,7 @@ static void ocelot_adjust_link(struct ocelot *ocelot, int port,
 			 SYS_MAC_FC_CFG, port);
 	ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
 }
+EXPORT_SYMBOL(ocelot_adjust_link);
 
 static void ocelot_port_adjust_link(struct net_device *dev)
 {
@@ -481,8 +484,8 @@ static void ocelot_port_adjust_link(struct net_device *dev)
 	ocelot_adjust_link(ocelot, port, dev->phydev);
 }
 
-static void ocelot_port_enable(struct ocelot *ocelot, int port,
-			       struct phy_device *phy)
+void ocelot_port_enable(struct ocelot *ocelot, int port,
+			struct phy_device *phy)
 {
 	/* Enable receiving frames on the port, and activate auto-learning of
 	 * MAC addresses.
@@ -492,6 +495,7 @@ static void ocelot_port_enable(struct ocelot *ocelot, int port,
 			 ANA_PORT_PORT_CFG_PORTID_VAL(port),
 			 ANA_PORT_PORT_CFG, port);
 }
+EXPORT_SYMBOL(ocelot_port_enable);
 
 static int ocelot_port_open(struct net_device *dev)
 {
@@ -526,7 +530,7 @@ static int ocelot_port_open(struct net_device *dev)
 	return 0;
 }
 
-static void ocelot_port_disable(struct ocelot *ocelot, int port)
+void ocelot_port_disable(struct ocelot *ocelot, int port)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
 
@@ -534,6 +538,7 @@ static void ocelot_port_disable(struct ocelot *ocelot, int port)
 	ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
 		       QSYS_SWITCH_PORT_MODE, port);
 }
+EXPORT_SYMBOL(ocelot_port_disable);
 
 static int ocelot_port_stop(struct net_device *dev)
 {
@@ -790,9 +795,8 @@ static void ocelot_get_stats64(struct net_device *dev,
 	stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
 }
 
-static int ocelot_fdb_add(struct ocelot *ocelot, int port,
-			  const unsigned char *addr, u16 vid,
-			  bool vlan_aware)
+int ocelot_fdb_add(struct ocelot *ocelot, int port,
+		   const unsigned char *addr, u16 vid, bool vlan_aware)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
 
@@ -812,6 +816,7 @@ static int ocelot_fdb_add(struct ocelot *ocelot, int port,
 
 	return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
 }
+EXPORT_SYMBOL(ocelot_fdb_add);
 
 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
 			       struct net_device *dev,
@@ -826,11 +831,12 @@ static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
 	return ocelot_fdb_add(ocelot, port, addr, vid, priv->vlan_aware);
 }
 
-static int ocelot_fdb_del(struct ocelot *ocelot, int port,
-			  const unsigned char *addr, u16 vid)
+int ocelot_fdb_del(struct ocelot *ocelot, int port,
+		   const unsigned char *addr, u16 vid)
 {
 	return ocelot_mact_forget(ocelot, addr, vid);
 }
+EXPORT_SYMBOL(ocelot_fdb_del);
 
 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
 			       struct net_device *dev,
@@ -940,8 +946,8 @@ static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
 	return 0;
 }
 
-static int ocelot_fdb_dump(struct ocelot *ocelot, int port,
-			   dsa_fdb_dump_cb_t *cb, void *data)
+int ocelot_fdb_dump(struct ocelot *ocelot, int port,
+		    dsa_fdb_dump_cb_t *cb, void *data)
 {
 	int i, j;
 
@@ -973,6 +979,7 @@ static int ocelot_fdb_dump(struct ocelot *ocelot, int port,
 
 	return 0;
 }
+EXPORT_SYMBOL(ocelot_fdb_dump);
 
 static int ocelot_port_fdb_dump(struct sk_buff *skb,
 				struct netlink_callback *cb,
@@ -1153,8 +1160,7 @@ static const struct net_device_ops ocelot_port_netdev_ops = {
 	.ndo_do_ioctl			= ocelot_ioctl,
 };
 
-static void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset,
-			       u8 *data)
+void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
 {
 	int i;
 
@@ -1165,6 +1171,7 @@ static void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset,
 		memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
 		       ETH_GSTRING_LEN);
 }
+EXPORT_SYMBOL(ocelot_get_strings);
 
 static void ocelot_port_get_strings(struct net_device *netdev, u32 sset,
 				    u8 *data)
@@ -1216,7 +1223,7 @@ static void ocelot_check_stats_work(struct work_struct *work)
 			   OCELOT_STATS_CHECK_DELAY);
 }
 
-static void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
+void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
 {
 	int i;
 
@@ -1227,6 +1234,7 @@ static void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
 	for (i = 0; i < ocelot->num_stats; i++)
 		*data++ = ocelot->stats[port * ocelot->num_stats + i];
 }
+EXPORT_SYMBOL(ocelot_get_ethtool_stats);
 
 static void ocelot_port_get_ethtool_stats(struct net_device *dev,
 					  struct ethtool_stats *stats,
@@ -1239,13 +1247,14 @@ static void ocelot_port_get_ethtool_stats(struct net_device *dev,
 	ocelot_get_ethtool_stats(ocelot, port, data);
 }
 
-static int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
+int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
 {
 	if (sset != ETH_SS_STATS)
 		return -EOPNOTSUPP;
 
 	return ocelot->num_stats;
 }
+EXPORT_SYMBOL(ocelot_get_sset_count);
 
 static int ocelot_port_get_sset_count(struct net_device *dev, int sset)
 {
@@ -1256,8 +1265,8 @@ static int ocelot_port_get_sset_count(struct net_device *dev, int sset)
 	return ocelot_get_sset_count(ocelot, port, sset);
 }
 
-static int ocelot_get_ts_info(struct ocelot *ocelot, int port,
-			      struct ethtool_ts_info *info)
+int ocelot_get_ts_info(struct ocelot *ocelot, int port,
+		       struct ethtool_ts_info *info)
 {
 	info->phc_index = ocelot->ptp_clock ?
 			  ptp_clock_index(ocelot->ptp_clock) : -1;
@@ -1273,6 +1282,7 @@ static int ocelot_get_ts_info(struct ocelot *ocelot, int port,
 
 	return 0;
 }
+EXPORT_SYMBOL(ocelot_get_ts_info);
 
 static int ocelot_port_get_ts_info(struct net_device *dev,
 				   struct ethtool_ts_info *info)
@@ -1296,8 +1306,7 @@ static const struct ethtool_ops ocelot_ethtool_ops = {
 	.get_ts_info		= ocelot_port_get_ts_info,
 };
 
-static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port,
-					u8 state)
+void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
 {
 	u32 port_cfg;
 	int p, i;
@@ -1358,6 +1367,7 @@ static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port,
 		}
 	}
 }
+EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
 
 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port,
 					   struct switchdev_trans *trans,
@@ -1369,11 +1379,12 @@ static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port,
 	ocelot_bridge_stp_state_set(ocelot, port, state);
 }
 
-static void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
+void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
 {
 	ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2),
 		     ANA_AUTOAGE);
 }
+EXPORT_SYMBOL(ocelot_set_ageing_time);
 
 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port,
 					unsigned long ageing_clock_t)
@@ -1604,8 +1615,8 @@ static int ocelot_port_obj_del(struct net_device *dev,
 	return ret;
 }
 
-static int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
-				   struct net_device *bridge)
+int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
+			    struct net_device *bridge)
 {
 	if (!ocelot->bridge_mask) {
 		ocelot->hw_bridge_dev = bridge;
@@ -1620,9 +1631,10 @@ static int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
 
 	return 0;
 }
+EXPORT_SYMBOL(ocelot_port_bridge_join);
 
-static int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
-				    struct net_device *bridge)
+int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
+			     struct net_device *bridge)
 {
 	ocelot->bridge_mask &= ~BIT(port);
 
@@ -1633,6 +1645,7 @@ static int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
 	ocelot_port_set_pvid(ocelot, port, 0);
 	return ocelot_port_set_native_vlan(ocelot, port, 0);
 }
+EXPORT_SYMBOL(ocelot_port_bridge_leave);
 
 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
 {
@@ -2119,7 +2132,7 @@ static void ocelot_port_set_mtu(struct ocelot *ocelot, int port, size_t mtu)
 	ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
 }
 
-static void ocelot_init_port(struct ocelot *ocelot, int port)
+void ocelot_init_port(struct ocelot *ocelot, int port)
 {
 	struct ocelot_port *ocelot_port = ocelot->ports[port];
 
@@ -2166,6 +2179,7 @@ static void ocelot_init_port(struct ocelot *ocelot, int port)
 	/* Enable vcap lookups */
 	ocelot_vcap_enable(ocelot, port);
 }
+EXPORT_SYMBOL(ocelot_init_port);
 
 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
 		      void __iomem *regs,
@@ -2211,7 +2225,6 @@ int ocelot_probe_port(struct ocelot *ocelot, u8 port,
 
 	return err;
 }
-EXPORT_SYMBOL(ocelot_probe_port);
 
 void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
 			 enum ocelot_tag_prefix injection,
diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
index 199ca2d6ea32..325afea3e846 100644
--- a/drivers/net/ethernet/mscc/ocelot.h
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -18,6 +18,7 @@
 #include <linux/ptp_clock_kernel.h>
 #include <linux/regmap.h>
 
+#include <soc/mscc/ocelot.h>
 #include "ocelot_ana.h"
 #include "ocelot_dev.h"
 #include "ocelot_qsys.h"
@@ -52,376 +53,6 @@ struct frame_info {
 	u32 timestamp;	/* rew_val */
 };
 
-#define IFH_INJ_BYPASS	BIT(31)
-#define IFH_INJ_POP_CNT_DISABLE (3 << 28)
-
-#define IFH_TAG_TYPE_C 0
-#define IFH_TAG_TYPE_S 1
-
-#define IFH_REW_OP_NOOP			0x0
-#define IFH_REW_OP_DSCP			0x1
-#define IFH_REW_OP_ONE_STEP_PTP		0x2
-#define IFH_REW_OP_TWO_STEP_PTP		0x3
-#define IFH_REW_OP_ORIGIN_PTP		0x5
-
-#define OCELOT_TAG_LEN			16
-#define OCELOT_SHORT_PREFIX_LEN		4
-#define OCELOT_LONG_PREFIX_LEN		16
-
-#define OCELOT_SPEED_2500 0
-#define OCELOT_SPEED_1000 1
-#define OCELOT_SPEED_100  2
-#define OCELOT_SPEED_10   3
-
-#define TARGET_OFFSET 24
-#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
-#define REG(reg, offset) [reg & REG_MASK] = offset
-
-enum ocelot_target {
-	ANA = 1,
-	QS,
-	QSYS,
-	REW,
-	SYS,
-	S2,
-	HSIO,
-	PTP,
-	TARGET_MAX,
-};
-
-enum ocelot_reg {
-	ANA_ADVLEARN = ANA << TARGET_OFFSET,
-	ANA_VLANMASK,
-	ANA_PORT_B_DOMAIN,
-	ANA_ANAGEFIL,
-	ANA_ANEVENTS,
-	ANA_STORMLIMIT_BURST,
-	ANA_STORMLIMIT_CFG,
-	ANA_ISOLATED_PORTS,
-	ANA_COMMUNITY_PORTS,
-	ANA_AUTOAGE,
-	ANA_MACTOPTIONS,
-	ANA_LEARNDISC,
-	ANA_AGENCTRL,
-	ANA_MIRRORPORTS,
-	ANA_EMIRRORPORTS,
-	ANA_FLOODING,
-	ANA_FLOODING_IPMC,
-	ANA_SFLOW_CFG,
-	ANA_PORT_MODE,
-	ANA_CUT_THRU_CFG,
-	ANA_PGID_PGID,
-	ANA_TABLES_ANMOVED,
-	ANA_TABLES_MACHDATA,
-	ANA_TABLES_MACLDATA,
-	ANA_TABLES_STREAMDATA,
-	ANA_TABLES_MACACCESS,
-	ANA_TABLES_MACTINDX,
-	ANA_TABLES_VLANACCESS,
-	ANA_TABLES_VLANTIDX,
-	ANA_TABLES_ISDXACCESS,
-	ANA_TABLES_ISDXTIDX,
-	ANA_TABLES_ENTRYLIM,
-	ANA_TABLES_PTP_ID_HIGH,
-	ANA_TABLES_PTP_ID_LOW,
-	ANA_TABLES_STREAMACCESS,
-	ANA_TABLES_STREAMTIDX,
-	ANA_TABLES_SEQ_HISTORY,
-	ANA_TABLES_SEQ_MASK,
-	ANA_TABLES_SFID_MASK,
-	ANA_TABLES_SFIDACCESS,
-	ANA_TABLES_SFIDTIDX,
-	ANA_MSTI_STATE,
-	ANA_OAM_UPM_LM_CNT,
-	ANA_SG_ACCESS_CTRL,
-	ANA_SG_CONFIG_REG_1,
-	ANA_SG_CONFIG_REG_2,
-	ANA_SG_CONFIG_REG_3,
-	ANA_SG_CONFIG_REG_4,
-	ANA_SG_CONFIG_REG_5,
-	ANA_SG_GCL_GS_CONFIG,
-	ANA_SG_GCL_TI_CONFIG,
-	ANA_SG_STATUS_REG_1,
-	ANA_SG_STATUS_REG_2,
-	ANA_SG_STATUS_REG_3,
-	ANA_PORT_VLAN_CFG,
-	ANA_PORT_DROP_CFG,
-	ANA_PORT_QOS_CFG,
-	ANA_PORT_VCAP_CFG,
-	ANA_PORT_VCAP_S1_KEY_CFG,
-	ANA_PORT_VCAP_S2_CFG,
-	ANA_PORT_PCP_DEI_MAP,
-	ANA_PORT_CPU_FWD_CFG,
-	ANA_PORT_CPU_FWD_BPDU_CFG,
-	ANA_PORT_CPU_FWD_GARP_CFG,
-	ANA_PORT_CPU_FWD_CCM_CFG,
-	ANA_PORT_PORT_CFG,
-	ANA_PORT_POL_CFG,
-	ANA_PORT_PTP_CFG,
-	ANA_PORT_PTP_DLY1_CFG,
-	ANA_PORT_PTP_DLY2_CFG,
-	ANA_PORT_SFID_CFG,
-	ANA_PFC_PFC_CFG,
-	ANA_PFC_PFC_TIMER,
-	ANA_IPT_OAM_MEP_CFG,
-	ANA_IPT_IPT,
-	ANA_PPT_PPT,
-	ANA_FID_MAP_FID_MAP,
-	ANA_AGGR_CFG,
-	ANA_CPUQ_CFG,
-	ANA_CPUQ_CFG2,
-	ANA_CPUQ_8021_CFG,
-	ANA_DSCP_CFG,
-	ANA_DSCP_REWR_CFG,
-	ANA_VCAP_RNG_TYPE_CFG,
-	ANA_VCAP_RNG_VAL_CFG,
-	ANA_VRAP_CFG,
-	ANA_VRAP_HDR_DATA,
-	ANA_VRAP_HDR_MASK,
-	ANA_DISCARD_CFG,
-	ANA_FID_CFG,
-	ANA_POL_PIR_CFG,
-	ANA_POL_CIR_CFG,
-	ANA_POL_MODE_CFG,
-	ANA_POL_PIR_STATE,
-	ANA_POL_CIR_STATE,
-	ANA_POL_STATE,
-	ANA_POL_FLOWC,
-	ANA_POL_HYST,
-	ANA_POL_MISC_CFG,
-	QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
-	QS_XTR_RD,
-	QS_XTR_FRM_PRUNING,
-	QS_XTR_FLUSH,
-	QS_XTR_DATA_PRESENT,
-	QS_XTR_CFG,
-	QS_INJ_GRP_CFG,
-	QS_INJ_WR,
-	QS_INJ_CTRL,
-	QS_INJ_STATUS,
-	QS_INJ_ERR,
-	QS_INH_DBG,
-	QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
-	QSYS_SWITCH_PORT_MODE,
-	QSYS_STAT_CNT_CFG,
-	QSYS_EEE_CFG,
-	QSYS_EEE_THRES,
-	QSYS_IGR_NO_SHARING,
-	QSYS_EGR_NO_SHARING,
-	QSYS_SW_STATUS,
-	QSYS_EXT_CPU_CFG,
-	QSYS_PAD_CFG,
-	QSYS_CPU_GROUP_MAP,
-	QSYS_QMAP,
-	QSYS_ISDX_SGRP,
-	QSYS_TIMED_FRAME_ENTRY,
-	QSYS_TFRM_MISC,
-	QSYS_TFRM_PORT_DLY,
-	QSYS_TFRM_TIMER_CFG_1,
-	QSYS_TFRM_TIMER_CFG_2,
-	QSYS_TFRM_TIMER_CFG_3,
-	QSYS_TFRM_TIMER_CFG_4,
-	QSYS_TFRM_TIMER_CFG_5,
-	QSYS_TFRM_TIMER_CFG_6,
-	QSYS_TFRM_TIMER_CFG_7,
-	QSYS_TFRM_TIMER_CFG_8,
-	QSYS_RED_PROFILE,
-	QSYS_RES_QOS_MODE,
-	QSYS_RES_CFG,
-	QSYS_RES_STAT,
-	QSYS_EGR_DROP_MODE,
-	QSYS_EQ_CTRL,
-	QSYS_EVENTS_CORE,
-	QSYS_QMAXSDU_CFG_0,
-	QSYS_QMAXSDU_CFG_1,
-	QSYS_QMAXSDU_CFG_2,
-	QSYS_QMAXSDU_CFG_3,
-	QSYS_QMAXSDU_CFG_4,
-	QSYS_QMAXSDU_CFG_5,
-	QSYS_QMAXSDU_CFG_6,
-	QSYS_QMAXSDU_CFG_7,
-	QSYS_PREEMPTION_CFG,
-	QSYS_CIR_CFG,
-	QSYS_EIR_CFG,
-	QSYS_SE_CFG,
-	QSYS_SE_DWRR_CFG,
-	QSYS_SE_CONNECT,
-	QSYS_SE_DLB_SENSE,
-	QSYS_CIR_STATE,
-	QSYS_EIR_STATE,
-	QSYS_SE_STATE,
-	QSYS_HSCH_MISC_CFG,
-	QSYS_TAG_CONFIG,
-	QSYS_TAS_PARAM_CFG_CTRL,
-	QSYS_PORT_MAX_SDU,
-	QSYS_PARAM_CFG_REG_1,
-	QSYS_PARAM_CFG_REG_2,
-	QSYS_PARAM_CFG_REG_3,
-	QSYS_PARAM_CFG_REG_4,
-	QSYS_PARAM_CFG_REG_5,
-	QSYS_GCL_CFG_REG_1,
-	QSYS_GCL_CFG_REG_2,
-	QSYS_PARAM_STATUS_REG_1,
-	QSYS_PARAM_STATUS_REG_2,
-	QSYS_PARAM_STATUS_REG_3,
-	QSYS_PARAM_STATUS_REG_4,
-	QSYS_PARAM_STATUS_REG_5,
-	QSYS_PARAM_STATUS_REG_6,
-	QSYS_PARAM_STATUS_REG_7,
-	QSYS_PARAM_STATUS_REG_8,
-	QSYS_PARAM_STATUS_REG_9,
-	QSYS_GCL_STATUS_REG_1,
-	QSYS_GCL_STATUS_REG_2,
-	REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
-	REW_TAG_CFG,
-	REW_PORT_CFG,
-	REW_DSCP_CFG,
-	REW_PCP_DEI_QOS_MAP_CFG,
-	REW_PTP_CFG,
-	REW_PTP_DLY1_CFG,
-	REW_RED_TAG_CFG,
-	REW_DSCP_REMAP_DP1_CFG,
-	REW_DSCP_REMAP_CFG,
-	REW_STAT_CFG,
-	REW_REW_STICKY,
-	REW_PPT,
-	SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
-	SYS_COUNT_RX_UNICAST,
-	SYS_COUNT_RX_MULTICAST,
-	SYS_COUNT_RX_BROADCAST,
-	SYS_COUNT_RX_SHORTS,
-	SYS_COUNT_RX_FRAGMENTS,
-	SYS_COUNT_RX_JABBERS,
-	SYS_COUNT_RX_CRC_ALIGN_ERRS,
-	SYS_COUNT_RX_SYM_ERRS,
-	SYS_COUNT_RX_64,
-	SYS_COUNT_RX_65_127,
-	SYS_COUNT_RX_128_255,
-	SYS_COUNT_RX_256_1023,
-	SYS_COUNT_RX_1024_1526,
-	SYS_COUNT_RX_1527_MAX,
-	SYS_COUNT_RX_PAUSE,
-	SYS_COUNT_RX_CONTROL,
-	SYS_COUNT_RX_LONGS,
-	SYS_COUNT_RX_CLASSIFIED_DROPS,
-	SYS_COUNT_TX_OCTETS,
-	SYS_COUNT_TX_UNICAST,
-	SYS_COUNT_TX_MULTICAST,
-	SYS_COUNT_TX_BROADCAST,
-	SYS_COUNT_TX_COLLISION,
-	SYS_COUNT_TX_DROPS,
-	SYS_COUNT_TX_PAUSE,
-	SYS_COUNT_TX_64,
-	SYS_COUNT_TX_65_127,
-	SYS_COUNT_TX_128_511,
-	SYS_COUNT_TX_512_1023,
-	SYS_COUNT_TX_1024_1526,
-	SYS_COUNT_TX_1527_MAX,
-	SYS_COUNT_TX_AGING,
-	SYS_RESET_CFG,
-	SYS_SR_ETYPE_CFG,
-	SYS_VLAN_ETYPE_CFG,
-	SYS_PORT_MODE,
-	SYS_FRONT_PORT_MODE,
-	SYS_FRM_AGING,
-	SYS_STAT_CFG,
-	SYS_SW_STATUS,
-	SYS_MISC_CFG,
-	SYS_REW_MAC_HIGH_CFG,
-	SYS_REW_MAC_LOW_CFG,
-	SYS_TIMESTAMP_OFFSET,
-	SYS_CMID,
-	SYS_PAUSE_CFG,
-	SYS_PAUSE_TOT_CFG,
-	SYS_ATOP,
-	SYS_ATOP_TOT_CFG,
-	SYS_MAC_FC_CFG,
-	SYS_MMGT,
-	SYS_MMGT_FAST,
-	SYS_EVENTS_DIF,
-	SYS_EVENTS_CORE,
-	SYS_CNT,
-	SYS_PTP_STATUS,
-	SYS_PTP_TXSTAMP,
-	SYS_PTP_NXT,
-	SYS_PTP_CFG,
-	SYS_RAM_INIT,
-	SYS_CM_ADDR,
-	SYS_CM_DATA_WR,
-	SYS_CM_DATA_RD,
-	SYS_CM_OP,
-	SYS_CM_DATA,
-	S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
-	S2_CORE_MV_CFG,
-	S2_CACHE_ENTRY_DAT,
-	S2_CACHE_MASK_DAT,
-	S2_CACHE_ACTION_DAT,
-	S2_CACHE_CNT_DAT,
-	S2_CACHE_TG_DAT,
-	PTP_PIN_CFG = PTP << TARGET_OFFSET,
-	PTP_PIN_TOD_SEC_MSB,
-	PTP_PIN_TOD_SEC_LSB,
-	PTP_PIN_TOD_NSEC,
-	PTP_CFG_MISC,
-	PTP_CLK_CFG_ADJ_CFG,
-	PTP_CLK_CFG_ADJ_FREQ,
-};
-
-enum ocelot_regfield {
-	ANA_ADVLEARN_VLAN_CHK,
-	ANA_ADVLEARN_LEARN_MIRROR,
-	ANA_ANEVENTS_FLOOD_DISCARD,
-	ANA_ANEVENTS_MSTI_DROP,
-	ANA_ANEVENTS_ACLKILL,
-	ANA_ANEVENTS_ACLUSED,
-	ANA_ANEVENTS_AUTOAGE,
-	ANA_ANEVENTS_VS2TTL1,
-	ANA_ANEVENTS_STORM_DROP,
-	ANA_ANEVENTS_LEARN_DROP,
-	ANA_ANEVENTS_AGED_ENTRY,
-	ANA_ANEVENTS_CPU_LEARN_FAILED,
-	ANA_ANEVENTS_AUTO_LEARN_FAILED,
-	ANA_ANEVENTS_LEARN_REMOVE,
-	ANA_ANEVENTS_AUTO_LEARNED,
-	ANA_ANEVENTS_AUTO_MOVED,
-	ANA_ANEVENTS_DROPPED,
-	ANA_ANEVENTS_CLASSIFIED_DROP,
-	ANA_ANEVENTS_CLASSIFIED_COPY,
-	ANA_ANEVENTS_VLAN_DISCARD,
-	ANA_ANEVENTS_FWD_DISCARD,
-	ANA_ANEVENTS_MULTICAST_FLOOD,
-	ANA_ANEVENTS_UNICAST_FLOOD,
-	ANA_ANEVENTS_DEST_KNOWN,
-	ANA_ANEVENTS_BUCKET3_MATCH,
-	ANA_ANEVENTS_BUCKET2_MATCH,
-	ANA_ANEVENTS_BUCKET1_MATCH,
-	ANA_ANEVENTS_BUCKET0_MATCH,
-	ANA_ANEVENTS_CPU_OPERATION,
-	ANA_ANEVENTS_DMAC_LOOKUP,
-	ANA_ANEVENTS_SMAC_LOOKUP,
-	ANA_ANEVENTS_SEQ_GEN_ERR_0,
-	ANA_ANEVENTS_SEQ_GEN_ERR_1,
-	ANA_TABLES_MACACCESS_B_DOM,
-	ANA_TABLES_MACTINDX_BUCKET,
-	ANA_TABLES_MACTINDX_M_INDEX,
-	QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
-	QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
-	QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
-	QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
-	QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
-	SYS_RESET_CFG_CORE_ENA,
-	SYS_RESET_CFG_MEM_ENA,
-	SYS_RESET_CFG_MEM_INIT,
-	REGFIELD_MAX
-};
-
-enum ocelot_clk_pins {
-	ALT_PPS_PIN	= 1,
-	EXT_CLK_PIN,
-	ALT_LDST_PIN,
-	TOD_ACC_PIN
-};
-
 struct ocelot_multicast {
 	struct list_head list;
 	unsigned char addr[ETH_ALEN];
@@ -429,88 +60,6 @@ struct ocelot_multicast {
 	u16 ports;
 };
 
-enum ocelot_tag_prefix {
-	OCELOT_TAG_PREFIX_DISABLED	= 0,
-	OCELOT_TAG_PREFIX_NONE,
-	OCELOT_TAG_PREFIX_SHORT,
-	OCELOT_TAG_PREFIX_LONG,
-};
-
-struct ocelot_port;
-struct ocelot;
-
-struct ocelot_stat_layout {
-	u32 offset;
-	char name[ETH_GSTRING_LEN];
-};
-
-struct ocelot_ops {
-	void (*pcs_init)(struct ocelot *ocelot, int port);
-	int (*reset)(struct ocelot *ocelot);
-};
-
-struct ocelot {
-	const struct ocelot_ops *ops;
-	struct device *dev;
-
-	struct regmap *targets[TARGET_MAX];
-	struct regmap_field *regfields[REGFIELD_MAX];
-	const u32 *const *map;
-	const struct ocelot_stat_layout *stats_layout;
-	unsigned int num_stats;
-
-	u8 base_mac[ETH_ALEN];
-
-	struct net_device *hw_bridge_dev;
-	u16 bridge_mask;
-	u16 bridge_fwd_mask;
-
-	struct workqueue_struct *ocelot_owq;
-
-	int shared_queue_sz;
-
-	u8 num_phys_ports;
-	u8 num_cpu_ports;
-	u8 cpu;
-	struct ocelot_port **ports;
-
-	u32 *lags;
-
-	/* Keep track of the vlan port masks */
-	u32 vlan_mask[VLAN_N_VID];
-
-	struct list_head multicast;
-
-	/* Workqueue to check statistics for overflow with its lock */
-	struct mutex stats_lock;
-	u64 *stats;
-	struct delayed_work stats_work;
-	struct workqueue_struct *stats_queue;
-
-	u8 ptp:1;
-	struct ptp_clock *ptp_clock;
-	struct ptp_clock_info ptp_info;
-	struct hwtstamp_config hwtstamp_config;
-	struct mutex ptp_lock; /* Protects the PTP interface state */
-	spinlock_t ptp_clock_lock; /* Protects the PTP clock */
-};
-
-struct ocelot_port {
-	struct ocelot *ocelot;
-
-	void __iomem *regs;
-
-	/* Ingress default VLAN (pvid) */
-	u16 pvid;
-
-	/* Egress default VLAN (vid) */
-	u16 vid;
-
-	u8 ptp_cmd;
-	struct list_head skbs;
-	u8 ts_id;
-};
-
 struct ocelot_port_private {
 	struct ocelot_port port;
 	struct net_device *dev;
@@ -531,37 +80,12 @@ struct ocelot_skb {
 	u8 id;
 };
 
-u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
-#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
-#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
-#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
-#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
-
-void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
-#define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
-#define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
-#define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
-#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
-
-void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
-		     u32 offset);
-#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
-#define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
-#define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
-#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
-
 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
 
-int ocelot_regfields_init(struct ocelot *ocelot,
-			  const struct reg_field *const regfields);
-struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
-
 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
 
-int ocelot_init(struct ocelot *ocelot);
-void ocelot_deinit(struct ocelot *ocelot);
 int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops);
 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
 		      void __iomem *regs,
@@ -575,7 +99,7 @@ extern struct notifier_block ocelot_netdevice_nb;
 extern struct notifier_block ocelot_switchdev_nb;
 extern struct notifier_block ocelot_switchdev_blocking_nb;
 
-int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
-void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts);
+#define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
+#define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
 
 #endif
diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h
new file mode 100644
index 000000000000..dd14d6dde3ab
--- /dev/null
+++ b/include/soc/mscc/ocelot.h
@@ -0,0 +1,698 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* Copyright (c) 2017 Microsemi Corporation
+ */
+
+#ifndef _SOC_MSCC_OCELOT_H
+#define _SOC_MSCC_OCELOT_H
+
+#include <linux/ptp_clock_kernel.h>
+#include <linux/net_tstamp.h>
+#include <linux/if_vlan.h>
+#include <linux/regmap.h>
+#include <net/dsa.h>
+
+#define IFH_INJ_BYPASS			BIT(31)
+#define IFH_INJ_POP_CNT_DISABLE		(3 << 28)
+
+#define IFH_TAG_TYPE_C			0
+#define IFH_TAG_TYPE_S			1
+
+#define IFH_REW_OP_NOOP			0x0
+#define IFH_REW_OP_DSCP			0x1
+#define IFH_REW_OP_ONE_STEP_PTP		0x2
+#define IFH_REW_OP_TWO_STEP_PTP		0x3
+#define IFH_REW_OP_ORIGIN_PTP		0x5
+
+#define OCELOT_TAG_LEN			16
+#define OCELOT_SHORT_PREFIX_LEN		4
+#define OCELOT_LONG_PREFIX_LEN		16
+
+#define OCELOT_SPEED_2500		0
+#define OCELOT_SPEED_1000		1
+#define OCELOT_SPEED_100		2
+#define OCELOT_SPEED_10			3
+
+#define TARGET_OFFSET			24
+#define REG_MASK			GENMASK(TARGET_OFFSET - 1, 0)
+#define REG(reg, offset)		[reg & REG_MASK] = offset
+
+#define REG_RESERVED_ADDR		0xffffffff
+#define REG_RESERVED(reg)		REG(reg, REG_RESERVED_ADDR)
+
+enum ocelot_target {
+	ANA = 1,
+	QS,
+	QSYS,
+	REW,
+	SYS,
+	S2,
+	HSIO,
+	PTP,
+	GCB,
+	TARGET_MAX,
+};
+
+enum ocelot_reg {
+	ANA_ADVLEARN = ANA << TARGET_OFFSET,
+	ANA_VLANMASK,
+	ANA_PORT_B_DOMAIN,
+	ANA_ANAGEFIL,
+	ANA_ANEVENTS,
+	ANA_STORMLIMIT_BURST,
+	ANA_STORMLIMIT_CFG,
+	ANA_ISOLATED_PORTS,
+	ANA_COMMUNITY_PORTS,
+	ANA_AUTOAGE,
+	ANA_MACTOPTIONS,
+	ANA_LEARNDISC,
+	ANA_AGENCTRL,
+	ANA_MIRRORPORTS,
+	ANA_EMIRRORPORTS,
+	ANA_FLOODING,
+	ANA_FLOODING_IPMC,
+	ANA_SFLOW_CFG,
+	ANA_PORT_MODE,
+	ANA_CUT_THRU_CFG,
+	ANA_PGID_PGID,
+	ANA_TABLES_ANMOVED,
+	ANA_TABLES_MACHDATA,
+	ANA_TABLES_MACLDATA,
+	ANA_TABLES_STREAMDATA,
+	ANA_TABLES_MACACCESS,
+	ANA_TABLES_MACTINDX,
+	ANA_TABLES_VLANACCESS,
+	ANA_TABLES_VLANTIDX,
+	ANA_TABLES_ISDXACCESS,
+	ANA_TABLES_ISDXTIDX,
+	ANA_TABLES_ENTRYLIM,
+	ANA_TABLES_PTP_ID_HIGH,
+	ANA_TABLES_PTP_ID_LOW,
+	ANA_TABLES_STREAMACCESS,
+	ANA_TABLES_STREAMTIDX,
+	ANA_TABLES_SEQ_HISTORY,
+	ANA_TABLES_SEQ_MASK,
+	ANA_TABLES_SFID_MASK,
+	ANA_TABLES_SFIDACCESS,
+	ANA_TABLES_SFIDTIDX,
+	ANA_MSTI_STATE,
+	ANA_OAM_UPM_LM_CNT,
+	ANA_SG_ACCESS_CTRL,
+	ANA_SG_CONFIG_REG_1,
+	ANA_SG_CONFIG_REG_2,
+	ANA_SG_CONFIG_REG_3,
+	ANA_SG_CONFIG_REG_4,
+	ANA_SG_CONFIG_REG_5,
+	ANA_SG_GCL_GS_CONFIG,
+	ANA_SG_GCL_TI_CONFIG,
+	ANA_SG_STATUS_REG_1,
+	ANA_SG_STATUS_REG_2,
+	ANA_SG_STATUS_REG_3,
+	ANA_PORT_VLAN_CFG,
+	ANA_PORT_DROP_CFG,
+	ANA_PORT_QOS_CFG,
+	ANA_PORT_VCAP_CFG,
+	ANA_PORT_VCAP_S1_KEY_CFG,
+	ANA_PORT_VCAP_S2_CFG,
+	ANA_PORT_PCP_DEI_MAP,
+	ANA_PORT_CPU_FWD_CFG,
+	ANA_PORT_CPU_FWD_BPDU_CFG,
+	ANA_PORT_CPU_FWD_GARP_CFG,
+	ANA_PORT_CPU_FWD_CCM_CFG,
+	ANA_PORT_PORT_CFG,
+	ANA_PORT_POL_CFG,
+	ANA_PORT_PTP_CFG,
+	ANA_PORT_PTP_DLY1_CFG,
+	ANA_PORT_PTP_DLY2_CFG,
+	ANA_PORT_SFID_CFG,
+	ANA_PFC_PFC_CFG,
+	ANA_PFC_PFC_TIMER,
+	ANA_IPT_OAM_MEP_CFG,
+	ANA_IPT_IPT,
+	ANA_PPT_PPT,
+	ANA_FID_MAP_FID_MAP,
+	ANA_AGGR_CFG,
+	ANA_CPUQ_CFG,
+	ANA_CPUQ_CFG2,
+	ANA_CPUQ_8021_CFG,
+	ANA_DSCP_CFG,
+	ANA_DSCP_REWR_CFG,
+	ANA_VCAP_RNG_TYPE_CFG,
+	ANA_VCAP_RNG_VAL_CFG,
+	ANA_VRAP_CFG,
+	ANA_VRAP_HDR_DATA,
+	ANA_VRAP_HDR_MASK,
+	ANA_DISCARD_CFG,
+	ANA_FID_CFG,
+	ANA_POL_PIR_CFG,
+	ANA_POL_CIR_CFG,
+	ANA_POL_MODE_CFG,
+	ANA_POL_PIR_STATE,
+	ANA_POL_CIR_STATE,
+	ANA_POL_STATE,
+	ANA_POL_FLOWC,
+	ANA_POL_HYST,
+	ANA_POL_MISC_CFG,
+	QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
+	QS_XTR_RD,
+	QS_XTR_FRM_PRUNING,
+	QS_XTR_FLUSH,
+	QS_XTR_DATA_PRESENT,
+	QS_XTR_CFG,
+	QS_INJ_GRP_CFG,
+	QS_INJ_WR,
+	QS_INJ_CTRL,
+	QS_INJ_STATUS,
+	QS_INJ_ERR,
+	QS_INH_DBG,
+	QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
+	QSYS_SWITCH_PORT_MODE,
+	QSYS_STAT_CNT_CFG,
+	QSYS_EEE_CFG,
+	QSYS_EEE_THRES,
+	QSYS_IGR_NO_SHARING,
+	QSYS_EGR_NO_SHARING,
+	QSYS_SW_STATUS,
+	QSYS_EXT_CPU_CFG,
+	QSYS_PAD_CFG,
+	QSYS_CPU_GROUP_MAP,
+	QSYS_QMAP,
+	QSYS_ISDX_SGRP,
+	QSYS_TIMED_FRAME_ENTRY,
+	QSYS_TFRM_MISC,
+	QSYS_TFRM_PORT_DLY,
+	QSYS_TFRM_TIMER_CFG_1,
+	QSYS_TFRM_TIMER_CFG_2,
+	QSYS_TFRM_TIMER_CFG_3,
+	QSYS_TFRM_TIMER_CFG_4,
+	QSYS_TFRM_TIMER_CFG_5,
+	QSYS_TFRM_TIMER_CFG_6,
+	QSYS_TFRM_TIMER_CFG_7,
+	QSYS_TFRM_TIMER_CFG_8,
+	QSYS_RED_PROFILE,
+	QSYS_RES_QOS_MODE,
+	QSYS_RES_CFG,
+	QSYS_RES_STAT,
+	QSYS_EGR_DROP_MODE,
+	QSYS_EQ_CTRL,
+	QSYS_EVENTS_CORE,
+	QSYS_QMAXSDU_CFG_0,
+	QSYS_QMAXSDU_CFG_1,
+	QSYS_QMAXSDU_CFG_2,
+	QSYS_QMAXSDU_CFG_3,
+	QSYS_QMAXSDU_CFG_4,
+	QSYS_QMAXSDU_CFG_5,
+	QSYS_QMAXSDU_CFG_6,
+	QSYS_QMAXSDU_CFG_7,
+	QSYS_PREEMPTION_CFG,
+	QSYS_CIR_CFG,
+	QSYS_EIR_CFG,
+	QSYS_SE_CFG,
+	QSYS_SE_DWRR_CFG,
+	QSYS_SE_CONNECT,
+	QSYS_SE_DLB_SENSE,
+	QSYS_CIR_STATE,
+	QSYS_EIR_STATE,
+	QSYS_SE_STATE,
+	QSYS_HSCH_MISC_CFG,
+	QSYS_TAG_CONFIG,
+	QSYS_TAS_PARAM_CFG_CTRL,
+	QSYS_PORT_MAX_SDU,
+	QSYS_PARAM_CFG_REG_1,
+	QSYS_PARAM_CFG_REG_2,
+	QSYS_PARAM_CFG_REG_3,
+	QSYS_PARAM_CFG_REG_4,
+	QSYS_PARAM_CFG_REG_5,
+	QSYS_GCL_CFG_REG_1,
+	QSYS_GCL_CFG_REG_2,
+	QSYS_PARAM_STATUS_REG_1,
+	QSYS_PARAM_STATUS_REG_2,
+	QSYS_PARAM_STATUS_REG_3,
+	QSYS_PARAM_STATUS_REG_4,
+	QSYS_PARAM_STATUS_REG_5,
+	QSYS_PARAM_STATUS_REG_6,
+	QSYS_PARAM_STATUS_REG_7,
+	QSYS_PARAM_STATUS_REG_8,
+	QSYS_PARAM_STATUS_REG_9,
+	QSYS_GCL_STATUS_REG_1,
+	QSYS_GCL_STATUS_REG_2,
+	REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
+	REW_TAG_CFG,
+	REW_PORT_CFG,
+	REW_DSCP_CFG,
+	REW_PCP_DEI_QOS_MAP_CFG,
+	REW_PTP_CFG,
+	REW_PTP_DLY1_CFG,
+	REW_RED_TAG_CFG,
+	REW_DSCP_REMAP_DP1_CFG,
+	REW_DSCP_REMAP_CFG,
+	REW_STAT_CFG,
+	REW_REW_STICKY,
+	REW_PPT,
+	SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
+	SYS_COUNT_RX_UNICAST,
+	SYS_COUNT_RX_MULTICAST,
+	SYS_COUNT_RX_BROADCAST,
+	SYS_COUNT_RX_SHORTS,
+	SYS_COUNT_RX_FRAGMENTS,
+	SYS_COUNT_RX_JABBERS,
+	SYS_COUNT_RX_CRC_ALIGN_ERRS,
+	SYS_COUNT_RX_SYM_ERRS,
+	SYS_COUNT_RX_64,
+	SYS_COUNT_RX_65_127,
+	SYS_COUNT_RX_128_255,
+	SYS_COUNT_RX_256_1023,
+	SYS_COUNT_RX_1024_1526,
+	SYS_COUNT_RX_1527_MAX,
+	SYS_COUNT_RX_PAUSE,
+	SYS_COUNT_RX_CONTROL,
+	SYS_COUNT_RX_LONGS,
+	SYS_COUNT_RX_CLASSIFIED_DROPS,
+	SYS_COUNT_TX_OCTETS,
+	SYS_COUNT_TX_UNICAST,
+	SYS_COUNT_TX_MULTICAST,
+	SYS_COUNT_TX_BROADCAST,
+	SYS_COUNT_TX_COLLISION,
+	SYS_COUNT_TX_DROPS,
+	SYS_COUNT_TX_PAUSE,
+	SYS_COUNT_TX_64,
+	SYS_COUNT_TX_65_127,
+	SYS_COUNT_TX_128_511,
+	SYS_COUNT_TX_512_1023,
+	SYS_COUNT_TX_1024_1526,
+	SYS_COUNT_TX_1527_MAX,
+	SYS_COUNT_TX_AGING,
+	SYS_RESET_CFG,
+	SYS_SR_ETYPE_CFG,
+	SYS_VLAN_ETYPE_CFG,
+	SYS_PORT_MODE,
+	SYS_FRONT_PORT_MODE,
+	SYS_FRM_AGING,
+	SYS_STAT_CFG,
+	SYS_SW_STATUS,
+	SYS_MISC_CFG,
+	SYS_REW_MAC_HIGH_CFG,
+	SYS_REW_MAC_LOW_CFG,
+	SYS_TIMESTAMP_OFFSET,
+	SYS_CMID,
+	SYS_PAUSE_CFG,
+	SYS_PAUSE_TOT_CFG,
+	SYS_ATOP,
+	SYS_ATOP_TOT_CFG,
+	SYS_MAC_FC_CFG,
+	SYS_MMGT,
+	SYS_MMGT_FAST,
+	SYS_EVENTS_DIF,
+	SYS_EVENTS_CORE,
+	SYS_CNT,
+	SYS_PTP_STATUS,
+	SYS_PTP_TXSTAMP,
+	SYS_PTP_NXT,
+	SYS_PTP_CFG,
+	SYS_RAM_INIT,
+	SYS_CM_ADDR,
+	SYS_CM_DATA_WR,
+	SYS_CM_DATA_RD,
+	SYS_CM_OP,
+	SYS_CM_DATA,
+	S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
+	S2_CORE_MV_CFG,
+	S2_CACHE_ENTRY_DAT,
+	S2_CACHE_MASK_DAT,
+	S2_CACHE_ACTION_DAT,
+	S2_CACHE_CNT_DAT,
+	S2_CACHE_TG_DAT,
+	PTP_PIN_CFG = PTP << TARGET_OFFSET,
+	PTP_PIN_TOD_SEC_MSB,
+	PTP_PIN_TOD_SEC_LSB,
+	PTP_PIN_TOD_NSEC,
+	PTP_CFG_MISC,
+	PTP_CLK_CFG_ADJ_CFG,
+	PTP_CLK_CFG_ADJ_FREQ,
+	GCB_SOFT_RST = GCB << TARGET_OFFSET,
+};
+
+enum ocelot_regfield {
+	ANA_ADVLEARN_VLAN_CHK,
+	ANA_ADVLEARN_LEARN_MIRROR,
+	ANA_ANEVENTS_FLOOD_DISCARD,
+	ANA_ANEVENTS_MSTI_DROP,
+	ANA_ANEVENTS_ACLKILL,
+	ANA_ANEVENTS_ACLUSED,
+	ANA_ANEVENTS_AUTOAGE,
+	ANA_ANEVENTS_VS2TTL1,
+	ANA_ANEVENTS_STORM_DROP,
+	ANA_ANEVENTS_LEARN_DROP,
+	ANA_ANEVENTS_AGED_ENTRY,
+	ANA_ANEVENTS_CPU_LEARN_FAILED,
+	ANA_ANEVENTS_AUTO_LEARN_FAILED,
+	ANA_ANEVENTS_LEARN_REMOVE,
+	ANA_ANEVENTS_AUTO_LEARNED,
+	ANA_ANEVENTS_AUTO_MOVED,
+	ANA_ANEVENTS_DROPPED,
+	ANA_ANEVENTS_CLASSIFIED_DROP,
+	ANA_ANEVENTS_CLASSIFIED_COPY,
+	ANA_ANEVENTS_VLAN_DISCARD,
+	ANA_ANEVENTS_FWD_DISCARD,
+	ANA_ANEVENTS_MULTICAST_FLOOD,
+	ANA_ANEVENTS_UNICAST_FLOOD,
+	ANA_ANEVENTS_DEST_KNOWN,
+	ANA_ANEVENTS_BUCKET3_MATCH,
+	ANA_ANEVENTS_BUCKET2_MATCH,
+	ANA_ANEVENTS_BUCKET1_MATCH,
+	ANA_ANEVENTS_BUCKET0_MATCH,
+	ANA_ANEVENTS_CPU_OPERATION,
+	ANA_ANEVENTS_DMAC_LOOKUP,
+	ANA_ANEVENTS_SMAC_LOOKUP,
+	ANA_ANEVENTS_SEQ_GEN_ERR_0,
+	ANA_ANEVENTS_SEQ_GEN_ERR_1,
+	ANA_TABLES_MACACCESS_B_DOM,
+	ANA_TABLES_MACTINDX_BUCKET,
+	ANA_TABLES_MACTINDX_M_INDEX,
+	QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
+	QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
+	QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
+	QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
+	QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
+	SYS_RESET_CFG_CORE_ENA,
+	SYS_RESET_CFG_MEM_ENA,
+	SYS_RESET_CFG_MEM_INIT,
+	GCB_SOFT_RST_SWC_RST,
+	REGFIELD_MAX
+};
+
+enum ocelot_clk_pins {
+	ALT_PPS_PIN	= 1,
+	EXT_CLK_PIN,
+	ALT_LDST_PIN,
+	TOD_ACC_PIN
+};
+
+struct ocelot_stat_layout {
+	u32 offset;
+	char name[ETH_GSTRING_LEN];
+};
+
+enum ocelot_tag_prefix {
+	OCELOT_TAG_PREFIX_DISABLED	= 0,
+	OCELOT_TAG_PREFIX_NONE,
+	OCELOT_TAG_PREFIX_SHORT,
+	OCELOT_TAG_PREFIX_LONG,
+};
+
+struct ocelot;
+
+struct ocelot_ops {
+	void (*pcs_init)(struct ocelot *ocelot, int port);
+	int (*reset)(struct ocelot *ocelot);
+};
+
+struct ocelot_port {
+	struct ocelot			*ocelot;
+
+	void __iomem			*regs;
+
+	/* Ingress default VLAN (pvid) */
+	u16				pvid;
+
+	/* Egress default VLAN (vid) */
+	u16				vid;
+
+	u8				ptp_cmd;
+	struct list_head		skbs;
+	u8				ts_id;
+};
+
+struct ocelot {
+	struct device			*dev;
+
+	const struct ocelot_ops		*ops;
+	struct regmap			*targets[TARGET_MAX];
+	struct regmap_field		*regfields[REGFIELD_MAX];
+	const u32 *const		*map;
+	const struct ocelot_stat_layout	*stats_layout;
+	unsigned int			num_stats;
+
+	int				shared_queue_sz;
+
+	struct net_device		*hw_bridge_dev;
+	u16				bridge_mask;
+	u16				bridge_fwd_mask;
+
+	struct ocelot_port		**ports;
+
+	u8				base_mac[ETH_ALEN];
+
+	/* Keep track of the vlan port masks */
+	u32				vlan_mask[VLAN_N_VID];
+
+	u8				num_phys_ports;
+	u8				num_cpu_ports;
+	u8				cpu;
+
+	u32				*lags;
+
+	struct list_head		multicast;
+
+	/* Workqueue to check statistics for overflow with its lock */
+	struct mutex			stats_lock;
+	u64				*stats;
+	struct delayed_work		stats_work;
+	struct workqueue_struct		*stats_queue;
+
+	u8				ptp:1;
+	struct ptp_clock		*ptp_clock;
+	struct ptp_clock_info		ptp_info;
+	struct hwtstamp_config		hwtstamp_config;
+	/* Protects the PTP interface state */
+	struct mutex			ptp_lock;
+	/* Protects the PTP clock */
+	spinlock_t			ptp_clock_lock;
+
+	void (*port_pcs_init)(struct ocelot_port *port);
+};
+
+#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
+#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
+#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
+#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
+
+#define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
+#define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
+#define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
+#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
+
+#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
+#define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
+#define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
+#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
+
+#if IS_ENABLED(CONFIG_MSCC_OCELOT_SWITCH)
+
+/* I/O */
+u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
+void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
+u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
+void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
+void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
+		     u32 offset);
+
+/* Hardware initialization */
+int ocelot_regfields_init(struct ocelot *ocelot,
+			  const struct reg_field *const regfields);
+struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
+void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
+			 enum ocelot_tag_prefix injection,
+			 enum ocelot_tag_prefix extraction);
+int ocelot_init(struct ocelot *ocelot);
+void ocelot_deinit(struct ocelot *ocelot);
+void ocelot_init_port(struct ocelot *ocelot, int port);
+
+/* DSA callbacks */
+void ocelot_port_enable(struct ocelot *ocelot, int port,
+			struct phy_device *phy);
+void ocelot_port_disable(struct ocelot *ocelot, int port);
+void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
+void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
+int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
+int ocelot_get_ts_info(struct ocelot *ocelot, int port,
+		       struct ethtool_ts_info *info);
+void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
+void ocelot_adjust_link(struct ocelot *ocelot, int port,
+			struct phy_device *phydev);
+void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
+				bool vlan_aware);
+void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
+int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
+			    struct net_device *bridge);
+int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
+			     struct net_device *bridge);
+int ocelot_fdb_dump(struct ocelot *ocelot, int port,
+		    dsa_fdb_dump_cb_t *cb, void *data);
+int ocelot_fdb_add(struct ocelot *ocelot, int port,
+		   const unsigned char *addr, u16 vid, bool vlan_aware);
+int ocelot_fdb_del(struct ocelot *ocelot, int port,
+		   const unsigned char *addr, u16 vid);
+int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
+		    bool untagged);
+int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
+int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
+void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts);
+
+#else
+
+/* I/O */
+u32 ocelot_port_readl(struct ocelot_port *port, u32 reg)
+{
+	return 0;
+}
+
+void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg)
+{
+}
+
+u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset)
+{
+	return 0;
+}
+
+void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset)
+{
+}
+
+void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
+		     u32 offset)
+{
+}
+
+/* Hardware initialization */
+int ocelot_regfields_init(struct ocelot *ocelot,
+			  const struct reg_field *const regfields)
+{
+	return 0;
+}
+
+struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res)
+{
+	return NULL;
+}
+
+void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
+			 enum ocelot_tag_prefix injection,
+			 enum ocelot_tag_prefix extraction)
+{
+}
+
+int ocelot_init(struct ocelot *ocelot)
+{
+	return 0;
+}
+
+void ocelot_deinit(struct ocelot *ocelot)
+{
+}
+
+void ocelot_init_port(struct ocelot *ocelot, int port)
+{
+}
+
+/* DSA callbacks */
+void ocelot_port_enable(struct ocelot *ocelot, int port,
+			struct phy_device *phy)
+{
+}
+
+void ocelot_port_disable(struct ocelot *ocelot, int port)
+{
+}
+
+void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
+{
+}
+
+void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
+{
+}
+
+int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
+{
+	return 0;
+}
+
+int ocelot_get_ts_info(struct ocelot *ocelot, int port,
+		       struct ethtool_ts_info *info)
+{
+	return 0;
+}
+
+void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
+{
+}
+
+void ocelot_adjust_link(struct ocelot *ocelot, int port,
+			struct phy_device *phydev)
+{
+}
+
+void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
+				bool vlan_aware)
+{
+}
+
+void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
+{
+}
+
+int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
+			    struct net_device *bridge)
+{
+	return 0;
+}
+
+int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
+			     struct net_device *bridge)
+{
+	return 0;
+}
+
+int ocelot_fdb_dump(struct ocelot *ocelot, int port,
+		    dsa_fdb_dump_cb_t *cb, void *data)
+{
+	return 0;
+}
+
+int ocelot_fdb_add(struct ocelot *ocelot, int port,
+		   const unsigned char *addr, u16 vid, bool vlan_aware)
+{
+	return 0;
+}
+
+int ocelot_fdb_del(struct ocelot *ocelot, int port,
+		   const unsigned char *addr, u16 vid)
+{
+	return 0;
+}
+
+int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
+		    bool untagged)
+{
+	return 0;
+}
+
+int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
+{
+	return 0;
+}
+
+int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts)
+{
+	return 0;
+}
+
+void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts)
+{
+	return 0;
+}
+
+#endif
+
+#endif
-- 
2.17.1

Re: [PATCH net-next 08/12] net: mscc: ocelot: publish structure definitions to include/soc/mscc/ocelot.h

[Andrew Lunn]

> diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h

..

> +#else
> +
> +/* I/O */
> +u32 ocelot_port_readl(struct ocelot_port *port, u32 reg)
> +{
> +	return 0;
> +}

These stubs are for when the core is missing? I don't think that makes
sense. What use is a DSA or switchdev driver without the core? I would
put in a hard dependency in the Kconfig, so the DSA driver can only be
built when the core is available, and skip these stubs.

      Andrew

Re: [PATCH net-next 08/12] net: mscc: ocelot: publish structure definitions to include/soc/mscc/ocelot.h

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 16:42, Andrew Lunn <andrew@lunn.ch> wrote:
>
> > diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h
>
> ..
>
> > +#else
> > +
> > +/* I/O */
> > +u32 ocelot_port_readl(struct ocelot_port *port, u32 reg)
> > +{
> > +     return 0;
> > +}
>
> These stubs are for when the core is missing? I don't think that makes
> sense. What use is a DSA or switchdev driver without the core? I would
> put in a hard dependency in the Kconfig, so the DSA driver can only be
> built when the core is available, and skip these stubs.
>
>       Andrew

Yes it doesn't make too much sense, I was on the fence about adding it
and then just decided to play on the safe side. I'll remove it.

Re: [PATCH net-next 08/12] net: mscc: ocelot: publish structure definitions to include/soc/mscc/ocelot.h

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> We will be registering another switch driver based on ocelot, which
> lives under drivers/net/dsa.
> 
> Make sure the Felix DSA front-end has the necessary abstractions to
> implement a new Ocelot driver instantiation. This includes the function
> prototypes for implementing DSA callbacks.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH net-next 08/12] net: mscc: ocelot: publish structure definitions to include/soc/mscc/ocelot.h

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1564 bytes --]

Hi Vladimir,

I love your patch! Yet something to improve:

[auto build test ERROR on net-next/master]
[cannot apply to v5.4-rc7 next-20191111]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vladimir-Oltean/DSA-driver-for-Vitesse-Felix-switch/20191113-100022
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git e0580b50d9d4b61d6c56085acdc2bb01c040aca9
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 7.4.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.4.0 make.cross ARCH=ia64 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> ERROR: "ocelot_probe_port" [drivers/net/ethernet/mscc/ocelot_board.ko] undefined!
   ERROR: "ocelot_chip_init" [drivers/net/ethernet/mscc/ocelot_board.ko] undefined!
   ERROR: "ia64_delay_loop" [drivers/net/phy/mdio-cavium.ko] undefined!
   ERROR: "ia64_delay_loop" [drivers/spi/spi-thunderx.ko] undefined!

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 54944 bytes --]

[PATCH net-next 09/12] net: mscc: ocelot: publish ocelot_sys.h to include/soc/mscc

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

The Felix DSA driver needs to write to SYS_RAM_INIT_RAM_INIT for its own
chip initialization process.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.h                      | 2 +-
 {drivers/net/ethernet => include/soc}/mscc/ocelot_sys.h | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename {drivers/net/ethernet => include/soc}/mscc/ocelot_sys.h (100%)

diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
index 325afea3e846..32fef4f495aa 100644
--- a/drivers/net/ethernet/mscc/ocelot.h
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -18,12 +18,12 @@
 #include <linux/ptp_clock_kernel.h>
 #include <linux/regmap.h>
 
+#include <soc/mscc/ocelot_sys.h>
 #include <soc/mscc/ocelot.h>
 #include "ocelot_ana.h"
 #include "ocelot_dev.h"
 #include "ocelot_qsys.h"
 #include "ocelot_rew.h"
-#include "ocelot_sys.h"
 #include "ocelot_qs.h"
 #include "ocelot_tc.h"
 #include "ocelot_ptp.h"
diff --git a/drivers/net/ethernet/mscc/ocelot_sys.h b/include/soc/mscc/ocelot_sys.h
similarity index 100%
rename from drivers/net/ethernet/mscc/ocelot_sys.h
rename to include/soc/mscc/ocelot_sys.h
-- 
2.17.1

Re: [PATCH net-next 09/12] net: mscc: ocelot: publish ocelot_sys.h to include/soc/mscc

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> The Felix DSA driver needs to write to SYS_RAM_INIT_RAM_INIT for its own
> chip initialization process.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
>  drivers/net/ethernet/mscc/ocelot.h                      | 2 +-
>  {drivers/net/ethernet => include/soc}/mscc/ocelot_sys.h | 0
>  2 files changed, 1 insertion(+), 1 deletion(-)
>  rename {drivers/net/ethernet => include/soc}/mscc/ocelot_sys.h (100%)

This was not done before for include/soc/mscc/ocelot_hsio.h but you need
an update to the MAINTAINERS file to catch that file now:

$ ./scripts/get_maintainer.pl -f include/soc/mscc/ocelot_hsio.h
linux-kernel@vger.kernel.org (open list)

expected:


Alexandre Belloni <alexandre.belloni@bootlin.com> (supporter:MICROSEMI
ETHERNET SWITCH DRIVER)
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
(supporter:MICROSEMI ETHERNET SWITCH DRIVER)
"David S. Miller" <davem@davemloft.net> (odd fixer:NETWORKING DRIVERS)
netdev@vger.kernel.org (open list:MICROSEMI ETHERNET SWITCH DRIVER)


> 
> diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h
> index 325afea3e846..32fef4f495aa 100644
> --- a/drivers/net/ethernet/mscc/ocelot.h
> +++ b/drivers/net/ethernet/mscc/ocelot.h
> @@ -18,12 +18,12 @@
>  #include <linux/ptp_clock_kernel.h>
>  #include <linux/regmap.h>
>  
> +#include <soc/mscc/ocelot_sys.h>
>  #include <soc/mscc/ocelot.h>
>  #include "ocelot_ana.h"
>  #include "ocelot_dev.h"
>  #include "ocelot_qsys.h"
>  #include "ocelot_rew.h"
> -#include "ocelot_sys.h"
>  #include "ocelot_qs.h"
>  #include "ocelot_tc.h"
>  #include "ocelot_ptp.h"
> diff --git a/drivers/net/ethernet/mscc/ocelot_sys.h b/include/soc/mscc/ocelot_sys.h
> similarity index 100%
> rename from drivers/net/ethernet/mscc/ocelot_sys.h
> rename to include/soc/mscc/ocelot_sys.h
> 


-- 
Florian

[PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

The vitesse/ folder will contain drivers for switching chips derived
from legacy Vitesse IPs (VSC family), including those produced by
Microsemi and Microchip (acquirers of Vitesse).

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/dsa/Kconfig                       | 31 +------------------
 drivers/net/dsa/Makefile                      |  4 +--
 drivers/net/dsa/vitesse/Kconfig               | 31 +++++++++++++++++++
 drivers/net/dsa/vitesse/Makefile              |  3 ++
 .../vsc73xx-core.c}                           |  2 +-
 .../vsc73xx-platform.c}                       |  2 +-
 .../vsc73xx-spi.c}                            |  2 +-
 .../{vitesse-vsc73xx.h => vitesse/vsc73xx.h}  |  0
 8 files changed, 39 insertions(+), 36 deletions(-)
 create mode 100644 drivers/net/dsa/vitesse/Kconfig
 create mode 100644 drivers/net/dsa/vitesse/Makefile
 rename drivers/net/dsa/{vitesse-vsc73xx-core.c => vitesse/vsc73xx-core.c} (99%)
 rename drivers/net/dsa/{vitesse-vsc73xx-platform.c => vitesse/vsc73xx-platform.c} (99%)
 rename drivers/net/dsa/{vitesse-vsc73xx-spi.c => vitesse/vsc73xx-spi.c} (99%)
 rename drivers/net/dsa/{vitesse-vsc73xx.h => vitesse/vsc73xx.h} (100%)

diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 685e12b05a7c..ec91960e58ac 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -99,35 +99,6 @@ config NET_DSA_SMSC_LAN9303_MDIO
 	  Enable access functions if the SMSC/Microchip LAN9303 is configured
 	  for MDIO managed mode.
 
-config NET_DSA_VITESSE_VSC73XX
-	tristate
-	depends on OF
-	depends on NET_DSA
-	select FIXED_PHY
-	select VITESSE_PHY
-	select GPIOLIB
-	---help---
-	  This enables support for the Vitesse VSC7385, VSC7388,
-	  VSC7395 and VSC7398 SparX integrated ethernet switches.
+source "drivers/net/dsa/vitesse/Kconfig"
 
-config NET_DSA_VITESSE_VSC73XX_SPI
-	tristate "Vitesse VSC7385/7388/7395/7398 SPI mode support"
-	depends on OF
-	depends on NET_DSA
-	depends on SPI
-	select NET_DSA_VITESSE_VSC73XX
-	---help---
-	  This enables support for the Vitesse VSC7385, VSC7388, VSC7395
-	  and VSC7398 SparX integrated ethernet switches in SPI managed mode.
-
-config NET_DSA_VITESSE_VSC73XX_PLATFORM
-	tristate "Vitesse VSC7385/7388/7395/7398 Platform mode support"
-	depends on OF
-	depends on NET_DSA
-	depends on HAS_IOMEM
-	select NET_DSA_VITESSE_VSC73XX
-	---help---
-	  This enables support for the Vitesse VSC7385, VSC7388, VSC7395
-	  and VSC7398 SparX integrated ethernet switches, connected over
-	  a CPU-attached address bus and work in memory-mapped I/O mode.
 endmenu
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index ae70b79628d6..158d34f8c085 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -14,10 +14,8 @@ realtek-smi-objs		:= realtek-smi-core.o rtl8366.o rtl8366rb.o
 obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
 obj-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o
 obj-$(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) += lan9303_mdio.o
-obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX) += vitesse-vsc73xx-core.o
-obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM) += vitesse-vsc73xx-platform.o
-obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) += vitesse-vsc73xx-spi.o
 obj-y				+= b53/
 obj-y				+= microchip/
 obj-y				+= mv88e6xxx/
 obj-y				+= sja1105/
+obj-y				+= vitesse/
diff --git a/drivers/net/dsa/vitesse/Kconfig b/drivers/net/dsa/vitesse/Kconfig
new file mode 100644
index 000000000000..54be4b34fd17
--- /dev/null
+++ b/drivers/net/dsa/vitesse/Kconfig
@@ -0,0 +1,31 @@
+config NET_DSA_VITESSE_VSC73XX
+	tristate
+	depends on OF
+	depends on NET_DSA
+	select FIXED_PHY
+	select VITESSE_PHY
+	select GPIOLIB
+	---help---
+	  This enables support for the Vitesse VSC7385, VSC7388,
+	  VSC7395 and VSC7398 SparX integrated ethernet switches.
+
+config NET_DSA_VITESSE_VSC73XX_SPI
+	tristate "Vitesse VSC7385/7388/7395/7398 SPI mode support"
+	depends on OF
+	depends on NET_DSA
+	depends on SPI
+	select NET_DSA_VITESSE_VSC73XX
+	---help---
+	  This enables support for the Vitesse VSC7385, VSC7388, VSC7395
+	  and VSC7398 SparX integrated ethernet switches in SPI managed mode.
+
+config NET_DSA_VITESSE_VSC73XX_PLATFORM
+	tristate "Vitesse VSC7385/7388/7395/7398 Platform mode support"
+	depends on OF
+	depends on NET_DSA
+	depends on HAS_IOMEM
+	select NET_DSA_VITESSE_VSC73XX
+	---help---
+	  This enables support for the Vitesse VSC7385, VSC7388, VSC7395
+	  and VSC7398 SparX integrated ethernet switches, connected over
+	  a CPU-attached address bus and work in memory-mapped I/O mode.
diff --git a/drivers/net/dsa/vitesse/Makefile b/drivers/net/dsa/vitesse/Makefile
new file mode 100644
index 000000000000..adceeeec5d12
--- /dev/null
+++ b/drivers/net/dsa/vitesse/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX) += vsc73xx-core.o
+obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM) += vsc73xx-platform.o
+obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) += vsc73xx-spi.o
diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse/vsc73xx-core.c
similarity index 99%
rename from drivers/net/dsa/vitesse-vsc73xx-core.c
rename to drivers/net/dsa/vitesse/vsc73xx-core.c
index 42c1574d45f2..d44dc5821938 100644
--- a/drivers/net/dsa/vitesse-vsc73xx-core.c
+++ b/drivers/net/dsa/vitesse/vsc73xx-core.c
@@ -28,7 +28,7 @@
 #include <linux/random.h>
 #include <net/dsa.h>
 
-#include "vitesse-vsc73xx.h"
+#include "vsc73xx.h"
 
 #define VSC73XX_BLOCK_MAC	0x1 /* Subblocks 0-4, 6 (CPU port) */
 #define VSC73XX_BLOCK_ANALYZER	0x2 /* Only subblock 0 */
diff --git a/drivers/net/dsa/vitesse-vsc73xx-platform.c b/drivers/net/dsa/vitesse/vsc73xx-platform.c
similarity index 99%
rename from drivers/net/dsa/vitesse-vsc73xx-platform.c
rename to drivers/net/dsa/vitesse/vsc73xx-platform.c
index 0541785f9fee..0ccf622aff96 100644
--- a/drivers/net/dsa/vitesse-vsc73xx-platform.c
+++ b/drivers/net/dsa/vitesse/vsc73xx-platform.c
@@ -20,7 +20,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 
-#include "vitesse-vsc73xx.h"
+#include "vsc73xx.h"
 
 #define VSC73XX_CMD_PLATFORM_BLOCK_SHIFT		14
 #define VSC73XX_CMD_PLATFORM_BLOCK_MASK			0x7
diff --git a/drivers/net/dsa/vitesse-vsc73xx-spi.c b/drivers/net/dsa/vitesse/vsc73xx-spi.c
similarity index 99%
rename from drivers/net/dsa/vitesse-vsc73xx-spi.c
rename to drivers/net/dsa/vitesse/vsc73xx-spi.c
index e73c8fcddc9f..d75fcee0defb 100644
--- a/drivers/net/dsa/vitesse-vsc73xx-spi.c
+++ b/drivers/net/dsa/vitesse/vsc73xx-spi.c
@@ -17,7 +17,7 @@
 #include <linux/of.h>
 #include <linux/spi/spi.h>
 
-#include "vitesse-vsc73xx.h"
+#include "vsc73xx.h"
 
 #define VSC73XX_CMD_SPI_MODE_READ		0
 #define VSC73XX_CMD_SPI_MODE_WRITE		1
diff --git a/drivers/net/dsa/vitesse-vsc73xx.h b/drivers/net/dsa/vitesse/vsc73xx.h
similarity index 100%
rename from drivers/net/dsa/vitesse-vsc73xx.h
rename to drivers/net/dsa/vitesse/vsc73xx.h
-- 
2.17.1

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Alexandre Belloni]

Hi,

On 12/11/2019 14:44:18+0200, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> The vitesse/ folder will contain drivers for switching chips derived
> from legacy Vitesse IPs (VSC family), including those produced by
> Microsemi and Microchip (acquirers of Vitesse).
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
>  drivers/net/dsa/Kconfig                       | 31 +------------------
>  drivers/net/dsa/Makefile                      |  4 +--
>  drivers/net/dsa/vitesse/Kconfig               | 31 +++++++++++++++++++
>  drivers/net/dsa/vitesse/Makefile              |  3 ++
>  .../vsc73xx-core.c}                           |  2 +-
>  .../vsc73xx-platform.c}                       |  2 +-
>  .../vsc73xx-spi.c}                            |  2 +-
>  .../{vitesse-vsc73xx.h => vitesse/vsc73xx.h}  |  0
>  8 files changed, 39 insertions(+), 36 deletions(-)
>  create mode 100644 drivers/net/dsa/vitesse/Kconfig
>  create mode 100644 drivers/net/dsa/vitesse/Makefile
>  rename drivers/net/dsa/{vitesse-vsc73xx-core.c => vitesse/vsc73xx-core.c} (99%)
>  rename drivers/net/dsa/{vitesse-vsc73xx-platform.c => vitesse/vsc73xx-platform.c} (99%)
>  rename drivers/net/dsa/{vitesse-vsc73xx-spi.c => vitesse/vsc73xx-spi.c} (99%)
>  rename drivers/net/dsa/{vitesse-vsc73xx.h => vitesse/vsc73xx.h} (100%)
> 

As there are no commonalities between the vsc73xx and felix drivers,
shouldn't you simply leave that one out and have felix in the existing
microchip folder?

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 15:09, Alexandre Belloni
<alexandre.belloni@bootlin.com> wrote:
>
> Hi,
>
> On 12/11/2019 14:44:18+0200, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > The vitesse/ folder will contain drivers for switching chips derived
> > from legacy Vitesse IPs (VSC family), including those produced by
> > Microsemi and Microchip (acquirers of Vitesse).
> >
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > ---
> >  drivers/net/dsa/Kconfig                       | 31 +------------------
> >  drivers/net/dsa/Makefile                      |  4 +--
> >  drivers/net/dsa/vitesse/Kconfig               | 31 +++++++++++++++++++
> >  drivers/net/dsa/vitesse/Makefile              |  3 ++
> >  .../vsc73xx-core.c}                           |  2 +-
> >  .../vsc73xx-platform.c}                       |  2 +-
> >  .../vsc73xx-spi.c}                            |  2 +-
> >  .../{vitesse-vsc73xx.h => vitesse/vsc73xx.h}  |  0
> >  8 files changed, 39 insertions(+), 36 deletions(-)
> >  create mode 100644 drivers/net/dsa/vitesse/Kconfig
> >  create mode 100644 drivers/net/dsa/vitesse/Makefile
> >  rename drivers/net/dsa/{vitesse-vsc73xx-core.c => vitesse/vsc73xx-core.c} (99%)
> >  rename drivers/net/dsa/{vitesse-vsc73xx-platform.c => vitesse/vsc73xx-platform.c} (99%)
> >  rename drivers/net/dsa/{vitesse-vsc73xx-spi.c => vitesse/vsc73xx-spi.c} (99%)
> >  rename drivers/net/dsa/{vitesse-vsc73xx.h => vitesse/vsc73xx.h} (100%)
> >
>
> As there are no commonalities between the vsc73xx and felix drivers,
> shouldn't you simply leave that one out and have felix in the existing
> microchip folder?
>

I don't have a strong preference, although where I come from, all new
NXP networking drivers are still labeled as "freescale" even though
there is no code reuse. There are even less commonalities with
Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
old vsc73xx. I'll let the ex-Vitesse people decide.


> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Allan W. Nielsen]

The 11/12/2019 15:40, Vladimir Oltean wrote:
> External E-Mail
> 
> 
> On Tue, 12 Nov 2019 at 15:09, Alexandre Belloni
> <alexandre.belloni@bootlin.com> wrote:
> >
> > Hi,
> >
> > On 12/11/2019 14:44:18+0200, Vladimir Oltean wrote:
> > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > >
> > > The vitesse/ folder will contain drivers for switching chips derived
> > > from legacy Vitesse IPs (VSC family), including those produced by
> > > Microsemi and Microchip (acquirers of Vitesse).
> > >
> > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > > ---
> > >  drivers/net/dsa/Kconfig                       | 31 +------------------
> > >  drivers/net/dsa/Makefile                      |  4 +--
> > >  drivers/net/dsa/vitesse/Kconfig               | 31 +++++++++++++++++++
> > >  drivers/net/dsa/vitesse/Makefile              |  3 ++
> > >  .../vsc73xx-core.c}                           |  2 +-
> > >  .../vsc73xx-platform.c}                       |  2 +-
> > >  .../vsc73xx-spi.c}                            |  2 +-
> > >  .../{vitesse-vsc73xx.h => vitesse/vsc73xx.h}  |  0
> > >  8 files changed, 39 insertions(+), 36 deletions(-)
> > >  create mode 100644 drivers/net/dsa/vitesse/Kconfig
> > >  create mode 100644 drivers/net/dsa/vitesse/Makefile
> > >  rename drivers/net/dsa/{vitesse-vsc73xx-core.c => vitesse/vsc73xx-core.c} (99%)
> > >  rename drivers/net/dsa/{vitesse-vsc73xx-platform.c => vitesse/vsc73xx-platform.c} (99%)
> > >  rename drivers/net/dsa/{vitesse-vsc73xx-spi.c => vitesse/vsc73xx-spi.c} (99%)
> > >  rename drivers/net/dsa/{vitesse-vsc73xx.h => vitesse/vsc73xx.h} (100%)
> > >
> >
> > As there are no commonalities between the vsc73xx and felix drivers,
> > shouldn't you simply leave that one out and have felix in the existing
> > microchip folder?
> >
> 
> I don't have a strong preference, although where I come from, all new
> NXP networking drivers are still labeled as "freescale" even though
> there is no code reuse. There are even less commonalities with
> Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
> old vsc73xx. I'll let the ex-Vitesse people decide.
I'm on the same page as Alexandre here.

I think we should leave vsc73xx where it is already, and put the felix driver in
the drivers/net/ethernet/mscc/ folder where ocelot is already.

/Allan

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Andrew Lunn]

> > > As there are no commonalities between the vsc73xx and felix drivers,
> > > shouldn't you simply leave that one out and have felix in the existing
> > > microchip folder?
> > >
> > 
> > I don't have a strong preference, although where I come from, all new
> > NXP networking drivers are still labeled as "freescale" even though
> > there is no code reuse. There are even less commonalities with
> > Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
> > old vsc73xx. I'll let the ex-Vitesse people decide.
> I'm on the same page as Alexandre here.

Leaving them where they are makes maintenance easier. Fixes are easier
to backport if things don't move around.

> I think we should leave vsc73xx where it is already, and put the felix driver in
> the drivers/net/ethernet/mscc/ folder where ocelot is already.

Currently, all DSA drivers are in drivers/net/dsa. We do occasionally
make changes over all DSA drivers at once, so it is nice they are all
together. So i would prefer the DSA part of Felix is also there. But
the core can be in drivers/net/ethernet/mscc/.

    Andrew

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Allan W. Nielsen]

The 11/12/2019 15:50, Andrew Lunn wrote:
> External E-Mail
> 
> 
> > > > As there are no commonalities between the vsc73xx and felix drivers,
> > > > shouldn't you simply leave that one out and have felix in the existing
> > > > microchip folder?
> > > >
> > > 
> > > I don't have a strong preference, although where I come from, all new
> > > NXP networking drivers are still labeled as "freescale" even though
> > > there is no code reuse. There are even less commonalities with
> > > Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
> > > old vsc73xx. I'll let the ex-Vitesse people decide.
> > I'm on the same page as Alexandre here.
> 
> Leaving them where they are makes maintenance easier. Fixes are easier
> to backport if things don't move around.
> 
> > I think we should leave vsc73xx where it is already, and put the felix driver in
> > the drivers/net/ethernet/mscc/ folder where ocelot is already.
> 
> Currently, all DSA drivers are in drivers/net/dsa. We do occasionally
> make changes over all DSA drivers at once, so it is nice they are all
> together. So i would prefer the DSA part of Felix is also there. But
> the core can be in drivers/net/ethernet/mscc/.
Ahh, my bad.

In that case I do not have any strong feelings on this either.

I should say that we are discussing to add support for a Ocelot VSC7511 as a DSA
driver. This one does not have an internal MIPS CPU.

The vsc73xx, felix and the drivers in dsa/microchip does not share any
functionallity. Not in SW and not in HW.

Maybe felix should just go directly into drivers/net/dsa/, and then if we add
support for VSC7511 then they can both live in drivers/net/dsa/ocelot/

/Allan

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 16:57, Allan W. Nielsen
<allan.nielsen@microchip.com> wrote:
>
> The 11/12/2019 15:50, Andrew Lunn wrote:
> > External E-Mail
> >
> >
> > > > > As there are no commonalities between the vsc73xx and felix drivers,
> > > > > shouldn't you simply leave that one out and have felix in the existing
> > > > > microchip folder?
> > > > >
> > > >
> > > > I don't have a strong preference, although where I come from, all new
> > > > NXP networking drivers are still labeled as "freescale" even though
> > > > there is no code reuse. There are even less commonalities with
> > > > Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
> > > > old vsc73xx. I'll let the ex-Vitesse people decide.
> > > I'm on the same page as Alexandre here.
> >
> > Leaving them where they are makes maintenance easier. Fixes are easier
> > to backport if things don't move around.
> >
> > > I think we should leave vsc73xx where it is already, and put the felix driver in
> > > the drivers/net/ethernet/mscc/ folder where ocelot is already.
> >
> > Currently, all DSA drivers are in drivers/net/dsa. We do occasionally
> > make changes over all DSA drivers at once, so it is nice they are all
> > together. So i would prefer the DSA part of Felix is also there. But
> > the core can be in drivers/net/ethernet/mscc/.
> Ahh, my bad.
>
> In that case I do not have any strong feelings on this either.
>
> I should say that we are discussing to add support for a Ocelot VSC7511 as a DSA
> driver. This one does not have an internal MIPS CPU.
>
> The vsc73xx, felix and the drivers in dsa/microchip does not share any
> functionallity. Not in SW and not in HW.
>
> Maybe felix should just go directly into drivers/net/dsa/, and then if we add
> support for VSC7511 then they can both live in drivers/net/dsa/ocelot/
>
> /Allan

When the felix driver is going to support the vsc7511 ocelot switch
through the ocelot core, it will be naming chaos. Maybe we need to
clarify what "felix" means (at the moment it means VSC9959). What if
we just make it mean "DSA driver for Ocelot", and it supports both the
VSC751x (Ocelot) and the VSC9959 (Felix) families? Is anybody else
instantiating the VSC9959 core, or close derivatives, except NXP
LS1028A? If the answer is yes, are those other instantiations PCI
devices, or something else? I would appreciate if you could take a
look through the probing part of patch 11/12 (the "felix_instance_tbl"
part and felix-regs.c) and see if there are any naming changes I can
make that would make it easier for you to fit in one more device. Of
course, I don't expect to make radical changes, you'd still need to do
some refactoring if you decide to add your vsc7511, I just care that
the refactoring doesn't change any current semantics.

Regards,
-Vladimir

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Allan W. Nielsen]

The 11/12/2019 17:26, Vladimir Oltean wrote:
> External E-Mail
> 
> 
> On Tue, 12 Nov 2019 at 16:57, Allan W. Nielsen
> <allan.nielsen@microchip.com> wrote:
> >
> > The 11/12/2019 15:50, Andrew Lunn wrote:
> > > External E-Mail
> > >
> > >
> > > > > > As there are no commonalities between the vsc73xx and felix drivers,
> > > > > > shouldn't you simply leave that one out and have felix in the existing
> > > > > > microchip folder?
> > > > > >
> > > > >
> > > > > I don't have a strong preference, although where I come from, all new
> > > > > NXP networking drivers are still labeled as "freescale" even though
> > > > > there is no code reuse. There are even less commonalities with
> > > > > Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
> > > > > old vsc73xx. I'll let the ex-Vitesse people decide.
> > > > I'm on the same page as Alexandre here.
> > >
> > > Leaving them where they are makes maintenance easier. Fixes are easier
> > > to backport if things don't move around.
> > >
> > > > I think we should leave vsc73xx where it is already, and put the felix driver in
> > > > the drivers/net/ethernet/mscc/ folder where ocelot is already.
> > >
> > > Currently, all DSA drivers are in drivers/net/dsa. We do occasionally
> > > make changes over all DSA drivers at once, so it is nice they are all
> > > together. So i would prefer the DSA part of Felix is also there. But
> > > the core can be in drivers/net/ethernet/mscc/.
> > Ahh, my bad.
> >
> > In that case I do not have any strong feelings on this either.
> >
> > I should say that we are discussing to add support for a Ocelot VSC7511 as a DSA
> > driver. This one does not have an internal MIPS CPU.
> >
> > The vsc73xx, felix and the drivers in dsa/microchip does not share any
> > functionallity. Not in SW and not in HW.
> >
> > Maybe felix should just go directly into drivers/net/dsa/, and then if we add
> > support for VSC7511 then they can both live in drivers/net/dsa/ocelot/


A bit of background such that people outside NXP/MCHP has a better change to
follow and add to the discussion.

Ocelot is a family name covering 4 VSC parts (VSC7511-14), and a IP used by NXP
(VSC9959).

VSC7511-14 are all register compatible, it uses the same serdes etc.

VSC7511/12 are "unmanaged" meaning that they do not have an embedded CPU.

VSC7513/14 has an embedded MIPS CPU.

VSC9959 not the same core as VSC7511-14, it is a newer generation with more
features, it is not register compatible, but all the basic functionallity is
very similar VSC7511-14 which is why it can call into the
drivers/net/ethernet/mscc/ocelot.c file.

It is likely that NXP want to add more features in felix/VSC9959 which does not
exists in VSC7511-14.

> When the felix driver is going to support the vsc7511 ocelot switch
> through the ocelot core, it will be naming chaos.
I do not think a VSC7511 will be based on Felix, but it will relay on the
refacturing/restructuring you have done in Ocelot.

VSC7511 will use the same PCS and serdes settings as Ocelot (VSC7513/VSC7514)

> Maybe we need to clarify what "felix" means (at the moment it means VSC9959).
Yes.

> What if we just make it mean "DSA driver for Ocelot", and it supports both the
> VSC751x (Ocelot) and the VSC9959 (Felix) families?
I'm not too keen on using the felix name for that.

Here is my suggestion:

Drop the felix name and put it in drivers/net/dsa/ocelot_vsc9959* (this would be
my preference)

Or if you want the felix name put it in drivers/net/dsa/ocelot_felix*

Or if we want folders put it in drivers/net/dsa/ocelot/vsc9959*

When we get to it, we can add vsc7511/12 in drivers/net/dsa/ocelot_vsc7512*

To be consisten and clean up (my) earlier mistake we should rename the
drivers/net/ethernet/mscc/ocelot_board.c to
drivers/net/ethernet/mscc/ocelot_vsc7514.c (as it is really not board stuff, but
ocelot internal cpu stuff).

Andrew also pointed out that the stuff put into this file did not seem very
board related.

> Is anybody else instantiating the VSC9959 core, or close derivatives, except
> NXP LS1028A? If the answer is yes, are those other instantiations PCI devices,
> or something else?
Not what I'm aware of.

> I would appreciate if you could take a
> look through the probing part of patch 11/12 (the "felix_instance_tbl"
> part and felix-regs.c) and see if there are any naming changes I can
> make that would make it easier for you to fit in one more device.
Will do.

> Of course, I don't expect to make radical changes, you'd still need to do some
> refactoring if you decide to add your vsc7511, I just care that the
> refactoring doesn't change any current semantics.
The majority of the needed changes to add vsc7511 has been done by now ;-)

/Allan

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 21:10, Allan W. Nielsen
<allan.nielsen@microchip.com> wrote:
>
> The 11/12/2019 17:26, Vladimir Oltean wrote:
> > External E-Mail
> >
> >
> > On Tue, 12 Nov 2019 at 16:57, Allan W. Nielsen
> > <allan.nielsen@microchip.com> wrote:
> > >
> > > The 11/12/2019 15:50, Andrew Lunn wrote:
> > > > External E-Mail
> > > >
> > > >
> > > > > > > As there are no commonalities between the vsc73xx and felix drivers,
> > > > > > > shouldn't you simply leave that one out and have felix in the existing
> > > > > > > microchip folder?
> > > > > > >
> > > > > >
> > > > > > I don't have a strong preference, although where I come from, all new
> > > > > > NXP networking drivers are still labeled as "freescale" even though
> > > > > > there is no code reuse. There are even less commonalities with
> > > > > > Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
> > > > > > old vsc73xx. I'll let the ex-Vitesse people decide.
> > > > > I'm on the same page as Alexandre here.
> > > >
> > > > Leaving them where they are makes maintenance easier. Fixes are easier
> > > > to backport if things don't move around.
> > > >
> > > > > I think we should leave vsc73xx where it is already, and put the felix driver in
> > > > > the drivers/net/ethernet/mscc/ folder where ocelot is already.
> > > >
> > > > Currently, all DSA drivers are in drivers/net/dsa. We do occasionally
> > > > make changes over all DSA drivers at once, so it is nice they are all
> > > > together. So i would prefer the DSA part of Felix is also there. But
> > > > the core can be in drivers/net/ethernet/mscc/.
> > > Ahh, my bad.
> > >
> > > In that case I do not have any strong feelings on this either.
> > >
> > > I should say that we are discussing to add support for a Ocelot VSC7511 as a DSA
> > > driver. This one does not have an internal MIPS CPU.
> > >
> > > The vsc73xx, felix and the drivers in dsa/microchip does not share any
> > > functionallity. Not in SW and not in HW.
> > >
> > > Maybe felix should just go directly into drivers/net/dsa/, and then if we add
> > > support for VSC7511 then they can both live in drivers/net/dsa/ocelot/
>
>
> A bit of background such that people outside NXP/MCHP has a better change to
> follow and add to the discussion.
>
> Ocelot is a family name covering 4 VSC parts (VSC7511-14), and a IP used by NXP
> (VSC9959).
>
> VSC7511-14 are all register compatible, it uses the same serdes etc.
>
> VSC7511/12 are "unmanaged" meaning that they do not have an embedded CPU.
>
> VSC7513/14 has an embedded MIPS CPU.
>
> VSC9959 not the same core as VSC7511-14, it is a newer generation with more
> features, it is not register compatible, but all the basic functionallity is
> very similar VSC7511-14 which is why it can call into the
> drivers/net/ethernet/mscc/ocelot.c file.
>
> It is likely that NXP want to add more features in felix/VSC9959 which does not
> exists in VSC7511-14.
>
> > When the felix driver is going to support the vsc7511 ocelot switch
> > through the ocelot core, it will be naming chaos.
> I do not think a VSC7511 will be based on Felix, but it will relay on the
> refacturing/restructuring you have done in Ocelot.
>
> VSC7511 will use the same PCS and serdes settings as Ocelot (VSC7513/VSC7514)
>
> > Maybe we need to clarify what "felix" means (at the moment it means VSC9959).
> Yes.
>
> > What if we just make it mean "DSA driver for Ocelot", and it supports both the
> > VSC751x (Ocelot) and the VSC9959 (Felix) families?
> I'm not too keen on using the felix name for that.
>
> Here is my suggestion:
>
> Drop the felix name and put it in drivers/net/dsa/ocelot_vsc9959* (this would be
> my preference)
>

This has one big issue: the name is very long! I can't see myself
prefixing all function and structure names with ocelot_vsc9959_*.
Felix is just 5 letters. And I can't use "ocelot" either, since that
is taken :)
So the DSA driver needs its own (short) name.

> Or if you want the felix name put it in drivers/net/dsa/ocelot_felix*
>
> Or if we want folders put it in drivers/net/dsa/ocelot/vsc9959*
>

The way I see an Ocelot DSA driver, it would be done a la mv88e6xxx,
aka a single struct dsa_switch_ops registered for the entire family,
and function pointers where the implementation differs. You're not
proposing that here, but rather that each switch driver works in
parallel with each other, and they all call into the Ocelot core. That
would produce a lot more boilerplate, I think.
And if the DSA driver for Ocelot ends up supporting more than 1
device, its name should better not contain "vsc9959" since that's
rather specific.

> When we get to it, we can add vsc7511/12 in drivers/net/dsa/ocelot_vsc7512*
>
> To be consisten and clean up (my) earlier mistake we should rename the
> drivers/net/ethernet/mscc/ocelot_board.c to
> drivers/net/ethernet/mscc/ocelot_vsc7514.c (as it is really not board stuff, but
> ocelot internal cpu stuff).
>
> Andrew also pointed out that the stuff put into this file did not seem very
> board related.
>
> > Is anybody else instantiating the VSC9959 core, or close derivatives, except
> > NXP LS1028A? If the answer is yes, are those other instantiations PCI devices,
> > or something else?
> Not what I'm aware of.
>

Ok, this is good to know.

> > I would appreciate if you could take a
> > look through the probing part of patch 11/12 (the "felix_instance_tbl"
> > part and felix-regs.c) and see if there are any naming changes I can
> > make that would make it easier for you to fit in one more device.
> Will do.
>
> > Of course, I don't expect to make radical changes, you'd still need to do some
> > refactoring if you decide to add your vsc7511, I just care that the
> > refactoring doesn't change any current semantics.
> The majority of the needed changes to add vsc7511 has been done by now ;-)
>
> /Allan
>

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Allan W. Nielsen]

The 11/12/2019 21:26, Vladimir Oltean wrote:
> External E-Mail
> 
> 
> On Tue, 12 Nov 2019 at 21:10, Allan W. Nielsen
> <allan.nielsen@microchip.com> wrote:
> >
> > The 11/12/2019 17:26, Vladimir Oltean wrote:
> > > External E-Mail
> > >
> > >
> > > On Tue, 12 Nov 2019 at 16:57, Allan W. Nielsen
> > > <allan.nielsen@microchip.com> wrote:
> > > >
> > > > The 11/12/2019 15:50, Andrew Lunn wrote:
> > > > > External E-Mail
> > > > >
> > > > >
> > > > > > > > As there are no commonalities between the vsc73xx and felix drivers,
> > > > > > > > shouldn't you simply leave that one out and have felix in the existing
> > > > > > > > microchip folder?
> > > > > > > >
> > > > > > >
> > > > > > > I don't have a strong preference, although where I come from, all new
> > > > > > > NXP networking drivers are still labeled as "freescale" even though
> > > > > > > there is no code reuse. There are even less commonalities with
> > > > > > > Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
> > > > > > > old vsc73xx. I'll let the ex-Vitesse people decide.
> > > > > > I'm on the same page as Alexandre here.
> > > > >
> > > > > Leaving them where they are makes maintenance easier. Fixes are easier
> > > > > to backport if things don't move around.
> > > > >
> > > > > > I think we should leave vsc73xx where it is already, and put the felix driver in
> > > > > > the drivers/net/ethernet/mscc/ folder where ocelot is already.
> > > > >
> > > > > Currently, all DSA drivers are in drivers/net/dsa. We do occasionally
> > > > > make changes over all DSA drivers at once, so it is nice they are all
> > > > > together. So i would prefer the DSA part of Felix is also there. But
> > > > > the core can be in drivers/net/ethernet/mscc/.
> > > > Ahh, my bad.
> > > >
> > > > In that case I do not have any strong feelings on this either.
> > > >
> > > > I should say that we are discussing to add support for a Ocelot VSC7511 as a DSA
> > > > driver. This one does not have an internal MIPS CPU.
> > > >
> > > > The vsc73xx, felix and the drivers in dsa/microchip does not share any
> > > > functionallity. Not in SW and not in HW.
> > > >
> > > > Maybe felix should just go directly into drivers/net/dsa/, and then if we add
> > > > support for VSC7511 then they can both live in drivers/net/dsa/ocelot/
> >
> >
> > A bit of background such that people outside NXP/MCHP has a better change to
> > follow and add to the discussion.
> >
> > Ocelot is a family name covering 4 VSC parts (VSC7511-14), and a IP used by NXP
> > (VSC9959).
> >
> > VSC7511-14 are all register compatible, it uses the same serdes etc.
> >
> > VSC7511/12 are "unmanaged" meaning that they do not have an embedded CPU.
> >
> > VSC7513/14 has an embedded MIPS CPU.
> >
> > VSC9959 not the same core as VSC7511-14, it is a newer generation with more
> > features, it is not register compatible, but all the basic functionallity is
> > very similar VSC7511-14 which is why it can call into the
> > drivers/net/ethernet/mscc/ocelot.c file.
> >
> > It is likely that NXP want to add more features in felix/VSC9959 which does not
> > exists in VSC7511-14.
> >
> > > When the felix driver is going to support the vsc7511 ocelot switch
> > > through the ocelot core, it will be naming chaos.
> > I do not think a VSC7511 will be based on Felix, but it will relay on the
> > refacturing/restructuring you have done in Ocelot.
> >
> > VSC7511 will use the same PCS and serdes settings as Ocelot (VSC7513/VSC7514)
> >
> > > Maybe we need to clarify what "felix" means (at the moment it means VSC9959).
> > Yes.
> >
> > > What if we just make it mean "DSA driver for Ocelot", and it supports both the
> > > VSC751x (Ocelot) and the VSC9959 (Felix) families?
> > I'm not too keen on using the felix name for that.
> >
> > Here is my suggestion:
> >
> > Drop the felix name and put it in drivers/net/dsa/ocelot_vsc9959* (this would be
> > my preference)
> >
> 
> This has one big issue: the name is very long! I can't see myself
> prefixing all function and structure names with ocelot_vsc9959_*.
> Felix is just 5 letters. And I can't use "ocelot" either, since that
> is taken :)
> So the DSA driver needs its own (short) name.
I certainly agree that ocelot_vsc9959_* is too long a prefix.

If you put it in drivers/net/dsa/ocelot_felix* or drivers/net/dsa/ocelot/felix*
then you can prefix with 'felix_'.

If you put it in drivers/net/dsa/ocelot_vsc9959* or drivers/net/dsa/ocelot/vsc9959*
then you can prefix with 'vsc9959_'.

The one thing all of this parts has in common is that they are all based on the
Ocelot family, which is why I suggest to include this into the path. It will
provide more information than putting it in the vitesse/microchip folders.

> > Or if you want the felix name put it in drivers/net/dsa/ocelot_felix*
> >
> > Or if we want folders put it in drivers/net/dsa/ocelot/vsc9959*
> >
> 
> The way I see an Ocelot DSA driver, it would be done a la mv88e6xxx,
> aka a single struct dsa_switch_ops registered for the entire family,
> and function pointers where the implementation differs. You're not
> proposing that here, but rather that each switch driver works in
> parallel with each other, and they all call into the Ocelot core. That
> would produce a lot more boilerplate, I think.
> And if the DSA driver for Ocelot ends up supporting more than 1
> device, its name should better not contain "vsc9959" since that's
> rather specific.
A vsc7511/12 will not share code with felix/vsc9959. I do not expect any other
IP/chip will be register compatible with vsc9959.

A vsc7511/12 will use the ocelot DSA tagger, but other from that it will call into the
ocelot driver (I think).

But to be honest, I do not think we should spend too much energy on vsc7511/12
now. When/if it comes, we will see how it fit best.

/Allan

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Vladimir Oltean]

On Tue, 12 Nov 2019 at 21:48, Allan W. Nielsen
<allan.nielsen@microchip.com> wrote:
>
> The 11/12/2019 21:26, Vladimir Oltean wrote:
> > External E-Mail
> >
> >
> > On Tue, 12 Nov 2019 at 21:10, Allan W. Nielsen
> > <allan.nielsen@microchip.com> wrote:
> > >
> > > The 11/12/2019 17:26, Vladimir Oltean wrote:
> > > > External E-Mail
> > > >
> > > >
> > > > On Tue, 12 Nov 2019 at 16:57, Allan W. Nielsen
> > > > <allan.nielsen@microchip.com> wrote:
> > > > >
> > > > > The 11/12/2019 15:50, Andrew Lunn wrote:
> > > > > > External E-Mail
> > > > > >
> > > > > >
> > > > > > > > > As there are no commonalities between the vsc73xx and felix drivers,
> > > > > > > > > shouldn't you simply leave that one out and have felix in the existing
> > > > > > > > > microchip folder?
> > > > > > > > >
> > > > > > > >
> > > > > > > > I don't have a strong preference, although where I come from, all new
> > > > > > > > NXP networking drivers are still labeled as "freescale" even though
> > > > > > > > there is no code reuse. There are even less commonalities with
> > > > > > > > Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
> > > > > > > > old vsc73xx. I'll let the ex-Vitesse people decide.
> > > > > > > I'm on the same page as Alexandre here.
> > > > > >
> > > > > > Leaving them where they are makes maintenance easier. Fixes are easier
> > > > > > to backport if things don't move around.
> > > > > >
> > > > > > > I think we should leave vsc73xx where it is already, and put the felix driver in
> > > > > > > the drivers/net/ethernet/mscc/ folder where ocelot is already.
> > > > > >
> > > > > > Currently, all DSA drivers are in drivers/net/dsa. We do occasionally
> > > > > > make changes over all DSA drivers at once, so it is nice they are all
> > > > > > together. So i would prefer the DSA part of Felix is also there. But
> > > > > > the core can be in drivers/net/ethernet/mscc/.
> > > > > Ahh, my bad.
> > > > >
> > > > > In that case I do not have any strong feelings on this either.
> > > > >
> > > > > I should say that we are discussing to add support for a Ocelot VSC7511 as a DSA
> > > > > driver. This one does not have an internal MIPS CPU.
> > > > >
> > > > > The vsc73xx, felix and the drivers in dsa/microchip does not share any
> > > > > functionallity. Not in SW and not in HW.
> > > > >
> > > > > Maybe felix should just go directly into drivers/net/dsa/, and then if we add
> > > > > support for VSC7511 then they can both live in drivers/net/dsa/ocelot/
> > >
> > >
> > > A bit of background such that people outside NXP/MCHP has a better change to
> > > follow and add to the discussion.
> > >
> > > Ocelot is a family name covering 4 VSC parts (VSC7511-14), and a IP used by NXP
> > > (VSC9959).
> > >
> > > VSC7511-14 are all register compatible, it uses the same serdes etc.
> > >
> > > VSC7511/12 are "unmanaged" meaning that they do not have an embedded CPU.
> > >
> > > VSC7513/14 has an embedded MIPS CPU.
> > >
> > > VSC9959 not the same core as VSC7511-14, it is a newer generation with more
> > > features, it is not register compatible, but all the basic functionallity is
> > > very similar VSC7511-14 which is why it can call into the
> > > drivers/net/ethernet/mscc/ocelot.c file.
> > >
> > > It is likely that NXP want to add more features in felix/VSC9959 which does not
> > > exists in VSC7511-14.
> > >
> > > > When the felix driver is going to support the vsc7511 ocelot switch
> > > > through the ocelot core, it will be naming chaos.
> > > I do not think a VSC7511 will be based on Felix, but it will relay on the
> > > refacturing/restructuring you have done in Ocelot.
> > >
> > > VSC7511 will use the same PCS and serdes settings as Ocelot (VSC7513/VSC7514)
> > >
> > > > Maybe we need to clarify what "felix" means (at the moment it means VSC9959).
> > > Yes.
> > >
> > > > What if we just make it mean "DSA driver for Ocelot", and it supports both the
> > > > VSC751x (Ocelot) and the VSC9959 (Felix) families?
> > > I'm not too keen on using the felix name for that.
> > >
> > > Here is my suggestion:
> > >
> > > Drop the felix name and put it in drivers/net/dsa/ocelot_vsc9959* (this would be
> > > my preference)
> > >
> >
> > This has one big issue: the name is very long! I can't see myself
> > prefixing all function and structure names with ocelot_vsc9959_*.
> > Felix is just 5 letters. And I can't use "ocelot" either, since that
> > is taken :)
> > So the DSA driver needs its own (short) name.
> I certainly agree that ocelot_vsc9959_* is too long a prefix.
>
> If you put it in drivers/net/dsa/ocelot_felix* or drivers/net/dsa/ocelot/felix*
> then you can prefix with 'felix_'.
>
> If you put it in drivers/net/dsa/ocelot_vsc9959* or drivers/net/dsa/ocelot/vsc9959*
> then you can prefix with 'vsc9959_'.
>
> The one thing all of this parts has in common is that they are all based on the
> Ocelot family, which is why I suggest to include this into the path. It will
> provide more information than putting it in the vitesse/microchip folders.
>
> > > Or if you want the felix name put it in drivers/net/dsa/ocelot_felix*
> > >
> > > Or if we want folders put it in drivers/net/dsa/ocelot/vsc9959*
> > >
> >
> > The way I see an Ocelot DSA driver, it would be done a la mv88e6xxx,
> > aka a single struct dsa_switch_ops registered for the entire family,
> > and function pointers where the implementation differs. You're not
> > proposing that here, but rather that each switch driver works in
> > parallel with each other, and they all call into the Ocelot core. That
> > would produce a lot more boilerplate, I think.
> > And if the DSA driver for Ocelot ends up supporting more than 1
> > device, its name should better not contain "vsc9959" since that's
> > rather specific.
> A vsc7511/12 will not share code with felix/vsc9959. I do not expect any other
> IP/chip will be register compatible with vsc9959.
>

I don't exactly understand this comment. Register-incompatible in a
logical sense, or in a layout sense? Judging from the attachment in
chapter 6 of the VSC7511 datasheet [1], at least the basic
functionality appears to be almost the same. And for the rest, there's
regmap magic.

> A vsc7511/12 will use the ocelot DSA tagger, but other from that it will call into the
> ocelot driver (I think).
>
> But to be honest, I do not think we should spend too much energy on vsc7511/12
> now. When/if it comes, we will see how it fit best.
>
> /Allan

Ok. So the driver will still be called "felix", it will instantiate a
struct felix_info_vsc9959 instead of the current felix_info_ls1028a,
but will live in the root drivers/net/dsa folder. Then, when/if you
add support for vsc7511, you'll move both into an "ocelot" folder and
figure out how much of the driver minus the tagger is worth reusing
(aka instantiate a struct felix_info_vsc7511). Agree?

[1]: http://ww1.microchip.com/downloads/en/DeviceDoc/VMDS-10488.pdf

-Vladimir

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Allan W. Nielsen]

> > > The way I see an Ocelot DSA driver, it would be done a la mv88e6xxx,
> > > aka a single struct dsa_switch_ops registered for the entire family,
> > > and function pointers where the implementation differs. You're not
> > > proposing that here, but rather that each switch driver works in
> > > parallel with each other, and they all call into the Ocelot core. That
> > > would produce a lot more boilerplate, I think.
> > > And if the DSA driver for Ocelot ends up supporting more than 1
> > > device, its name should better not contain "vsc9959" since that's
> > > rather specific.
> > A vsc7511/12 will not share code with felix/vsc9959. I do not expect any other
> > IP/chip will be register compatible with vsc9959.
> I don't exactly understand this comment. Register-incompatible in a
> logical sense, or in a layout sense? Judging from the attachment in
> chapter 6 of the VSC7511 datasheet [1], at least the basic
> functionality appears to be almost the same. And for the rest, there's
> regmap magic.
My point is that vsc7511 has more in commen with vsc7514 than it has with
felix/vsc9959.

vsc7511 will use the same regmaps as those in vsc7514 (with different helper
functions as it will be accessing the reguster via SPI).

As far as I recall, felix/vsc9959 has slightly different (in-compatible) PTP
functionallity than vsc7511-14, which needs to be handled in the felix/vsc9959
driver. The same apply if you want to add support for TAS/taprio as this
featurte are not to be found in vsc7511-14.

> > A vsc7511/12 will use the ocelot DSA tagger, but other from that it will call into the
> > ocelot driver (I think).
> >
> > But to be honest, I do not think we should spend too much energy on vsc7511/12
> > now. When/if it comes, we will see how it fit best.
> 
> Ok. So the driver will still be called "felix", it will instantiate a
> struct felix_info_vsc9959 instead of the current felix_info_ls1028a,
> but will live in the root drivers/net/dsa folder. Then, when/if you
> add support for vsc7511, you'll move both into an "ocelot" folder and
> figure out how much of the driver minus the tagger is worth reusing
> (aka instantiate a struct felix_info_vsc7511). Agree?
Agree.

/Allan

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Alexandre Belloni]

On 13/11/2019 08:38:22+0100, Allan W. Nielsen wrote:
> > > > The way I see an Ocelot DSA driver, it would be done a la mv88e6xxx,
> > > > aka a single struct dsa_switch_ops registered for the entire family,
> > > > and function pointers where the implementation differs. You're not
> > > > proposing that here, but rather that each switch driver works in
> > > > parallel with each other, and they all call into the Ocelot core. That
> > > > would produce a lot more boilerplate, I think.
> > > > And if the DSA driver for Ocelot ends up supporting more than 1
> > > > device, its name should better not contain "vsc9959" since that's
> > > > rather specific.
> > > A vsc7511/12 will not share code with felix/vsc9959. I do not expect any other
> > > IP/chip will be register compatible with vsc9959.
> > I don't exactly understand this comment. Register-incompatible in a
> > logical sense, or in a layout sense? Judging from the attachment in
> > chapter 6 of the VSC7511 datasheet [1], at least the basic
> > functionality appears to be almost the same. And for the rest, there's
> > regmap magic.
> My point is that vsc7511 has more in commen with vsc7514 than it has with
> felix/vsc9959.
> 
> vsc7511 will use the same regmaps as those in vsc7514 (with different helper
> functions as it will be accessing the reguster via SPI).
> 

regmap will properly abstract the underlying bus, this was the whole
point of using it.


-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH net-next 10/12] net: dsa: vitesse: move vsc73xx driver to a separate folder

[Florian Fainelli]

On 11/12/19 6:50 AM, Andrew Lunn wrote:
>>>> As there are no commonalities between the vsc73xx and felix drivers,
>>>> shouldn't you simply leave that one out and have felix in the existing
>>>> microchip folder?
>>>>
>>>
>>> I don't have a strong preference, although where I come from, all new
>>> NXP networking drivers are still labeled as "freescale" even though
>>> there is no code reuse. There are even less commonalities with
>>> Microchip (ex-Micrel, if I am not mistaken) KSZ switches than with the
>>> old vsc73xx. I'll let the ex-Vitesse people decide.
>> I'm on the same page as Alexandre here.
> 
> Leaving them where they are makes maintenance easier. Fixes are easier
> to backport if things don't move around.

Agree

> 
>> I think we should leave vsc73xx where it is already, and put the felix driver in
>> the drivers/net/ethernet/mscc/ folder where ocelot is already.
> 
> Currently, all DSA drivers are in drivers/net/dsa. We do occasionally
> make changes over all DSA drivers at once, so it is nice they are all
> together. So i would prefer the DSA part of Felix is also there. But
> the core can be in drivers/net/ethernet/mscc/.

And agree here as well.
-- 
Florian

[PATCH net-next 11/12] net: dsa: vitesse: add basic Felix switch driver

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This supports an Ethernet switching core from Vitesse / Microsemi /
Microchip (VSC9959) that can be integrated on different SoCs as a PCIe
endpoint device.

The functionality is provided by the core of the Ocelot switch driver
(net/ethernet/mscc). In this regard, the current driver is an instance
of Microsemi's Ocelot core driver, with a DSA front-end.

The patch adds the logic for probing a PCI device and defines the
register map for the Felix switch core, since it has some differences in
register addresses and bitfield mappings compared to the Ocelot switch.

Also some registers or bitfields present on Ocelot are not available on
Felix. It is very possible that even other instantiations of the Felix
core, on other SoC's, will have shuffled ("optimized") register maps as
well, so this driver declares the register map as part of the "instance
table" (currently the NXP LS1028A is the only instance).  Other than
that, the common registers and bitfields have the same functionality and
share the same name.

In a few cases, some h/w operations have to be done differently on Felix
due to missing bitfields.  This is the case for the switch core reset
and init.  Because for this operation Ocelot uses some bits that are not
present on Felix, the latter has to use a register from the global
registers block (GCB) instead.

Although it is a PCI driver, it relies on DT bindings for compatibility
with DSA (CPU port link, PHY library). It does not have any custom
device tree bindings, since we would like to minimize its dependency on
device tree though.

Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 MAINTAINERS                          |   7 +
 drivers/net/dsa/vitesse/Kconfig      |  12 +
 drivers/net/dsa/vitesse/Makefile     |   7 +
 drivers/net/dsa/vitesse/felix-regs.c | 647 +++++++++++++++++++++++++++
 drivers/net/dsa/vitesse/felix.c      | 359 +++++++++++++++
 drivers/net/dsa/vitesse/felix.h      |  36 ++
 6 files changed, 1068 insertions(+)
 create mode 100644 drivers/net/dsa/vitesse/felix-regs.c
 create mode 100644 drivers/net/dsa/vitesse/felix.c
 create mode 100644 drivers/net/dsa/vitesse/felix.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 3e57fc1d9962..486300903366 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17359,6 +17359,13 @@ S:	Maintained
 F:	drivers/input/serio/userio.c
 F:	include/uapi/linux/userio.h
 
+VITESSE FELIX ETHERNET SWITCH DRIVER
+M:	Vladimir Oltean <vladimir.oltean@nxp.com>
+M:	Claudiu Manoil <claudiu.manoil@nxp.com>
+L:	netdev@vger.kernel.org
+S:	Maintained
+F:	drivers/net/dsa/vitesse/felix*
+
 VIVID VIRTUAL VIDEO DRIVER
 M:	Hans Verkuil <hverkuil@xs4all.nl>
 L:	linux-media@vger.kernel.org
diff --git a/drivers/net/dsa/vitesse/Kconfig b/drivers/net/dsa/vitesse/Kconfig
index 54be4b34fd17..ca47c55f9733 100644
--- a/drivers/net/dsa/vitesse/Kconfig
+++ b/drivers/net/dsa/vitesse/Kconfig
@@ -1,3 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_VITESSE_FELIX
+	tristate "Felix Ethernet switch support"
+	depends on NET_DSA && PCI
+	select MSCC_OCELOT_SWITCH
+	help
+	  This driver supports the Felix (VSC9959) network switch, which is a
+	  variant of the Vitesse Ocelot switch core that is embedded as a PCIe
+	  function of the NXP LS1028A ENETC integrated endpoint. It reuses
+	  large portions of the Ocelot common driver core, while presenting the
+	  switch as a DSA device.
+
 config NET_DSA_VITESSE_VSC73XX
 	tristate
 	depends on OF
diff --git a/drivers/net/dsa/vitesse/Makefile b/drivers/net/dsa/vitesse/Makefile
index adceeeec5d12..f0c0581aa670 100644
--- a/drivers/net/dsa/vitesse/Makefile
+++ b/drivers/net/dsa/vitesse/Makefile
@@ -1,3 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_NET_DSA_VITESSE_FELIX) += vsc_felix.o
+
+vsc_felix-objs := \
+	felix.o \
+	felix-regs.o
+
 obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX) += vsc73xx-core.o
 obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM) += vsc73xx-platform.o
 obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) += vsc73xx-spi.o
diff --git a/drivers/net/dsa/vitesse/felix-regs.c b/drivers/net/dsa/vitesse/felix-regs.c
new file mode 100644
index 000000000000..5b6df2a1636f
--- /dev/null
+++ b/drivers/net/dsa/vitesse/felix-regs.c
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright 2017 Microsemi Corporation
+ * Copyright 2018-2019 NXP Semiconductors
+ */
+#include <soc/mscc/ocelot_sys.h>
+#include <soc/mscc/ocelot.h>
+#include <linux/iopoll.h>
+#include <linux/pci.h>
+#include "felix.h"
+
+static const u32 felix_ls1028a_ana_regmap[] = {
+	REG(ANA_ADVLEARN,			0x0089a0),
+	REG(ANA_VLANMASK,			0x0089a4),
+	REG_RESERVED(ANA_PORT_B_DOMAIN),
+	REG(ANA_ANAGEFIL,			0x0089ac),
+	REG(ANA_ANEVENTS,			0x0089b0),
+	REG(ANA_STORMLIMIT_BURST,		0x0089b4),
+	REG(ANA_STORMLIMIT_CFG,			0x0089b8),
+	REG(ANA_ISOLATED_PORTS,			0x0089c8),
+	REG(ANA_COMMUNITY_PORTS,		0x0089cc),
+	REG(ANA_AUTOAGE,			0x0089d0),
+	REG(ANA_MACTOPTIONS,			0x0089d4),
+	REG(ANA_LEARNDISC,			0x0089d8),
+	REG(ANA_AGENCTRL,			0x0089dc),
+	REG(ANA_MIRRORPORTS,			0x0089e0),
+	REG(ANA_EMIRRORPORTS,			0x0089e4),
+	REG(ANA_FLOODING,			0x0089e8),
+	REG(ANA_FLOODING_IPMC,			0x008a08),
+	REG(ANA_SFLOW_CFG,			0x008a0c),
+	REG(ANA_PORT_MODE,			0x008a28),
+	REG(ANA_CUT_THRU_CFG,			0x008a48),
+	REG(ANA_PGID_PGID,			0x008400),
+	REG(ANA_TABLES_ANMOVED,			0x007f1c),
+	REG(ANA_TABLES_MACHDATA,		0x007f20),
+	REG(ANA_TABLES_MACLDATA,		0x007f24),
+	REG(ANA_TABLES_STREAMDATA,		0x007f28),
+	REG(ANA_TABLES_MACACCESS,		0x007f2c),
+	REG(ANA_TABLES_MACTINDX,		0x007f30),
+	REG(ANA_TABLES_VLANACCESS,		0x007f34),
+	REG(ANA_TABLES_VLANTIDX,		0x007f38),
+	REG(ANA_TABLES_ISDXACCESS,		0x007f3c),
+	REG(ANA_TABLES_ISDXTIDX,		0x007f40),
+	REG(ANA_TABLES_ENTRYLIM,		0x007f00),
+	REG(ANA_TABLES_PTP_ID_HIGH,		0x007f44),
+	REG(ANA_TABLES_PTP_ID_LOW,		0x007f48),
+	REG(ANA_TABLES_STREAMACCESS,		0x007f4c),
+	REG(ANA_TABLES_STREAMTIDX,		0x007f50),
+	REG(ANA_TABLES_SEQ_HISTORY,		0x007f54),
+	REG(ANA_TABLES_SEQ_MASK,		0x007f58),
+	REG(ANA_TABLES_SFID_MASK,		0x007f5c),
+	REG(ANA_TABLES_SFIDACCESS,		0x007f60),
+	REG(ANA_TABLES_SFIDTIDX,		0x007f64),
+	REG(ANA_MSTI_STATE,			0x008600),
+	REG(ANA_OAM_UPM_LM_CNT,			0x008000),
+	REG(ANA_SG_ACCESS_CTRL,			0x008a64),
+	REG(ANA_SG_CONFIG_REG_1,		0x007fb0),
+	REG(ANA_SG_CONFIG_REG_2,		0x007fb4),
+	REG(ANA_SG_CONFIG_REG_3,		0x007fb8),
+	REG(ANA_SG_CONFIG_REG_4,		0x007fbc),
+	REG(ANA_SG_CONFIG_REG_5,		0x007fc0),
+	REG(ANA_SG_GCL_GS_CONFIG,		0x007f80),
+	REG(ANA_SG_GCL_TI_CONFIG,		0x007f90),
+	REG(ANA_SG_STATUS_REG_1,		0x008980),
+	REG(ANA_SG_STATUS_REG_2,		0x008984),
+	REG(ANA_SG_STATUS_REG_3,		0x008988),
+	REG(ANA_PORT_VLAN_CFG,			0x007800),
+	REG(ANA_PORT_DROP_CFG,			0x007804),
+	REG(ANA_PORT_QOS_CFG,			0x007808),
+	REG(ANA_PORT_VCAP_CFG,			0x00780c),
+	REG(ANA_PORT_VCAP_S1_KEY_CFG,		0x007810),
+	REG(ANA_PORT_VCAP_S2_CFG,		0x00781c),
+	REG(ANA_PORT_PCP_DEI_MAP,		0x007820),
+	REG(ANA_PORT_CPU_FWD_CFG,		0x007860),
+	REG(ANA_PORT_CPU_FWD_BPDU_CFG,		0x007864),
+	REG(ANA_PORT_CPU_FWD_GARP_CFG,		0x007868),
+	REG(ANA_PORT_CPU_FWD_CCM_CFG,		0x00786c),
+	REG(ANA_PORT_PORT_CFG,			0x007870),
+	REG(ANA_PORT_POL_CFG,			0x007874),
+	REG(ANA_PORT_PTP_CFG,			0x007878),
+	REG(ANA_PORT_PTP_DLY1_CFG,		0x00787c),
+	REG(ANA_PORT_PTP_DLY2_CFG,		0x007880),
+	REG(ANA_PORT_SFID_CFG,			0x007884),
+	REG(ANA_PFC_PFC_CFG,			0x008800),
+	REG_RESERVED(ANA_PFC_PFC_TIMER),
+	REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
+	REG_RESERVED(ANA_IPT_IPT),
+	REG_RESERVED(ANA_PPT_PPT),
+	REG_RESERVED(ANA_FID_MAP_FID_MAP),
+	REG(ANA_AGGR_CFG,			0x008a68),
+	REG(ANA_CPUQ_CFG,			0x008a6c),
+	REG_RESERVED(ANA_CPUQ_CFG2),
+	REG(ANA_CPUQ_8021_CFG,			0x008a74),
+	REG(ANA_DSCP_CFG,			0x008ab4),
+	REG(ANA_DSCP_REWR_CFG,			0x008bb4),
+	REG(ANA_VCAP_RNG_TYPE_CFG,		0x008bf4),
+	REG(ANA_VCAP_RNG_VAL_CFG,		0x008c14),
+	REG_RESERVED(ANA_VRAP_CFG),
+	REG_RESERVED(ANA_VRAP_HDR_DATA),
+	REG_RESERVED(ANA_VRAP_HDR_MASK),
+	REG(ANA_DISCARD_CFG,			0x008c40),
+	REG(ANA_FID_CFG,			0x008c44),
+	REG(ANA_POL_PIR_CFG,			0x004000),
+	REG(ANA_POL_CIR_CFG,			0x004004),
+	REG(ANA_POL_MODE_CFG,			0x004008),
+	REG(ANA_POL_PIR_STATE,			0x00400c),
+	REG(ANA_POL_CIR_STATE,			0x004010),
+	REG_RESERVED(ANA_POL_STATE),
+	REG(ANA_POL_FLOWC,			0x008c48),
+	REG(ANA_POL_HYST,			0x008cb4),
+	REG_RESERVED(ANA_POL_MISC_CFG),
+};
+
+static const u32 felix_ls1028a_qs_regmap[] = {
+	REG(QS_XTR_GRP_CFG,			0x000000),
+	REG(QS_XTR_RD,				0x000008),
+	REG(QS_XTR_FRM_PRUNING,			0x000010),
+	REG(QS_XTR_FLUSH,			0x000018),
+	REG(QS_XTR_DATA_PRESENT,		0x00001c),
+	REG(QS_XTR_CFG,				0x000020),
+	REG(QS_INJ_GRP_CFG,			0x000024),
+	REG(QS_INJ_WR,				0x00002c),
+	REG(QS_INJ_CTRL,			0x000034),
+	REG(QS_INJ_STATUS,			0x00003c),
+	REG(QS_INJ_ERR,				0x000040),
+	REG_RESERVED(QS_INH_DBG),
+};
+
+static const u32 felix_ls1028a_s2_regmap[] = {
+	REG(S2_CORE_UPDATE_CTRL,		0x000000),
+	REG(S2_CORE_MV_CFG,			0x000004),
+	REG(S2_CACHE_ENTRY_DAT,			0x000008),
+	REG(S2_CACHE_MASK_DAT,			0x000108),
+	REG(S2_CACHE_ACTION_DAT,		0x000208),
+	REG(S2_CACHE_CNT_DAT,			0x000308),
+	REG(S2_CACHE_TG_DAT,			0x000388),
+};
+
+static const u32 felix_ls1028a_qsys_regmap[] = {
+	REG(QSYS_PORT_MODE,			0x00f460),
+	REG(QSYS_SWITCH_PORT_MODE,		0x00f480),
+	REG(QSYS_STAT_CNT_CFG,			0x00f49c),
+	REG(QSYS_EEE_CFG,			0x00f4a0),
+	REG(QSYS_EEE_THRES,			0x00f4b8),
+	REG(QSYS_IGR_NO_SHARING,		0x00f4bc),
+	REG(QSYS_EGR_NO_SHARING,		0x00f4c0),
+	REG(QSYS_SW_STATUS,			0x00f4c4),
+	REG(QSYS_EXT_CPU_CFG,			0x00f4e0),
+	REG_RESERVED(QSYS_PAD_CFG),
+	REG(QSYS_CPU_GROUP_MAP,			0x00f4e8),
+	REG_RESERVED(QSYS_QMAP),
+	REG_RESERVED(QSYS_ISDX_SGRP),
+	REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
+	REG(QSYS_TFRM_MISC,			0x00f50c),
+	REG(QSYS_TFRM_PORT_DLY,			0x00f510),
+	REG(QSYS_TFRM_TIMER_CFG_1,		0x00f514),
+	REG(QSYS_TFRM_TIMER_CFG_2,		0x00f518),
+	REG(QSYS_TFRM_TIMER_CFG_3,		0x00f51c),
+	REG(QSYS_TFRM_TIMER_CFG_4,		0x00f520),
+	REG(QSYS_TFRM_TIMER_CFG_5,		0x00f524),
+	REG(QSYS_TFRM_TIMER_CFG_6,		0x00f528),
+	REG(QSYS_TFRM_TIMER_CFG_7,		0x00f52c),
+	REG(QSYS_TFRM_TIMER_CFG_8,		0x00f530),
+	REG(QSYS_RED_PROFILE,			0x00f534),
+	REG(QSYS_RES_QOS_MODE,			0x00f574),
+	REG(QSYS_RES_CFG,			0x00c000),
+	REG(QSYS_RES_STAT,			0x00c004),
+	REG(QSYS_EGR_DROP_MODE,			0x00f578),
+	REG(QSYS_EQ_CTRL,			0x00f57c),
+	REG_RESERVED(QSYS_EVENTS_CORE),
+	REG(QSYS_QMAXSDU_CFG_0,			0x00f584),
+	REG(QSYS_QMAXSDU_CFG_1,			0x00f5a0),
+	REG(QSYS_QMAXSDU_CFG_2,			0x00f5bc),
+	REG(QSYS_QMAXSDU_CFG_3,			0x00f5d8),
+	REG(QSYS_QMAXSDU_CFG_4,			0x00f5f4),
+	REG(QSYS_QMAXSDU_CFG_5,			0x00f610),
+	REG(QSYS_QMAXSDU_CFG_6,			0x00f62c),
+	REG(QSYS_QMAXSDU_CFG_7,			0x00f648),
+	REG(QSYS_PREEMPTION_CFG,		0x00f664),
+	REG_RESERVED(QSYS_CIR_CFG),
+	REG(QSYS_EIR_CFG,			0x000004),
+	REG(QSYS_SE_CFG,			0x000008),
+	REG(QSYS_SE_DWRR_CFG,			0x00000c),
+	REG_RESERVED(QSYS_SE_CONNECT),
+	REG(QSYS_SE_DLB_SENSE,			0x000040),
+	REG(QSYS_CIR_STATE,			0x000044),
+	REG(QSYS_EIR_STATE,			0x000048),
+	REG_RESERVED(QSYS_SE_STATE),
+	REG(QSYS_HSCH_MISC_CFG,			0x00f67c),
+	REG(QSYS_TAG_CONFIG,			0x00f680),
+	REG(QSYS_TAS_PARAM_CFG_CTRL,		0x00f698),
+	REG(QSYS_PORT_MAX_SDU,			0x00f69c),
+	REG(QSYS_PARAM_CFG_REG_1,		0x00f440),
+	REG(QSYS_PARAM_CFG_REG_2,		0x00f444),
+	REG(QSYS_PARAM_CFG_REG_3,		0x00f448),
+	REG(QSYS_PARAM_CFG_REG_4,		0x00f44c),
+	REG(QSYS_PARAM_CFG_REG_5,		0x00f450),
+	REG(QSYS_GCL_CFG_REG_1,			0x00f454),
+	REG(QSYS_GCL_CFG_REG_2,			0x00f458),
+	REG(QSYS_PARAM_STATUS_REG_1,		0x00f400),
+	REG(QSYS_PARAM_STATUS_REG_2,		0x00f404),
+	REG(QSYS_PARAM_STATUS_REG_3,		0x00f408),
+	REG(QSYS_PARAM_STATUS_REG_4,		0x00f40c),
+	REG(QSYS_PARAM_STATUS_REG_5,		0x00f410),
+	REG(QSYS_PARAM_STATUS_REG_6,		0x00f414),
+	REG(QSYS_PARAM_STATUS_REG_7,		0x00f418),
+	REG(QSYS_PARAM_STATUS_REG_8,		0x00f41c),
+	REG(QSYS_PARAM_STATUS_REG_9,		0x00f420),
+	REG(QSYS_GCL_STATUS_REG_1,		0x00f424),
+	REG(QSYS_GCL_STATUS_REG_2,		0x00f428),
+};
+
+static const u32 felix_ls1028a_rew_regmap[] = {
+	REG(REW_PORT_VLAN_CFG,			0x000000),
+	REG(REW_TAG_CFG,			0x000004),
+	REG(REW_PORT_CFG,			0x000008),
+	REG(REW_DSCP_CFG,			0x00000c),
+	REG(REW_PCP_DEI_QOS_MAP_CFG,		0x000010),
+	REG(REW_PTP_CFG,			0x000050),
+	REG(REW_PTP_DLY1_CFG,			0x000054),
+	REG(REW_RED_TAG_CFG,			0x000058),
+	REG(REW_DSCP_REMAP_DP1_CFG,		0x000410),
+	REG(REW_DSCP_REMAP_CFG,			0x000510),
+	REG_RESERVED(REW_STAT_CFG),
+	REG_RESERVED(REW_REW_STICKY),
+	REG_RESERVED(REW_PPT),
+};
+
+static const u32 felix_ls1028a_sys_regmap[] = {
+	REG(SYS_COUNT_RX_OCTETS,		0x000000),
+	REG(SYS_COUNT_RX_MULTICAST,		0x000008),
+	REG(SYS_COUNT_RX_SHORTS,		0x000010),
+	REG(SYS_COUNT_RX_FRAGMENTS,		0x000014),
+	REG(SYS_COUNT_RX_JABBERS,		0x000018),
+	REG(SYS_COUNT_RX_64,			0x000024),
+	REG(SYS_COUNT_RX_65_127,		0x000028),
+	REG(SYS_COUNT_RX_128_255,		0x00002c),
+	REG(SYS_COUNT_RX_256_1023,		0x000030),
+	REG(SYS_COUNT_RX_1024_1526,		0x000034),
+	REG(SYS_COUNT_RX_1527_MAX,		0x000038),
+	REG(SYS_COUNT_RX_LONGS,			0x000044),
+	REG(SYS_COUNT_TX_OCTETS,		0x000200),
+	REG(SYS_COUNT_TX_COLLISION,		0x000210),
+	REG(SYS_COUNT_TX_DROPS,			0x000214),
+	REG(SYS_COUNT_TX_64,			0x00021c),
+	REG(SYS_COUNT_TX_65_127,		0x000220),
+	REG(SYS_COUNT_TX_128_511,		0x000224),
+	REG(SYS_COUNT_TX_512_1023,		0x000228),
+	REG(SYS_COUNT_TX_1024_1526,		0x00022c),
+	REG(SYS_COUNT_TX_1527_MAX,		0x000230),
+	REG(SYS_COUNT_TX_AGING,			0x000278),
+	REG(SYS_RESET_CFG,			0x000e00),
+	REG(SYS_SR_ETYPE_CFG,			0x000e04),
+	REG(SYS_VLAN_ETYPE_CFG,			0x000e08),
+	REG(SYS_PORT_MODE,			0x000e0c),
+	REG(SYS_FRONT_PORT_MODE,		0x000e2c),
+	REG(SYS_FRM_AGING,			0x000e44),
+	REG(SYS_STAT_CFG,			0x000e48),
+	REG(SYS_SW_STATUS,			0x000e4c),
+	REG_RESERVED(SYS_MISC_CFG),
+	REG(SYS_REW_MAC_HIGH_CFG,		0x000e6c),
+	REG(SYS_REW_MAC_LOW_CFG,		0x000e84),
+	REG(SYS_TIMESTAMP_OFFSET,		0x000e9c),
+	REG(SYS_PAUSE_CFG,			0x000ea0),
+	REG(SYS_PAUSE_TOT_CFG,			0x000ebc),
+	REG(SYS_ATOP,				0x000ec0),
+	REG(SYS_ATOP_TOT_CFG,			0x000edc),
+	REG(SYS_MAC_FC_CFG,			0x000ee0),
+	REG(SYS_MMGT,				0x000ef8),
+	REG_RESERVED(SYS_MMGT_FAST),
+	REG_RESERVED(SYS_EVENTS_DIF),
+	REG_RESERVED(SYS_EVENTS_CORE),
+	REG_RESERVED(SYS_CNT),
+	REG(SYS_PTP_STATUS,			0x000f14),
+	REG(SYS_PTP_TXSTAMP,			0x000f18),
+	REG(SYS_PTP_NXT,			0x000f1c),
+	REG(SYS_PTP_CFG,			0x000f20),
+	REG(SYS_RAM_INIT,			0x000f24),
+	REG_RESERVED(SYS_CM_ADDR),
+	REG_RESERVED(SYS_CM_DATA_WR),
+	REG_RESERVED(SYS_CM_DATA_RD),
+	REG_RESERVED(SYS_CM_OP),
+	REG_RESERVED(SYS_CM_DATA),
+};
+
+static const u32 felix_ls1028a_gcb_regmap[] = {
+	REG(GCB_SOFT_RST,			0x000004),
+};
+
+static const u32 *felix_ls1028a_regmap[] = {
+	[ANA]	= felix_ls1028a_ana_regmap,
+	[QS]	= felix_ls1028a_qs_regmap,
+	[QSYS]	= felix_ls1028a_qsys_regmap,
+	[REW]	= felix_ls1028a_rew_regmap,
+	[SYS]	= felix_ls1028a_sys_regmap,
+	[S2]	= felix_ls1028a_s2_regmap,
+	[GCB]	= felix_ls1028a_gcb_regmap,
+};
+
+/* Addresses are relative to the PCI device's base address and
+ * will be fixed up at ioremap time.
+ */
+static struct resource felix_ls1028a_target_io_res[] = {
+	[ANA] = {
+		.start	= 0x0280000,
+		.end	= 0x028ffff,
+		.name	= "ana",
+	},
+	[QS] = {
+		.start	= 0x0080000,
+		.end	= 0x00800ff,
+		.name	= "qs",
+	},
+	[QSYS] = {
+		.start	= 0x0200000,
+		.end	= 0x021ffff,
+		.name	= "qsys",
+	},
+	[REW] = {
+		.start	= 0x0030000,
+		.end	= 0x003ffff,
+		.name	= "rew",
+	},
+	[SYS] = {
+		.start	= 0x0010000,
+		.end	= 0x001ffff,
+		.name	= "sys",
+	},
+	[S2] = {
+		.start	= 0x0060000,
+		.end	= 0x00603ff,
+		.name	= "s2",
+	},
+	[GCB] = {
+		.start	= 0x0070000,
+		.end	= 0x00701ff,
+		.name	= "devcpu_gcb",
+	},
+};
+
+static struct resource felix_ls1028a_port_io_res[] = {
+	{
+		.start	= 0x0100000,
+		.end	= 0x010ffff,
+		.name	= "port0",
+	},
+	{
+		.start	= 0x0110000,
+		.end	= 0x011ffff,
+		.name	= "port1",
+	},
+	{
+		.start	= 0x0120000,
+		.end	= 0x012ffff,
+		.name	= "port2",
+	},
+	{
+		.start	= 0x0130000,
+		.end	= 0x013ffff,
+		.name	= "port3",
+	},
+	{
+		.start	= 0x0140000,
+		.end	= 0x014ffff,
+		.name	= "port4",
+	},
+	{
+		.start	= 0x0150000,
+		.end	= 0x015ffff,
+		.name	= "port5",
+	},
+};
+
+static const struct reg_field felix_regfields[] = {
+	[ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
+	[ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
+	[ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
+	[ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
+	[ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
+	[ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
+	[ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
+	[ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
+	[ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
+	[ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
+	[ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
+	[ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
+	[ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
+	[ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
+	[ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
+	[ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
+	[ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
+	[ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
+	[ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
+	[ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
+	[ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
+	[ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
+	[ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
+	[ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
+	[ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
+	[ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
+	[ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
+	[ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
+	[ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
+	[ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
+	[ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
+	[SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
+	[GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
+};
+
+static const struct ocelot_stat_layout felix_ls1028a_stats_layout[] = {
+	{ .offset = 0x00,	.name = "rx_octets", },
+	{ .offset = 0x01,	.name = "rx_unicast", },
+	{ .offset = 0x02,	.name = "rx_multicast", },
+	{ .offset = 0x03,	.name = "rx_broadcast", },
+	{ .offset = 0x04,	.name = "rx_shorts", },
+	{ .offset = 0x05,	.name = "rx_fragments", },
+	{ .offset = 0x06,	.name = "rx_jabbers", },
+	{ .offset = 0x07,	.name = "rx_crc_align_errs", },
+	{ .offset = 0x08,	.name = "rx_sym_errs", },
+	{ .offset = 0x09,	.name = "rx_frames_below_65_octets", },
+	{ .offset = 0x0A,	.name = "rx_frames_65_to_127_octets", },
+	{ .offset = 0x0B,	.name = "rx_frames_128_to_255_octets", },
+	{ .offset = 0x0C,	.name = "rx_frames_256_to_511_octets", },
+	{ .offset = 0x0D,	.name = "rx_frames_512_to_1023_octets", },
+	{ .offset = 0x0E,	.name = "rx_frames_1024_to_1526_octets", },
+	{ .offset = 0x0F,	.name = "rx_frames_over_1526_octets", },
+	{ .offset = 0x10,	.name = "rx_pause", },
+	{ .offset = 0x11,	.name = "rx_control", },
+	{ .offset = 0x12,	.name = "rx_longs", },
+	{ .offset = 0x13,	.name = "rx_classified_drops", },
+	{ .offset = 0x14,	.name = "rx_red_prio_0", },
+	{ .offset = 0x15,	.name = "rx_red_prio_1", },
+	{ .offset = 0x16,	.name = "rx_red_prio_2", },
+	{ .offset = 0x17,	.name = "rx_red_prio_3", },
+	{ .offset = 0x18,	.name = "rx_red_prio_4", },
+	{ .offset = 0x19,	.name = "rx_red_prio_5", },
+	{ .offset = 0x1A,	.name = "rx_red_prio_6", },
+	{ .offset = 0x1B,	.name = "rx_red_prio_7", },
+	{ .offset = 0x1C,	.name = "rx_yellow_prio_0", },
+	{ .offset = 0x1D,	.name = "rx_yellow_prio_1", },
+	{ .offset = 0x1E,	.name = "rx_yellow_prio_2", },
+	{ .offset = 0x1F,	.name = "rx_yellow_prio_3", },
+	{ .offset = 0x20,	.name = "rx_yellow_prio_4", },
+	{ .offset = 0x21,	.name = "rx_yellow_prio_5", },
+	{ .offset = 0x22,	.name = "rx_yellow_prio_6", },
+	{ .offset = 0x23,	.name = "rx_yellow_prio_7", },
+	{ .offset = 0x24,	.name = "rx_green_prio_0", },
+	{ .offset = 0x25,	.name = "rx_green_prio_1", },
+	{ .offset = 0x26,	.name = "rx_green_prio_2", },
+	{ .offset = 0x27,	.name = "rx_green_prio_3", },
+	{ .offset = 0x28,	.name = "rx_green_prio_4", },
+	{ .offset = 0x29,	.name = "rx_green_prio_5", },
+	{ .offset = 0x2A,	.name = "rx_green_prio_6", },
+	{ .offset = 0x2B,	.name = "rx_green_prio_7", },
+	{ .offset = 0x80,	.name = "tx_octets", },
+	{ .offset = 0x81,	.name = "tx_unicast", },
+	{ .offset = 0x82,	.name = "tx_multicast", },
+	{ .offset = 0x83,	.name = "tx_broadcast", },
+	{ .offset = 0x84,	.name = "tx_collision", },
+	{ .offset = 0x85,	.name = "tx_drops", },
+	{ .offset = 0x86,	.name = "tx_pause", },
+	{ .offset = 0x87,	.name = "tx_frames_below_65_octets", },
+	{ .offset = 0x88,	.name = "tx_frames_65_to_127_octets", },
+	{ .offset = 0x89,	.name = "tx_frames_128_255_octets", },
+	{ .offset = 0x8B,	.name = "tx_frames_256_511_octets", },
+	{ .offset = 0x8C,	.name = "tx_frames_1024_1526_octets", },
+	{ .offset = 0x8D,	.name = "tx_frames_over_1526_octets", },
+	{ .offset = 0x8E,	.name = "tx_yellow_prio_0", },
+	{ .offset = 0x8F,	.name = "tx_yellow_prio_1", },
+	{ .offset = 0x90,	.name = "tx_yellow_prio_2", },
+	{ .offset = 0x91,	.name = "tx_yellow_prio_3", },
+	{ .offset = 0x92,	.name = "tx_yellow_prio_4", },
+	{ .offset = 0x93,	.name = "tx_yellow_prio_5", },
+	{ .offset = 0x94,	.name = "tx_yellow_prio_6", },
+	{ .offset = 0x95,	.name = "tx_yellow_prio_7", },
+	{ .offset = 0x96,	.name = "tx_green_prio_0", },
+	{ .offset = 0x97,	.name = "tx_green_prio_1", },
+	{ .offset = 0x98,	.name = "tx_green_prio_2", },
+	{ .offset = 0x99,	.name = "tx_green_prio_3", },
+	{ .offset = 0x9A,	.name = "tx_green_prio_4", },
+	{ .offset = 0x9B,	.name = "tx_green_prio_5", },
+	{ .offset = 0x9C,	.name = "tx_green_prio_6", },
+	{ .offset = 0x9D,	.name = "tx_green_prio_7", },
+	{ .offset = 0x9E,	.name = "tx_aged", },
+	{ .offset = 0x100,	.name = "drop_local", },
+	{ .offset = 0x101,	.name = "drop_tail", },
+	{ .offset = 0x102,	.name = "drop_yellow_prio_0", },
+	{ .offset = 0x103,	.name = "drop_yellow_prio_1", },
+	{ .offset = 0x104,	.name = "drop_yellow_prio_2", },
+	{ .offset = 0x105,	.name = "drop_yellow_prio_3", },
+	{ .offset = 0x106,	.name = "drop_yellow_prio_4", },
+	{ .offset = 0x107,	.name = "drop_yellow_prio_5", },
+	{ .offset = 0x108,	.name = "drop_yellow_prio_6", },
+	{ .offset = 0x109,	.name = "drop_yellow_prio_7", },
+	{ .offset = 0x10A,	.name = "drop_green_prio_0", },
+	{ .offset = 0x10B,	.name = "drop_green_prio_1", },
+	{ .offset = 0x10C,	.name = "drop_green_prio_2", },
+	{ .offset = 0x10D,	.name = "drop_green_prio_3", },
+	{ .offset = 0x10E,	.name = "drop_green_prio_4", },
+	{ .offset = 0x10F,	.name = "drop_green_prio_5", },
+	{ .offset = 0x110,	.name = "drop_green_prio_6", },
+	{ .offset = 0x111,	.name = "drop_green_prio_7", },
+};
+
+#define FELIX_INIT_TIMEOUT			50000
+#define FELIX_GCB_RST_SLEEP			100
+#define FELIX_SYS_RAMINIT_SLEEP			80
+
+static int felix_gcb_soft_rst_status(struct ocelot *ocelot)
+{
+	int val;
+
+	regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val);
+
+	return val;
+}
+
+static int felix_sys_ram_init_status(struct ocelot *ocelot)
+{
+	return ocelot_read(ocelot, SYS_RAM_INIT);
+}
+
+static int felix_ls1028a_reset(struct ocelot *ocelot)
+{
+	int val, err;
+
+	/* soft-reset the switch core */
+	regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1);
+
+	err = readx_poll_timeout(felix_gcb_soft_rst_status, ocelot, val, !val,
+				 FELIX_GCB_RST_SLEEP, FELIX_INIT_TIMEOUT);
+	if (err) {
+		dev_err(ocelot->dev, "timeout: switch core reset\n");
+		return err;
+	}
+
+	/* initialize switch mem ~40us */
+	ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
+	err = readx_poll_timeout(felix_sys_ram_init_status, ocelot, val, !val,
+				 FELIX_SYS_RAMINIT_SLEEP, FELIX_INIT_TIMEOUT);
+	if (err) {
+		dev_err(ocelot->dev, "timeout: switch sram init\n");
+		return err;
+	}
+
+	/* enable switch core */
+	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
+
+	return 0;
+}
+
+static const struct ocelot_ops felix_ls1028a_ops = {
+	.reset			= felix_ls1028a_reset,
+};
+
+struct felix_info felix_info_ls1028a = {
+	.target_io_res		= felix_ls1028a_target_io_res,
+	.port_io_res		= felix_ls1028a_port_io_res,
+	.map			= felix_ls1028a_regmap,
+	.ops			= &felix_ls1028a_ops,
+	.stats_layout		= felix_ls1028a_stats_layout,
+	.num_stats		= ARRAY_SIZE(felix_ls1028a_stats_layout),
+	.shared_queue_sz	= 128 * 1024,
+	.num_ports		= 6,
+	.pci_bar		= 4,
+};
+
+int felix_init_structs(struct felix *felix, int num_phys_ports)
+{
+	struct ocelot *ocelot = &felix->ocelot;
+	resource_size_t base;
+	int port, i, err;
+
+	ocelot->num_phys_ports = num_phys_ports;
+	ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports,
+				     sizeof(struct ocelot_port *), GFP_KERNEL);
+	if (!ocelot->ports)
+		return -ENOMEM;
+
+	ocelot->map		= felix->info->map;
+	ocelot->stats_layout	= felix->info->stats_layout;
+	ocelot->num_stats	= felix->info->num_stats;
+	ocelot->shared_queue_sz	= felix->info->shared_queue_sz;
+	ocelot->ops		= felix->info->ops;
+
+	base = pci_resource_start(felix->pdev, felix->info->pci_bar);
+
+	for (i = 0; i < TARGET_MAX; i++) {
+		struct regmap *target;
+		struct resource *res;
+
+		if (!felix->info->target_io_res[i].name)
+			continue;
+
+		res = &felix->info->target_io_res[i];
+		res->flags = IORESOURCE_MEM;
+		res->start += base;
+		res->end += base;
+
+		target = ocelot_regmap_init(ocelot, res);
+		if (IS_ERR(target)) {
+			dev_err(ocelot->dev,
+				"Failed to map device memory space\n");
+			return PTR_ERR(target);
+		}
+
+		ocelot->targets[i] = target;
+	}
+
+	err = ocelot_regfields_init(ocelot, felix_regfields);
+	if (err) {
+		dev_err(ocelot->dev, "failed to init reg fields map\n");
+		return err;
+	}
+
+	for (port = 0; port < num_phys_ports; port++) {
+		struct ocelot_port *ocelot_port;
+		void __iomem *port_regs;
+		struct resource *res;
+
+		ocelot_port = devm_kzalloc(ocelot->dev,
+					   sizeof(struct ocelot_port),
+					   GFP_KERNEL);
+		if (!ocelot_port) {
+			dev_err(ocelot->dev,
+				"failed to allocate port memory\n");
+			return -ENOMEM;
+		}
+
+		res = &felix->info->port_io_res[port];
+		res->flags = IORESOURCE_MEM;
+		res->start += base;
+		res->end += base;
+
+		port_regs = devm_ioremap_resource(ocelot->dev, res);
+		if (IS_ERR(port_regs)) {
+			dev_err(ocelot->dev,
+				"failed to map registers for port %d\n", port);
+			return PTR_ERR(port_regs);
+		}
+
+		ocelot_port->ocelot = ocelot;
+		ocelot_port->regs = port_regs;
+		ocelot->ports[port] = ocelot_port;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/dsa/vitesse/felix.c b/drivers/net/dsa/vitesse/felix.c
new file mode 100644
index 000000000000..0f433971335a
--- /dev/null
+++ b/drivers/net/dsa/vitesse/felix.c
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019 NXP Semiconductors
+ */
+#include <uapi/linux/if_bridge.h>
+#include <soc/mscc/ocelot.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/of.h>
+#include <net/dsa.h>
+#include "felix.h"
+
+static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds,
+						    int port)
+{
+	return DSA_TAG_PROTO_NONE;
+}
+
+static int felix_set_ageing_time(struct dsa_switch *ds,
+				 unsigned int ageing_time)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	ocelot_set_ageing_time(ocelot, ageing_time);
+
+	return 0;
+}
+
+static void felix_adjust_link(struct dsa_switch *ds, int port,
+			      struct phy_device *phydev)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	ocelot_adjust_link(ocelot, port, phydev);
+}
+
+static int felix_fdb_dump(struct dsa_switch *ds, int port,
+			  dsa_fdb_dump_cb_t *cb, void *data)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	return ocelot_fdb_dump(ocelot, port, cb, data);
+}
+
+static int felix_fdb_add(struct dsa_switch *ds, int port,
+			 const unsigned char *addr, u16 vid)
+{
+	struct ocelot *ocelot = ds->priv;
+	bool vlan_aware;
+
+	vlan_aware = dsa_port_is_vlan_filtering(dsa_to_port(ds, port));
+
+	return ocelot_fdb_add(ocelot, port, addr, vid, vlan_aware);
+}
+
+static int felix_fdb_del(struct dsa_switch *ds, int port,
+			 const unsigned char *addr, u16 vid)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	return ocelot_fdb_del(ocelot, port, addr, vid);
+}
+
+static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port,
+				       u8 state)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	return ocelot_bridge_stp_state_set(ocelot, port, state);
+}
+
+static int felix_bridge_join(struct dsa_switch *ds, int port,
+			     struct net_device *br)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	return ocelot_port_bridge_join(ocelot, port, br);
+}
+
+static void felix_bridge_leave(struct dsa_switch *ds, int port,
+			       struct net_device *br)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	ocelot_port_bridge_leave(ocelot, port, br);
+}
+
+/* This callback needs to be present */
+static int felix_vlan_prepare(struct dsa_switch *ds, int port,
+			      const struct switchdev_obj_port_vlan *vlan)
+{
+	return 0;
+}
+
+static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	ocelot_port_vlan_filtering(ocelot, port, enabled);
+
+	return 0;
+}
+
+static void felix_vlan_add(struct dsa_switch *ds, int port,
+			   const struct switchdev_obj_port_vlan *vlan)
+{
+	struct ocelot *ocelot = ds->priv;
+	u16 vid;
+	int err;
+
+	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
+		err = ocelot_vlan_add(ocelot, port, vid,
+				      vlan->flags & BRIDGE_VLAN_INFO_PVID,
+				      vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
+		if (err) {
+			dev_err(ds->dev, "Failed to add VLAN %d to port %d: %d\n",
+				vid, port, err);
+			return;
+		}
+	}
+}
+
+static int felix_vlan_del(struct dsa_switch *ds, int port,
+			  const struct switchdev_obj_port_vlan *vlan)
+{
+	struct ocelot *ocelot = ds->priv;
+	u16 vid;
+	int err;
+
+	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
+		err = ocelot_vlan_del(ocelot, port, vid);
+		if (err) {
+			dev_err(ds->dev, "Failed to remove VLAN %d from port %d: %d\n",
+				vid, port, err);
+			return err;
+		}
+	}
+	return 0;
+}
+
+static int felix_port_enable(struct dsa_switch *ds, int port,
+			     struct phy_device *phy)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	ocelot_port_enable(ocelot, port, phy);
+
+	return 0;
+}
+
+static void felix_port_disable(struct dsa_switch *ds, int port)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	return ocelot_port_disable(ocelot, port);
+}
+
+static void felix_get_strings(struct dsa_switch *ds, int port,
+			      u32 stringset, u8 *data)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	return ocelot_get_strings(ocelot, port, stringset, data);
+}
+
+static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	ocelot_get_ethtool_stats(ocelot, port, data);
+}
+
+static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	return ocelot_get_sset_count(ocelot, port, sset);
+}
+
+static int felix_get_ts_info(struct dsa_switch *ds, int port,
+			     struct ethtool_ts_info *info)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	return ocelot_get_ts_info(ocelot, port, info);
+}
+
+/* Hardware initialization done here so that we can allocate structures with
+ * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing
+ * us to allocate structures twice (leak memory) and map PCI memory twice
+ * (which will not work).
+ */
+static int felix_setup(struct dsa_switch *ds)
+{
+	struct ocelot *ocelot = ds->priv;
+	struct felix *felix = ocelot_to_felix(ocelot);
+	int port, err;
+
+	err = felix_init_structs(felix, ds->num_ports);
+	if (err)
+		return err;
+
+	ocelot_init(ocelot);
+
+	for (port = 0; port < ds->num_ports; port++)
+		ocelot_init_port(ocelot, port);
+
+	/* Set the CPU port as one of the non-NPI ports, so that the switch
+	 * is dumb for now and passes untagged traffic to/from the CPU.
+	 */
+	ocelot_set_cpu_port(ocelot, ds->num_ports,
+			    OCELOT_TAG_PREFIX_NONE,
+			    OCELOT_TAG_PREFIX_NONE);
+
+	return 0;
+}
+
+static void felix_teardown(struct dsa_switch *ds)
+{
+	struct ocelot *ocelot = ds->priv;
+
+	/* stop workqueue thread */
+	ocelot_deinit(ocelot);
+}
+
+static const struct dsa_switch_ops felix_switch_ops = {
+	.get_tag_protocol	= felix_get_tag_protocol,
+	.setup			= felix_setup,
+	.teardown		= felix_teardown,
+	.set_ageing_time	= felix_set_ageing_time,
+	.get_strings		= felix_get_strings,
+	.get_ethtool_stats	= felix_get_ethtool_stats,
+	.get_sset_count		= felix_get_sset_count,
+	.get_ts_info		= felix_get_ts_info,
+	.adjust_link		= felix_adjust_link,
+	.port_enable		= felix_port_enable,
+	.port_disable		= felix_port_disable,
+	.port_fdb_dump		= felix_fdb_dump,
+	.port_fdb_add		= felix_fdb_add,
+	.port_fdb_del		= felix_fdb_del,
+	.port_bridge_join	= felix_bridge_join,
+	.port_bridge_leave	= felix_bridge_leave,
+	.port_stp_state_set	= felix_bridge_stp_state_set,
+	.port_vlan_prepare	= felix_vlan_prepare,
+	.port_vlan_filtering	= felix_vlan_filtering,
+	.port_vlan_add		= felix_vlan_add,
+	.port_vlan_del		= felix_vlan_del,
+};
+
+static struct felix_info *felix_instance_tbl[] = {
+	[FELIX_INSTANCE_LS1028A] = &felix_info_ls1028a,
+};
+
+static int felix_pci_probe(struct pci_dev *pdev,
+			   const struct pci_device_id *id)
+{
+	enum felix_instance instance = id->driver_data;
+	struct dsa_switch *ds;
+	struct ocelot *ocelot;
+	struct felix *felix;
+	int err;
+
+	err = pci_enable_device(pdev);
+	if (err) {
+		dev_err(&pdev->dev, "device enable failed\n");
+		goto err_pci_enable;
+	}
+
+	/* set up for high or low dma */
+	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
+	if (err) {
+		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+		if (err) {
+			dev_err(&pdev->dev,
+				"DMA configuration failed: 0x%x\n", err);
+			goto err_dma;
+		}
+	}
+
+	felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
+	if (!felix) {
+		err = -ENOMEM;
+		dev_err(&pdev->dev, "Failed to allocate driver memory\n");
+		goto err_alloc_felix;
+	}
+
+	pci_set_drvdata(pdev, felix);
+	ocelot = &felix->ocelot;
+	ocelot->dev = &pdev->dev;
+	felix->pdev = pdev;
+	felix->info = felix_instance_tbl[instance];
+
+	pci_set_master(pdev);
+
+	ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
+	if (!ds) {
+		err = -ENOMEM;
+		dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
+		goto err_alloc_ds;
+	}
+
+	ds->dev = &pdev->dev;
+	ds->num_ports = felix->info->num_ports;
+	ds->ops = &felix_switch_ops;
+	ds->priv = ocelot;
+	felix->ds = ds;
+
+	err = dsa_register_switch(ds);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
+		goto err_register_ds;
+	}
+
+	return 0;
+
+err_register_ds:
+	kfree(ds);
+err_alloc_ds:
+err_alloc_felix:
+	kfree(felix);
+err_dma:
+	pci_disable_device(pdev);
+err_pci_enable:
+	return err;
+}
+
+static void felix_pci_remove(struct pci_dev *pdev)
+{
+	struct felix *felix;
+
+	felix = pci_get_drvdata(pdev);
+
+	dsa_unregister_switch(felix->ds);
+
+	kfree(felix->ds);
+	kfree(felix);
+
+	pci_disable_device(pdev);
+}
+
+static struct pci_device_id felix_ids[] = {
+	{
+		PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
+		.driver_data = FELIX_INSTANCE_LS1028A,
+	},
+	{ 0, }
+};
+MODULE_DEVICE_TABLE(pci, felix_ids);
+
+static struct pci_driver felix_pci_driver = {
+	.name		= KBUILD_MODNAME,
+	.id_table	= felix_ids,
+	.probe		= felix_pci_probe,
+	.remove		= felix_pci_remove,
+};
+
+module_pci_driver(felix_pci_driver);
+
+MODULE_DESCRIPTION("Felix Switch driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/net/dsa/vitesse/felix.h b/drivers/net/dsa/vitesse/felix.h
new file mode 100644
index 000000000000..05209e1c415d
--- /dev/null
+++ b/drivers/net/dsa/vitesse/felix.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2019 NXP Semiconductors
+ */
+#ifndef _MSCC_FELIX_H
+#define _MSCC_FELIX_H
+
+#define ocelot_to_felix(o)		container_of((o), struct felix, ocelot)
+
+enum felix_instance {
+	FELIX_INSTANCE_LS1028A		= 0,
+};
+
+struct felix_info {
+	struct resource			*target_io_res;
+	struct resource			*port_io_res;
+	const u32 *const		*map;
+	const struct ocelot_ops		*ops;
+	int				shared_queue_sz;
+	const struct ocelot_stat_layout	*stats_layout;
+	unsigned int			num_stats;
+	int				num_ports;
+	int				pci_bar;
+};
+
+struct felix {
+	struct dsa_switch		*ds;
+	struct pci_dev			*pdev;
+	struct felix_info		*info;
+	struct ocelot			ocelot;
+};
+
+extern struct felix_info		felix_info_ls1028a;
+
+int felix_init_structs(struct felix *felix, int num_phys_ports);
+
+#endif
-- 
2.17.1

[PATCH net-next 12/12] net: dsa: vitesse: add tagger for Ocelot/Felix switches

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

While it is entirely possible that this tagger format is in fact more
generic than just these 2 switch families, I don't have that knowledge.
The Seville switch in NXP T1040 has a similar frame format, but there
are enough differences (e.g. DEST field starts at bit 57 instead of 56)
that calling this file tag_vitesse.c is a bit of a stretch at the
moment. The frame format has been listed in a comment so that people who
add support for further Vitesse switches can rework this tagger while
keeping compatibility with Felix.

The "ocelot" name was chosen instead of "felix" because even the Ocelot
switch can act as a DSA device when it is used in NPI mode, and the Felix
tagger format is almost identical. Currently it is only used for the
Felix switch embedded in the NXP LS1028A chip.

The ABI for this tagger should be considered "not stable" at the moment.
The DSA tag is always placed before the Ethernet header and therefore,
we are using the long prefix for RX tags to avoid putting the DSA master
port in promiscuous mode. Once there will be an API in DSA for drivers
to request DSA masters to be in promiscuous mode unconditionally, we
will switch to the "no prefix" extraction frame header, which will save
16 padding bytes for each RX frame.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 MAINTAINERS                     |   1 +
 drivers/net/dsa/vitesse/Kconfig |   1 +
 drivers/net/dsa/vitesse/felix.c |  15 +--
 include/net/dsa.h               |   2 +
 net/dsa/Kconfig                 |   7 +
 net/dsa/Makefile                |   1 +
 net/dsa/tag_ocelot.c            | 229 ++++++++++++++++++++++++++++++++
 7 files changed, 248 insertions(+), 8 deletions(-)
 create mode 100644 net/dsa/tag_ocelot.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 486300903366..e86c4199a52f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17365,6 +17365,7 @@ M:	Claudiu Manoil <claudiu.manoil@nxp.com>
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/dsa/vitesse/felix*
+F:	net/dsa/tag_ocelot.c
 
 VIVID VIRTUAL VIDEO DRIVER
 M:	Hans Verkuil <hverkuil@xs4all.nl>
diff --git a/drivers/net/dsa/vitesse/Kconfig b/drivers/net/dsa/vitesse/Kconfig
index ca47c55f9733..e3b82a8db4b7 100644
--- a/drivers/net/dsa/vitesse/Kconfig
+++ b/drivers/net/dsa/vitesse/Kconfig
@@ -3,6 +3,7 @@ config NET_DSA_VITESSE_FELIX
 	tristate "Felix Ethernet switch support"
 	depends on NET_DSA && PCI
 	select MSCC_OCELOT_SWITCH
+	select NET_DSA_TAG_OCELOT
 	help
 	  This driver supports the Felix (VSC9959) network switch, which is a
 	  variant of the Vitesse Ocelot switch core that is embedded as a PCIe
diff --git a/drivers/net/dsa/vitesse/felix.c b/drivers/net/dsa/vitesse/felix.c
index 0f433971335a..e2439e9a1a12 100644
--- a/drivers/net/dsa/vitesse/felix.c
+++ b/drivers/net/dsa/vitesse/felix.c
@@ -12,7 +12,7 @@
 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds,
 						    int port)
 {
-	return DSA_TAG_PROTO_NONE;
+	return DSA_TAG_PROTO_OCELOT;
 }
 
 static int felix_set_ageing_time(struct dsa_switch *ds,
@@ -201,15 +201,14 @@ static int felix_setup(struct dsa_switch *ds)
 
 	ocelot_init(ocelot);
 
-	for (port = 0; port < ds->num_ports; port++)
+	for (port = 0; port < ds->num_ports; port++) {
 		ocelot_init_port(ocelot, port);
 
-	/* Set the CPU port as one of the non-NPI ports, so that the switch
-	 * is dumb for now and passes untagged traffic to/from the CPU.
-	 */
-	ocelot_set_cpu_port(ocelot, ds->num_ports,
-			    OCELOT_TAG_PREFIX_NONE,
-			    OCELOT_TAG_PREFIX_NONE);
+		if (port == dsa_upstream_port(ds, port))
+			ocelot_set_cpu_port(ocelot, port,
+					    OCELOT_TAG_PREFIX_NONE,
+					    OCELOT_TAG_PREFIX_LONG);
+	}
 
 	return 0;
 }
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 9507611a41f0..6767dc3f66c0 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -42,6 +42,7 @@ struct phylink_link_state;
 #define DSA_TAG_PROTO_8021Q_VALUE		12
 #define DSA_TAG_PROTO_SJA1105_VALUE		13
 #define DSA_TAG_PROTO_KSZ8795_VALUE		14
+#define DSA_TAG_PROTO_OCELOT_VALUE		15
 
 enum dsa_tag_protocol {
 	DSA_TAG_PROTO_NONE		= DSA_TAG_PROTO_NONE_VALUE,
@@ -59,6 +60,7 @@ enum dsa_tag_protocol {
 	DSA_TAG_PROTO_8021Q		= DSA_TAG_PROTO_8021Q_VALUE,
 	DSA_TAG_PROTO_SJA1105		= DSA_TAG_PROTO_SJA1105_VALUE,
 	DSA_TAG_PROTO_KSZ8795		= DSA_TAG_PROTO_KSZ8795_VALUE,
+	DSA_TAG_PROTO_OCELOT		= DSA_TAG_PROTO_OCELOT_VALUE,
 };
 
 struct packet_type;
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index 29e2bd5cc5af..fd9ef19a9581 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -67,6 +67,13 @@ config NET_DSA_TAG_EDSA
 	  Say Y or M if you want to enable support for tagging frames for the
 	  Marvell switches which use EtherType DSA headers.
 
+config NET_DSA_TAG_OCELOT
+	tristate "Tag driver for Vitesse Ocelot/Felix switch"
+	select PACKING
+	help
+	  Say Y or M if you want to enable support for tagging frames with the
+	  Vitesse Ocelot (VSC7514) and Felix (VSC9959) switching cores.
+
 config NET_DSA_TAG_MTK
 	tristate "Tag driver for Mediatek switches"
 	help
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
index 2c6d286f0511..9a482c38bdb1 100644
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_NET_DSA_TAG_GSWIP) += tag_gswip.o
 obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
 obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
 obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
+obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
 obj-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
 obj-$(CONFIG_NET_DSA_TAG_SJA1105) += tag_sja1105.o
 obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o
diff --git a/net/dsa/tag_ocelot.c b/net/dsa/tag_ocelot.c
new file mode 100644
index 000000000000..078d4790669d
--- /dev/null
+++ b/net/dsa/tag_ocelot.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019 NXP Semiconductors
+ */
+#include <soc/mscc/ocelot.h>
+#include <linux/packing.h>
+#include "dsa_priv.h"
+
+/* The CPU injection header and the CPU extraction header can have 3 types of
+ * prefixes: long, short and no prefix. The format of the header itself is the
+ * same in all 3 cases.
+ *
+ * Extraction with long prefix:
+ *
+ * +-------------------+-------------------+------+------+------------+-------+
+ * | ff:ff:ff:ff:ff:ff | ff:ff:ff:ff:ff:ff | 8880 | 000a | extraction | frame |
+ * |                   |                   |      |      |   header   |       |
+ * +-------------------+-------------------+------+------+------------+-------+
+ *        48 bits             48 bits      16 bits 16 bits  128 bits
+ *
+ * Extraction with short prefix:
+ *
+ *                                         +------+------+------------+-------+
+ *                                         | 8880 | 000a | extraction | frame |
+ *                                         |      |      |   header   |       |
+ *                                         +------+------+------------+-------+
+ *                                         16 bits 16 bits  128 bits
+ *
+ * Extraction with no prefix:
+ *
+ *                                                       +------------+-------+
+ *                                                       | extraction | frame |
+ *                                                       |   header   |       |
+ *                                                       +------------+-------+
+ *                                                          128 bits
+ *
+ *
+ * Injection with long prefix:
+ *
+ * +-------------------+-------------------+------+------+------------+-------+
+ * |      any dmac     |      any smac     | 8880 | 000a | injection  | frame |
+ * |                   |                   |      |      |   header   |       |
+ * +-------------------+-------------------+------+------+------------+-------+
+ *        48 bits             48 bits      16 bits 16 bits  128 bits
+ *
+ * Injection with short prefix:
+ *
+ *                                         +------+------+------------+-------+
+ *                                         | 8880 | 000a | injection  | frame |
+ *                                         |      |      |   header   |       |
+ *                                         +------+------+------------+-------+
+ *                                         16 bits 16 bits  128 bits
+ *
+ * Injection with no prefix:
+ *
+ *                                                       +------------+-------+
+ *                                                       | injection  | frame |
+ *                                                       |   header   |       |
+ *                                                       +------------+-------+
+ *                                                          128 bits
+ *
+ * The injection header looks like this (network byte order, bit 127
+ * is part of lowest address byte in memory, bit 0 is part of highest
+ * address byte):
+ *
+ *         +------+------+------+------+------+------+------+------+
+ * 127:120 |BYPASS| MASQ |          MASQ_PORT        |REW_OP|REW_OP|
+ *         +------+------+------+------+------+------+------+------+
+ * 119:112 |                         REW_OP                        |
+ *         +------+------+------+------+------+------+------+------+
+ * 111:104 |                         REW_VAL                       |
+ *         +------+------+------+------+------+------+------+------+
+ * 103: 96 |                         REW_VAL                       |
+ *         +------+------+------+------+------+------+------+------+
+ *  95: 88 |                         REW_VAL                       |
+ *         +------+------+------+------+------+------+------+------+
+ *  87: 80 |                         REW_VAL                       |
+ *         +------+------+------+------+------+------+------+------+
+ *  79: 72 |                          RSV                          |
+ *         +------+------+------+------+------+------+------+------+
+ *  71: 64 |            RSV            |           DEST            |
+ *         +------+------+------+------+------+------+------+------+
+ *  63: 56 |                         DEST                          |
+ *         +------+------+------+------+------+------+------+------+
+ *  55: 48 |                          RSV                          |
+ *         +------+------+------+------+------+------+------+------+
+ *  47: 40 |  RSV |         SRC_PORT          |     RSV     |TFRM_TIMER|
+ *         +------+------+------+------+------+------+------+------+
+ *  39: 32 |     TFRM_TIMER     |               RSV                |
+ *         +------+------+------+------+------+------+------+------+
+ *  31: 24 |  RSV |  DP  |   POP_CNT   |           CPUQ            |
+ *         +------+------+------+------+------+------+------+------+
+ *  23: 16 |           CPUQ            |      QOS_CLASS     |TAG_TYPE|
+ *         +------+------+------+------+------+------+------+------+
+ *  15:  8 |         PCP        |  DEI |            VID            |
+ *         +------+------+------+------+------+------+------+------+
+ *   7:  0 |                          VID                          |
+ *         +------+------+------+------+------+------+------+------+
+ *
+ * And the extraction header looks like this:
+ *
+ *         +------+------+------+------+------+------+------+------+
+ * 127:120 |  RSV |                  REW_OP                        |
+ *         +------+------+------+------+------+------+------+------+
+ * 119:112 |       REW_OP       |              REW_VAL             |
+ *         +------+------+------+------+------+------+------+------+
+ * 111:104 |                         REW_VAL                       |
+ *         +------+------+------+------+------+------+------+------+
+ * 103: 96 |                         REW_VAL                       |
+ *         +------+------+------+------+------+------+------+------+
+ *  95: 88 |                         REW_VAL                       |
+ *         +------+------+------+------+------+------+------+------+
+ *  87: 80 |       REW_VAL      |               LLEN               |
+ *         +------+------+------+------+------+------+------+------+
+ *  79: 72 | LLEN |                      WLEN                      |
+ *         +------+------+------+------+------+------+------+------+
+ *  71: 64 | WLEN |                      RSV                       |
+ *         +------+------+------+------+------+------+------+------+
+ *  63: 56 |                          RSV                          |
+ *         +------+------+------+------+------+------+------+------+
+ *  55: 48 |                          RSV                          |
+ *         +------+------+------+------+------+------+------+------+
+ *  47: 40 | RSV  |          SRC_PORT         |       ACL_ID       |
+ *         +------+------+------+------+------+------+------+------+
+ *  39: 32 |       ACL_ID       |  RSV |         SFLOW_ID          |
+ *         +------+------+------+------+------+------+------+------+
+ *  31: 24 |ACL_HIT| DP  |  LRN_FLAGS  |           CPUQ            |
+ *         +------+------+------+------+------+------+------+------+
+ *  23: 16 |           CPUQ            |      QOS_CLASS     |TAG_TYPE|
+ *         +------+------+------+------+------+------+------+------+
+ *  15:  8 |         PCP        |  DEI |            VID            |
+ *         +------+------+------+------+------+------+------+------+
+ *   7:  0 |                          VID                          |
+ *         +------+------+------+------+------+------+------+------+
+ */
+
+static struct sk_buff *ocelot_xmit(struct sk_buff *skb,
+				   struct net_device *netdev)
+{
+	struct dsa_port *dp = dsa_slave_to_port(netdev);
+	u64 bypass, dest, src, qos_class;
+	struct dsa_switch *ds = dp->ds;
+	int port = dp->index;
+	u8 *injection;
+
+	if (unlikely(skb_cow_head(skb, OCELOT_TAG_LEN) < 0)) {
+		netdev_err(netdev, "Cannot make room for tag.\n");
+		return NULL;
+	}
+
+	injection = skb_push(skb, OCELOT_TAG_LEN);
+
+	memset(injection, 0, OCELOT_TAG_LEN);
+
+	src = dsa_upstream_port(ds, port);
+	dest = BIT(port);
+	bypass = true;
+	qos_class = skb->priority;
+
+	packing(injection, &bypass,   127, 127, OCELOT_TAG_LEN, PACK, 0);
+	packing(injection, &dest,      68,  56, OCELOT_TAG_LEN, PACK, 0);
+	packing(injection, &src,       46,  43, OCELOT_TAG_LEN, PACK, 0);
+	packing(injection, &qos_class, 19,  17, OCELOT_TAG_LEN, PACK, 0);
+
+	return skb;
+}
+
+static struct sk_buff *ocelot_rcv(struct sk_buff *skb,
+				  struct net_device *netdev,
+				  struct packet_type *pt)
+{
+	u64 src_port, qos_class;
+	u8 *start = skb->data;
+	u8 *extraction;
+
+	/* Revert skb->data by the amount consumed by the DSA master,
+	 * so it points to the beginning of the frame.
+	 */
+	skb_push(skb, ETH_HLEN);
+	/* We don't care about the long prefix, it is just for easy entrance
+	 * into the DSA master's RX filter. Discard it now by moving it into
+	 * the headroom.
+	 */
+	skb_pull(skb, OCELOT_LONG_PREFIX_LEN);
+	/* And skb->data now points to the extraction frame header.
+	 * Keep a pointer to it.
+	 */
+	extraction = skb->data;
+	/* Now the EFH is part of the headroom as well */
+	skb_pull(skb, OCELOT_TAG_LEN);
+	/* Reset the pointer to the real MAC header */
+	skb_reset_mac_header(skb);
+	skb_reset_mac_len(skb);
+	/* And move skb->data to the correct location again */
+	skb_pull(skb, ETH_HLEN);
+
+	/* Remove from inet csum the extraction header */
+	skb_postpull_rcsum(skb, start, OCELOT_LONG_PREFIX_LEN + OCELOT_TAG_LEN);
+
+	packing(extraction, &src_port,  46, 43, OCELOT_TAG_LEN, UNPACK, 0);
+	packing(extraction, &qos_class, 19, 17, OCELOT_TAG_LEN, UNPACK, 0);
+
+	skb->dev = dsa_master_find_slave(netdev, 0, src_port);
+	if (!skb->dev)
+		/* The switch will reflect back some frames sent through
+		 * sockets opened on the bare DSA master. These will come back
+		 * with src_port equal to the index of the CPU port, for which
+		 * there is no slave registered. So don't print any error
+		 * message here (ignore and drop those frames).
+		 */
+		return NULL;
+
+	skb->offload_fwd_mark = 1;
+	skb->priority = qos_class;
+
+	return skb;
+}
+
+static struct dsa_device_ops ocelot_netdev_ops = {
+	.name			= "ocelot",
+	.proto			= DSA_TAG_PROTO_OCELOT,
+	.xmit			= ocelot_xmit,
+	.rcv			= ocelot_rcv,
+	.overhead		= OCELOT_TAG_LEN + OCELOT_LONG_PREFIX_LEN,
+};
+
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_OCELOT);
+
+module_dsa_tag_driver(ocelot_netdev_ops);
-- 
2.17.1

Re: [PATCH net-next 12/12] net: dsa: vitesse: add tagger for Ocelot/Felix switches

[Florian Fainelli]

On 11/12/19 4:44 AM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> While it is entirely possible that this tagger format is in fact more
> generic than just these 2 switch families, I don't have that knowledge.
> The Seville switch in NXP T1040 has a similar frame format, but there
> are enough differences (e.g. DEST field starts at bit 57 instead of 56)
> that calling this file tag_vitesse.c is a bit of a stretch at the
> moment. The frame format has been listed in a comment so that people who
> add support for further Vitesse switches can rework this tagger while
> keeping compatibility with Felix.
> 
> The "ocelot" name was chosen instead of "felix" because even the Ocelot
> switch can act as a DSA device when it is used in NPI mode, and the Felix
> tagger format is almost identical. Currently it is only used for the
> Felix switch embedded in the NXP LS1028A chip.
> 
> The ABI for this tagger should be considered "not stable" at the moment.
> The DSA tag is always placed before the Ethernet header and therefore,
> we are using the long prefix for RX tags to avoid putting the DSA master
> port in promiscuous mode. Once there will be an API in DSA for drivers
> to request DSA masters to be in promiscuous mode unconditionally, we
> will switch to the "no prefix" extraction frame header, which will save
> 16 padding bytes for each RX frame.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH net-next 12/12] net: dsa: vitesse: add tagger for Ocelot/Felix switches

[Andrew Lunn]

> --- a/drivers/net/dsa/vitesse/felix.c
> +++ b/drivers/net/dsa/vitesse/felix.c
> @@ -12,7 +12,7 @@
>  static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds,
>  						    int port)
>  {
> -	return DSA_TAG_PROTO_NONE;
> +	return DSA_TAG_PROTO_OCELOT;
>  }

I would swap the order of these and the previous patch so you can
avoid this.

> --- a/net/dsa/Kconfig
> +++ b/net/dsa/Kconfig
> @@ -67,6 +67,13 @@ config NET_DSA_TAG_EDSA
>  	  Say Y or M if you want to enable support for tagging frames for the
>  	  Marvell switches which use EtherType DSA headers.
>  
> +config NET_DSA_TAG_OCELOT
> +	tristate "Tag driver for Vitesse Ocelot/Felix switch"
> +	select PACKING
> +	help
> +	  Say Y or M if you want to enable support for tagging frames with the
> +	  Vitesse Ocelot (VSC7514) and Felix (VSC9959) switching cores.
> +
>  config NET_DSA_TAG_MTK
>  	tristate "Tag driver for Mediatek switches"
>  	help

This file is sorted so that the tristate strings appear in alphabetic
order when you do make menuconfig. This mean this entry to too early, and
NXP SJA1105 so too late. :-(

    Andrew