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From: Richard Henderson <richard.henderson@linaro.org>
To: "Rémi Denis-Courmont" <remi@remlab.net>, qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org, remi.denis.courmont@huawei.com
Subject: Re: [PATCH 1/3] target/arm: keep translation start level unsigned
Date: Thu, 31 Dec 2020 08:43:15 -0800	[thread overview]
Message-ID: <1b14279c-f620-5c03-b25c-a52fa370cc8e@linaro.org> (raw)
In-Reply-To: <9468010.vzF1F9XyNR@philogene>

On 12/31/20 1:59 AM, Rémi Denis-Courmont wrote:
> Le jeudi 31 décembre 2020, 00:38:14 EET Richard Henderson a écrit :
>> On 12/30/20 2:10 PM, Richard Henderson wrote:
>>> On 12/18/20 6:33 AM, remi.denis.courmont@huawei.com wrote:
>>>> From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
>>>>
>>>> Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
>>>> ---
>>>>
>>>>  target/arm/helper.c | 14 ++++++--------
>>>>  1 file changed, 6 insertions(+), 8 deletions(-)
>>>
>>> The patch does more than what is described above.
>>>
>>>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>>>> index df195c314c..b927e53ab0 100644
>>>> --- a/target/arm/helper.c
>>>> +++ b/target/arm/helper.c
>>>>
>>>> @@ -10821,17 +10821,12 @@ do_fault:
>>>>   * Returns true if the suggested S2 translation parameters are OK and
>>>>   * false otherwise.
>>>>   */
>>>>
>>>> -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
>>>> +static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint32_t
>>>> level,
>>>>
>>>>                                 int inputsize, int stride)
>>>>  
>>>>  {
>>>>  
>>>>      const int grainsize = stride + 3;
>>>>      int startsizecheck;
>>>>
>>>> -    /* Negative levels are never allowed.  */
>>>> -    if (level < 0) {
>>>> -        return false;
>>>> -    }
>>>> -
>>>
>>> I would expect this to be the only hunk from the patch description. 
>>> Probably changing this negative check to a >= 3 check.
>>
>> Having read the next patch, I think you should drop this type change.
>>
>>>> @@ -11203,7 +11201,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
>>>> uint64_t address,>> 
>>>>          if (!aarch64 || stride == 9) {
>>>>          
>>>>              /* AArch32 or 4KB pages */
>>>>
>>>> -            startlevel = 2 - sl0;
>>>> +            startlevel = (2 - sl0) & 3;
>>
>> This hunk belongs with the next patch, implementing TTST, and should be
>> conditional.  I.e.
>>
>>     if (stride == 9) {
>>         startlevel = 2 - sl0;
>>         if (aarch64 &&
>>             cpu_isar_feature(aa64_st, env_archcpu(env)) {
>>             startlevel &= 3;
>>         }
> 
> You can do that but:
> 1) Nothing in the spec says that SL0 == b11 without ST means start level -1. 
> It's undefined, and I don't see any reasons to treat it differently than with 
> ST.

By that logic there's no reason to treat it differently at all; you could drop
the feature check entirely.  In lieu, -1 makes a decent error indicator.

> 2) Functionally, checking for ST seems to belong naturally within 
> check_s2_mmu_setup() in this particular case.

I guess.  I'll leave it to Peter's preference.


r~


  reply	other threads:[~2020-12-31 16:45 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-18 14:32 [RFC][PATCH 0/3] ARMv8.4-TTST extension Rémi Denis-Courmont
2020-12-18 14:33 ` [PATCH 1/3] target/arm: keep translation start level unsigned remi.denis.courmont
2020-12-30 22:10   ` Richard Henderson
2020-12-30 22:38     ` Richard Henderson
2020-12-31  9:59       ` Rémi Denis-Courmont
2020-12-31 16:43         ` Richard Henderson [this message]
2021-01-07 19:55           ` Peter Maydell
2020-12-31  9:55     ` Rémi Denis-Courmont
2020-12-31 16:54       ` Richard Henderson
2020-12-18 14:33 ` [PATCH 2/3] target/arm: ARMv8.4-TTST extension remi.denis.courmont
2020-12-30 22:36   ` Richard Henderson
2020-12-18 14:33 ` [PATCH 3/3] target/arm: enable Small Translation tables in max CPU remi.denis.courmont
2020-12-30 22:37   ` Richard Henderson

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