From: remi.denis.courmont@huawei.com
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: [PATCH 2/3] target/arm: ARMv8.4-TTST extension
Date: Fri, 18 Dec 2020 16:33:20 +0200 [thread overview]
Message-ID: <20201218143321.102872-2-remi.denis.courmont@huawei.com> (raw)
In-Reply-To: <7884934.NyiUUSuA9g@basile.remlab.net>
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
This adds for the Small Translation tables extension in AArch64 state.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
---
target/arm/cpu.h | 5 +++++
target/arm/helper.c | 13 ++++++++++---
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 39abb2a36b..604b9cdd0e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3991,6 +3991,11 @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
}
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
+}
+
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b927e53ab0..c3a186db35 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10851,7 +10851,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint32_t level,
if (level == 0 && pamax <= 42) {
return false;
}
- if (level == 3) {
+ if (level == 3 && !cpu_isar_feature(aa64_st, cpu)) {
return false;
}
break;
@@ -10946,7 +10946,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
{
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
bool epd, hpd, using16k, using64k;
- int select, tsz, tbi;
+ int select, tsz, tbi, max_tsz;
if (!regime_has_2_ranges(mmu_idx)) {
select = 0;
@@ -10981,7 +10981,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
hpd = extract64(tcr, 42, 1);
}
}
- tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
+
+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
+ max_tsz = 48 - using64k;
+ } else {
+ max_tsz = 39;
+ }
+
+ tsz = MIN(tsz, max_tsz);
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
/* Present TBI as a composite with TBID. */
--
2.29.2
next prev parent reply other threads:[~2020-12-18 14:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-18 14:32 [RFC][PATCH 0/3] ARMv8.4-TTST extension Rémi Denis-Courmont
2020-12-18 14:33 ` [PATCH 1/3] target/arm: keep translation start level unsigned remi.denis.courmont
2020-12-30 22:10 ` Richard Henderson
2020-12-30 22:38 ` Richard Henderson
2020-12-31 9:59 ` Rémi Denis-Courmont
2020-12-31 16:43 ` Richard Henderson
2021-01-07 19:55 ` Peter Maydell
2020-12-31 9:55 ` Rémi Denis-Courmont
2020-12-31 16:54 ` Richard Henderson
2020-12-18 14:33 ` remi.denis.courmont [this message]
2020-12-30 22:36 ` [PATCH 2/3] target/arm: ARMv8.4-TTST extension Richard Henderson
2020-12-18 14:33 ` [PATCH 3/3] target/arm: enable Small Translation tables in max CPU remi.denis.courmont
2020-12-30 22:37 ` Richard Henderson
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