From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, beata.michalska@linaro.org
Subject: [Qemu-devel] [PATCH for-4.2 20/24] target/arm: Flush tlbs for E2&0 translation regime
Date: Fri, 19 Jul 2019 14:03:22 -0700 [thread overview]
Message-ID: <20190719210326.15466-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190719210326.15466-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 22eb056b27..fe022f51d6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3915,8 +3915,11 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
static int vae1_tlbmask(CPUARMState *env)
{
+ /* Since we exclude secure first, we may read HCR_EL2 directly. */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0;
+ } else if (env->cp15.hcr_el2 & HCR_E2H) {
+ return ARMMMUIdxBit_E2 | ARMMMUIdxBit_E0;
} else {
return ARMMMUIdxBit_E1 | ARMMMUIdxBit_E0;
}
@@ -3954,7 +3957,12 @@ static int vmalle1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) {
- return ARMMMUIdxBit_E1 | ARMMMUIdxBit_E0 | ARMMMUIdxBit_Stage2;
+ /* Since we exclude secure first, we may read HCR_EL2 directly. */
+ if (env->cp15.hcr_el2 & HCR_E2H) {
+ return ARMMMUIdxBit_E2 | ARMMMUIdxBit_E0;
+ } else {
+ return ARMMMUIdxBit_E1 | ARMMMUIdxBit_E0 | ARMMMUIdxBit_Stage2;
+ }
} else {
return ARMMMUIdxBit_E1 | ARMMMUIdxBit_E0;
}
@@ -3969,13 +3977,22 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx(cs, mask);
}
+static int vae2_tlbmask(CPUARMState *env)
+{
+ if (arm_hcr_el2_eff(env) & HCR_E2H) {
+ return ARMMMUIdxBit_E0 | ARMMMUIdxBit_E2;
+ } else {
+ return ARMMMUIdxBit_E2;
+ }
+}
+
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vae2_tlbmask(env);
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx(cs, mask);
}
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4000,8 +4017,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
+ int mask = vae2_tlbmask(env);
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4019,11 +4037,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
* Currently handles both VAE2 and VALE2, since we don't support
* flush-last-level-only.
*/
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vae2_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.17.1
next prev parent reply other threads:[~2019-07-19 21:30 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-19 21:03 [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 01/24] cputlb: Add tlb_set_asid_for_mmuidx Richard Henderson
2019-07-22 9:53 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 02/24] cputlb: Add tlb_flush_asid_by_mmuidx and friends Richard Henderson
2019-07-22 10:04 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 03/24] target/arm: Install ASIDs for long-form from EL1 Richard Henderson
2019-07-22 15:28 ` Alex Bennée
2019-07-22 15:48 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 04/24] target/arm: Install ASIDs for short-form " Richard Henderson
2019-07-24 11:47 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 05/24] target/arm: Install ASIDs for EL2 Richard Henderson
2019-07-24 11:49 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 06/24] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-07-24 12:59 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 07/24] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-07-24 13:01 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 08/24] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-07-24 13:57 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 09/24] target/arm: Add TTBR1_EL2 Richard Henderson
2019-07-24 14:12 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-07-24 14:47 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 11/24] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-07-24 20:05 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 12/24] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-07-25 14:01 ` Alex Bennée
2019-07-25 14:24 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 13/24] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-07-25 14:02 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 14/24] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-07-25 14:08 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 15/24] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-07-25 15:57 ` Alex Bennée
2019-07-25 18:18 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 16/24] target/arm: Add regime_has_2_ranges Richard Henderson
2019-07-25 15:59 ` Alex Bennée
2019-07-25 18:28 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 17/24] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-07-25 16:01 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 18/24] target/arm: Update arm_sctlr " Richard Henderson
2019-07-25 16:02 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 19/24] target/arm: Install asids for E2&0 translation regime Richard Henderson
2019-07-19 21:03 ` Richard Henderson [this message]
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 21/24] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 22/24] target/arm: Update regime_is_user for EL2&0 Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 23/24] target/arm: Update {fp, sve}_exception_el for VHE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 24/24] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-07-22 7:31 ` [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE Alex Bennée
2019-07-22 9:37 ` Alex Bennée
2019-07-22 15:10 ` Richard Henderson
2019-07-25 16:15 ` Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190719210326.15466-21-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=beata.michalska@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).