From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, beata.michalska@linaro.org
Subject: Re: [Qemu-devel] [PATCH for-4.2 13/24] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask
Date: Thu, 25 Jul 2019 15:02:36 +0100 [thread overview]
Message-ID: <87zhl2yzyb.fsf@linaro.org> (raw)
In-Reply-To: <20190719210326.15466-14-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> No functional change, but unify code sequences.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/helper.c | 118 ++++++++++++++------------------------------
> 1 file changed, 37 insertions(+), 81 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 9a9809ff4f..7adbf51479 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3901,70 +3901,61 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
> * Page D4-1736 (DDI0487A.b)
> */
>
> +static int vae1_tlbmask(CPUARMState *env)
> +{
> + if (arm_is_secure_below_el3(env)) {
> + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
> + } else {
> + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
> + }
> +}
> +
> static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> CPUState *cs = env_cpu(env);
> - bool sec = arm_is_secure_below_el3(env);
> + int mask = vae1_tlbmask(env);
>
> - if (sec) {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
> }
>
> static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> CPUState *cs = env_cpu(env);
> + int mask = vae1_tlbmask(env);
>
> if (tlb_force_broadcast(env)) {
> tlbi_aa64_vmalle1is_write(env, NULL, value);
> return;
> }
>
> + tlb_flush_by_mmuidx(cs, mask);
> +}
> +
> +static int vmalle1_tlbmask(CPUARMState *env)
> +{
> + /*
> + * Note that the 'ALL' scope must invalidate both stage 1 and
> + * stage 2 translations, whereas most other scopes only invalidate
> + * stage 1 translations.
> + */
> if (arm_is_secure_below_el3(env)) {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
> + } else if (arm_feature(env, ARM_FEATURE_EL2)) {
> + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;
> } else {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
> }
> }
>
> static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - /* Note that the 'ALL' scope must invalidate both stage 1 and
> - * stage 2 translations, whereas most other scopes only invalidate
> - * stage 1 translations.
> - */
> - ARMCPU *cpu = env_archcpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> + int mask = vmalle1_tlbmask(env);
>
> - if (arm_is_secure_below_el3(env)) {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else {
> - if (arm_feature(env, ARM_FEATURE_EL2)) {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0 |
> - ARMMMUIdxBit_S2NS);
> - } else {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> - }
> + tlb_flush_by_mmuidx(cs, mask);
> }
>
> static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3988,28 +3979,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - /* Note that the 'ALL' scope must invalidate both stage 1 and
> - * stage 2 translations, whereas most other scopes only invalidate
> - * stage 1 translations.
> - */
> CPUState *cs = env_cpu(env);
> - bool sec = arm_is_secure_below_el3(env);
> - bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
> + int mask = vmalle1_tlbmask(env);
>
> - if (sec) {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else if (has_el2) {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0 |
> - ARMMMUIdxBit_S2NS);
> - } else {
> - tlb_flush_by_mmuidx_all_cpus_synced(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
> }
>
> static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -4059,20 +4032,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = env_archcpu(env);
> - CPUState *cs = CPU(cpu);
> - bool sec = arm_is_secure_below_el3(env);
> + CPUState *cs = env_cpu(env);
> + int mask = vae1_tlbmask(env);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> - if (sec) {
> - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else {
> - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
> }
>
> static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -4083,8 +4047,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> * since we don't support flush-for-specific-ASID-only or
> * flush-last-level-only.
> */
> - ARMCPU *cpu = env_archcpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> + int mask = vae1_tlbmask(env);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> if (tlb_force_broadcast(env)) {
> @@ -4092,15 +4056,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> return;
> }
>
> - if (arm_is_secure_below_el3(env)) {
> - tlb_flush_page_by_mmuidx(cs, pageaddr,
> - ARMMMUIdxBit_S1SE1 |
> - ARMMMUIdxBit_S1SE0);
> - } else {
> - tlb_flush_page_by_mmuidx(cs, pageaddr,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0);
> - }
> + tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
> }
>
> static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
Alex Bennée
next prev parent reply other threads:[~2019-07-25 14:02 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-19 21:03 [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 01/24] cputlb: Add tlb_set_asid_for_mmuidx Richard Henderson
2019-07-22 9:53 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 02/24] cputlb: Add tlb_flush_asid_by_mmuidx and friends Richard Henderson
2019-07-22 10:04 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 03/24] target/arm: Install ASIDs for long-form from EL1 Richard Henderson
2019-07-22 15:28 ` Alex Bennée
2019-07-22 15:48 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 04/24] target/arm: Install ASIDs for short-form " Richard Henderson
2019-07-24 11:47 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 05/24] target/arm: Install ASIDs for EL2 Richard Henderson
2019-07-24 11:49 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 06/24] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-07-24 12:59 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 07/24] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-07-24 13:01 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 08/24] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-07-24 13:57 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 09/24] target/arm: Add TTBR1_EL2 Richard Henderson
2019-07-24 14:12 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-07-24 14:47 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 11/24] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-07-24 20:05 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 12/24] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-07-25 14:01 ` Alex Bennée
2019-07-25 14:24 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 13/24] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-07-25 14:02 ` Alex Bennée [this message]
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 14/24] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-07-25 14:08 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 15/24] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-07-25 15:57 ` Alex Bennée
2019-07-25 18:18 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 16/24] target/arm: Add regime_has_2_ranges Richard Henderson
2019-07-25 15:59 ` Alex Bennée
2019-07-25 18:28 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 17/24] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-07-25 16:01 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 18/24] target/arm: Update arm_sctlr " Richard Henderson
2019-07-25 16:02 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 19/24] target/arm: Install asids for E2&0 translation regime Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 20/24] target/arm: Flush tlbs " Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 21/24] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 22/24] target/arm: Update regime_is_user for EL2&0 Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 23/24] target/arm: Update {fp, sve}_exception_el for VHE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 24/24] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-07-22 7:31 ` [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE Alex Bennée
2019-07-22 9:37 ` Alex Bennée
2019-07-22 15:10 ` Richard Henderson
2019-07-25 16:15 ` Alex Bennée
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