From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, beata.michalska@linaro.org
Subject: Re: [Qemu-devel] [PATCH for-4.2 14/24] target/arm: Simplify tlb_force_broadcast alternatives
Date: Thu, 25 Jul 2019 15:08:03 +0100 [thread overview]
Message-ID: <87y30myzp8.fsf@linaro.org> (raw)
In-Reply-To: <20190719210326.15466-15-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> Rather than call to a separate function and re-compute any
> parameters for the flush, simply use the correct flush
> function directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.c | 52 +++++++++++++++++++++------------------------
> 1 file changed, 24 insertions(+), 28 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 7adbf51479..2b95fc763f 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -626,56 +626,54 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Invalidate all (TLBIALL) */
> - ARMCPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
>
> if (tlb_force_broadcast(env)) {
> - tlbiall_is_write(env, NULL, value);
> - return;
> + tlb_flush_all_cpus_synced(cs);
> + } else {
> + tlb_flush(cs);
> }
> -
> - tlb_flush(CPU(cpu));
> }
>
> static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
> - ARMCPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
>
> + value &= TARGET_PAGE_MASK;
I'm fairly sure this is superfluous (we certainly mask pages in the
cputlb code, don't know if we do at the translation end).
> if (tlb_force_broadcast(env)) {
> - tlbimva_is_write(env, NULL, value);
> - return;
> + tlb_flush_page_all_cpus_synced(cs, value);
> + } else {
> + tlb_flush_page(cs, value);
> }
> -
> - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
> }
>
> static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Invalidate by ASID (TLBIASID) */
> - ARMCPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
>
> if (tlb_force_broadcast(env)) {
> - tlbiasid_is_write(env, NULL, value);
> - return;
> + tlb_flush_all_cpus_synced(cs);
> + } else {
> + tlb_flush(cs);
> }
> -
> - tlb_flush(CPU(cpu));
> }
>
> static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
> - ARMCPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
>
> + value &= TARGET_PAGE_MASK;
> if (tlb_force_broadcast(env)) {
> - tlbimvaa_is_write(env, NULL, value);
> - return;
> + tlb_flush_page_all_cpus_synced(cs, value);
> + } else {
> + tlb_flush_page(cs, value);
> }
> -
> - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
> }
>
> static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3926,11 +3924,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> int mask = vae1_tlbmask(env);
>
> if (tlb_force_broadcast(env)) {
> - tlbi_aa64_vmalle1is_write(env, NULL, value);
> - return;
> + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
> + } else {
> + tlb_flush_by_mmuidx(cs, mask);
> }
> -
> - tlb_flush_by_mmuidx(cs, mask);
> }
>
> static int vmalle1_tlbmask(CPUARMState *env)
> @@ -4052,11 +4049,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> if (tlb_force_broadcast(env)) {
> - tlbi_aa64_vae1is_write(env, NULL, value);
> - return;
> + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
> + } else {
> + tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
> }
> -
> - tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
> }
>
> static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
Anyway:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
next prev parent reply other threads:[~2019-07-25 14:08 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-19 21:03 [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 01/24] cputlb: Add tlb_set_asid_for_mmuidx Richard Henderson
2019-07-22 9:53 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 02/24] cputlb: Add tlb_flush_asid_by_mmuidx and friends Richard Henderson
2019-07-22 10:04 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 03/24] target/arm: Install ASIDs for long-form from EL1 Richard Henderson
2019-07-22 15:28 ` Alex Bennée
2019-07-22 15:48 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 04/24] target/arm: Install ASIDs for short-form " Richard Henderson
2019-07-24 11:47 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 05/24] target/arm: Install ASIDs for EL2 Richard Henderson
2019-07-24 11:49 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 06/24] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-07-24 12:59 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 07/24] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-07-24 13:01 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 08/24] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-07-24 13:57 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 09/24] target/arm: Add TTBR1_EL2 Richard Henderson
2019-07-24 14:12 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-07-24 14:47 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 11/24] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-07-24 20:05 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 12/24] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-07-25 14:01 ` Alex Bennée
2019-07-25 14:24 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 13/24] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-07-25 14:02 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 14/24] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-07-25 14:08 ` Alex Bennée [this message]
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 15/24] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-07-25 15:57 ` Alex Bennée
2019-07-25 18:18 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 16/24] target/arm: Add regime_has_2_ranges Richard Henderson
2019-07-25 15:59 ` Alex Bennée
2019-07-25 18:28 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 17/24] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-07-25 16:01 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 18/24] target/arm: Update arm_sctlr " Richard Henderson
2019-07-25 16:02 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 19/24] target/arm: Install asids for E2&0 translation regime Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 20/24] target/arm: Flush tlbs " Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 21/24] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 22/24] target/arm: Update regime_is_user for EL2&0 Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 23/24] target/arm: Update {fp, sve}_exception_el for VHE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 24/24] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-07-22 7:31 ` [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE Alex Bennée
2019-07-22 9:37 ` Alex Bennée
2019-07-22 15:10 ` Richard Henderson
2019-07-25 16:15 ` Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87y30myzp8.fsf@linaro.org \
--to=alex.bennee@linaro.org \
--cc=beata.michalska@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).