From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, beata.michalska@linaro.org
Subject: [Qemu-devel] [PATCH for-4.2 02/24] cputlb: Add tlb_flush_asid_by_mmuidx and friends
Date: Fri, 19 Jul 2019 14:03:04 -0700 [thread overview]
Message-ID: <20190719210326.15466-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190719210326.15466-1-richard.henderson@linaro.org>
Since we have remembered ASIDs, we can further minimize flushing
by comparing against the one we want to flush.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 16 +++++++++++++
include/qom/cpu.h | 1 +
accel/tcg/cputlb.c | 51 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 68 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 9c77aa5bf9..0d890e1e60 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -240,6 +240,22 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
*/
void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid,
uint16_t idxmap, uint16_t dep_idxmap);
+/**
+ * tlb_flush_asid_by_mmuidx:
+ * @cpu: Originating CPU of the flush
+ * @asid: Address Space Identifier
+ * @idxmap: bitmap of MMU indexes to flush if asid matches
+ *
+ * For each mmu index, if @asid matches the value previously saved via
+ * tlb_set_asid_for_mmuidx, flush the index.
+ */
+void tlb_flush_asid_by_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap);
+/* Similarly, broadcasting to all cpus. */
+void tlb_flush_asid_by_mmuidx_all_cpus(CPUState *cpu, uint32_t asid,
+ uint16_t idxmap);
+/* Similarly, waiting for the broadcast to complete. */
+void tlb_flush_asid_by_mmuidx_all_cpus_synced(CPUState *cpu, uint32_t asid,
+ uint16_t idxmap);
/**
* tlb_set_page_with_attrs:
* @cpu: CPU to add this TLB entry for
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 5ee0046b62..4ae6ea3e1d 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -283,6 +283,7 @@ struct hax_vcpu_state;
typedef union {
int host_int;
unsigned long host_ulong;
+ uint64_t host_uint64;
void *host_ptr;
vaddr target_ptr;
} run_on_cpu_data;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index c68f57755b..3ef68a11bf 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -540,6 +540,57 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr)
tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS);
}
+static void tlb_flush_asid_by_mmuidx_async_work(CPUState *cpu,
+ run_on_cpu_data data)
+{
+ CPUTLB *tlb = cpu_tlb(cpu);
+ uint32_t asid = data.host_uint64;
+ uint16_t idxmap = data.host_uint64 >> 32;
+ uint16_t to_flush = 0, work;
+
+ assert_cpu_is_self(cpu);
+
+ for (work = idxmap; work != 0; work &= work - 1) {
+ int mmu_idx = ctz32(work);
+ if (tlb->d[mmu_idx].asid == asid) {
+ to_flush |= 1 << mmu_idx;
+ }
+ }
+
+ if (to_flush) {
+ tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(to_flush));
+ }
+}
+
+void tlb_flush_asid_by_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap)
+{
+ run_on_cpu_data data = { .host_uint64 = deposit64(asid, 32, 32, idxmap) };
+
+ if (cpu->created && !qemu_cpu_is_self(cpu)) {
+ async_run_on_cpu(cpu, tlb_flush_asid_by_mmuidx_async_work, data);
+ } else {
+ tlb_flush_asid_by_mmuidx_async_work(cpu, data);
+ }
+}
+
+void tlb_flush_asid_by_mmuidx_all_cpus(CPUState *src_cpu,
+ uint32_t asid, uint16_t idxmap)
+{
+ run_on_cpu_data data = { .host_uint64 = deposit64(asid, 32, 32, idxmap) };
+
+ flush_all_helper(src_cpu, tlb_flush_asid_by_mmuidx_async_work, data);
+ tlb_flush_asid_by_mmuidx_async_work(src_cpu, data);
+}
+
+void tlb_flush_asid_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
+ uint32_t asid, uint16_t idxmap)
+{
+ run_on_cpu_data data = { .host_uint64 = deposit64(asid, 32, 32, idxmap) };
+
+ flush_all_helper(src_cpu, tlb_flush_asid_by_mmuidx_async_work, data);
+ async_safe_run_on_cpu(src_cpu, tlb_flush_asid_by_mmuidx_async_work, data);
+}
+
void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap,
uint16_t depmap)
{
--
2.17.1
next prev parent reply other threads:[~2019-07-19 21:04 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-19 21:03 [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 01/24] cputlb: Add tlb_set_asid_for_mmuidx Richard Henderson
2019-07-22 9:53 ` Alex Bennée
2019-07-19 21:03 ` Richard Henderson [this message]
2019-07-22 10:04 ` [Qemu-devel] [PATCH for-4.2 02/24] cputlb: Add tlb_flush_asid_by_mmuidx and friends Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 03/24] target/arm: Install ASIDs for long-form from EL1 Richard Henderson
2019-07-22 15:28 ` Alex Bennée
2019-07-22 15:48 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 04/24] target/arm: Install ASIDs for short-form " Richard Henderson
2019-07-24 11:47 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 05/24] target/arm: Install ASIDs for EL2 Richard Henderson
2019-07-24 11:49 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 06/24] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-07-24 12:59 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 07/24] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-07-24 13:01 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 08/24] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-07-24 13:57 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 09/24] target/arm: Add TTBR1_EL2 Richard Henderson
2019-07-24 14:12 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-07-24 14:47 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 11/24] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-07-24 20:05 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 12/24] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-07-25 14:01 ` Alex Bennée
2019-07-25 14:24 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 13/24] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-07-25 14:02 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 14/24] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-07-25 14:08 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 15/24] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-07-25 15:57 ` Alex Bennée
2019-07-25 18:18 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 16/24] target/arm: Add regime_has_2_ranges Richard Henderson
2019-07-25 15:59 ` Alex Bennée
2019-07-25 18:28 ` Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 17/24] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-07-25 16:01 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 18/24] target/arm: Update arm_sctlr " Richard Henderson
2019-07-25 16:02 ` Alex Bennée
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 19/24] target/arm: Install asids for E2&0 translation regime Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 20/24] target/arm: Flush tlbs " Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 21/24] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 22/24] target/arm: Update regime_is_user for EL2&0 Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 23/24] target/arm: Update {fp, sve}_exception_el for VHE Richard Henderson
2019-07-19 21:03 ` [Qemu-devel] [PATCH for-4.2 24/24] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-07-22 7:31 ` [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE Alex Bennée
2019-07-22 9:37 ` Alex Bennée
2019-07-22 15:10 ` Richard Henderson
2019-07-25 16:15 ` Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190719210326.15466-3-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=beata.michalska@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).