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* [PULL 00/18] riscv-to-apply queue
@ 2020-08-25 18:48 Alistair Francis
  2020-08-25 18:48 ` [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT Alistair Francis
                   ` (19 more replies)
  0 siblings, 20 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-25 18:48 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, alistair.francis

The following changes since commit 7774e403f2ac58b3e87bfe8d2f77676501ba893e:

  Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging (2020-08-25 10:54:51 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200825

for you to fetch changes up to e39a8320b088dd5efc9ebaafe387e52b3d962665:

  target/riscv: Support the Virtual Instruction fault (2020-08-25 09:11:36 -0700)

----------------------------------------------------------------
This pull request first adds support for multi-socket NUMA RISC-V
machines. The Spike and Virt machines both support NUMA sockets.

This PR also updates the current experimental Hypervisor support to the
v0.6.1 spec.

----------------------------------------------------------------
Alistair Francis (13):
      target/riscv: Allow setting a two-stage lookup in the virt status
      target/riscv: Allow generating hlv/hlvx/hsv instructions
      target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
      target/riscv: Don't allow guest to write to htinst
      target/riscv: Convert MSTATUS MTL to GVA
      target/riscv: Fix the interrupt cause code
      target/riscv: Update the Hypervisor trap return/entry
      target/riscv: Update the CSRs to the v0.6 Hyp extension
      target/riscv: Only support a single VSXL length
      target/riscv: Only support little endian guests
      target/riscv: Support the v0.6 Hypervisor extension CRSs
      target/riscv: Return the exception from invalid CSR accesses
      target/riscv: Support the Virtual Instruction fault

Anup Patel (5):
      hw/riscv: Allow creating multiple instances of CLINT
      hw/riscv: Allow creating multiple instances of PLIC
      hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
      hw/riscv: spike: Allow creating multiple NUMA sockets
      hw/riscv: virt: Allow creating multiple NUMA sockets

 include/hw/riscv/numa.h                 | 113 +++++++
 include/hw/riscv/sifive_clint.h         |   7 +-
 include/hw/riscv/sifive_plic.h          |  12 +-
 include/hw/riscv/spike.h                |  11 +-
 include/hw/riscv/virt.h                 |   9 +-
 target/riscv/cpu.h                      |   2 +
 target/riscv/cpu_bits.h                 |  25 +-
 target/riscv/helper.h                   |   4 +
 target/riscv/insn32-64.decode           |   5 +
 target/riscv/insn32.decode              |  11 +
 hw/riscv/numa.c                         | 242 +++++++++++++++
 hw/riscv/sifive_clint.c                 |  20 +-
 hw/riscv/sifive_e.c                     |   4 +-
 hw/riscv/sifive_plic.c                  |  24 +-
 hw/riscv/sifive_u.c                     |   4 +-
 hw/riscv/spike.c                        | 232 +++++++++-----
 hw/riscv/virt.c                         | 526 ++++++++++++++++++--------------
 target/riscv/cpu_helper.c               | 123 ++++----
 target/riscv/csr.c                      | 171 +++++++++--
 target/riscv/op_helper.c                | 176 ++++++++++-
 target/riscv/translate.c                |  10 -
 hw/riscv/meson.build                    |   1 +
 target/riscv/insn_trans/trans_rvh.c.inc | 342 ++++++++++++++++++++-
 23 files changed, 1630 insertions(+), 444 deletions(-)
 create mode 100644 include/hw/riscv/numa.h
 create mode 100644 hw/riscv/numa.c


^ permalink raw reply	[flat|nested] 32+ messages in thread
end of thread, other threads:[~2021-08-12 14:58 UTC | newest]

Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-25 18:48 [PULL 00/18] riscv-to-apply queue Alistair Francis
2020-08-25 18:48 ` [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT Alistair Francis
2020-08-25 18:48 ` [PULL 02/18] hw/riscv: Allow creating multiple instances of PLIC Alistair Francis
2020-08-25 18:48 ` [PULL 03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines Alistair Francis
2020-08-25 18:48 ` [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets Alistair Francis
2020-08-25 18:48 ` [PULL 05/18] hw/riscv: virt: " Alistair Francis
2021-08-09  9:46   ` Peter Maydell
2021-08-12 14:57     ` Peter Maydell
2020-08-25 18:48 ` [PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status Alistair Francis
2020-08-25 18:48 ` [PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions Alistair Francis
2020-08-25 18:48 ` [PULL 08/18] target/riscv: Do two-stage lookups on " Alistair Francis
2020-08-25 18:48 ` [PULL 09/18] target/riscv: Don't allow guest to write to htinst Alistair Francis
2020-08-25 18:48 ` [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA Alistair Francis
2020-08-25 18:48 ` [PULL 11/18] target/riscv: Fix the interrupt cause code Alistair Francis
2020-08-25 18:48 ` [PULL 12/18] target/riscv: Update the Hypervisor trap return/entry Alistair Francis
2020-08-25 18:48 ` [PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension Alistair Francis
2020-08-25 18:48 ` [PULL 14/18] target/riscv: Only support a single VSXL length Alistair Francis
2020-08-25 18:48 ` [PULL 15/18] target/riscv: Only support little endian guests Alistair Francis
2020-08-25 18:48 ` [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs Alistair Francis
2020-08-25 18:48 ` [PULL 17/18] target/riscv: Return the exception from invalid CSR accesses Alistair Francis
2020-08-25 18:48 ` [PULL 18/18] target/riscv: Support the Virtual Instruction fault Alistair Francis
2020-08-25 21:24 ` [PULL 00/18] riscv-to-apply queue Peter Maydell
2020-08-25 21:21   ` Alistair Francis
2020-08-25 21:49     ` Peter Maydell
2020-08-25 22:30       ` Alistair Francis
2020-08-26  3:21         ` Bin Meng
2020-08-26  9:25           ` Peter Maydell
2020-08-26 10:06             ` Bin Meng
2020-08-27 15:44               ` Alistair Francis
2020-08-29 15:49         ` LIU Zhiwei
2020-08-29 17:30           ` Alistair Francis
2020-08-26  9:28 ` Peter Maydell

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