From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH 11/38] target/riscv: SIMD 8-bit Multiply Instructions
Date: Fri, 12 Feb 2021 23:02:29 +0800 [thread overview]
Message-ID: <20210212150256.885-12-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 7 ++
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvp.c.inc | 8 +++
target/riscv/packed_helper.c | 93 +++++++++++++++++++++++++
4 files changed, 115 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index bc60712bd9..6bb601b436 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1221,3 +1221,10 @@ DEF_HELPER_3(umul16, i64, env, tl, tl)
DEF_HELPER_3(umulx16, i64, env, tl, tl)
DEF_HELPER_3(khm16, tl, env, tl, tl)
DEF_HELPER_3(khmx16, tl, env, tl, tl)
+
+DEF_HELPER_3(smul8, i64, env, tl, tl)
+DEF_HELPER_3(smulx8, i64, env, tl, tl)
+DEF_HELPER_3(umul8, i64, env, tl, tl)
+DEF_HELPER_3(umulx8, i64, env, tl, tl)
+DEF_HELPER_3(khm8, tl, env, tl, tl)
+DEF_HELPER_3(khmx8, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 38519a477c..9d165efba9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -688,3 +688,10 @@ umul16 1011000 ..... ..... 000 ..... 1111111 @r
umulx16 1011001 ..... ..... 000 ..... 1111111 @r
khm16 1000011 ..... ..... 000 ..... 1111111 @r
khmx16 1001011 ..... ..... 000 ..... 1111111 @r
+
+smul8 1010100 ..... ..... 000 ..... 1111111 @r
+smulx8 1010101 ..... ..... 000 ..... 1111111 @r
+umul8 1011100 ..... ..... 000 ..... 1111111 @r
+umulx8 1011101 ..... ..... 000 ..... 1111111 @r
+khm8 1000111 ..... ..... 000 ..... 1111111 @r
+khmx8 1001111 ..... ..... 000 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 7e5bf9041d..336f3418b1 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -436,3 +436,11 @@ GEN_RVP_R_D64_OOL(umul16);
GEN_RVP_R_D64_OOL(umulx16);
GEN_RVP_R_OOL(khm16);
GEN_RVP_R_OOL(khmx16);
+
+/* SIMD 8-bit Multiply Instructions */
+GEN_RVP_R_D64_OOL(smul8);
+GEN_RVP_R_D64_OOL(smulx8);
+GEN_RVP_R_D64_OOL(umul8);
+GEN_RVP_R_D64_OOL(umulx8);
+GEN_RVP_R_OOL(khm8);
+GEN_RVP_R_OOL(khmx8);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 13fed2c4d1..56baefeb8e 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -827,3 +827,96 @@ static inline void do_khmx16(CPURISCVState *env, void *vd, void *va,
}
RVPR(khmx16, 2, 2);
+
+/* SIMD 8-bit Multiply Instructions */
+static inline void do_smul8(CPURISCVState *env, void *vd, void *va, void *vb)
+{
+ int16_t *d = vd;
+ int8_t *a = va, *b = vb;
+ d[H2(0)] = (int16_t)a[H1(0)] * b[H1(0)];
+ d[H2(1)] = (int16_t)a[H1(1)] * b[H1(1)];
+ d[H2(2)] = (int16_t)a[H1(2)] * b[H1(2)];
+ d[H2(3)] = (int16_t)a[H1(3)] * b[H1(3)];
+}
+
+RVPR64(smul8);
+
+static inline void do_smulx8(CPURISCVState *env, void *vd, void *va, void *vb)
+{
+ int16_t *d = vd;
+ int8_t *a = va, *b = vb;
+ d[H2(0)] = (int16_t)a[H1(0)] * b[H1(1)];
+ d[H2(1)] = (int16_t)a[H1(1)] * b[H1(0)];
+ d[H2(2)] = (int16_t)a[H1(2)] * b[H1(3)];
+ d[H2(3)] = (int16_t)a[H1(3)] * b[H1(2)];
+}
+
+RVPR64(smulx8);
+
+static inline void do_umul8(CPURISCVState *env, void *vd, void *va, void *vb)
+{
+ uint16_t *d = vd;
+ uint8_t *a = va, *b = vb;
+ d[H2(0)] = (uint16_t)a[H1(0)] * b[H1(0)];
+ d[H2(1)] = (uint16_t)a[H1(1)] * b[H1(1)];
+ d[H2(2)] = (uint16_t)a[H1(2)] * b[H1(2)];
+ d[H2(3)] = (uint16_t)a[H1(3)] * b[H1(3)];
+}
+
+RVPR64(umul8);
+
+static inline void do_umulx8(CPURISCVState *env, void *vd, void *va, void *vb)
+{
+ uint16_t *d = vd;
+ uint8_t *a = va, *b = vb;
+ d[H2(0)] = (uint16_t)a[H1(0)] * b[H1(1)];
+ d[H2(1)] = (uint16_t)a[H1(1)] * b[H1(0)];
+ d[H2(2)] = (uint16_t)a[H1(2)] * b[H1(3)];
+ d[H2(3)] = (uint16_t)a[H1(3)] * b[H1(2)];
+}
+
+RVPR64(umulx8);
+
+static inline void do_khm8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va, *b = vb;
+
+ if (a[i] == INT8_MIN && b[i] == INT8_MIN) {
+ env->vxsat = 1;
+ d[i] = INT8_MAX;
+ } else {
+ d[i] = (int16_t)a[i] * b[i] >> 7;
+ }
+}
+
+RVPR(khm8, 1, 1);
+
+static inline void do_khmx8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va, *b = vb;
+ /*
+ * t[x] = ra.B[x] s* rb.B[y];
+ * rt.B[x] = SAT.Q7(t[x] s>> 7);
+ *
+ * (RV32: (x,y)=(3,2),(2,3),
+ * (1,0),(0,1),
+ * (RV64: (x,y)=(7,6),(6,7),(5,4),(4,5),
+ * (3,2),(2,3),(1,0),(0,1))
+ */
+ if (a[H1(i)] == INT8_MIN && b[H1(i + 1)] == INT8_MIN) {
+ env->vxsat = 1;
+ d[H1(i)] = INT8_MAX;
+ } else {
+ d[H1(i)] = (int16_t)a[H1(i)] * b[H1(i + 1)] >> 7;
+ }
+ if (a[H1(i + 1)] == INT8_MIN && b[H1(i)] == INT8_MIN) {
+ env->vxsat = 1;
+ d[H1(i + 1)] = INT8_MAX;
+ } else {
+ d[H1(i + 1)] = (int16_t)a[H1(i + 1)] * b[H1(i)] >> 7;
+ }
+}
+
+RVPR(khmx8, 2, 1);
--
2.17.1
next prev parent reply other threads:[~2021-02-12 15:34 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei [this message]
2021-03-15 21:33 ` [PATCH 11/38] target/riscv: SIMD 8-bit " Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
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