From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions
Date: Fri, 12 Feb 2021 23:02:48 +0800 [thread overview]
Message-ID: <20210212150256.885-31-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 9 ++
target/riscv/insn32-64.decode | 15 ++++
target/riscv/insn_trans/trans_rvp.c.inc | 16 ++++
target/riscv/packed_helper.c | 104 ++++++++++++++++++++++++
4 files changed, 144 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 0ade207de6..673bc4f628 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1425,4 +1425,13 @@ DEF_HELPER_3(rstsa32, tl, env, tl, tl)
DEF_HELPER_3(urstsa32, tl, env, tl, tl)
DEF_HELPER_3(kstsa32, tl, env, tl, tl)
DEF_HELPER_3(ukstsa32, tl, env, tl, tl)
+
+DEF_HELPER_3(sra32, tl, env, tl, tl)
+DEF_HELPER_3(sra32_u, tl, env, tl, tl)
+DEF_HELPER_3(srl32, tl, env, tl, tl)
+DEF_HELPER_3(srl32_u, tl, env, tl, tl)
+DEF_HELPER_3(sll32, tl, env, tl, tl)
+DEF_HELPER_3(ksll32, tl, env, tl, tl)
+DEF_HELPER_3(kslra32, tl, env, tl, tl)
+DEF_HELPER_3(kslra32_u, tl, env, tl, tl)
#endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 66eec1a44a..6f0f2923ca 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -114,3 +114,18 @@ rstsa32 1011001 ..... ..... 010 ..... 1111111 @r
urstsa32 1101001 ..... ..... 010 ..... 1111111 @r
kstsa32 1100001 ..... ..... 010 ..... 1111111 @r
ukstsa32 1110001 ..... ..... 010 ..... 1111111 @r
+
+sra32 0101000 ..... ..... 010 ..... 1111111 @r
+sra32_u 0110000 ..... ..... 010 ..... 1111111 @r
+srai32 0111000 ..... ..... 010 ..... 1111111 @sh5
+srai32_u 1000000 ..... ..... 010 ..... 1111111 @sh5
+srl32 0101001 ..... ..... 010 ..... 1111111 @r
+srl32_u 0110001 ..... ..... 010 ..... 1111111 @r
+srli32 0111001 ..... ..... 010 ..... 1111111 @sh5
+srli32_u 1000001 ..... ..... 010 ..... 1111111 @sh5
+sll32 0101010 ..... ..... 010 ..... 1111111 @r
+slli32 0111010 ..... ..... 010 ..... 1111111 @sh5
+ksll32 0110010 ..... ..... 010 ..... 1111111 @r
+kslli32 1000010 ..... ..... 010 ..... 1111111 @sh5
+kslra32 0101011 ..... ..... 010 ..... 1111111 @r
+kslra32_u 0110011 ..... ..... 010 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index ea673b3aca..e52f268a57 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1156,4 +1156,20 @@ GEN_RVP_R_OOL(rstsa32);
GEN_RVP_R_OOL(urstsa32);
GEN_RVP_R_OOL(kstsa32);
GEN_RVP_R_OOL(ukstsa32);
+
+/* (RV64 Only) SIMD 32-bit Shift Instructions */
+GEN_RVP_SHIFT(sra32, tcg_gen_gvec_sars, 2);
+GEN_RVP_SHIFTI(srai32, sra32, NULL);
+GEN_RVP_R_OOL(sra32_u);
+GEN_RVP_SHIFTI(srai32_u, sra32_u, NULL);
+GEN_RVP_SHIFT(srl32, tcg_gen_gvec_shrs, 2);
+GEN_RVP_SHIFTI(srli32, srl32, NULL);
+GEN_RVP_R_OOL(srl32_u);
+GEN_RVP_SHIFTI(srli32_u, srl32_u, NULL);
+GEN_RVP_SHIFT(sll32, tcg_gen_gvec_shls, 2);
+GEN_RVP_SHIFTI(slli32, sll32, NULL);
+GEN_RVP_R_OOL(ksll32);
+GEN_RVP_SHIFTI(kslli32, ksll32, NULL);
+GEN_RVP_R_OOL(kslra32);
+GEN_RVP_R_OOL(kslra32_u);
#endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index bb56933c39..c168c51eff 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3273,4 +3273,108 @@ static inline void do_ukstsa32(CPURISCVState *env, void *vd, void *va,
}
RVPR(ukstsa32, 2, 4);
+
+/* (RV64 Only) SIMD 32-bit Shift Instructions */
+static inline void do_sra32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x1f;
+ d[i] = a[i] >> shift;
+}
+
+RVPR(sra32, 1, 4);
+
+static inline void do_srl32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint32_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x1f;
+ d[i] = a[i] >> shift;
+}
+
+RVPR(srl32, 1, 4);
+
+static inline void do_sll32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint32_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x1f;
+ d[i] = a[i] << shift;
+}
+
+RVPR(sll32, 1, 4);
+
+static inline void do_sra32_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x1f;
+
+ d[i] = vssra32(env, 0, a[i], shift);
+}
+
+RVPR(sra32_u, 1, 4);
+
+static inline void do_srl32_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint32_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x1f;
+
+ d[i] = vssrl32(env, 0, a[i], shift);
+}
+
+RVPR(srl32_u, 1, 4);
+
+static inline void do_ksll32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va, result;
+ uint8_t shift = *(uint8_t *)vb & 0x1f;
+
+ result = a[i] << shift;
+ if (shift > clrsb32(a[i])) {
+ env->vxsat = 0x1;
+ d[i] = (a[i] & INT32_MIN) ? INT32_MIN : INT32_MAX;
+ } else {
+ d[i] = result;
+ }
+}
+
+RVPR(ksll32, 1, 4);
+
+static inline void do_kslra32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint32_t *d = vd, *a = va;
+ int32_t shift = sextract32((*(uint32_t *)vb), 0, 6);
+
+ if (shift >= 0) {
+ do_ksll32(env, vd, va, vb, i);
+ } else {
+ shift = -shift;
+ shift = (shift == 32) ? 31 : shift;
+ d[i] = a[i] >> shift;
+ }
+}
+
+RVPR(kslra32, 1, 4);
+
+static inline void do_kslra32_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint32_t *d = vd, *a = va;
+ int32_t shift = sextract32((*(uint32_t *)vb), 0, 6);
+
+ if (shift >= 0) {
+ do_ksll32(env, vd, va, vb, i);
+ } else {
+ shift = -shift;
+ shift = (shift == 32) ? 31 : shift;
+ d[i] = vssra32(env, 0, a[i], shift);
+ }
+}
+
+RVPR(kslra32_u, 1, 4);
#endif
--
2.17.1
next prev parent reply other threads:[~2021-02-12 16:10 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei [this message]
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
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