From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions
Date: Fri, 12 Feb 2021 23:02:44 +0800 [thread overview]
Message-ID: <20210212150256.885-27-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 15 ++
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvp.c.inc | 17 ++
target/riscv/packed_helper.c | 214 ++++++++++++++++++++++++
4 files changed, 262 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index fdfd3177db..a6f62295e9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1366,3 +1366,18 @@ DEF_HELPER_3(khmbt, tl, env, tl, tl)
DEF_HELPER_3(khmtt, tl, env, tl, tl)
DEF_HELPER_3(ukaddh, tl, env, tl, tl)
DEF_HELPER_3(uksubh, tl, env, tl, tl)
+
+DEF_HELPER_3(kaddw, tl, env, tl, tl)
+DEF_HELPER_3(ukaddw, tl, env, tl, tl)
+DEF_HELPER_3(ksubw, tl, env, tl, tl)
+DEF_HELPER_3(uksubw, tl, env, tl, tl)
+DEF_HELPER_3(kdmbb, tl, env, tl, tl)
+DEF_HELPER_3(kdmbt, tl, env, tl, tl)
+DEF_HELPER_3(kdmtt, tl, env, tl, tl)
+DEF_HELPER_3(kslraw, tl, env, tl, tl)
+DEF_HELPER_3(kslraw_u, tl, env, tl, tl)
+DEF_HELPER_3(ksllw, tl, env, tl, tl)
+DEF_HELPER_4(kdmabb, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmabt, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmatt, tl, env, tl, tl, tl)
+DEF_HELPER_2(kabsw, tl, env, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b31bec9c75..0b8f8d4c42 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -836,3 +836,19 @@ khmbt 0001110 ..... ..... 001 ..... 1111111 @r
khmtt 0010110 ..... ..... 001 ..... 1111111 @r
ukaddh 0001010 ..... ..... 001 ..... 1111111 @r
uksubh 0001011 ..... ..... 001 ..... 1111111 @r
+
+kaddw 0000000 ..... ..... 001 ..... 1111111 @r
+ukaddw 0001000 ..... ..... 001 ..... 1111111 @r
+ksubw 0000001 ..... ..... 001 ..... 1111111 @r
+uksubw 0001001 ..... ..... 001 ..... 1111111 @r
+kdmbb 0000101 ..... ..... 001 ..... 1111111 @r
+kdmbt 0001101 ..... ..... 001 ..... 1111111 @r
+kdmtt 0010101 ..... ..... 001 ..... 1111111 @r
+kslraw 0110111 ..... ..... 001 ..... 1111111 @r
+kslraw_u 0111111 ..... ..... 001 ..... 1111111 @r
+ksllw 0010011 ..... ..... 001 ..... 1111111 @r
+kslliw 0011011 ..... ..... 001 ..... 1111111 @sh5
+kdmabb 1101001 ..... ..... 001 ..... 1111111 @r
+kdmabt 1110001 ..... ..... 001 ..... 1111111 @r
+kdmatt 1111001 ..... ..... 001 ..... 1111111 @r
+kabsw 1010110 10100 ..... 000 ..... 1111111 @r2
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index b4f6b74b70..a57776303a 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -829,3 +829,20 @@ GEN_RVP_R_OOL(khmbt);
GEN_RVP_R_OOL(khmtt);
GEN_RVP_R_OOL(ukaddh);
GEN_RVP_R_OOL(uksubh);
+
+/* Non-SIMD Q31 saturation ALU Instructions */
+GEN_RVP_R_OOL(kaddw);
+GEN_RVP_R_OOL(ukaddw);
+GEN_RVP_R_OOL(ksubw);
+GEN_RVP_R_OOL(uksubw);
+GEN_RVP_R_OOL(kdmbb);
+GEN_RVP_R_OOL(kdmbt);
+GEN_RVP_R_OOL(kdmtt);
+GEN_RVP_R_OOL(kslraw);
+GEN_RVP_R_OOL(kslraw_u);
+GEN_RVP_R_OOL(ksllw);
+GEN_RVP_SHIFTI(kslliw, ksllw, NULL);
+GEN_RVP_R_ACC_OOL(kdmabb);
+GEN_RVP_R_ACC_OOL(kdmabt);
+GEN_RVP_R_ACC_OOL(kdmatt);
+GEN_RVP_R2_OOL(kabsw);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 68db0b1f61..d2f7ec26f9 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -2613,3 +2613,217 @@ static inline void do_uksubh(CPURISCVState *env, void *vd, void *va,
}
RVPR(uksubh, 2, 4);
+
+/* Q31 saturation Instructions */
+static inline void do_kaddw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va, *b = vb;
+
+ *d = sadd32(env, 0, a[H4(i)], b[H4(i)]);
+}
+
+RVPR(kaddw, 2, 4);
+
+static inline void do_ukaddw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ uint32_t *a = va, *b = vb;
+
+ *d = (int32_t)saddu32(env, 0, a[H4(i)], b[H4(i)]);
+}
+
+RVPR(ukaddw, 2, 4);
+
+static inline void do_ksubw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va, *b = vb;
+
+ *d = ssub32(env, 0, a[H4(i)], b[H4(i)]);
+}
+
+RVPR(ksubw, 2, 4);
+
+static inline void do_uksubw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ uint32_t *a = va, *b = vb;
+
+ *d = (int32_t)ssubu32(env, 0, a[H4(i)], b[H4(i)]);
+}
+
+RVPR(uksubw, 2, 4);
+
+static inline void do_kdmbb(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ *d = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+}
+
+RVPR(kdmbb, 4, 2);
+
+static inline void do_kdmbt(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ *d = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR(kdmbt, 4, 2);
+
+static inline void do_kdmtt(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ *d = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR(kdmtt, 4, 2);
+
+static inline void do_kslraw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va;
+ int32_t shift = sextract32((*(uint32_t *)vb), 0, 6);
+
+ if (shift >= 0) {
+ *d = (int32_t)sat64(env, (int64_t)a[H4(i)] << shift, 31);
+ } else {
+ shift = -shift;
+ shift = (shift == 32) ? 31 : shift;
+ *d = a[H4(i)] >> shift;
+ }
+}
+
+RVPR(kslraw, 2, 4);
+
+static inline void do_kslraw_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va;
+ int32_t shift = sextract32((*(uint32_t *)vb), 0, 6);
+
+ if (shift >= 0) {
+ *d = (int32_t)sat64(env, (int64_t)a[H4(i)] << shift, 31);
+ } else {
+ shift = -shift;
+ shift = (shift == 32) ? 31 : shift;
+ *d = vssra32(env, 0, a[H4(i)], shift);
+ }
+}
+
+RVPR(kslraw_u, 2, 4);
+
+static inline void do_ksllw(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ target_long *d = vd;
+ int32_t *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0x1f;
+
+ *d = (int32_t)sat64(env, (int64_t)a[H4(i)] << shift, 31);
+}
+
+RVPR(ksllw, 2, 4);
+
+static inline void do_kdmabb(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+ *d = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmabb, 4, 2);
+
+static inline void do_kdmabt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+ *d = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmabt, 4, 2);
+
+static inline void do_kdmatt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ target_long *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+ *d = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmatt, 4, 2);
+
+static inline void do_kabsw(CPURISCVState *env, void *vd, void *va, uint8_t i)
+
+{
+ target_long *d = vd;
+ int32_t *a = va;
+
+ if (a[H4(i)] == INT32_MIN) {
+ *d = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int32_t)abs(a[H4(i)]);
+ }
+}
+
+RVPR2(kabsw, 2, 4);
--
2.17.1
next prev parent reply other threads:[~2021-02-12 15:58 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei [this message]
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
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