From: Palmer Dabbelt <palmer@dabbelt.com>
To: zhiwei_liu@c-sky.com
Cc: richard.henderson@linaro.org, zhiwei_liu@c-sky.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
alistair23@gmail.com
Subject: Re: [PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions
Date: Sun, 23 May 2021 21:46:41 -0700 (PDT) [thread overview]
Message-ID: <mhng-473b2bdf-9ee3-4780-87bf-e8adabce949c@palmerdabbelt-glaptop> (raw)
In-Reply-To: <20210212150256.885-8-zhiwei_liu@c-sky.com>
On Fri, 12 Feb 2021 07:02:25 PST (-0800), zhiwei_liu@c-sky.com wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
I know it's always kind of akward for this type of patches, but IIUC
they're all supposed to have some sort of description.
> ---
> target/riscv/helper.h | 9 +++
> target/riscv/insn32.decode | 17 ++++
> target/riscv/insn_trans/trans_rvp.c.inc | 16 ++++
> target/riscv/packed_helper.c | 102 ++++++++++++++++++++++++
> 4 files changed, 144 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 20bf400ac2..0ecd4d53f9 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1193,3 +1193,12 @@ DEF_HELPER_3(sll16, tl, env, tl, tl)
> DEF_HELPER_3(ksll16, tl, env, tl, tl)
> DEF_HELPER_3(kslra16, tl, env, tl, tl)
> DEF_HELPER_3(kslra16_u, tl, env, tl, tl)
> +
> +DEF_HELPER_3(sra8, tl, env, tl, tl)
> +DEF_HELPER_3(sra8_u, tl, env, tl, tl)
> +DEF_HELPER_3(srl8, tl, env, tl, tl)
> +DEF_HELPER_3(srl8_u, tl, env, tl, tl)
> +DEF_HELPER_3(sll8, tl, env, tl, tl)
> +DEF_HELPER_3(ksll8, tl, env, tl, tl)
> +DEF_HELPER_3(kslra8, tl, env, tl, tl)
> +DEF_HELPER_3(kslra8_u, tl, env, tl, tl)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6f053bfeb7..cc782fcde5 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -24,6 +24,7 @@
>
> %sh10 20:10
> %sh4 20:4
> +%sh3 20:3
> %csr 20:12
> %rm 12:3
> %nf 29:3 !function=ex_plus_1
> @@ -61,6 +62,7 @@
>
> @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
> @sh4 ...... ...... ..... ... ..... ....... &shift shamt=%sh4 %rs1 %rd
> +@sh3 ...... ...... ..... ... ..... ....... &shift shamt=%sh3 %rs1 %rd
> @csr ............ ..... ... ..... ....... %csr %rs1 %rd
>
> @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
> @@ -652,3 +654,18 @@ ksll16 0110010 ..... ..... 000 ..... 1111111 @r
> kslli16 0111010 1.... ..... 000 ..... 1111111 @sh4
> kslra16 0101011 ..... ..... 000 ..... 1111111 @r
> kslra16_u 0110011 ..... ..... 000 ..... 1111111 @r
> +
> +sra8 0101100 ..... ..... 000 ..... 1111111 @r
> +sra8_u 0110100 ..... ..... 000 ..... 1111111 @r
> +srai8 0111100 00... ..... 000 ..... 1111111 @sh3
> +srai8_u 0111100 01... ..... 000 ..... 1111111 @sh3
> +srl8 0101101 ..... ..... 000 ..... 1111111 @r
> +srl8_u 0110101 ..... ..... 000 ..... 1111111 @r
> +srli8 0111101 00... ..... 000 ..... 1111111 @sh3
> +srli8_u 0111101 01... ..... 000 ..... 1111111 @sh3
> +sll8 0101110 ..... ..... 000 ..... 1111111 @r
> +slli8 0111110 00... ..... 000 ..... 1111111 @sh3
> +ksll8 0110110 ..... ..... 000 ..... 1111111 @r
> +kslli8 0111110 01... ..... 000 ..... 1111111 @sh3
> +kslra8 0101111 ..... ..... 000 ..... 1111111 @r
> +kslra8_u 0110111 ..... ..... 000 ..... 1111111 @r
> diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
> index 848edab7e5..12a64849eb 100644
> --- a/target/riscv/insn_trans/trans_rvp.c.inc
> +++ b/target/riscv/insn_trans/trans_rvp.c.inc
> @@ -353,3 +353,19 @@ GEN_RVP_SHIFTI(slli16, sll16, tcg_gen_vec_shl16i_i64);
> GEN_RVP_SHIFTI(srai16_u, sra16_u, NULL);
> GEN_RVP_SHIFTI(srli16_u, srl16_u, NULL);
> GEN_RVP_SHIFTI(kslli16, ksll16, NULL);
> +
> +/* SIMD 8-bit Shift Instructions */
> +GEN_RVP_SHIFT(sra8, tcg_gen_gvec_sars, 0);
> +GEN_RVP_SHIFT(srl8, tcg_gen_gvec_shrs, 0);
> +GEN_RVP_SHIFT(sll8, tcg_gen_gvec_shls, 0);
> +GEN_RVP_R_OOL(sra8_u);
> +GEN_RVP_R_OOL(srl8_u);
> +GEN_RVP_R_OOL(ksll8);
> +GEN_RVP_R_OOL(kslra8);
> +GEN_RVP_R_OOL(kslra8_u);
> +GEN_RVP_SHIFTI(srai8, sra8, tcg_gen_vec_sar8i_i64);
> +GEN_RVP_SHIFTI(srli8, srl8, tcg_gen_vec_shr8i_i64);
> +GEN_RVP_SHIFTI(slli8, sll8, tcg_gen_vec_shl8i_i64);
> +GEN_RVP_SHIFTI(srai8_u, sra8_u, NULL);
> +GEN_RVP_SHIFTI(srli8_u, srl8_u, NULL);
> +GEN_RVP_SHIFTI(kslli8, ksll8, NULL);
> diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
> index 7e31c2fe46..ab9ebc472b 100644
> --- a/target/riscv/packed_helper.c
> +++ b/target/riscv/packed_helper.c
> @@ -529,3 +529,105 @@ static inline void do_kslra16_u(CPURISCVState *env, void *vd, void *va,
> }
>
> RVPR(kslra16_u, 1, 2);
> +
> +/* SIMD 8-bit Shift Instructions */
> +static inline void do_sra8(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + int8_t *d = vd, *a = va;
> + uint8_t shift = *(uint8_t *)vb & 0x7;
> + d[i] = a[i] >> shift;
> +}
> +
> +RVPR(sra8, 1, 1);
> +
> +static inline void do_srl8(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + uint8_t *d = vd, *a = va;
> + uint8_t shift = *(uint8_t *)vb & 0x7;
> + d[i] = a[i] >> shift;
> +}
> +
> +RVPR(srl8, 1, 1);
> +
> +static inline void do_sll8(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + uint8_t *d = vd, *a = va;
> + uint8_t shift = *(uint8_t *)vb & 0x7;
> + d[i] = a[i] << shift;
> +}
> +
> +RVPR(sll8, 1, 1);
> +
> +static inline void do_sra8_u(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + int8_t *d = vd, *a = va;
> + uint8_t shift = *(uint8_t *)vb & 0x7;
> + d[i] = vssra8(env, 0, a[i], shift);
> +}
> +
> +RVPR(sra8_u, 1, 1);
> +
> +static inline void do_srl8_u(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + uint8_t *d = vd, *a = va;
> + uint8_t shift = *(uint8_t *)vb & 0x7;
> + d[i] = vssrl8(env, 0, a[i], shift);
> +}
> +
> +RVPR(srl8_u, 1, 1);
> +
> +static inline void do_ksll8(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + int8_t *d = vd, *a = va, result;
> + uint8_t shift = *(uint8_t *)vb & 0x7;
> +
> + result = a[i] << shift;
> + if (shift > (clrsb32(a[i]) - 24)) {
> + env->vxsat = 0x1;
> + d[i] = (a[i] & INT8_MIN) ? INT8_MIN : INT8_MAX;
> + } else {
> + d[i] = result;
> + }
> +}
> +
> +RVPR(ksll8, 1, 1);
> +
> +static inline void do_kslra8(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + int8_t *d = vd, *a = va;
> + int32_t shift = sextract32((*(uint32_t *)vb), 0, 4);
> +
> + if (shift >= 0) {
> + do_ksll8(env, vd, va, vb, i);
> + } else {
> + shift = -shift;
> + shift = (shift == 8) ? 7 : shift;
> + d[i] = a[i] >> shift;
> + }
> +}
> +
> +RVPR(kslra8, 1, 1);
> +
> +static inline void do_kslra8_u(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + int8_t *d = vd, *a = va;
> + int32_t shift = sextract32((*(uint32_t *)vb), 0, 4);
> +
> + if (shift >= 0) {
> + do_ksll8(env, vd, va, vb, i);
> + } else {
> + shift = -shift;
> + shift = (shift == 8) ? 7 : shift;
> + d[i] = vssra8(env, 0, a[i], shift);
> + }
> +}
> +
> +RVPR(kslra8_u, 1, 1);
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
next prev parent reply other threads:[~2021-05-24 4:47 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt [this message]
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
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