From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: Richard Henderson <richard.henderson@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions
Date: Tue, 16 Mar 2021 10:40:33 -0400 [thread overview]
Message-ID: <CAKmqyKP4H0SLPWw9d0qSOiErni-JQAXp-DNCuALUzCGy89AGFg@mail.gmail.com> (raw)
In-Reply-To: <20210212150256.885-15-zhiwei_liu@c-sky.com>
On Fri, Feb 12, 2021 at 10:32 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 11 +++
> target/riscv/insn32.decode | 11 +++
> target/riscv/insn_trans/trans_rvp.c.inc | 12 +++
> target/riscv/packed_helper.c | 121 ++++++++++++++++++++++++
> 4 files changed, 155 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 83778b532a..585905a689 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1252,3 +1252,14 @@ DEF_HELPER_2(clrs8, tl, env, tl)
> DEF_HELPER_2(clz8, tl, env, tl)
> DEF_HELPER_2(clo8, tl, env, tl)
> DEF_HELPER_2(swap8, tl, env, tl)
> +
> +DEF_HELPER_2(sunpkd810, tl, env, tl)
> +DEF_HELPER_2(sunpkd820, tl, env, tl)
> +DEF_HELPER_2(sunpkd830, tl, env, tl)
> +DEF_HELPER_2(sunpkd831, tl, env, tl)
> +DEF_HELPER_2(sunpkd832, tl, env, tl)
> +DEF_HELPER_2(zunpkd810, tl, env, tl)
> +DEF_HELPER_2(zunpkd820, tl, env, tl)
> +DEF_HELPER_2(zunpkd830, tl, env, tl)
> +DEF_HELPER_2(zunpkd831, tl, env, tl)
> +DEF_HELPER_2(zunpkd832, tl, env, tl)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e158066353..fa4a02c9db 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -720,3 +720,14 @@ clrs8 1010111 00000 ..... 000 ..... 1111111 @r2
> clz8 1010111 00001 ..... 000 ..... 1111111 @r2
> clo8 1010111 00011 ..... 000 ..... 1111111 @r2
> swap8 1010110 11000 ..... 000 ..... 1111111 @r2
> +
> +sunpkd810 1010110 01000 ..... 000 ..... 1111111 @r2
> +sunpkd820 1010110 01001 ..... 000 ..... 1111111 @r2
> +sunpkd830 1010110 01010 ..... 000 ..... 1111111 @r2
> +sunpkd831 1010110 01011 ..... 000 ..... 1111111 @r2
> +sunpkd832 1010110 10011 ..... 000 ..... 1111111 @r2
> +zunpkd810 1010110 01100 ..... 000 ..... 1111111 @r2
> +zunpkd820 1010110 01101 ..... 000 ..... 1111111 @r2
> +zunpkd830 1010110 01110 ..... 000 ..... 1111111 @r2
> +zunpkd831 1010110 01111 ..... 000 ..... 1111111 @r2
> +zunpkd832 1010110 10111 ..... 000 ..... 1111111 @r2
> diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
> index 5ad057d7ac..b69e964cb4 100644
> --- a/target/riscv/insn_trans/trans_rvp.c.inc
> +++ b/target/riscv/insn_trans/trans_rvp.c.inc
> @@ -499,3 +499,15 @@ GEN_RVP_R2_OOL(clrs8);
> GEN_RVP_R2_OOL(clz8);
> GEN_RVP_R2_OOL(clo8);
> GEN_RVP_R2_OOL(swap8);
> +
> +/* 8-bit Unpacking Instructions */
> +GEN_RVP_R2_OOL(sunpkd810);
> +GEN_RVP_R2_OOL(sunpkd820);
> +GEN_RVP_R2_OOL(sunpkd830);
> +GEN_RVP_R2_OOL(sunpkd831);
> +GEN_RVP_R2_OOL(sunpkd832);
> +GEN_RVP_R2_OOL(zunpkd810);
> +GEN_RVP_R2_OOL(zunpkd820);
> +GEN_RVP_R2_OOL(zunpkd830);
> +GEN_RVP_R2_OOL(zunpkd831);
> +GEN_RVP_R2_OOL(zunpkd832);
> diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
> index be91d308e5..d0dcb692f5 100644
> --- a/target/riscv/packed_helper.c
> +++ b/target/riscv/packed_helper.c
> @@ -1202,3 +1202,124 @@ static inline void do_swap8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> }
>
> RVPR2(swap8, 2, 1);
> +
> +/* 8-bit Unpacking Instructions */
> +static inline void
> +do_sunpkd810(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + int8_t *a = va;
> + int16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i)];
> + d[H2(i / 2 + 1)] = a[H1(i + 1)];
> +}
> +
> +RVPR2(sunpkd810, 4, 1);
> +
> +static inline void
> +do_sunpkd820(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + int8_t *a = va;
> + int16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i)];
> + d[H2(i / 2 + 1)] = a[H1(i + 2)];
> +}
> +
> +RVPR2(sunpkd820, 4, 1);
> +
> +static inline void
> +do_sunpkd830(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + int8_t *a = va;
> + int16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i)];
> + d[H2(i / 2 + 1)] = a[H1(i + 3)];
> +}
> +
> +RVPR2(sunpkd830, 4, 1);
> +
> +static inline void
> +do_sunpkd831(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + int8_t *a = va;
> + int16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i) + 1];
> + d[H2(i / 2 + 1)] = a[H1(i + 3)];
> +}
> +
> +RVPR2(sunpkd831, 4, 1);
> +
> +static inline void
> +do_sunpkd832(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + int8_t *a = va;
> + int16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i) + 2];
> + d[H2(i / 2 + 1)] = a[H1(i + 3)];
> +}
> +
> +RVPR2(sunpkd832, 4, 1);
> +
> +static inline void
> +do_zunpkd810(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + uint8_t *a = va;
> + uint16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i)];
> + d[H2(i / 2 + 1)] = a[H1(i + 1)];
> +}
> +
> +RVPR2(zunpkd810, 4, 1);
> +
> +static inline void
> +do_zunpkd820(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + uint8_t *a = va;
> + uint16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i)];
> + d[H2(i / 2 + 1)] = a[H1(i + 2)];
> +}
> +
> +RVPR2(zunpkd820, 4, 1);
> +
> +static inline void
> +do_zunpkd830(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + uint8_t *a = va;
> + uint16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i)];
> + d[H2(i / 2 + 1)] = a[H1(i + 3)];
> +}
> +
> +RVPR2(zunpkd830, 4, 1);
> +
> +static inline void
> +do_zunpkd831(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + uint8_t *a = va;
> + uint16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i) + 1];
> + d[H2(i / 2 + 1)] = a[H1(i + 3)];
> +}
> +
> +RVPR2(zunpkd831, 4, 1);
> +
> +static inline void
> +do_zunpkd832(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + uint8_t *a = va;
> + uint16_t *d = vd;
> +
> + d[H2(i / 2)] = a[H1(i) + 2];
> + d[H2(i / 2 + 1)] = a[H1(i + 3)];
> +}
> +
> +RVPR2(zunpkd832, 4, 1);
> --
> 2.17.1
>
next prev parent reply other threads:[~2021-03-16 14:43 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis [this message]
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
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