[PATCH] util/cacheflush: Fix error generated by clang

[PATCH] util/cacheflush: Fix error generated by clang

[Gan Qixin]

When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following
error:

../util/cacheflush.c:38:44: error: value size does not match register size
specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
    asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
                                           ^
../util/cacheflush.c:38:24: note: use constraint modifier "w"
    asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
                       ^~
                       %w0

Modify the type of save_ctr_el0 to uint64_t to fix it.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
---
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
---
 util/cacheflush.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/util/cacheflush.c b/util/cacheflush.c
index 6a20723902..933355b0c9 100644
--- a/util/cacheflush.c
+++ b/util/cacheflush.c
@@ -32,7 +32,7 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
  * We want to save the whole contents of CTR_EL0, so that we
  * have more than the linesize, but also IDC and DIC.
  */
-static unsigned int save_ctr_el0;
+static uint64_t save_ctr_el0;
 static void __attribute__((constructor)) init_ctr_el0(void)
 {
     asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
@@ -46,9 +46,9 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
 {
     const unsigned CTR_IDC = 1u << 28;
     const unsigned CTR_DIC = 1u << 29;
-    const unsigned int ctr_el0 = save_ctr_el0;
-    const uintptr_t icache_lsize = 4 << extract32(ctr_el0, 0, 4);
-    const uintptr_t dcache_lsize = 4 << extract32(ctr_el0, 16, 4);
+    const uint64_t ctr_el0 = save_ctr_el0;
+    const uintptr_t icache_lsize = 4 << extract64(ctr_el0, 0, 4);
+    const uintptr_t dcache_lsize = 4 << extract64(ctr_el0, 16, 4);
     uintptr_t p;
 
     /*
-- 
2.27.0

Re: [PATCH] util/cacheflush: Fix error generated by clang

[Richard Henderson]

On 1/14/21 9:56 PM, Gan Qixin wrote:
> When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following
> error:
> 
> ../util/cacheflush.c:38:44: error: value size does not match register size
> specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
>     asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
>                                            ^
> ../util/cacheflush.c:38:24: note: use constraint modifier "w"
>     asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
>                        ^~
>                        %w0
> 
> Modify the type of save_ctr_el0 to uint64_t to fix it.
> 
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Gan Qixin <ganqixin@huawei.com>
> ---
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  util/cacheflush.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

This is clang being overly-picky.  IMO it should have done the mrs into a
64-bit register, then truncated the value when storing to the 32-bit variable.
 Which is what GCC does.  Certainly the code as written only needs the low 20
bits of the result.

But your change will not really make any difference to the generated code,
except for 4 more bytes of storage, so:

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH] util/cacheflush: Fix error generated by clang

[Paolo Bonzini]

On 15/01/21 08:56, Gan Qixin wrote:
> When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following
> error:
> 
> ../util/cacheflush.c:38:44: error: value size does not match register size
> specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
>      asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
>                                             ^
> ../util/cacheflush.c:38:24: note: use constraint modifier "w"
>      asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
>                         ^~
>                         %w0
> 
> Modify the type of save_ctr_el0 to uint64_t to fix it.
> 
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Gan Qixin <ganqixin@huawei.com>
> ---
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   util/cacheflush.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/util/cacheflush.c b/util/cacheflush.c
> index 6a20723902..933355b0c9 100644
> --- a/util/cacheflush.c
> +++ b/util/cacheflush.c
> @@ -32,7 +32,7 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
>    * We want to save the whole contents of CTR_EL0, so that we
>    * have more than the linesize, but also IDC and DIC.
>    */
> -static unsigned int save_ctr_el0;
> +static uint64_t save_ctr_el0;
>   static void __attribute__((constructor)) init_ctr_el0(void)
>   {
>       asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
> @@ -46,9 +46,9 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
>   {
>       const unsigned CTR_IDC = 1u << 28;
>       const unsigned CTR_DIC = 1u << 29;
> -    const unsigned int ctr_el0 = save_ctr_el0;
> -    const uintptr_t icache_lsize = 4 << extract32(ctr_el0, 0, 4);
> -    const uintptr_t dcache_lsize = 4 << extract32(ctr_el0, 16, 4);
> +    const uint64_t ctr_el0 = save_ctr_el0;
> +    const uintptr_t icache_lsize = 4 << extract64(ctr_el0, 0, 4);
> +    const uintptr_t dcache_lsize = 4 << extract64(ctr_el0, 16, 4);
>       uintptr_t p;
>   
>       /*
> 

Queued, thanks.