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* [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
@ 2019-09-02 14:01 Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 1/8] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
                   ` (9 more replies)
  0 siblings, 10 replies; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo, philmd

This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet.
However I was able to execute simple code with functions. e.g fibonacci calculation.
This series of patches include a non real, sample board.
No fuses support yet. PC is set to 0 at reset.

the patches include the following
1. just a basic 8bit AVR CPU, without instruction decoding or translation
2. CPU features which allow define the following 8bit AVR cores
     avr1
     avr2 avr25
     avr3 avr31 avr35
     avr4
     avr5 avr51
     avr6
     xmega2 xmega4 xmega5 xmega6 xmega7
3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code
4. encoding for all AVR instructions
5. interrupt handling
6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
7. a decoder which given an opcode decides what istruction it is
8. translation of AVR instruction into TCG
9. all features together

changes since v3
1. rampD/X/Y/Z registers are encoded as 0x00ff0000 (instead of 0x000000ff) for faster address manipulaton
2. ffs changed to ctz32
3. duplicate code removed at avr_cpu_do_interrupt
4. using andc instead of not + and
5. fixing V flag calculation in varios instructions
6. freeing local variables in PUSH
7. tcg_const_local_i32 -> tcg_const_i32
8. using sextract32 instead of my implementation
9. fixing BLD instruction
10.xor(r) instead of 0xff - r at COM
11.fixing MULS/MULSU not to modify inputs' content
12.using SUB for NEG
13.fixing tcg_gen_qemu_ld/st call in XCH

changes since v4
1. target is now defined as big endian in order to optimize push_ret/pop_ret
2. all style warnings are fixed
3. adding cpu_set/get_sreg functions
4. simplifying gen_goto_tb as there is no real paging
5. env->pc -> env->pc_w
6. making flag dump more compact
7. more spacing
8. renaming CODE/DATA_INDEX -> MMU_CODE/DATA_IDX
9. removing avr_set_feature
10. SPL/SPH set bug fix
11. switching stb_phys to cpu_stb_data
12. cleaning up avr_decode
13. saving sreg, rampD/X/Y/Z, eind in HW format (savevm)
14. saving CPU features (savevm)

changes since v5
1. BLD bug fix
2. decoder generator is added

chages since v6
1. using cpu_get_sreg/cpu_set_sreg in avr_cpu_gdb_read_register/avr_cpu_gdb_write_register
2. configure the target as little endian because otherwise GDB does not work
3. fixing and testing gen_push_ret/gen_pop_ret

changes since v7
1. folding back v6
2. logging at helper_outb and helper_inb are done for non supported yet registers only
3. MAINTAINERS updated

changes since v8
1. removing hw/avr from hw/Makefile.obj as it should not be built for all
2. making linux compilable
3. testing on
    a. Mac, Apple LLVM version 7.0.0
    b. Ubuntu 12.04, gcc 4.9.2
    c. Fedora 23, gcc 5.3.1
4. folding back some patches
5. translation bug fixes for ORI, CPI, XOR instructions
6. propper handling of cpu register writes though memory

changes since v9
1. removing forward declarations of static functions
2. disabling debug prints
3. switching to case range instead of if else if ...
4. LD/ST IN/OUT accessing CPU maintainder registers are not routed to any device
5. commenst about sample board and sample IO device added
6. sample board description is more descriptive now
7. memory_region_allocate_system_memory is used to create RAM
8. now there are helper_fullrd & helper_fullwr when LD/ST try to access registers

changes since v10
1. movig back fullwr & fullrd into the commit where outb and inb were introduced
2. changing tlb_fill function signature
3. adding empty line between functions
4. adding newline on the last line of the file
5. using tb->flags to generae full access ST/LD instructions
6. fixing SBRC bug
7. folding back 10th commit
8. whenever a new file is introduced it's added to Makefile.objs

changes since v11
1. updating to v2.7.0-rc
2. removing assignment to env->fullacc from gen_intermediate_code

changes since v12
1. fixing spacing
2. fixing get/put_segment functions
3. removing target-avr/machine.h file
4. VMSTATE_SINGLE_TEST -> VMSTATE_SINGLE
5. comment spelling
6. removing hw/avr/sample_io.c
7. char const* -> const char*
8. proper ram allocation
9. fixing breakpoint functionality.
10.env1 -> env
11.fixing avr_cpu_gdb_write_register & avr_cpu_gdb_read_register functions
12.any cpu is removed
12.feature bits are not saved into vm state

changes since v13
1. rebasing to v2.7.0-rc1

changes since v14
1. I made self review with git gui tool. (I did not know such a thing exists)
2. removing all double/tripple spaces
3. removing comment reference to SampleIO
4. folding back some changes, so there is not deleted lines in my code
5. moving avr configuration, within configure file, before chris

changes since v15
1. removing IO registers cache from CPU
2. implementing CBI/SBI as read(helper_inb), modify, write(helper_outb)
3. implementing CBIC/SBIC as read(helper_inb), check, branch
4. adding missing tcg_temp_free_i32 for tcg_const_i32

changes since v16
1. removing EXT IO registers knoledge from CPU. These registers are accessible
   by LD/ST only. CPU has no interest in them

changes since v17 (by Richard Henderson)
This is Michael's v17, with some adjustments of my own:

1. Fix the whitespace errors reported by "git am",
2. Replace the utf-8 characters with normal ascii,
3. Ditch the separate compilation of translate.c.

I retained the two separate files that could be regenerated
from the included cpugen program, but merged in translate-insn.c.
Not that it matters, but the code generated is about 3k smaller.

changes since v18
1.  moving target-avr into target/avr
2.  do not call cpu_exec_initfn function from avr_cpu_initfn
3.  call cpu_exec_realizefn avr_cpu_realizefn
4.  do not fail sample machine creation if no rom is suplied
5.  add tcg_gen_exit_tb(0) for BS_BRANCH in gen_intermediate_code
6.  fix a register getters/setters in machine.c
7.  changing QEMU_ARCH_AVR from 1<<17 to 1<<18

changes since v19
1.  use decodetree.py tool to decode instructions
2.  adding USART
3.  adding 16 bit timer peripherals
4.  changing QEMU_ARCH_AVR from 1<<18 to 1<<20
5.  renaming tlb_fill to avr_cpu_tlb_fill

changes since v20
1.  use one CPU naming convention
2.  merging insn16.decode & insn32.decode files
3.  modifying skip next instruction mechanizm
4.  translate BREAK as NOP for now

changes since v21
1.  Reorganize bstate.
    This will make transition to <exec/translator.h> easier, and fixes a couple of bugs wrt single stepping
    by richard.henderson@linaro.org
2.  Drop cpc and fix page cross condition.
    by richard.henderson@linaro.org
3.  Refactor checking supported/unsupported instructions
4.  Add gdb-xml/avr-cpu.xml

changes since v22
1.  Rebase
2.  Split long comment

changes since v23
1.  remove avr_cpu_list_compare function
2.  modify avr_cpu_class_by_name function
3.  modify avr_cpu_list_entry function
4.  modify avr_cpu_list function

changes since v24
1.  remove AVR_CPU_TYPE_NAME macro

changes since v25
1.  fix patches. every file belong to one patch only
2.  change copyright year from 2016 to 2019
3.  create mask device to emulate prr0/prr1

changes since v26
1.  add avocado acceptence test
2.  add boot serial test

changes since v27
1.  list atmel2560 devices as unimplemented
2.  fix sram base/size 

changes since v28
1.  rebase
2.  fix includes & build

changes since v29
1.  fixing ownership
2.  using 'since' instread of 'added in'

Michael Rolnik (7):
  target/avr: Add outward facing interfaces and core CPU logic
  target/avr: Add instruction helpers
  target/avr: Add instruction decoding
  target/avr: Add instruction translation
  target/avr: Add example board configuration
  target/avr: Register AVR support with the rest of QEMU, the build
    system, and the MAINTAINERS file
  target/avr: Add tests

Sarah Harris (1):
  target/avr: Add limited support for USART and 16 bit timer peripherals

 MAINTAINERS                      |    6 +
 arch_init.c                      |    2 +
 configure                        |   93 +-
 default-configs/avr-softmmu.mak  |    5 +
 gdb-xml/avr-cpu.xml              |   49 +
 hw/Kconfig                       |    1 +
 hw/avr/Kconfig                   |    6 +
 hw/avr/Makefile.objs             |    1 +
 hw/avr/sample.c                  |  282 +++
 hw/char/Kconfig                  |    3 +
 hw/char/Makefile.objs            |    1 +
 hw/char/avr_usart.c              |  324 ++++
 hw/misc/Kconfig                  |    3 +
 hw/misc/Makefile.objs            |    2 +
 hw/misc/avr_mask.c               |  112 ++
 hw/timer/Kconfig                 |    3 +
 hw/timer/Makefile.objs           |    1 +
 hw/timer/avr_timer16.c           |  605 +++++++
 include/disas/dis-asm.h          |    6 +
 include/hw/char/avr_usart.h      |   97 +
 include/hw/misc/avr_mask.h       |   47 +
 include/hw/timer/avr_timer16.h   |   97 +
 include/sysemu/arch_init.h       |    1 +
 qapi/machine.json                |    3 +-
 target/avr/Makefile.objs         |   33 +
 target/avr/cpu-param.h           |   37 +
 target/avr/cpu-qom.h             |   54 +
 target/avr/cpu.c                 |  576 ++++++
 target/avr/cpu.h                 |  254 +++
 target/avr/gdbstub.c             |   85 +
 target/avr/helper.c              |  354 ++++
 target/avr/helper.h              |   29 +
 target/avr/insn.decode           |  175 ++
 target/avr/machine.c             |  121 ++
 target/avr/translate.c           | 2888 ++++++++++++++++++++++++++++++
 tests/Makefile.include           |    2 +
 tests/acceptance/machine_avr6.py |   36 +
 tests/boot-serial-test.c         |   10 +
 tests/machine-none-test.c        |    1 +
 39 files changed, 6361 insertions(+), 44 deletions(-)
 create mode 100644 default-configs/avr-softmmu.mak
 create mode 100644 gdb-xml/avr-cpu.xml
 create mode 100644 hw/avr/Kconfig
 create mode 100644 hw/avr/Makefile.objs
 create mode 100644 hw/avr/sample.c
 create mode 100644 hw/char/avr_usart.c
 create mode 100644 hw/misc/avr_mask.c
 create mode 100644 hw/timer/avr_timer16.c
 create mode 100644 include/hw/char/avr_usart.h
 create mode 100644 include/hw/misc/avr_mask.h
 create mode 100644 include/hw/timer/avr_timer16.h
 create mode 100644 target/avr/Makefile.objs
 create mode 100644 target/avr/cpu-param.h
 create mode 100644 target/avr/cpu-qom.h
 create mode 100644 target/avr/cpu.c
 create mode 100644 target/avr/cpu.h
 create mode 100644 target/avr/gdbstub.c
 create mode 100644 target/avr/helper.c
 create mode 100644 target/avr/helper.h
 create mode 100644 target/avr/insn.decode
 create mode 100644 target/avr/machine.c
 create mode 100644 target/avr/translate.c
 create mode 100644 tests/acceptance/machine_avr6.py

-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* [Qemu-devel] [PATCH v30 1/8] target/avr: Add outward facing interfaces and core CPU logic
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
@ 2019-09-02 14:01 ` Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 2/8] target/avr: Add instruction helpers Michael Rolnik
                   ` (8 subsequent siblings)
  9 siblings, 0 replies; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo, philmd

This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
---
 gdb-xml/avr-cpu.xml    |  49 ++++
 target/avr/cpu-param.h |  37 +++
 target/avr/cpu-qom.h   |  54 ++++
 target/avr/cpu.c       | 576 +++++++++++++++++++++++++++++++++++++++++
 target/avr/cpu.h       | 254 ++++++++++++++++++
 target/avr/gdbstub.c   |  85 ++++++
 target/avr/machine.c   | 121 +++++++++
 7 files changed, 1176 insertions(+)
 create mode 100644 gdb-xml/avr-cpu.xml
 create mode 100644 target/avr/cpu-param.h
 create mode 100644 target/avr/cpu-qom.h
 create mode 100644 target/avr/cpu.c
 create mode 100644 target/avr/cpu.h
 create mode 100644 target/avr/gdbstub.c
 create mode 100644 target/avr/machine.c

diff --git a/gdb-xml/avr-cpu.xml b/gdb-xml/avr-cpu.xml
new file mode 100644
index 0000000000..c4747f5b40
--- /dev/null
+++ b/gdb-xml/avr-cpu.xml
@@ -0,0 +1,49 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+     compatibility with older versions of tools that didn't use xml
+     register descriptions.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+  <reg name="r0" bitsize="8" type="int" regnum="0"/>
+  <reg name="r1" bitsize="8" type="int"/>
+  <reg name="r2" bitsize="8" type="int"/>
+  <reg name="r3" bitsize="8" type="int"/>
+  <reg name="r4" bitsize="8" type="int"/>
+  <reg name="r5" bitsize="8" type="int"/>
+  <reg name="r6" bitsize="8" type="int"/>
+  <reg name="r7" bitsize="8" type="int"/>
+  <reg name="r8" bitsize="8" type="int"/>
+  <reg name="r9" bitsize="8" type="int"/>
+  <reg name="r10" bitsize="8" type="int"/>
+  <reg name="r11" bitsize="8" type="int"/>
+  <reg name="r12" bitsize="8" type="int"/>
+  <reg name="r13" bitsize="8" type="int"/>
+  <reg name="r14" bitsize="8" type="int"/>
+  <reg name="r15" bitsize="8" type="int"/>
+  <reg name="r16" bitsize="8" type="int"/>
+  <reg name="r17" bitsize="8" type="int"/>
+  <reg name="r18" bitsize="8" type="int"/>
+  <reg name="r19" bitsize="8" type="int"/>
+  <reg name="r20" bitsize="8" type="int"/>
+  <reg name="r21" bitsize="8" type="int"/>
+  <reg name="r22" bitsize="8" type="int"/>
+  <reg name="r23" bitsize="8" type="int"/>
+  <reg name="r24" bitsize="8" type="int"/>
+  <reg name="r25" bitsize="8" type="int"/>
+  <reg name="r26" bitsize="8" type="int"/>
+  <reg name="r27" bitsize="8" type="int"/>
+  <reg name="r28" bitsize="8" type="int"/>
+  <reg name="r29" bitsize="8" type="int"/>
+  <reg name="r30" bitsize="8" type="int"/>
+  <reg name="r31" bitsize="8" type="int"/>
+  <reg name="sreg" bitsize="8" type="int"/>
+  <reg name="sp" bitsize="8" type="int"/>
+  <reg name="pc" bitsize="8" type="int"/>
+</feature>
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
new file mode 100644
index 0000000000..ccd1ea3429
--- /dev/null
+++ b/target/avr/cpu-param.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef AVR_CPU_PARAM_H
+#define AVR_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+/*
+ * TARGET_PAGE_BITS cannot be more than 8 bits because
+ * 1.  all IO registers occupy [0x0000 .. 0x00ff] address range, and they
+ *     should be implemented as a device and not memory
+ * 2.  SRAM starts at the address 0x0100
+ */
+#define TARGET_PAGE_BITS 8
+#define TARGET_PHYS_ADDR_SPACE_BITS 24
+#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define NB_MMU_MODES 2
+
+
+#endif
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
new file mode 100644
index 0000000000..e28b58c897
--- /dev/null
+++ b/target/avr/cpu-qom.h
@@ -0,0 +1,54 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef QEMU_AVR_QOM_H
+#define QEMU_AVR_QOM_H
+
+#include "hw/core/cpu.h"
+
+#define TYPE_AVR_CPU "avr-cpu"
+
+#define AVR_CPU_CLASS(klass) \
+    OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU)
+#define AVR_CPU(obj) \
+    OBJECT_CHECK(AVRCPU, (obj), TYPE_AVR_CPU)
+#define AVR_CPU_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(AVRCPUClass, (obj), TYPE_AVR_CPU)
+
+/**
+ *  AVRCPUClass:
+ *  @parent_realize: The parent class' realize handler.
+ *  @parent_reset: The parent class' reset handler.
+ *  @vr: Version Register value.
+ *
+ *  A AVR CPU model.
+ */
+typedef struct AVRCPUClass {
+    /*< private >*/
+    CPUClass parent_class;
+    /*< public >*/
+    DeviceRealize parent_realize;
+    void (*parent_reset)(CPUState *cpu);
+} AVRCPUClass;
+
+typedef struct AVRCPU AVRCPU;
+
+
+#endif /* !defined (QEMU_AVR_CPU_QOM_H) */
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
new file mode 100644
index 0000000000..dae56d7845
--- /dev/null
+++ b/target/avr/cpu.c
@@ -0,0 +1,576 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/qemu-print.h"
+#include "exec/exec-all.h"
+#include "cpu.h"
+
+static void avr_cpu_set_pc(CPUState *cs, vaddr value)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+
+    cpu->env.pc_w = value / 2; /* internally PC points to words */
+}
+
+static bool avr_cpu_has_work(CPUState *cs)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
+
+    return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
+            && cpu_interrupts_enabled(env);
+}
+
+static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
+
+    env->pc_w = tb->pc / 2; /* internally PC points to words */
+}
+
+static void avr_cpu_reset(CPUState *cs)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+    AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
+    CPUAVRState *env = &cpu->env;
+
+    mcc->parent_reset(cs);
+
+    env->pc_w = 0;
+    env->sregI = 1;
+    env->sregC = 0;
+    env->sregZ = 0;
+    env->sregN = 0;
+    env->sregV = 0;
+    env->sregS = 0;
+    env->sregH = 0;
+    env->sregT = 0;
+
+    env->rampD = 0;
+    env->rampX = 0;
+    env->rampY = 0;
+    env->rampZ = 0;
+    env->eind = 0;
+    env->sp = 0;
+
+    env->skip = 0;
+
+    memset(env->r, 0, sizeof(env->r));
+
+    tlb_flush(cs);
+}
+
+static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+    info->mach = bfd_arch_avr;
+    info->print_insn = NULL;
+}
+
+static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    CPUState *cs = CPU(dev);
+    AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
+    Error *local_err = NULL;
+
+    cpu_exec_realizefn(cs, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
+    }
+    qemu_init_vcpu(cs);
+    cpu_reset(cs);
+
+    mcc->parent_realize(dev, errp);
+}
+
+static void avr_cpu_set_int(void *opaque, int irq, int level)
+{
+    AVRCPU *cpu = opaque;
+    CPUAVRState *env = &cpu->env;
+    CPUState *cs = CPU(cpu);
+
+    uint64_t mask = (1ull << irq);
+    if (level) {
+        env->intsrc |= mask;
+        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+    } else {
+        env->intsrc &= ~mask;
+        if (env->intsrc == 0) {
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+        }
+    }
+}
+
+static void avr_cpu_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+
+    cpu_set_cpustate_pointers(cpu);
+
+#ifndef CONFIG_USER_ONLY
+    /* Set the number of interrupts supported by the CPU. */
+    qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 57);
+#endif
+}
+
+static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
+{
+    ObjectClass *oc;
+
+    oc = object_class_by_name(cpu_model);
+    if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
+        object_class_is_abstract(oc)) {
+        oc = NULL;
+    }
+    return oc;
+}
+
+static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
+    int i;
+
+    qemu_fprintf(f, "\n");
+    qemu_fprintf(f, "PC:    %06x\n", env->pc_w);
+    qemu_fprintf(f, "SP:      %04x\n", env->sp);
+    qemu_fprintf(f, "rampD:     %02x\n", env->rampD >> 16);
+    qemu_fprintf(f, "rampX:     %02x\n", env->rampX >> 16);
+    qemu_fprintf(f, "rampY:     %02x\n", env->rampY >> 16);
+    qemu_fprintf(f, "rampZ:     %02x\n", env->rampZ >> 16);
+    qemu_fprintf(f, "EIND:      %02x\n", env->eind >> 16);
+    qemu_fprintf(f, "X:       %02x%02x\n", env->r[27], env->r[26]);
+    qemu_fprintf(f, "Y:       %02x%02x\n", env->r[29], env->r[28]);
+    qemu_fprintf(f, "Z:       %02x%02x\n", env->r[31], env->r[30]);
+    qemu_fprintf(f, "SREG:    [ %c %c %c %c %c %c %c %c ]\n",
+                        env->sregI ? 'I' : '-',
+                        env->sregT ? 'T' : '-',
+                        env->sregH ? 'H' : '-',
+                        env->sregS ? 'S' : '-',
+                        env->sregV ? 'V' : '-',
+                        env->sregN ? '-' : 'N', /* Zf has negative logic */
+                        env->sregZ ? 'Z' : '-',
+                        env->sregC ? 'I' : '-');
+    qemu_fprintf(f, "SKIP:    %02x\n", env->skip);
+
+    qemu_fprintf(f, "\n");
+    for (i = 0; i < ARRAY_SIZE(env->r); i++) {
+        qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
+
+        if ((i % 8) == 7) {
+            qemu_fprintf(f, "\n");
+        }
+    }
+    qemu_fprintf(f, "\n");
+}
+
+static void avr_cpu_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    CPUClass *cc = CPU_CLASS(oc);
+    AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
+
+    mcc->parent_realize = dc->realize;
+    dc->realize = avr_cpu_realizefn;
+
+    mcc->parent_reset = cc->reset;
+    cc->reset = avr_cpu_reset;
+
+    cc->class_by_name = avr_cpu_class_by_name;
+
+    cc->has_work = avr_cpu_has_work;
+    cc->do_interrupt = avr_cpu_do_interrupt;
+    cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
+    cc->dump_state = avr_cpu_dump_state;
+    cc->set_pc = avr_cpu_set_pc;
+#if !defined(CONFIG_USER_ONLY)
+    cc->memory_rw_debug = avr_cpu_memory_rw_debug;
+#endif
+#ifdef CONFIG_USER_ONLY
+    cc->handle_mmu_fault = avr_cpu_handle_mmu_fault;
+#else
+    cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
+    cc->vmsd = &vms_avr_cpu;
+#endif
+    cc->disas_set_info = avr_cpu_disas_set_info;
+    cc->tlb_fill = avr_cpu_tlb_fill;
+    cc->tcg_initialize = avr_cpu_tcg_init;
+    cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
+    cc->gdb_read_register = avr_cpu_gdb_read_register;
+    cc->gdb_write_register = avr_cpu_gdb_write_register;
+    cc->gdb_num_core_regs = 35;
+    cc->gdb_core_xml_file = "avr-cpu.xml";
+}
+
+static void avr_avr1_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+}
+
+static void avr_avr2_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+}
+
+static void avr_avr25_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+}
+
+static void avr_avr3_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+}
+
+static void avr_avr31_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_RAMPZ);
+    avr_set_feature(env, AVR_FEATURE_ELPM);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+}
+
+static void avr_avr35_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+}
+
+static void avr_avr4_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+}
+
+static void avr_avr5_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+}
+
+static void avr_avr51_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_RAMPZ);
+    avr_set_feature(env, AVR_FEATURE_ELPMX);
+    avr_set_feature(env, AVR_FEATURE_ELPM);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+}
+
+static void avr_avr6_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_RAMPZ);
+    avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL);
+    avr_set_feature(env, AVR_FEATURE_ELPMX);
+    avr_set_feature(env, AVR_FEATURE_ELPM);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+}
+
+static void avr_xmega2_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+    avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+static void avr_xmega4_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_RAMPZ);
+    avr_set_feature(env, AVR_FEATURE_ELPMX);
+    avr_set_feature(env, AVR_FEATURE_ELPM);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+    avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+static void avr_xmega5_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_RAMPD);
+    avr_set_feature(env, AVR_FEATURE_RAMPX);
+    avr_set_feature(env, AVR_FEATURE_RAMPY);
+    avr_set_feature(env, AVR_FEATURE_RAMPZ);
+    avr_set_feature(env, AVR_FEATURE_ELPMX);
+    avr_set_feature(env, AVR_FEATURE_ELPM);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+    avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+static void avr_xmega6_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_RAMPZ);
+    avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL);
+    avr_set_feature(env, AVR_FEATURE_ELPMX);
+    avr_set_feature(env, AVR_FEATURE_ELPM);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+    avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+static void avr_xmega7_initfn(Object *obj)
+{
+    AVRCPU *cpu = AVR_CPU(obj);
+    CPUAVRState *env = &cpu->env;
+
+    avr_set_feature(env, AVR_FEATURE_LPM);
+    avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+    avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+    avr_set_feature(env, AVR_FEATURE_SRAM);
+    avr_set_feature(env, AVR_FEATURE_BREAK);
+
+    avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
+    avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+    avr_set_feature(env, AVR_FEATURE_RAMPD);
+    avr_set_feature(env, AVR_FEATURE_RAMPX);
+    avr_set_feature(env, AVR_FEATURE_RAMPY);
+    avr_set_feature(env, AVR_FEATURE_RAMPZ);
+    avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL);
+    avr_set_feature(env, AVR_FEATURE_ELPMX);
+    avr_set_feature(env, AVR_FEATURE_ELPM);
+    avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+    avr_set_feature(env, AVR_FEATURE_LPMX);
+    avr_set_feature(env, AVR_FEATURE_MOVW);
+    avr_set_feature(env, AVR_FEATURE_MUL);
+    avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+typedef struct AVRCPUInfo {
+    const char *name;
+    void (*initfn)(Object *obj);
+} AVRCPUInfo;
+
+
+static void avr_cpu_list_entry(gpointer data, gpointer user_data)
+{
+    const char *typename = object_class_get_name(OBJECT_CLASS(data));
+
+    qemu_printf("%s\n", typename);
+}
+
+void avr_cpu_list(void)
+{
+    GSList *list;
+    list = object_class_get_list_sorted(TYPE_AVR_CPU, false);
+    g_slist_foreach(list, avr_cpu_list_entry, NULL);
+    g_slist_free(list);
+}
+
+#define DEFINE_AVR_CPU_TYPE(model, initfn) \
+    { \
+        .parent = TYPE_AVR_CPU, \
+        .instance_init = initfn, \
+        .name = model "-avr-cpu", \
+    }
+
+static const TypeInfo avr_cpu_type_info[] = {
+    {
+        .name = TYPE_AVR_CPU,
+        .parent = TYPE_CPU,
+        .instance_size = sizeof(AVRCPU),
+        .instance_init = avr_cpu_initfn,
+        .class_size = sizeof(AVRCPUClass),
+        .class_init = avr_cpu_class_init,
+        .abstract = true,
+    },
+    DEFINE_AVR_CPU_TYPE("avr1", avr_avr1_initfn),
+    DEFINE_AVR_CPU_TYPE("avr2", avr_avr2_initfn),
+    DEFINE_AVR_CPU_TYPE("avr25", avr_avr25_initfn),
+    DEFINE_AVR_CPU_TYPE("avr3", avr_avr3_initfn),
+    DEFINE_AVR_CPU_TYPE("avr31", avr_avr31_initfn),
+    DEFINE_AVR_CPU_TYPE("avr35", avr_avr35_initfn),
+    DEFINE_AVR_CPU_TYPE("avr4", avr_avr4_initfn),
+    DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
+    DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
+    DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
+    DEFINE_AVR_CPU_TYPE("xmega2", avr_xmega2_initfn),
+    DEFINE_AVR_CPU_TYPE("xmega4", avr_xmega4_initfn),
+    DEFINE_AVR_CPU_TYPE("xmega5", avr_xmega5_initfn),
+    DEFINE_AVR_CPU_TYPE("xmega6", avr_xmega6_initfn),
+    DEFINE_AVR_CPU_TYPE("xmega7", avr_xmega7_initfn),
+};
+
+DEFINE_TYPES(avr_cpu_type_info)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
new file mode 100644
index 0000000000..45d644f4f4
--- /dev/null
+++ b/target/avr/cpu.h
@@ -0,0 +1,254 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef QEMU_AVR_CPU_H
+#define QEMU_AVR_CPU_H
+
+#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
+
+#define TCG_GUEST_DEFAULT_MO 0
+
+#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
+
+/*
+ * AVR has two memory spaces, data & code.
+ * e.g. both have 0 address
+ * ST/LD instructions access data space
+ * LPM/SPM and instruction fetching access code memory space
+ */
+#define MMU_CODE_IDX 0
+#define MMU_DATA_IDX 1
+
+#define EXCP_RESET 1
+#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
+
+/* Number of CPU registers */
+#define NO_CPU_REGISTERS 32
+/* Number of IO registers accessible by ld/st/in/out */
+#define NO_IO_REGISTERS 64
+
+/*
+ * Offsets of AVR memory regions in host memory space.
+ *
+ * This is needed because the AVR has separate code and data address
+ * spaces that both have start from zero but have to go somewhere in
+ * host memory.
+ *
+ * It's also useful to know where some things are, like the IO registers.
+ */
+/* Flash program memory */
+#define OFFSET_CODE 0x00000000
+/* CPU registers, IO registers, and SRAM */
+#define OFFSET_DATA 0x00800000
+/* CPU registers specifically, these are mapped at the start of data */
+#define OFFSET_CPU_REGISTERS OFFSET_DATA
+/*
+ * IO registers, including status register, stack pointer, and memory
+ * mapped peripherals, mapped just after CPU registers
+ */
+#define OFFSET_IO_REGISTERS (OFFSET_DATA + NO_CPU_REGISTERS)
+
+enum avr_features {
+    AVR_FEATURE_SRAM,
+
+    AVR_FEATURE_1_BYTE_PC,
+    AVR_FEATURE_2_BYTE_PC,
+    AVR_FEATURE_3_BYTE_PC,
+
+    AVR_FEATURE_1_BYTE_SP,
+    AVR_FEATURE_2_BYTE_SP,
+
+    AVR_FEATURE_BREAK,
+    AVR_FEATURE_DES,
+    AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */
+
+    AVR_FEATURE_EIJMP_EICALL,
+    AVR_FEATURE_IJMP_ICALL,
+    AVR_FEATURE_JMP_CALL,
+
+    AVR_FEATURE_ADIW_SBIW,
+
+    AVR_FEATURE_SPM,
+    AVR_FEATURE_SPMX,
+
+    AVR_FEATURE_ELPMX,
+    AVR_FEATURE_ELPM,
+    AVR_FEATURE_LPMX,
+    AVR_FEATURE_LPM,
+
+    AVR_FEATURE_MOVW,
+    AVR_FEATURE_MUL,
+    AVR_FEATURE_RAMPD,
+    AVR_FEATURE_RAMPX,
+    AVR_FEATURE_RAMPY,
+    AVR_FEATURE_RAMPZ,
+};
+
+typedef struct CPUAVRState CPUAVRState;
+
+struct CPUAVRState {
+    uint32_t pc_w; /* 0x003fffff up to 22 bits */
+
+    uint32_t sregC; /* 0x00000001 1 bits */
+    uint32_t sregZ; /* 0x0000ffff 16 bits, negative logic; */
+                    /* 0=flag set, >0=flag cleared */
+    uint32_t sregN; /* 0x00000001 1 bits */
+    uint32_t sregV; /* 0x00000001 1 bits */
+    uint32_t sregS; /* 0x00000001 1 bits */
+    uint32_t sregH; /* 0x00000001 1 bits */
+    uint32_t sregT; /* 0x00000001 1 bits */
+    uint32_t sregI; /* 0x00000001 1 bits */
+
+    uint32_t rampD; /* 0x00ff0000 8 bits */
+    uint32_t rampX; /* 0x00ff0000 8 bits */
+    uint32_t rampY; /* 0x00ff0000 8 bits */
+    uint32_t rampZ; /* 0x00ff0000 8 bits */
+    uint32_t eind; /* 0x00ff0000 8 bits */
+
+    uint32_t r[NO_CPU_REGISTERS]; /* 8 bits each */
+    uint32_t sp; /* 16 bits */
+
+    uint32_t skip; /* if set skip instruction */
+
+    uint64_t intsrc; /* interrupt sources */
+    bool fullacc; /* CPU/MEM if true MEM only otherwise */
+
+    uint32_t features;
+};
+
+/**
+ *  AVRCPU:
+ *  @env: #CPUAVRState
+ *
+ *  A AVR CPU.
+ */
+typedef struct AVRCPU {
+    /*< private >*/
+    CPUState parent_obj;
+    /*< public >*/
+
+    CPUNegativeOffsetState neg;
+    CPUAVRState env;
+} AVRCPU;
+
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vms_avr_cpu;
+#endif
+
+void avr_cpu_do_interrupt(CPUState *cpu);
+bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
+hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int avr_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+
+static inline int avr_feature(CPUAVRState *env, int feature)
+{
+    return (env->features & (1U << feature)) != 0;
+}
+
+static inline void avr_set_feature(CPUAVRState *env, int feature)
+{
+    env->features |= (1U << feature);
+}
+
+#define cpu_list avr_cpu_list
+#define cpu_signal_handler cpu_avr_signal_handler
+#define cpu_mmu_index avr_cpu_mmu_index
+
+static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
+{
+    return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
+}
+
+void avr_cpu_tcg_init(void);
+
+void avr_cpu_list(void);
+int cpu_avr_exec(CPUState *cpu);
+int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc);
+int avr_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
+                                int rw, int mmu_idx);
+int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf,
+                                int len, bool is_write);
+
+enum {
+    TB_FLAGS_FULL_ACCESS = 1,
+    TB_FLAGS_SKIP = 2,
+};
+
+static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong *pc,
+                                target_ulong *cs_base, uint32_t *pflags)
+{
+    uint32_t flags = 0;
+
+    *pc = env->pc_w * 2;
+    *cs_base = 0;
+
+    if (env->fullacc) {
+        flags |= TB_FLAGS_FULL_ACCESS;
+    }
+    if (env->skip) {
+        flags |= TB_FLAGS_SKIP;
+    }
+
+    *pflags = flags;
+}
+
+static inline int cpu_interrupts_enabled(CPUAVRState *env)
+{
+    return env->sregI != 0;
+}
+
+static inline uint8_t cpu_get_sreg(CPUAVRState *env)
+{
+    uint8_t sreg;
+    sreg = (env->sregC & 0x01) << 0
+         | (env->sregZ == 0 ? 1 : 0) << 1
+         | (env->sregN) << 2
+         | (env->sregV) << 3
+         | (env->sregS) << 4
+         | (env->sregH) << 5
+         | (env->sregT) << 6
+         | (env->sregI) << 7;
+    return sreg;
+}
+
+static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg)
+{
+    env->sregC = (sreg >> 0) & 0x01;
+    env->sregZ = (sreg >> 1) & 0x01 ? 0 : 1;
+    env->sregN = (sreg >> 2) & 0x01;
+    env->sregV = (sreg >> 3) & 0x01;
+    env->sregS = (sreg >> 4) & 0x01;
+    env->sregH = (sreg >> 5) & 0x01;
+    env->sregT = (sreg >> 6) & 0x01;
+    env->sregI = (sreg >> 7) & 0x01;
+}
+
+bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                        MMUAccessType access_type, int mmu_idx,
+                        bool probe, uintptr_t retaddr);
+
+typedef CPUAVRState CPUArchState;
+typedef AVRCPU ArchCPU;
+
+#include "exec/cpu-all.h"
+
+#endif /* !defined (QEMU_AVR_CPU_H) */
diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c
new file mode 100644
index 0000000000..20a5252482
--- /dev/null
+++ b/target/avr/gdbstub.c
@@ -0,0 +1,85 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
+
+int avr_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
+
+    /*  R */
+    if (n < 32) {
+        return gdb_get_reg8(mem_buf, env->r[n]);
+    }
+
+    /*  SREG */
+    if (n == 32) {
+        uint8_t sreg = cpu_get_sreg(env);
+
+        return gdb_get_reg8(mem_buf, sreg);
+    }
+
+    /*  SP */
+    if (n == 33) {
+        return gdb_get_reg16(mem_buf, env->sp & 0x0000ffff);
+    }
+
+    /*  PC */
+    if (n == 34) {
+        return gdb_get_reg32(mem_buf, env->pc_w * 2);
+    }
+
+    return 0;
+}
+
+int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
+
+    /*  R */
+    if (n < 32) {
+        env->r[n] = *mem_buf;
+        return 1;
+    }
+
+    /*  SREG */
+    if (n == 32) {
+        cpu_set_sreg(env, *mem_buf);
+        return 1;
+    }
+
+    /*  SP */
+    if (n == 33) {
+        env->sp = lduw_p(mem_buf);
+        return 2;
+    }
+
+    /*  PC */
+    if (n == 34) {
+        env->pc_w = ldl_p(mem_buf) / 2;
+        return 4;
+    }
+
+    return 0;
+}
diff --git a/target/avr/machine.c b/target/avr/machine.c
new file mode 100644
index 0000000000..f6dcda7adc
--- /dev/null
+++ b/target/avr/machine.c
@@ -0,0 +1,121 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+static int get_sreg(QEMUFile *f, void *opaque, size_t size,
+    const VMStateField *field)
+{
+    CPUAVRState *env = opaque;
+    uint8_t sreg;
+
+    sreg = qemu_get_byte(f);
+    cpu_set_sreg(env, sreg);
+    return 0;
+}
+
+static int put_sreg(
+    QEMUFile *f, void *opaque, size_t size,
+    const VMStateField *field, QJSON *vmdesc)
+{
+    CPUAVRState *env = opaque;
+    uint8_t sreg = cpu_get_sreg(env);
+
+    qemu_put_byte(f, sreg);
+    return 0;
+}
+
+static const VMStateInfo vms_sreg = {
+    .name = "sreg",
+    .get = get_sreg,
+    .put = put_sreg,
+};
+
+static int get_segment(
+    QEMUFile *f, void *opaque, size_t size, const VMStateField *field)
+{
+    uint32_t *ramp = opaque;
+    uint8_t temp;
+
+    temp = qemu_get_byte(f);
+    *ramp = ((uint32_t)temp) << 16;
+    return 0;
+}
+
+static int put_segment(
+    QEMUFile *f, void *opaque, size_t size,
+    const VMStateField *field, QJSON *vmdesc)
+{
+    uint32_t *ramp = opaque;
+    uint8_t temp = *ramp >> 16;
+
+    qemu_put_byte(f, temp);
+    return 0;
+}
+
+static const VMStateInfo vms_rampD = {
+    .name = "rampD",
+    .get = get_segment,
+    .put = put_segment,
+};
+static const VMStateInfo vms_rampX = {
+    .name = "rampX",
+    .get = get_segment,
+    .put = put_segment,
+};
+static const VMStateInfo vms_rampY = {
+    .name = "rampY",
+    .get = get_segment,
+    .put = put_segment,
+};
+static const VMStateInfo vms_rampZ = {
+    .name = "rampZ",
+    .get = get_segment,
+    .put = put_segment,
+};
+static const VMStateInfo vms_eind = {
+    .name = "eind",
+    .get = get_segment,
+    .put = put_segment,
+};
+
+const VMStateDescription vms_avr_cpu = {
+    .name = "cpu",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(env.pc_w, AVRCPU),
+        VMSTATE_UINT32(env.sp, AVRCPU),
+        VMSTATE_UINT32(env.skip, AVRCPU),
+
+        VMSTATE_UINT32_ARRAY(env.r, AVRCPU, NO_CPU_REGISTERS),
+
+        VMSTATE_SINGLE(env, AVRCPU, 0, vms_sreg, CPUAVRState),
+        VMSTATE_SINGLE(env.rampD, AVRCPU, 0, vms_rampD, uint32_t),
+        VMSTATE_SINGLE(env.rampX, AVRCPU, 0, vms_rampX, uint32_t),
+        VMSTATE_SINGLE(env.rampY, AVRCPU, 0, vms_rampY, uint32_t),
+        VMSTATE_SINGLE(env.rampZ, AVRCPU, 0, vms_rampZ, uint32_t),
+        VMSTATE_SINGLE(env.eind, AVRCPU, 0, vms_eind, uint32_t),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* [Qemu-devel] [PATCH v30 2/8] target/avr: Add instruction helpers
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 1/8] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
@ 2019-09-02 14:01 ` Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 3/8] target/avr: Add instruction decoding Michael Rolnik
                   ` (7 subsequent siblings)
  9 siblings, 0 replies; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo, philmd

Stubs for unimplemented instructions and helpers for instructions that need to interact with QEMU.
SPM and WDR are unimplemented because they require emulation of complex peripherals.
The implementation of SLEEP is very limited due to the lack of peripherals to generate wake interrupts.
Memory access instructions are implemented here because some address ranges actually refer to CPU registers.

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 target/avr/helper.c | 354 ++++++++++++++++++++++++++++++++++++++++++++
 target/avr/helper.h |  29 ++++
 2 files changed, 383 insertions(+)
 create mode 100644 target/avr/helper.c
 create mode 100644 target/avr/helper.h

diff --git a/target/avr/helper.c b/target/avr/helper.c
new file mode 100644
index 0000000000..f0f0d4f15a
--- /dev/null
+++ b/target/avr/helper.c
@@ -0,0 +1,354 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
+#include "exec/helper-proto.h"
+#include "exec/ioport.h"
+#include "qemu/host-utils.h"
+#include "qemu/error-report.h"
+
+bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+    bool ret = false;
+    CPUClass *cc = CPU_GET_CLASS(cs);
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
+
+    if (interrupt_request & CPU_INTERRUPT_RESET) {
+        if (cpu_interrupts_enabled(env)) {
+            cs->exception_index = EXCP_RESET;
+            cc->do_interrupt(cs);
+
+            cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
+
+            ret = true;
+        }
+    }
+    if (interrupt_request & CPU_INTERRUPT_HARD) {
+        if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
+            int index = ctz32(env->intsrc);
+            cs->exception_index = EXCP_INT(index);
+            cc->do_interrupt(cs);
+
+            env->intsrc &= env->intsrc - 1; /* clear the interrupt */
+            cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
+
+            ret = true;
+        }
+    }
+    return ret;
+}
+
+void avr_cpu_do_interrupt(CPUState *cs)
+{
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
+
+    uint32_t ret = env->pc_w;
+    int vector = 0;
+    int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
+    int base = 0;
+
+    if (cs->exception_index == EXCP_RESET) {
+        vector = 0;
+    } else if (env->intsrc != 0) {
+        vector = ctz32(env->intsrc) + 1;
+    }
+
+    if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
+        cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
+        cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
+    } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
+        cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
+    } else {
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
+    }
+
+    env->pc_w = base + vector * size;
+    env->sregI = 0; /* clear Global Interrupt Flag */
+
+    cs->exception_index = -1;
+}
+
+int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
+                                int len, bool is_write)
+{
+    return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
+}
+
+hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
+{
+    return addr; /* I assume 1:1 address correspondance */
+}
+
+int avr_cpu_handle_mmu_fault(
+    CPUState *cs, vaddr address, int size, int rw, int mmu_idx)
+{
+    /* currently it's assumed that this will never happen */
+    cs->exception_index = EXCP_DEBUG;
+    cpu_dump_state(cs, stderr, 0);
+    return 1;
+}
+
+bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                        MMUAccessType access_type, int mmu_idx,
+                        bool probe, uintptr_t retaddr)
+{
+    int prot = 0;
+    MemTxAttrs attrs = {};
+    uint32_t paddr;
+
+    address &= TARGET_PAGE_MASK;
+
+    if (mmu_idx == MMU_CODE_IDX) {
+        /* access to code in flash */
+        paddr = OFFSET_CODE + address;
+        prot = PAGE_READ | PAGE_EXEC;
+        if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
+            error_report("execution left flash memory");
+            exit(1);
+        }
+    } else if (address < NO_CPU_REGISTERS + NO_IO_REGISTERS) {
+        /*
+         * access to CPU registers, exit and rebuilt this TB to use full access
+         * incase it touches specially handled registers like SREG or SP
+         */
+        AVRCPU *cpu = AVR_CPU(cs);
+        CPUAVRState *env = &cpu->env;
+        env->fullacc = 1;
+        cpu_loop_exit_restore(cs, retaddr);
+    } else {
+        /* access to memory. nothing special */
+        paddr = OFFSET_DATA + address;
+        prot = PAGE_READ | PAGE_WRITE;
+    }
+
+    tlb_set_page_with_attrs(
+        cs, address, paddr, attrs, prot, mmu_idx, TARGET_PAGE_SIZE);
+
+    return true;
+}
+
+void helper_sleep(CPUAVRState *env)
+{
+    CPUState *cs = env_cpu(env);
+
+    cs->exception_index = EXCP_HLT;
+    cpu_loop_exit(cs);
+}
+
+void helper_unsupported(CPUAVRState *env)
+{
+    CPUState *cs = env_cpu(env);
+
+    /*
+     *  I count not find what happens on the real platform, so
+     *  it's EXCP_DEBUG for meanwhile
+     */
+    cs->exception_index = EXCP_DEBUG;
+    if (qemu_loglevel_mask(LOG_UNIMP)) {
+        qemu_log("UNSUPPORTED\n");
+        cpu_dump_state(cs, qemu_logfile, 0);
+    }
+    cpu_loop_exit(cs);
+}
+
+void helper_debug(CPUAVRState *env)
+{
+    CPUState *cs = env_cpu(env);
+
+    cs->exception_index = EXCP_DEBUG;
+    cpu_loop_exit(cs);
+}
+
+void helper_break(CPUAVRState *env)
+{
+    CPUState *cs = env_cpu(env);
+
+    cs->exception_index = EXCP_DEBUG;
+    cpu_loop_exit(cs);
+}
+
+void helper_wdr(CPUAVRState *env)
+{
+    CPUState *cs = env_cpu(env);
+
+    /* WD is not implemented yet, placeholder */
+    cs->exception_index = EXCP_DEBUG;
+    cpu_loop_exit(cs);
+}
+
+/*
+ * This function implements IN instruction
+ *
+ * It does the following
+ * a.  if an IO register belongs to CPU, its value is read and returned
+ * b.  otherwise io address is translated to mem address and physical memory
+ *     is read.
+ * c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
+ *
+ */
+target_ulong helper_inb(CPUAVRState *env, uint32_t port)
+{
+    target_ulong data = 0;
+
+    switch (port) {
+    case 0x38: /* RAMPD */
+        data = 0xff & (env->rampD >> 16);
+        break;
+    case 0x39: /* RAMPX */
+        data = 0xff & (env->rampX >> 16);
+        break;
+    case 0x3a: /* RAMPY */
+        data = 0xff & (env->rampY >> 16);
+        break;
+    case 0x3b: /* RAMPZ */
+        data = 0xff & (env->rampZ >> 16);
+        break;
+    case 0x3c: /* EIND */
+        data = 0xff & (env->eind >> 16);
+        break;
+    case 0x3d: /* SPL */
+        data = env->sp & 0x00ff;
+        break;
+    case 0x3e: /* SPH */
+        data = env->sp >> 8;
+        break;
+    case 0x3f: /* SREG */
+        data = cpu_get_sreg(env);
+        break;
+    default:
+        /* not a special register, pass to normal memory access */
+        cpu_physical_memory_read(OFFSET_IO_REGISTERS + port, &data, 1);
+    }
+
+    return data;
+}
+
+/*
+ *  This function implements OUT instruction
+ *
+ *  It does the following
+ *  a.  if an IO register belongs to CPU, its value is written into the register
+ *  b.  otherwise io address is translated to mem address and physical memory
+ *      is written.
+ *  c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
+ *
+ */
+void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
+{
+    data &= 0x000000ff;
+
+    switch (port) {
+    case 0x38: /* RAMPD */
+        if (avr_feature(env, AVR_FEATURE_RAMPD)) {
+            env->rampD = (data & 0xff) << 16;
+        }
+        break;
+    case 0x39: /* RAMPX */
+        if (avr_feature(env, AVR_FEATURE_RAMPX)) {
+            env->rampX = (data & 0xff) << 16;
+        }
+        break;
+    case 0x3a: /* RAMPY */
+        if (avr_feature(env, AVR_FEATURE_RAMPY)) {
+            env->rampY = (data & 0xff) << 16;
+        }
+        break;
+    case 0x3b: /* RAMPZ */
+        if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
+            env->rampZ = (data & 0xff) << 16;
+        }
+        break;
+    case 0x3c: /* EIDN */
+        env->eind = (data & 0xff) << 16;
+        break;
+    case 0x3d: /* SPL */
+        env->sp = (env->sp & 0xff00) | (data);
+        break;
+    case 0x3e: /* SPH */
+        if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
+            env->sp = (env->sp & 0x00ff) | (data << 8);
+        }
+        break;
+    case 0x3f: /* SREG */
+        cpu_set_sreg(env, data);
+        break;
+    default:
+        /* not a special register, pass to normal memory access */
+        cpu_physical_memory_write(OFFSET_IO_REGISTERS + port, &data, 1);
+    }
+}
+
+/*
+ *  this function implements LD instruction when there is a posibility to read
+ *  from a CPU register
+ */
+target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
+{
+    uint8_t data;
+
+    env->fullacc = false;
+
+    if (addr < NO_CPU_REGISTERS) {
+        /* CPU registers */
+        data = env->r[addr];
+    } else if (addr < NO_CPU_REGISTERS + NO_IO_REGISTERS) {
+        /* IO registers */
+        data = helper_inb(env, addr - NO_CPU_REGISTERS);
+    } else {
+        /* memory */
+        cpu_physical_memory_read(OFFSET_DATA + addr, &data, 1);
+    }
+    return data;
+}
+
+/*
+ *  this function implements ST instruction when there is a posibility to write
+ *  into a CPU register
+ */
+void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
+{
+    env->fullacc = false;
+
+    /* Following logic assumes this: */
+    assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
+    assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS + NO_CPU_REGISTERS);
+
+    if (addr < NO_CPU_REGISTERS) {
+        /* CPU registers */
+        env->r[addr] = data;
+    } else if (addr < NO_CPU_REGISTERS + NO_IO_REGISTERS) {
+        /* IO registers */
+        helper_outb(env, addr - NO_CPU_REGISTERS, data);
+    } else {
+        /* memory */
+        cpu_physical_memory_write(OFFSET_DATA + addr, &data, 1);
+    }
+}
diff --git a/target/avr/helper.h b/target/avr/helper.h
new file mode 100644
index 0000000000..bf087504a8
--- /dev/null
+++ b/target/avr/helper.h
@@ -0,0 +1,29 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+DEF_HELPER_1(wdr, void, env)
+DEF_HELPER_1(debug, void, env)
+DEF_HELPER_1(break, void, env)
+DEF_HELPER_1(sleep, void, env)
+DEF_HELPER_1(unsupported, void, env)
+DEF_HELPER_3(outb, void, env, i32, i32)
+DEF_HELPER_2(inb, tl, env, i32)
+DEF_HELPER_3(fullwr, void, env, i32, i32)
+DEF_HELPER_2(fullrd, tl, env, i32)
-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* [Qemu-devel] [PATCH v30 3/8] target/avr: Add instruction decoding
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 1/8] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 2/8] target/avr: Add instruction helpers Michael Rolnik
@ 2019-09-02 14:01 ` Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation Michael Rolnik
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo, philmd

This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 target/avr/insn.decode | 175 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 175 insertions(+)
 create mode 100644 target/avr/insn.decode

diff --git a/target/avr/insn.decode b/target/avr/insn.decode
new file mode 100644
index 0000000000..6b387762c6
--- /dev/null
+++ b/target/avr/insn.decode
@@ -0,0 +1,175 @@
+#
+#   A = [16 .. 31]
+#   B = [16 .. 23]
+#   C = [24, 26, 28, 30]
+#   D = [0, 2, 4, 6, 8, .. 30]
+
+%rd             4:5
+%rr             9:1 0:4
+
+&rd_rr          rd rr
+&rd_imm         rd imm
+
+@op_rd_rr       .... .. . ..... ....        &rd_rr      rd=%rd rr=%rr
+ADD             0000 11 . ..... ....        @op_rd_rr
+ADC             0001 11 . ..... ....        @op_rd_rr
+AND             0010 00 . ..... ....        @op_rd_rr
+CP              0001 01 . ..... ....        @op_rd_rr
+CPC             0000 01 . ..... ....        @op_rd_rr
+CPSE            0001 00 . ..... ....        @op_rd_rr
+EOR             0010 01 . ..... ....        @op_rd_rr
+MOV             0010 11 . ..... ....        @op_rd_rr
+MUL             1001 11 . ..... ....        @op_rd_rr
+OR              0010 10 . ..... ....        @op_rd_rr
+SBC             0000 10 . ..... ....        @op_rd_rr
+SUB             0001 10 . ..... ....        @op_rd_rr
+
+
+%rd_c           4:2                         !function=to_C
+%imm6           6:2 0:4
+
+@op_rd_imm6     .... .... .. .. ....        &rd_imm     rd=%rd_c imm=%imm6
+ADIW            1001 0110 .. .. ....        @op_rd_imm6
+SBIW            1001 0111 .. .. ....        @op_rd_imm6
+
+
+%rd_a           4:4                         !function=to_A
+%rr_a           0:4                         !function=to_A
+%rd_d           4:4                         !function=to_D
+%rr_d           0:4                         !function=to_D
+%imm8           8:4 0:4
+
+@op_rd_imm8     .... .... .... ....         &rd_imm     rd=%rd_a imm=%imm8
+ANDI            0111 .... .... ....         @op_rd_imm8
+CPI             0011 .... .... ....         @op_rd_imm8
+LDI             1110 .... .... ....         @op_rd_imm8
+ORI             0110 .... .... ....         @op_rd_imm8
+SBCI            0100 .... .... ....         @op_rd_imm8
+SUBI            0101 .... .... ....         @op_rd_imm8
+
+
+@op_rd          .... ... rd:5 ....
+ASR             1001 010 ..... 0101         @op_rd
+COM             1001 010 ..... 0000         @op_rd
+DEC             1001 010 ..... 1010         @op_rd
+ELPM2           1001 000 ..... 0110         @op_rd
+ELPMX           1001 000 ..... 0111         @op_rd
+INC             1001 010 ..... 0011         @op_rd
+LDX1            1001 000 ..... 1100         @op_rd
+LDX2            1001 000 ..... 1101         @op_rd
+LDX3            1001 000 ..... 1110         @op_rd
+LDY2            1001 000 ..... 1001         @op_rd
+LDY3            1001 000 ..... 1010         @op_rd
+LDZ2            1001 000 ..... 0001         @op_rd
+LDZ3            1001 000 ..... 0010         @op_rd
+LPM2            1001 000 ..... 0100         @op_rd
+LPMX            1001 000 ..... 0101         @op_rd
+LSR             1001 010 ..... 0110         @op_rd
+NEG             1001 010 ..... 0001         @op_rd
+POP             1001 000 ..... 1111         @op_rd
+PUSH            1001 001 ..... 1111         @op_rd
+ROR             1001 010 ..... 0111         @op_rd
+STY2            1001 001 ..... 1001         @op_rd
+STY3            1001 001 ..... 1010         @op_rd
+STZ2            1001 001 ..... 0001         @op_rd
+STZ3            1001 001 ..... 0010         @op_rd
+SWAP            1001 010 ..... 0010         @op_rd
+
+
+@op_bit         .... .... . bit:3 ....
+BCLR            1001 0100 1 ... 1000        @op_bit
+BSET            1001 0100 0 ... 1000        @op_bit
+
+
+@op_rd_bit      .... ... rd:5 . bit:3
+BLD             1111 100 ..... 0 ...        @op_rd_bit
+BST             1111 101 ..... 0 ...        @op_rd_bit
+
+
+@op_bit_imm     .... .. imm:s7 bit:3
+BRBC            1111 01 ....... ...         @op_bit_imm
+BRBS            1111 00 ....... ...         @op_bit_imm
+
+
+BREAK           1001 0101 1001 1000
+EICALL          1001 0101 0001 1001
+EIJMP           1001 0100 0001 1001
+ELPM1           1001 0101 1101 1000
+ICALL           1001 0101 0000 1001
+IJMP            1001 0100 0000 1001
+LPM1            1001 0101 1100 1000
+NOP             0000 0000 0000 0000
+RET             1001 0101 0000 1000
+RETI            1001 0101 0001 1000
+SLEEP           1001 0101 1000 1000
+SPM             1001 0101 1110 1000
+SPMX            1001 0101 1111 1000
+WDR             1001 0101 1010 1000
+
+
+@op_reg_bit     .... .... reg:5 bit:3
+CBI             1001 1000 ..... ...         @op_reg_bit
+SBI             1001 1010 ..... ...         @op_reg_bit
+SBIC            1001 1001 ..... ...         @op_reg_bit
+SBIS            1001 1011 ..... ...         @op_reg_bit
+
+
+DES             1001 0100 imm:4 1011
+
+
+%rd_b           4:3                         !function=to_B
+%rr_b           0:3                         !function=to_B
+@fmul           .... .... . ... . ...       &rd_rr      rd=%rd_b rr=%rr_b
+FMUL            0000 0011 0 ... 1 ...       @fmul
+FMULS           0000 0011 1 ... 0 ...       @fmul
+FMULSU          0000 0011 1 ... 1 ...       @fmul
+MULSU           0000 0011 0 ... 0 ...       @fmul
+
+
+%io_imm         9:2 0:4
+@io_rd_imm      .... . .. ..... ....        &rd_imm     rd=%rd imm=%io_imm
+IN              1011 0 .. ..... ....        @io_rd_imm
+OUT             1011 1 .. ..... ....        @io_rd_imm
+
+
+XCH             1001 001 rd:5 0100
+LAC             1001 001 rd:5 0110
+LAS             1001 001 rd:5 0101
+LAT             1001 001 rd:5 0111
+STX1            1001 001 rr:5 1100
+STX2            1001 001 rr:5 1101
+STX3            1001 001 rr:5 1110
+
+
+%ldst_d_imm     13:1 10:2 0:3
+@ldst_d         .. . . .. . rd:5  . ...     &rd_imm     imm=%ldst_d_imm
+LDDY            10 . 0 .. 0 ..... 1 ...     @ldst_d
+LDDZ            10 . 0 .. 0 ..... 0 ...     @ldst_d
+STDY            10 . 0 .. 1 ..... 1 ...     @ldst_d
+STDZ            10 . 0 .. 1 ..... 0 ...     @ldst_d
+
+
+MOVW            0000 0001 .... ....         &rd_rr      rd=%rd_d rr=%rr_d
+MULS            0000 0010 .... ....         &rd_rr      rd=%rd_a rr=%rr_a
+
+RCALL           1101 imm:s12
+RJMP            1100 imm:s12
+
+SBRC            1111 110 rr:5 0 bit:3
+SBRS            1111 111 rr:5 0 bit:3
+
+# The 22-bit immediate is partially in the opcode word,
+# and partially in the next.  Use append_16 to build the
+# complete 22-bit value.
+%imm_call       4:5 0:1                     !function=append_16
+CALL            1001 010 ..... 111 .        imm=%imm_call
+JMP             1001 010 ..... 110 .        imm=%imm_call
+
+
+# The 16-bit immediate is completely in the next word.
+# Fields cannot be defined with no bits, so we cannot play
+# the same trick and append to a zero-bit value.
+# Defer reading the immediate until trans_{LDS,STS}.
+@ldst_s         .... ... rd:5 ....          imm=0
+LDS             1001 000 ..... 0000         @ldst_s
+STS             1001 001 ..... 0000         @ldst_s
-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
                   ` (2 preceding siblings ...)
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 3/8] target/avr: Add instruction decoding Michael Rolnik
@ 2019-09-02 14:01 ` Michael Rolnik
  2019-10-11 14:13   ` Aleksandar Markovic
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 5/8] target/avr: Add limited support for USART and 16 bit timer peripherals Michael Rolnik
                   ` (5 subsequent siblings)
  9 siblings, 1 reply; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo, philmd

This includes:
- TCG translations for each instruction

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 target/avr/translate.c | 2888 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 2888 insertions(+)
 create mode 100644 target/avr/translate.c

diff --git a/target/avr/translate.c b/target/avr/translate.c
new file mode 100644
index 0000000000..42cb4a690c
--- /dev/null
+++ b/target/avr/translate.c
@@ -0,0 +1,2888 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/qemu-print.h"
+#include "tcg/tcg.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "disas/disas.h"
+#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
+#include "exec/helper-proto.h"
+#include "exec/helper-gen.h"
+#include "exec/log.h"
+#include "exec/gdbstub.h"
+#include "exec/translator.h"
+
+/*
+ *  Define if you want a BREAK instruction translated to a breakpoint
+ *  Active debugging connection is assumed
+ *  This is for
+ *  https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
+ *  tests
+ */
+#undef BREAKPOINT_ON_BREAK
+
+static TCGv cpu_pc;
+
+static TCGv cpu_Cf;
+static TCGv cpu_Zf;
+static TCGv cpu_Nf;
+static TCGv cpu_Vf;
+static TCGv cpu_Sf;
+static TCGv cpu_Hf;
+static TCGv cpu_Tf;
+static TCGv cpu_If;
+
+static TCGv cpu_rampD;
+static TCGv cpu_rampX;
+static TCGv cpu_rampY;
+static TCGv cpu_rampZ;
+
+static TCGv cpu_r[NO_CPU_REGISTERS];
+static TCGv cpu_eind;
+static TCGv cpu_sp;
+
+static TCGv cpu_skip;
+
+static const char reg_names[NO_CPU_REGISTERS][8] = {
+    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
+    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
+    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+};
+#define REG(x) (cpu_r[x])
+
+enum {
+    DISAS_EXIT   = DISAS_TARGET_0,  /* We want return to the cpu main loop.  */
+    DISAS_LOOKUP = DISAS_TARGET_1,  /* We have a variable condition exit.  */
+    DISAS_CHAIN  = DISAS_TARGET_2,  /* We have a single condition exit.  */
+};
+
+typedef struct DisasContext DisasContext;
+
+/* This is the state at translation time. */
+struct DisasContext {
+    TranslationBlock *tb;
+
+    CPUAVRState *env;
+    CPUState *cs;
+
+    target_long npc;
+    uint32_t opcode;
+
+    /* Routine used to access memory */
+    int memidx;
+    int bstate;
+    int singlestep;
+
+    TCGv skip_var0;
+    TCGv skip_var1;
+    TCGCond skip_cond;
+    bool free_skip_var0;
+};
+
+static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); }
+static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); }
+static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) * 2; }
+static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; }
+
+static uint16_t next_word(DisasContext *ctx)
+{
+    return cpu_lduw_code(ctx->env, ctx->npc++ * 2);
+}
+
+static int append_16(DisasContext *ctx, int x)
+{
+    return x << 16 | next_word(ctx);
+}
+
+static bool decode_insn(DisasContext *ctx, uint16_t insn);
+#include "decode_insn.inc.c"
+
+static bool avr_have_feature(DisasContext *ctx, int feature)
+{
+    if (!avr_feature(ctx->env, feature)) {
+        gen_helper_unsupported(cpu_env);
+        ctx->bstate = DISAS_NORETURN;
+        return false;
+    }
+    return true;
+}
+
+static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+{
+    TranslationBlock *tb = ctx->tb;
+
+    if (ctx->singlestep == 0) {
+        tcg_gen_goto_tb(n);
+        tcg_gen_movi_i32(cpu_pc, dest);
+        tcg_gen_exit_tb(tb, n);
+    } else {
+        tcg_gen_movi_i32(cpu_pc, dest);
+        gen_helper_debug(cpu_env);
+        tcg_gen_exit_tb(NULL, 0);
+    }
+    ctx->bstate = DISAS_NORETURN;
+}
+
+#include "exec/gen-icount.h"
+
+static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)
+{
+    TCGv t1 = tcg_temp_new_i32();
+    TCGv t2 = tcg_temp_new_i32();
+    TCGv t3 = tcg_temp_new_i32();
+
+    tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */
+    tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */
+    tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */
+    tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */
+    tcg_gen_or_tl(t1, t1, t3);
+
+    tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */
+    tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */
+    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+
+    tcg_temp_free_i32(t3);
+    tcg_temp_free_i32(t2);
+    tcg_temp_free_i32(t1);
+}
+
+static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr)
+{
+    TCGv t1 = tcg_temp_new_i32();
+    TCGv t2 = tcg_temp_new_i32();
+
+    /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R = (Rd ^ R) & ~(Rd ^ Rr) */
+    tcg_gen_xor_tl(t1, Rd, R);
+    tcg_gen_xor_tl(t2, Rd, Rr);
+    tcg_gen_andc_tl(t1, t1, t2);
+
+    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
+
+    tcg_temp_free_i32(t2);
+    tcg_temp_free_i32(t1);
+}
+
+static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)
+{
+    TCGv t1 = tcg_temp_new_i32();
+    TCGv t2 = tcg_temp_new_i32();
+    TCGv t3 = tcg_temp_new_i32();
+
+    /* Cf & Hf */
+    tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */
+    tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */
+    tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */
+    tcg_gen_and_tl(t3, t3, R);
+    tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
+    tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */
+    tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */
+    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+
+    tcg_temp_free_i32(t3);
+    tcg_temp_free_i32(t2);
+    tcg_temp_free_i32(t1);
+}
+
+static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr)
+{
+    TCGv t1 = tcg_temp_new_i32();
+    TCGv t2 = tcg_temp_new_i32();
+
+    /* Vf */
+    /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R = (Rd ^ R) & (Rd ^ R) */
+    tcg_gen_xor_tl(t1, Rd, R);
+    tcg_gen_xor_tl(t2, Rd, Rr);
+    tcg_gen_and_tl(t1, t1, t2);
+    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
+
+    tcg_temp_free_i32(t2);
+    tcg_temp_free_i32(t1);
+}
+
+static void gen_rshift_ZNVSf(TCGv R)
+{
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
+    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
+    tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf);
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+}
+
+static void gen_NSf(TCGv R)
+{
+    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+}
+
+static void gen_ZNSf(TCGv R)
+{
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
+    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+}
+
+static void gen_push_ret(DisasContext *ctx, int ret)
+{
+    if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
+
+        TCGv t0 = tcg_const_i32((ret & 0x0000ff));
+
+        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+        tcg_temp_free_i32(t0);
+    } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
+
+        TCGv t0 = tcg_const_i32((ret & 0x00ffff));
+
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+        tcg_temp_free_i32(t0);
+
+    } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
+
+        TCGv lo = tcg_const_i32((ret & 0x0000ff));
+        TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
+
+        tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
+        tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+        tcg_temp_free_i32(lo);
+        tcg_temp_free_i32(hi);
+    }
+}
+
+static void gen_pop_ret(DisasContext *ctx, TCGv ret)
+{
+    if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
+    } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+    } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
+        TCGv lo = tcg_temp_new_i32();
+        TCGv hi = tcg_temp_new_i32();
+
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+        tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
+        tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
+
+        tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
+
+        tcg_temp_free_i32(lo);
+        tcg_temp_free_i32(hi);
+    }
+}
+
+static void gen_jmp_ez(DisasContext *ctx)
+{
+    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
+    tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind);
+    ctx->bstate = DISAS_LOOKUP;
+}
+
+static void gen_jmp_z(DisasContext *ctx)
+{
+    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
+    ctx->bstate = DISAS_LOOKUP;
+}
+
+/*
+ *  in the gen_set_addr & gen_get_addr functions
+ *  H assumed to be in 0x00ff0000 format
+ *  M assumed to be in 0x000000ff format
+ *  L assumed to be in 0x000000ff format
+ */
+static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L)
+{
+
+    tcg_gen_andi_tl(L, addr, 0x000000ff);
+
+    tcg_gen_andi_tl(M, addr, 0x0000ff00);
+    tcg_gen_shri_tl(M, M, 8);
+
+    tcg_gen_andi_tl(H, addr, 0x00ff0000);
+}
+
+static void gen_set_xaddr(TCGv addr)
+{
+    gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]);
+}
+
+static void gen_set_yaddr(TCGv addr)
+{
+    gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]);
+}
+
+static void gen_set_zaddr(TCGv addr)
+{
+    gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]);
+}
+
+static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L)
+{
+    TCGv addr = tcg_temp_new_i32();
+
+    tcg_gen_deposit_tl(addr, M, H, 8, 8);
+    tcg_gen_deposit_tl(addr, L, addr, 8, 16);
+
+    return addr;
+}
+
+static TCGv gen_get_xaddr(void)
+{
+    return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]);
+}
+
+static TCGv gen_get_yaddr(void)
+{
+    return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]);
+}
+
+static TCGv gen_get_zaddr(void)
+{
+    return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]);
+}
+
+/*
+ *  Adds two registers and the contents of the C Flag and places the result in
+ *  the destination register Rd.
+ */
+static bool trans_ADC(DisasContext *ctx, arg_ADC *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */
+    tcg_gen_add_tl(R, R, cpu_Cf);
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_add_CHf(R, Rd, Rr);
+    gen_add_Vf(R, Rd, Rr);
+    gen_ZNSf(R);
+
+    /* R */
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  Adds two registers without the C Flag and places the result in the
+ *  destination register Rd.
+ */
+static bool trans_ADD(DisasContext *ctx, arg_ADD *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_add_CHf(R, Rd, Rr);
+    gen_add_Vf(R, Rd, Rr);
+    gen_ZNSf(R);
+
+    /* R */
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  Adds an immediate value (0 - 63) to a register pair and places the result
+ *  in the register pair. This instruction operates on the upper four register
+ *  pairs, and is well suited for operations on the pointer registers.  This
+ *  instruction is not available in all devices. Refer to the device specific
+ *  instruction set summary.
+ */
+static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) {
+        return true;
+    }
+
+    TCGv RdL = cpu_r[a->rd];
+    TCGv RdH = cpu_r[a->rd + 1];
+    int Imm = (a->imm);
+    TCGv R = tcg_temp_new_i32();
+    TCGv Rd = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */
+    tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */
+    tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */
+
+    /* Cf */
+    tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */
+    tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15);
+
+    /* Vf */
+    tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R & ~Rd */
+    tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15);
+
+    /* Zf */
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
+
+    /* Nf */
+    tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */
+
+    /* Sf */
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */
+
+    /* R */
+    tcg_gen_andi_tl(RdL, R, 0xff);
+    tcg_gen_shri_tl(RdH, R, 8);
+
+    tcg_temp_free_i32(Rd);
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  Performs the logical AND between the contents of register Rd and register
+ *  Rr and places the result in the destination register Rd.
+ */
+static bool trans_AND(DisasContext *ctx, arg_AND *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
+
+    /* Vf */
+    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
+
+    /* Zf */
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
+
+    gen_ZNSf(R);
+
+    /* R */
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  Performs the logical AND between the contents of register Rd and a constant
+ *  and places the result in the destination register Rd.
+ */
+static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    int Imm = (a->imm);
+
+    /* op */
+    tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd & Imm */
+
+    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
+    gen_ZNSf(Rd);
+
+    return true;
+}
+
+/*
+ *  Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0
+ *  is loaded into the C Flag of the SREG. This operation effectively divides a
+ *  signed value by two without changing its sign. The Carry Flag can be used to
+ *  round the result.
+ */
+static bool trans_ASR(DisasContext *ctx, arg_ASR *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv t0 = tcg_temp_new_i32();
+
+    /* Cf */
+    tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */
+
+    /* op */
+    tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */
+    tcg_gen_shri_tl(Rd, Rd, 1);
+    tcg_gen_or_tl(Rd, Rd, t0);
+
+    gen_rshift_ZNVSf(Rd);
+
+    tcg_temp_free_i32(t0);
+
+    return true;
+}
+
+/*
+ *  Clears a single Flag in SREG.
+ */
+static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
+{
+    switch (a->bit) {
+    case 0x00:
+        tcg_gen_movi_tl(cpu_Cf, 0x00);
+        break;
+    case 0x01:
+        tcg_gen_movi_tl(cpu_Zf, 0x01);
+        break;
+    case 0x02:
+        tcg_gen_movi_tl(cpu_Nf, 0x00);
+        break;
+    case 0x03:
+        tcg_gen_movi_tl(cpu_Vf, 0x00);
+        break;
+    case 0x04:
+        tcg_gen_movi_tl(cpu_Sf, 0x00);
+        break;
+    case 0x05:
+        tcg_gen_movi_tl(cpu_Hf, 0x00);
+        break;
+    case 0x06:
+        tcg_gen_movi_tl(cpu_Tf, 0x00);
+        break;
+    case 0x07:
+        tcg_gen_movi_tl(cpu_If, 0x00);
+        break;
+    }
+
+    return true;
+}
+
+/*
+ *  Copies the T Flag in the SREG (Status Register) to bit b in register Rd.
+ */
+static bool trans_BLD(DisasContext *ctx, arg_BLD *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv t1 = tcg_temp_new_i32();
+
+    tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */
+    tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */
+    tcg_gen_or_tl(Rd, Rd, t1);
+
+    tcg_temp_free_i32(t1);
+
+    return true;
+}
+
+/*
+ *  Conditional relative branch. Tests a single bit in SREG and branches
+ *  relatively to PC if the bit is cleared. This instruction branches relatively
+ *  to PC in either direction (PC - 63 < = destination <= PC + 64). The
+ *  parameter k is the offset from PC and is represented in two's complement
+ *  form.
+ */
+static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a)
+{
+    TCGLabel *not_taken = gen_new_label();
+    TCGCond cond = TCG_COND_EQ;
+    TCGv var;
+
+    switch (a->bit) {
+    case 0x00:
+        var = cpu_Cf;
+        break;
+    case 0x01:
+        cond = TCG_COND_NE;
+        var = cpu_Zf;
+        break;
+    case 0x02:
+        var = cpu_Nf;
+        break;
+    case 0x03:
+        var = cpu_Vf;
+        break;
+    case 0x04:
+        var = cpu_Sf;
+        break;
+    case 0x05:
+        var = cpu_Hf;
+        break;
+    case 0x06:
+        var = cpu_Tf;
+        break;
+    case 0x07:
+        var = cpu_If;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    tcg_gen_brcondi_i32(tcg_invert_cond(cond), var, 0, not_taken);
+    gen_goto_tb(ctx, 0, ctx->npc + a->imm);
+    gen_set_label(not_taken);
+
+    ctx->bstate = DISAS_CHAIN;
+    return true;
+}
+
+/*
+ *  Conditional relative branch. Tests a single bit in SREG and branches
+ *  relatively to PC if the bit is set. This instruction branches relatively to
+ *  PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k
+ *  is the offset from PC and is represented in two's complement form.
+ */
+static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a)
+{
+    TCGLabel *not_taken = gen_new_label();
+    TCGCond cond = TCG_COND_NE;
+    TCGv var;
+
+    switch (a->bit) {
+    case 0x00:
+        var = cpu_Cf;
+        break;
+    case 0x01:
+        cond = TCG_COND_EQ;
+        var = cpu_Zf;
+        break;
+    case 0x02:
+        var = cpu_Nf;
+        break;
+    case 0x03:
+        var = cpu_Vf;
+        break;
+    case 0x04:
+        var = cpu_Sf;
+        break;
+    case 0x05:
+        var = cpu_Hf;
+        break;
+    case 0x06:
+        var = cpu_Tf;
+        break;
+    case 0x07:
+        var = cpu_If;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    tcg_gen_brcondi_i32(tcg_invert_cond(cond), var, 0, not_taken);
+    gen_goto_tb(ctx, 0, ctx->npc + a->imm);
+    gen_set_label(not_taken);
+
+    ctx->bstate = DISAS_CHAIN;
+    return true;
+}
+
+/*
+ *  Sets a single Flag or bit in SREG.
+ */
+static bool trans_BSET(DisasContext *ctx, arg_BSET *a)
+{
+    switch (a->bit) {
+    case 0x00:
+        tcg_gen_movi_tl(cpu_Cf, 0x01);
+        break;
+    case 0x01:
+        tcg_gen_movi_tl(cpu_Zf, 0x00);
+        break;
+    case 0x02:
+        tcg_gen_movi_tl(cpu_Nf, 0x01);
+        break;
+    case 0x03:
+        tcg_gen_movi_tl(cpu_Vf, 0x01);
+        break;
+    case 0x04:
+        tcg_gen_movi_tl(cpu_Sf, 0x01);
+        break;
+    case 0x05:
+        tcg_gen_movi_tl(cpu_Hf, 0x01);
+        break;
+    case 0x06:
+        tcg_gen_movi_tl(cpu_Tf, 0x01);
+        break;
+    case 0x07:
+        tcg_gen_movi_tl(cpu_If, 0x01);
+        break;
+    }
+
+    return true;
+}
+
+/*
+ *  The BREAK instruction is used by the On-chip Debug system, and is
+ *  normally not used in the application software. When the BREAK instruction is
+ *  executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
+ *  Debugger access to internal resources.  If any Lock bits are set, or either
+ *  the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
+ *  instruction as a NOP and will not enter the Stopped mode.  This instruction
+ *  is not available in all devices. Refer to the device specific instruction
+ *  set summary.
+ */
+static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
+        return true;
+    }
+
+#ifdef BREAKPOINT_ON_BREAK
+    tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
+    gen_helper_debug(cpu_env);
+    ctx->bstate = DISAS_EXIT;
+#else
+    /* NOP */
+#endif
+
+    return true;
+}
+
+/*
+ *  Stores bit b from Rd to the T Flag in SREG (Status Register).
+ */
+static bool trans_BST(DisasContext *ctx, arg_BST *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+
+    tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit);
+    tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit);
+
+    return true;
+}
+
+/*
+ *  Calls to a subroutine within the entire Program memory. The return
+ *  address (to the instruction after the CALL) will be stored onto the Stack.
+ *  (See also RCALL). The Stack Pointer uses a post-decrement scheme during
+ *  CALL.  This instruction is not available in all devices. Refer to the device
+ *  specific instruction set summary.
+ */
+static bool trans_CALL(DisasContext *ctx, arg_CALL *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
+        return true;
+    }
+
+    int Imm = a->imm;
+    int ret = ctx->npc;
+
+    gen_push_ret(ctx, ret);
+    gen_goto_tb(ctx, 0, Imm);
+
+    return true;
+}
+
+/*
+ *  Clears a specified bit in an I/O Register. This instruction operates on
+ *  the lower 32 I/O Registers -- addresses 0-31.
+ */
+static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
+{
+    TCGv data = tcg_temp_new_i32();
+    TCGv port = tcg_const_i32(a->reg);
+
+    gen_helper_inb(data, cpu_env, port);
+    tcg_gen_andi_tl(data, data, ~(1 << a->bit));
+    gen_helper_outb(cpu_env, port, data);
+
+    tcg_temp_free_i32(data);
+    tcg_temp_free_i32(port);
+
+    return true;
+}
+
+/*
+ *  Clears the specified bits in register Rd. Performs the logical AND
+ *  between the contents of register Rd and the complement of the constant mask
+ *  K. The result will be placed in register Rd.
+ */
+static bool trans_COM(DisasContext *ctx, arg_COM *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv R = tcg_temp_new_i32();
+
+    tcg_gen_xori_tl(Rd, Rd, 0xff);
+
+    tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */
+    tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
+    gen_ZNSf(Rd);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction performs a compare between two registers Rd and Rr.
+ *  None of the registers are changed. All conditional branches can be used
+ *  after this instruction.
+ */
+static bool trans_CP(DisasContext *ctx, arg_CP *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_sub_CHf(R, Rd, Rr);
+    gen_sub_Vf(R, Rd, Rr);
+    gen_ZNSf(R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction performs a compare between two registers Rd and Rr and
+ *  also takes into account the previous carry. None of the registers are
+ *  changed. All conditional branches can be used after this instruction.
+ */
+static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
+    tcg_gen_sub_tl(R, R, cpu_Cf);
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_sub_CHf(R, Rd, Rr);
+    gen_sub_Vf(R, Rd, Rr);
+    gen_NSf(R);
+
+    /*
+     * Previous value remains unchanged when the result is zero;
+     * cleared otherwise.
+     */
+    tcg_gen_or_tl(cpu_Zf, cpu_Zf, R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction performs a compare between register Rd and a constant.
+ *  The register is not changed. All conditional branches can be used after this
+ *  instruction.
+ */
+static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    int Imm = a->imm;
+    TCGv Rr = tcg_const_i32(Imm);
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_sub_CHf(R, Rd, Rr);
+    gen_sub_Vf(R, Rd, Rr);
+    gen_ZNSf(R);
+
+    tcg_temp_free_i32(R);
+    tcg_temp_free_i32(Rr);
+
+    return true;
+}
+
+/*
+ *  This instruction performs a compare between two registers Rd and Rr, and
+ *  skips the next instruction if Rd = Rr.
+ */
+static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a)
+{
+    ctx->skip_cond = TCG_COND_EQ;
+    ctx->skip_var0 = cpu_r[a->rd];
+    ctx->skip_var1 = cpu_r[a->rr];
+    return true;
+}
+
+/*
+ *  Subtracts one -1- from the contents of register Rd and places the result
+ *  in the destination register Rd.  The C Flag in SREG is not affected by the
+ *  operation, thus allowing the DEC instruction to be used on a loop counter in
+ *  multiple-precision computations.  When operating on unsigned values, only
+ *  BREQ and BRNE branches can be expected to perform consistently.  When
+ *  operating on two's complement values, all signed branches are available.
+ */
+static bool trans_DEC(DisasContext *ctx, arg_DEC *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+
+    tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */
+    tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */
+
+    /* cpu_Vf = Rd == 0x7f */
+    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f);
+    gen_ZNSf(Rd);
+
+    return true;
+}
+
+/*
+ *  The module is an instruction set extension to the AVR CPU, performing
+ *  DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in
+ *  the CPU register file, registers R0-R7, where LSB of data is placed in LSB
+ *  of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including
+ *  parity bits) is placed in registers R8- R15, organized in the register file
+ *  with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES
+ *  instruction performs one round in the DES algorithm. Sixteen rounds must be
+ *  executed in increasing order to form the correct DES ciphertext or
+ *  plaintext. Intermediate results are stored in the register file (R0-R15)
+ *  after each DES instruction. The instruction's operand (K) determines which
+ *  round is executed, and the half carry flag (H) determines whether encryption
+ *  or decryption is performed.  The DES algorithm is described in
+ *  "Specifications for the Data Encryption Standard" (Federal Information
+ *  Processing Standards Publication 46). Intermediate results in this
+ *  implementation differ from the standard because the initial permutation and
+ *  the inverse initial permutation are performed each iteration. This does not
+ *  affect the result in the final ciphertext or plaintext, but reduces
+ *  execution time.
+ */
+static bool trans_DES(DisasContext *ctx, arg_DES *a)
+{
+    /* TODO */
+    if (!avr_have_feature(ctx, AVR_FEATURE_DES)) {
+        return true;
+    }
+
+    return true;
+}
+
+/*
+ *  Indirect call of a subroutine pointed to by the Z (16 bits) Pointer
+ *  Register in the Register File and the EIND Register in the I/O space. This
+ *  instruction allows for indirect calls to the entire 4M (words) Program
+ *  memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme
+ *  during EICALL.  This instruction is not available in all devices. Refer to
+ *  the device specific instruction set summary.
+ */
+static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
+        return true;
+    }
+
+    int ret = ctx->npc;
+
+    gen_push_ret(ctx, ret);
+    gen_jmp_ez(ctx);
+    return true;
+}
+
+/*
+ *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
+ *  Register in the Register File and the EIND Register in the I/O space. This
+ *  instruction allows for indirect jumps to the entire 4M (words) Program
+ *  memory space. See also IJMP.  This instruction is not available in all
+ *  devices. Refer to the device specific instruction set summary.
+ */
+static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
+        return true;
+    }
+
+    gen_jmp_ez(ctx);
+    return true;
+}
+
+/*
+ *  Loads one byte pointed to by the Z-register and the RAMPZ Register in
+ *  the I/O space, and places this byte in the destination register Rd. This
+ *  instruction features a 100% space effective constant initialization or
+ *  constant data fetch. The Program memory is organized in 16-bit words while
+ *  the Z-pointer is a byte address. Thus, the least significant bit of the
+ *  Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This
+ *  instruction can address the entire Program memory space. The Z-pointer
+ *  Register can either be left unchanged by the operation, or it can be
+ *  incremented. The incrementation applies to the entire 24-bit concatenation
+ *  of the RAMPZ and Z-pointer Registers.  Devices with Self-Programming
+ *  capability can use the ELPM instruction to read the Fuse and Lock bit value.
+ *  Refer to the device documentation for a detailed description.  This
+ *  instruction is not available in all devices. Refer to the device specific
+ *  instruction set summary.
+ */
+static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
+        return true;
+    }
+
+    TCGv Rd = cpu_r[0];
+    TCGv addr = gen_get_zaddr();
+
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
+        return true;
+    }
+
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) {
+        return true;
+    }
+
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
+
+    gen_set_zaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Performs the logical EOR between the contents of register Rd and
+ *  register Rr and places the result in the destination register Rd.
+ */
+static bool trans_EOR(DisasContext *ctx, arg_EOR *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+
+    tcg_gen_xor_tl(Rd, Rd, Rr);
+
+    tcg_gen_movi_tl(cpu_Vf, 0);
+    gen_ZNSf(Rd);
+
+    return true;
+}
+
+/*
+ *  This instruction performs 8-bit x 8-bit -> 16-bit unsigned
+ *  multiplication and shifts the result one bit left.
+ */
+static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
+        return true;
+    }
+
+    TCGv R0 = cpu_r[0];
+    TCGv R1 = cpu_r[1];
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */
+    tcg_gen_shli_tl(R, R, 1);
+
+    tcg_gen_andi_tl(R0, R, 0xff);
+    tcg_gen_shri_tl(R1, R, 8);
+    tcg_gen_andi_tl(R1, R1, 0xff);
+
+    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
+    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
+ *  and shifts the result one bit left.
+ */
+static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
+        return true;
+    }
+
+    TCGv R0 = cpu_r[0];
+    TCGv R1 = cpu_r[1];
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+    TCGv t0 = tcg_temp_new_i32();
+    TCGv t1 = tcg_temp_new_i32();
+
+    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
+    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */
+    tcg_gen_mul_tl(R, t0, t1); /* R = Rd *Rr */
+    tcg_gen_shli_tl(R, R, 1);
+
+    tcg_gen_andi_tl(R0, R, 0xff);
+    tcg_gen_shri_tl(R1, R, 8);
+    tcg_gen_andi_tl(R1, R1, 0xff);
+
+    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
+    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
+ *  and shifts the result one bit left.
+ */
+static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
+        return true;
+    }
+
+    TCGv R0 = cpu_r[0];
+    TCGv R1 = cpu_r[1];
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+    TCGv t0 = tcg_temp_new_i32();
+
+    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
+    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */
+    tcg_gen_shli_tl(R, R, 1);
+
+    tcg_gen_andi_tl(R0, R, 0xff);
+    tcg_gen_shri_tl(R1, R, 8);
+    tcg_gen_andi_tl(R1, R1, 0xff);
+
+    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
+    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
+
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  Calls to a subroutine within the entire 4M (words) Program memory. The
+ *  return address (to the instruction after the CALL) will be stored onto the
+ *  Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during
+ *  CALL.  This instruction is not available in all devices. Refer to the device
+ *  specific instruction set summary.
+ */
+static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
+        return true;
+    }
+
+    int ret = ctx->npc;
+
+    gen_push_ret(ctx, ret);
+    gen_jmp_z(ctx);
+
+    return true;
+}
+
+/*
+ *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
+ *  Register in the Register File. The Z-pointer Register is 16 bits wide and
+ *  allows jump within the lowest 64K words (128KB) section of Program memory.
+ *  This instruction is not available in all devices. Refer to the device
+ *  specific instruction set summary.
+ */
+static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
+        return true;
+    }
+
+    gen_jmp_z(ctx);
+
+    return true;
+}
+
+/*
+ *  Loads data from the I/O Space (Ports, Timers, Configuration Registers,
+ *  etc.) into register Rd in the Register File.
+ */
+static bool trans_IN(DisasContext *ctx, arg_IN *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv port = tcg_const_i32(a->imm);
+
+    gen_helper_inb(Rd, cpu_env, port);
+
+    tcg_temp_free_i32(port);
+
+    return true;
+}
+
+/*
+ *  Adds one -1- to the contents of register Rd and places the result in the
+ *  destination register Rd.  The C Flag in SREG is not affected by the
+ *  operation, thus allowing the INC instruction to be used on a loop counter in
+ *  multiple-precision computations.  When operating on unsigned numbers, only
+ *  BREQ and BRNE branches can be expected to perform consistently. When
+ *  operating on two's complement values, all signed branches are available.
+ */
+static bool trans_INC(DisasContext *ctx, arg_INC *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+
+    tcg_gen_addi_tl(Rd, Rd, 1);
+    tcg_gen_andi_tl(Rd, Rd, 0xff);
+
+    /* cpu_Vf = Rd == 0x80 */
+    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80);
+    gen_ZNSf(Rd);
+
+    return true;
+}
+
+/*
+ *  Jump to an address within the entire 4M (words) Program memory. See also
+ *  RJMP.  This instruction is not available in all devices. Refer to the device
+ *  specific instruction set summary.0
+ */
+static bool trans_JMP(DisasContext *ctx, arg_JMP *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
+        return true;
+    }
+
+    gen_goto_tb(ctx, 0, a->imm);
+
+    return true;
+}
+
+/*
+ *  Load one byte indirect from data space to register and stores an clear
+ *  the bits in data space specified by the register. The instruction can only
+ *  be used towards internal SRAM.  The data location is pointed to by the Z (16
+ *  bits) Pointer Register in the Register File. Memory access is limited to the
+ *  current data segment of 64KB. To access another data segment in devices with
+ *  more than 64KB data space, the RAMPZ in register in the I/O area has to be
+ *  changed.  The Z-pointer Register is left unchanged by the operation. This
+ *  instruction is especially suited for clearing status bits stored in SRAM.
+ */
+static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
+{
+    if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
+        gen_helper_fullwr(cpu_env, data, addr);
+    } else {
+        tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */
+    }
+}
+
+static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
+{
+    if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
+        gen_helper_fullrd(data, cpu_env, addr);
+    } else {
+        tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */
+    }
+}
+
+static bool trans_LAC(DisasContext *ctx, arg_LAC *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
+        return true;
+    }
+
+    TCGv Rr = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+    TCGv t0 = tcg_temp_new_i32();
+    TCGv t1 = tcg_temp_new_i32();
+
+    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
+        /* t1 = t0 & (0xff - Rr) = t0 and ~Rr */
+    tcg_gen_andc_tl(t1, t0, Rr);
+
+    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */
+    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Load one byte indirect from data space to register and set bits in data
+ *  space specified by the register. The instruction can only be used towards
+ *  internal SRAM.  The data location is pointed to by the Z (16 bits) Pointer
+ *  Register in the Register File. Memory access is limited to the current data
+ *  segment of 64KB. To access another data segment in devices with more than
+ *  64KB data space, the RAMPZ in register in the I/O area has to be changed.
+ *  The Z-pointer Register is left unchanged by the operation. This instruction
+ *  is especially suited for setting status bits stored in SRAM.
+ */
+static bool trans_LAS(DisasContext *ctx, arg_LAS *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
+        return true;
+    }
+
+    TCGv Rr = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+    TCGv t0 = tcg_temp_new_i32();
+    TCGv t1 = tcg_temp_new_i32();
+
+    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
+    tcg_gen_or_tl(t1, t0, Rr);
+
+    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */
+    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Load one byte indirect from data space to register and toggles bits in
+ *  the data space specified by the register.  The instruction can only be used
+ *  towards SRAM.  The data location is pointed to by the Z (16 bits) Pointer
+ *  Register in the Register File. Memory access is limited to the current data
+ *  segment of 64KB. To access another data segment in devices with more than
+ *  64KB data space, the RAMPZ in register in the I/O area has to be changed.
+ *  The Z-pointer Register is left unchanged by the operation. This instruction
+ *  is especially suited for changing status bits stored in SRAM.
+ */
+static bool trans_LAT(DisasContext *ctx, arg_LAT *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
+        return true;
+    }
+
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+    TCGv t0 = tcg_temp_new_i32();
+    TCGv t1 = tcg_temp_new_i32();
+
+    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
+    tcg_gen_xor_tl(t1, t0, Rd);
+
+    tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */
+    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Loads one byte indirect from the data space to a register. For parts
+ *  with SRAM, the data space consists of the Register File, I/O memory and
+ *  internal SRAM (and external SRAM if applicable). For parts without SRAM, the
+ *  data space consists of the Register File only. In some parts the Flash
+ *  Memory has been mapped to the data space and can be read using this command.
+ *  The EEPROM has a separate address space.  The data location is pointed to by
+ *  the X (16 bits) Pointer Register in the Register File. Memory access is
+ *  limited to the current data segment of 64KB. To access another data segment
+ *  in devices with more than 64KB data space, the RAMPX in register in the I/O
+ *  area has to be changed.  The X-pointer Register can either be left unchanged
+ *  by the operation, or it can be post-incremented or predecremented.  These
+ *  features are especially suited for accessing arrays, tables, and Stack
+ *  Pointer usage of the X-pointer Register. Note that only the low byte of the
+ *  X-pointer is updated in devices with no more than 256 bytes data space. For
+ *  such devices, the high byte of the pointer is not used by this instruction
+ *  and can be used for other purposes. The RAMPX Register in the I/O area is
+ *  updated in parts with more than 64KB data space or more than 64KB Program
+ *  memory, and the increment/decrement is added to the entire 24-bit address on
+ *  such devices.  Not all variants of this instruction is available in all
+ *  devices. Refer to the device specific instruction set summary.  In the
+ *  Reduced Core tinyAVR the LD instruction can be used to achieve the same
+ *  operation as LPM since the program memory is mapped to the data memory
+ *  space.
+ */
+static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_xaddr();
+
+    gen_data_load(ctx, Rd, addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_xaddr();
+
+    gen_data_load(ctx, Rd, addr);
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
+
+    gen_set_xaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_xaddr();
+
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
+    gen_data_load(ctx, Rd, addr);
+    gen_set_xaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Loads one byte indirect with or without displacement from the data space
+ *  to a register. For parts with SRAM, the data space consists of the Register
+ *  File, I/O memory and internal SRAM (and external SRAM if applicable). For
+ *  parts without SRAM, the data space consists of the Register File only. In
+ *  some parts the Flash Memory has been mapped to the data space and can be
+ *  read using this command. The EEPROM has a separate address space.  The data
+ *  location is pointed to by the Y (16 bits) Pointer Register in the Register
+ *  File. Memory access is limited to the current data segment of 64KB. To
+ *  access another data segment in devices with more than 64KB data space, the
+ *  RAMPY in register in the I/O area has to be changed.  The Y-pointer Register
+ *  can either be left unchanged by the operation, or it can be post-incremented
+ *  or predecremented.  These features are especially suited for accessing
+ *  arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that
+ *  only the low byte of the Y-pointer is updated in devices with no more than
+ *  256 bytes data space. For such devices, the high byte of the pointer is not
+ *  used by this instruction and can be used for other purposes. The RAMPY
+ *  Register in the I/O area is updated in parts with more than 64KB data space
+ *  or more than 64KB Program memory, and the increment/decrement/displacement
+ *  is added to the entire 24-bit address on such devices.  Not all variants of
+ *  this instruction is available in all devices. Refer to the device specific
+ *  instruction set summary.  In the Reduced Core tinyAVR the LD instruction can
+ *  be used to achieve the same operation as LPM since the program memory is
+ *  mapped to the data memory space.
+ */
+static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_yaddr();
+
+    gen_data_load(ctx, Rd, addr);
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
+
+    gen_set_yaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_yaddr();
+
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
+    gen_data_load(ctx, Rd, addr);
+    gen_set_yaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_yaddr();
+
+    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
+    gen_data_load(ctx, Rd, addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Loads one byte indirect with or without displacement from the data space
+ *  to a register. For parts with SRAM, the data space consists of the Register
+ *  File, I/O memory and internal SRAM (and external SRAM if applicable). For
+ *  parts without SRAM, the data space consists of the Register File only. In
+ *  some parts the Flash Memory has been mapped to the data space and can be
+ *  read using this command. The EEPROM has a separate address space.  The data
+ *  location is pointed to by the Z (16 bits) Pointer Register in the Register
+ *  File. Memory access is limited to the current data segment of 64KB. To
+ *  access another data segment in devices with more than 64KB data space, the
+ *  RAMPZ in register in the I/O area has to be changed.  The Z-pointer Register
+ *  can either be left unchanged by the operation, or it can be post-incremented
+ *  or predecremented.  These features are especially suited for Stack Pointer
+ *  usage of the Z-pointer Register, however because the Z-pointer Register can
+ *  be used for indirect subroutine calls, indirect jumps and table lookup, it
+ *  is often more convenient to use the X or Y-pointer as a dedicated Stack
+ *  Pointer. Note that only the low byte of the Z-pointer is updated in devices
+ *  with no more than 256 bytes data space. For such devices, the high byte of
+ *  the pointer is not used by this instruction and can be used for other
+ *  purposes. The RAMPZ Register in the I/O area is updated in parts with more
+ *  than 64KB data space or more than 64KB Program memory, and the
+ *  increment/decrement/displacement is added to the entire 24-bit address on
+ *  such devices.  Not all variants of this instruction is available in all
+ *  devices. Refer to the device specific instruction set summary.  In the
+ *  Reduced Core tinyAVR the LD instruction can be used to achieve the same
+ *  operation as LPM since the program memory is mapped to the data memory
+ *  space.  For using the Z-pointer for table lookup in Program memory see the
+ *  LPM and ELPM instructions.
+ */
+static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+
+    gen_data_load(ctx, Rd, addr);
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
+
+    gen_set_zaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
+    gen_data_load(ctx, Rd, addr);
+
+    gen_set_zaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+
+    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
+    gen_data_load(ctx, Rd, addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ * Loads an 8 bit constant directly to register 16 to 31.
+ */
+static bool trans_LDI(DisasContext *ctx, arg_LDI *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    int imm = a->imm;
+
+    tcg_gen_movi_tl(Rd, imm);
+
+    return true;
+}
+
+/*
+ *  Loads one byte from the data space to a register. For parts with SRAM,
+ *  the data space consists of the Register File, I/O memory and internal SRAM
+ *  (and external SRAM if applicable). For parts without SRAM, the data space
+ *  consists of the register file only. The EEPROM has a separate address space.
+ *  A 16-bit address must be supplied. Memory access is limited to the current
+ *  data segment of 64KB. The LDS instruction uses the RAMPD Register to access
+ *  memory above 64KB. To access another data segment in devices with more than
+ *  64KB data space, the RAMPD in register in the I/O area has to be changed.
+ *  This instruction is not available in all devices. Refer to the device
+ *  specific instruction set summary.
+ */
+static bool trans_LDS(DisasContext *ctx, arg_LDS *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = tcg_temp_new_i32();
+    TCGv H = cpu_rampD;
+    a->imm = next_word(ctx);
+
+    tcg_gen_mov_tl(addr, H); /* addr = H:M:L */
+    tcg_gen_shli_tl(addr, addr, 16);
+    tcg_gen_ori_tl(addr, addr, a->imm);
+
+    gen_data_load(ctx, Rd, addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Loads one byte pointed to by the Z-register into the destination
+ *  register Rd. This instruction features a 100% space effective constant
+ *  initialization or constant data fetch. The Program memory is organized in
+ *  16-bit words while the Z-pointer is a byte address. Thus, the least
+ *  significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high
+ *  byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of
+ *  Program memory. The Zpointer Register can either be left unchanged by the
+ *  operation, or it can be incremented. The incrementation does not apply to
+ *  the RAMPZ Register.  Devices with Self-Programming capability can use the
+ *  LPM instruction to read the Fuse and Lock bit values.  Refer to the device
+ *  documentation for a detailed description.  The LPM instruction is not
+ *  available in all devices. Refer to the device specific instruction set
+ *  summary
+ */
+static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
+        return true;
+    }
+
+    TCGv Rd = cpu_r[0];
+    TCGv addr = tcg_temp_new_i32();
+    TCGv H = cpu_r[31];
+    TCGv L = cpu_r[30];
+
+    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
+    tcg_gen_or_tl(addr, addr, L);
+
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
+        return true;
+    }
+
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = tcg_temp_new_i32();
+    TCGv H = cpu_r[31];
+    TCGv L = cpu_r[30];
+
+    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
+    tcg_gen_or_tl(addr, addr, L);
+
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) {
+        return true;
+    }
+
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = tcg_temp_new_i32();
+    TCGv H = cpu_r[31];
+    TCGv L = cpu_r[30];
+
+    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
+    tcg_gen_or_tl(addr, addr, L);
+
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
+
+    tcg_gen_andi_tl(L, addr, 0xff);
+
+    tcg_gen_shri_tl(addr, addr, 8);
+    tcg_gen_andi_tl(H, addr, 0xff);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is
+ *  loaded into the C Flag of the SREG. This operation effectively divides an
+ *  unsigned value by two. The C Flag can be used to round the result.
+ */
+static bool trans_LSR(DisasContext *ctx, arg_LSR *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+
+    tcg_gen_andi_tl(cpu_Cf, Rd, 1);
+
+    tcg_gen_shri_tl(Rd, Rd, 1);
+
+    tcg_gen_mov_tl(cpu_Zf, Rd);
+    tcg_gen_movi_tl(cpu_Nf, 0);
+    tcg_gen_mov_tl(cpu_Vf, cpu_Cf);
+    tcg_gen_mov_tl(cpu_Sf, cpu_Vf);
+
+    return true;
+}
+
+/*
+ *  This instruction makes a copy of one register into another. The source
+ *  register Rr is left unchanged, while the destination register Rd is loaded
+ *  with a copy of Rr.
+ */
+static bool trans_MOV(DisasContext *ctx, arg_MOV *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+
+    tcg_gen_mov_tl(Rd, Rr);
+
+    return true;
+}
+
+/*
+ *  This instruction makes a copy of one register pair into another register
+ *  pair. The source register pair Rr+1:Rr is left unchanged, while the
+ *  destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr.  This
+ *  instruction is not available in all devices. Refer to the device specific
+ *  instruction set summary.
+ */
+static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) {
+        return true;
+    }
+
+    TCGv RdL = cpu_r[a->rd];
+    TCGv RdH = cpu_r[a->rd + 1];
+    TCGv RrL = cpu_r[a->rr];
+    TCGv RrH = cpu_r[a->rr + 1];
+
+    tcg_gen_mov_tl(RdH, RrH);
+    tcg_gen_mov_tl(RdL, RrL);
+
+    return true;
+}
+
+/*
+ *  This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication.
+ */
+static bool trans_MUL(DisasContext *ctx, arg_MUL *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
+        return true;
+    }
+
+    TCGv R0 = cpu_r[0];
+    TCGv R1 = cpu_r[1];
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */
+
+    tcg_gen_andi_tl(R0, R, 0xff);
+    tcg_gen_shri_tl(R1, R, 8);
+
+    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */
+    tcg_gen_mov_tl(cpu_Zf, R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication.
+ */
+static bool trans_MULS(DisasContext *ctx, arg_MULS *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
+        return true;
+    }
+
+    TCGv R0 = cpu_r[0];
+    TCGv R1 = cpu_r[1];
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+    TCGv t0 = tcg_temp_new_i32();
+    TCGv t1 = tcg_temp_new_i32();
+
+    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
+    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */
+    tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */
+
+    tcg_gen_andi_tl(R0, R, 0xff);
+    tcg_gen_shri_tl(R1, R, 8);
+
+    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */
+    tcg_gen_mov_tl(cpu_Zf, R);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a
+ *  signed and an unsigned number.
+ */
+static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
+        return true;
+    }
+
+    TCGv R0 = cpu_r[0];
+    TCGv R1 = cpu_r[1];
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+    TCGv t0 = tcg_temp_new_i32();
+
+    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
+    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */
+
+    tcg_gen_andi_tl(R0, R, 0xff);
+    tcg_gen_shri_tl(R1, R, 8);
+
+    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
+    tcg_gen_mov_tl(cpu_Zf, R);
+
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  Replaces the contents of register Rd with its two's complement; the
+ *  value $80 is left unchanged.
+ */
+static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv t0 = tcg_const_i32(0);
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_sub_CHf(R, t0, Rd);
+    gen_sub_Vf(R, t0, Rd);
+    gen_ZNSf(R);
+
+    /* R */
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction performs a single cycle No Operation.
+ */
+static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
+{
+
+    /* NOP */
+
+    return true;
+}
+
+/*
+ *  Performs the logical OR between the contents of register Rd and register
+ *  Rr and places the result in the destination register Rd.
+ */
+static bool trans_OR(DisasContext *ctx, arg_OR *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    tcg_gen_or_tl(R, Rd, Rr);
+
+    tcg_gen_movi_tl(cpu_Vf, 0);
+    gen_ZNSf(R);
+
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  Performs the logical OR between the contents of register Rd and a
+ *  constant and places the result in the destination register Rd.
+ */
+static bool trans_ORI(DisasContext *ctx, arg_ORI *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    int Imm = (a->imm);
+
+    tcg_gen_ori_tl(Rd, Rd, Imm); /* Rd = Rd | Imm */
+
+    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
+    gen_ZNSf(Rd);
+
+    return true;
+}
+
+/*
+ *  Stores data from register Rr in the Register File to I/O Space (Ports,
+ *  Timers, Configuration Registers, etc.).
+ */
+static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv port = tcg_const_i32(a->imm);
+
+    gen_helper_outb(cpu_env, port, Rd);
+
+    tcg_temp_free_i32(port);
+
+    return true;
+}
+
+/*
+ *  This instruction loads register Rd with a byte from the STACK. The Stack
+ *  Pointer is pre-incremented by 1 before the POP.  This instruction is not
+ *  available in all devices. Refer to the device specific instruction set
+ *  summary.
+ */
+static bool trans_POP(DisasContext *ctx, arg_POP *a)
+{
+    /*
+     * Using a temp to work around some strange behaviour:
+     * tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+     * gen_data_load(ctx, Rd, cpu_sp);
+     * seems to cause the add to happen twice.
+     * This doesn't happen if either the add or the load is removed.
+     */
+    TCGv t1 = tcg_temp_new_i32();
+    TCGv Rd = cpu_r[a->rd];
+
+    tcg_gen_addi_tl(t1, cpu_sp, 1);
+    gen_data_load(ctx, Rd, t1);
+    tcg_gen_mov_tl(cpu_sp, t1);
+
+    return true;
+}
+
+/*
+ *  This instruction stores the contents of register Rr on the STACK. The
+ *  Stack Pointer is post-decremented by 1 after the PUSH.  This instruction is
+ *  not available in all devices. Refer to the device specific instruction set
+ *  summary.
+ */
+static bool trans_PUSH(DisasContext *ctx, arg_PUSH *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+
+    gen_data_store(ctx, Rd, cpu_sp);
+    tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+    return true;
+}
+
+/*
+ *  Relative call to an address within PC - 2K + 1 and PC + 2K (words). The
+ *  return address (the instruction after the RCALL) is stored onto the Stack.
+ *  See also CALL. For AVR microcontrollers with Program memory not exceeding 4K
+ *  words (8KB) this instruction can address the entire memory from every
+ *  address location. The Stack Pointer uses a post-decrement scheme during
+ *  RCALL.
+ */
+static bool trans_RCALL(DisasContext *ctx, arg_RCALL *a)
+{
+    int ret = ctx->npc;
+    int dst = ctx->npc + a->imm;
+
+    gen_push_ret(ctx, ret);
+    gen_goto_tb(ctx, 0, dst);
+
+    return true;
+}
+
+/*
+ *  Returns from subroutine. The return address is loaded from the STACK.
+ *  The Stack Pointer uses a preincrement scheme during RET.
+ */
+static bool trans_RET(DisasContext *ctx, arg_RET *a)
+{
+    gen_pop_ret(ctx, cpu_pc);
+
+    ctx->bstate = DISAS_LOOKUP;
+    return true;
+}
+
+/*
+ *  Returns from interrupt. The return address is loaded from the STACK and
+ *  the Global Interrupt Flag is set.  Note that the Status Register is not
+ *  automatically stored when entering an interrupt routine, and it is not
+ *  restored when returning from an interrupt routine. This must be handled by
+ *  the application program. The Stack Pointer uses a pre-increment scheme
+ *  during RETI.
+ */
+static bool trans_RETI(DisasContext *ctx, arg_RETI *a)
+{
+    gen_pop_ret(ctx, cpu_pc);
+    tcg_gen_movi_tl(cpu_If, 1);
+
+    /* Need to return to main loop to re-evaluate interrupts.  */
+    ctx->bstate = DISAS_EXIT;
+    return true;
+}
+
+/*
+ *  Relative jump to an address within PC - 2K +1 and PC + 2K (words). For
+ *  AVR microcontrollers with Program memory not exceeding 4K words (8KB) this
+ *  instruction can address the entire memory from every address location. See
+ *  also JMP.
+ */
+static bool trans_RJMP(DisasContext *ctx, arg_RJMP *a)
+{
+    int dst = ctx->npc + a->imm;
+
+    gen_goto_tb(ctx, 0, dst);
+
+    return true;
+}
+
+/*
+ *  Shifts all bits in Rd one place to the right. The C Flag is shifted into
+ *  bit 7 of Rd. Bit 0 is shifted into the C Flag.  This operation, combined
+ *  with ASR, effectively divides multi-byte signed values by two. Combined with
+ *  LSR it effectively divides multi-byte unsigned values by two. The Carry Flag
+ *  can be used to round the result.
+ */
+static bool trans_ROR(DisasContext *ctx, arg_ROR *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv t0 = tcg_temp_new_i32();
+
+    tcg_gen_shli_tl(t0, cpu_Cf, 7);
+    tcg_gen_andi_tl(cpu_Cf, Rd, 1);
+    tcg_gen_shri_tl(Rd, Rd, 1);
+    tcg_gen_or_tl(Rd, Rd, t0);
+
+    gen_rshift_ZNVSf(Rd);
+
+    tcg_temp_free_i32(t0);
+
+    return true;
+}
+
+/*
+ *  Subtracts two registers and subtracts with the C Flag and places the
+ *  result in the destination register Rd.
+ */
+static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
+    tcg_gen_sub_tl(R, R, cpu_Cf);
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_sub_CHf(R, Rd, Rr);
+    gen_sub_Vf(R, Rd, Rr);
+    gen_NSf(R);
+
+    /*
+     * Previous value remains unchanged when the result is zero;
+     * cleared otherwise.
+     */
+    tcg_gen_or_tl(cpu_Zf, cpu_Zf, R);
+
+    /* R */
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  SBCI -- Subtract Immediate with Carry
+ */
+static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = tcg_const_i32(a->imm);
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
+    tcg_gen_sub_tl(R, R, cpu_Cf);
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_sub_CHf(R, Rd, Rr);
+    gen_sub_Vf(R, Rd, Rr);
+    gen_NSf(R);
+
+    /*
+     * Previous value remains unchanged when the result is zero;
+     * cleared otherwise.
+     */
+    tcg_gen_or_tl(cpu_Zf, cpu_Zf, R);
+
+    /* R */
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(R);
+    tcg_temp_free_i32(Rr);
+
+    return true;
+}
+
+/*
+ *  Sets a specified bit in an I/O Register. This instruction operates on
+ *  the lower 32 I/O Registers -- addresses 0-31.
+ */
+static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
+{
+    TCGv data = tcg_temp_new_i32();
+    TCGv port = tcg_const_i32(a->reg);
+
+    gen_helper_inb(data, cpu_env, port);
+    tcg_gen_ori_tl(data, data, 1 << a->bit);
+    gen_helper_outb(cpu_env, port, data);
+
+    tcg_temp_free_i32(port);
+    tcg_temp_free_i32(data);
+
+    return true;
+}
+
+/*
+ *  This instruction tests a single bit in an I/O Register and skips the
+ *  next instruction if the bit is cleared. This instruction operates on the
+ *  lower 32 I/O Registers -- addresses 0-31.
+ */
+static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
+{
+    TCGv temp = tcg_const_i32(a->reg);
+
+    gen_helper_inb(temp, cpu_env, temp);
+    tcg_gen_andi_tl(temp, temp, 1 << a->bit);
+    ctx->skip_cond = TCG_COND_EQ;
+    ctx->skip_var0 = temp;
+    ctx->free_skip_var0 = true;
+
+    return true;
+}
+
+/*
+ *  This instruction tests a single bit in an I/O Register and skips the
+ *  next instruction if the bit is set. This instruction operates on the lower
+ *  32 I/O Registers -- addresses 0-31.
+ */
+static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
+{
+    TCGv temp = tcg_const_i32(a->reg);
+
+    gen_helper_inb(temp, cpu_env, temp);
+    tcg_gen_andi_tl(temp, temp, 1 << a->bit);
+    ctx->skip_cond = TCG_COND_NE;
+    ctx->skip_var0 = temp;
+    ctx->free_skip_var0 = true;
+
+    return true;
+}
+
+/*
+ *  Subtracts an immediate value (0-63) from a register pair and places the
+ *  result in the register pair. This instruction operates on the upper four
+ *  register pairs, and is well suited for operations on the Pointer Registers.
+ *  This instruction is not available in all devices. Refer to the device
+ *  specific instruction set summary.
+ */
+static bool trans_SBIW(DisasContext *ctx, arg_SBIW *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) {
+        return true;
+    }
+
+    TCGv RdL = cpu_r[a->rd];
+    TCGv RdH = cpu_r[a->rd + 1];
+    int Imm = (a->imm);
+    TCGv R = tcg_temp_new_i32();
+    TCGv Rd = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */
+    tcg_gen_subi_tl(R, Rd, Imm); /* R = Rd - Imm */
+    tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */
+
+    /* Cf */
+    tcg_gen_andc_tl(cpu_Cf, R, Rd);
+    tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); /* Cf = R & ~Rd */
+
+    /* Vf */
+    tcg_gen_andc_tl(cpu_Vf, Rd, R);
+    tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); /* Vf = Rd & ~R */
+
+    /* Zf */
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
+
+    /* Nf */
+    tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */
+
+    /* Sf */
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+
+    /* R */
+    tcg_gen_andi_tl(RdL, R, 0xff);
+    tcg_gen_shri_tl(RdH, R, 8);
+
+    tcg_temp_free_i32(Rd);
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  This instruction tests a single bit in a register and skips the next
+ *  instruction if the bit is cleared.
+ */
+static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a)
+{
+    TCGv Rr = cpu_r[a->rr];
+
+    ctx->skip_cond = TCG_COND_EQ;
+    ctx->skip_var0 = tcg_temp_new();
+    ctx->free_skip_var0 = true;
+
+    tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit);
+    return true;
+}
+
+/*
+ *  This instruction tests a single bit in a register and skips the next
+ *  instruction if the bit is set.
+ */
+static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
+{
+    TCGv Rr = cpu_r[a->rr];
+
+    ctx->skip_cond = TCG_COND_NE;
+    ctx->skip_var0 = tcg_temp_new();
+    ctx->free_skip_var0 = true;
+
+    tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit);
+    return true;
+}
+
+/*
+ *  This instruction sets the circuit in sleep mode defined by the MCU
+ *  Control Register.
+ */
+static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
+{
+    gen_helper_sleep(cpu_env);
+    ctx->bstate = DISAS_NORETURN;
+    return true;
+}
+
+/*
+ *  SPM can be used to erase a page in the Program memory, to write a page
+ *  in the Program memory (that is already erased), and to set Boot Loader Lock
+ *  bits. In some devices, the Program memory can be written one word at a time,
+ *  in other devices an entire page can be programmed simultaneously after first
+ *  filling a temporary page buffer. In all cases, the Program memory must be
+ *  erased one page at a time. When erasing the Program memory, the RAMPZ and
+ *  Z-register are used as page address. When writing the Program memory, the
+ *  RAMPZ and Z-register are used as page or word address, and the R1:R0
+ *  register pair is used as data(1). When setting the Boot Loader Lock bits,
+ *  the R1:R0 register pair is used as data. Refer to the device documentation
+ *  for detailed description of SPM usage. This instruction can address the
+ *  entire Program memory.  The SPM instruction is not available in all devices.
+ *  Refer to the device specific instruction set summary.  Note: 1. R1
+ *  determines the instruction high byte, and R0 determines the instruction low
+ *  byte.
+ */
+static bool trans_SPM(DisasContext *ctx, arg_SPM *a)
+{
+    /* TODO */
+    if (!avr_have_feature(ctx, AVR_FEATURE_SPM)) {
+        return true;
+    }
+
+    return true;
+}
+
+static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a)
+{
+    /* TODO */
+    if (!avr_have_feature(ctx, AVR_FEATURE_SPMX)) {
+        return true;
+    }
+
+    return true;
+}
+
+static bool trans_STX1(DisasContext *ctx, arg_STX1 *a)
+{
+    TCGv Rd = cpu_r[a->rr];
+    TCGv addr = gen_get_xaddr();
+
+    gen_data_store(ctx, Rd, addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_STX2(DisasContext *ctx, arg_STX2 *a)
+{
+    TCGv Rd = cpu_r[a->rr];
+    TCGv addr = gen_get_xaddr();
+
+    gen_data_store(ctx, Rd, addr);
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
+    gen_set_xaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_STX3(DisasContext *ctx, arg_STX3 *a)
+{
+    TCGv Rd = cpu_r[a->rr];
+    TCGv addr = gen_get_xaddr();
+
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
+    gen_data_store(ctx, Rd, addr);
+    gen_set_xaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_STY2(DisasContext *ctx, arg_STY2 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_yaddr();
+
+    gen_data_store(ctx, Rd, addr);
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
+    gen_set_yaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_STY3(DisasContext *ctx, arg_STY3 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_yaddr();
+
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
+    gen_data_store(ctx, Rd, addr);
+    gen_set_yaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_STDY(DisasContext *ctx, arg_STDY *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_yaddr();
+
+    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
+    gen_data_store(ctx, Rd, addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+
+    gen_data_store(ctx, Rd, addr);
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
+
+    gen_set_zaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
+    gen_data_store(ctx, Rd, addr);
+
+    gen_set_zaddr(addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = gen_get_zaddr();
+
+    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
+    gen_data_store(ctx, Rd, addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Stores one byte from a Register to the data space. For parts with SRAM,
+ *  the data space consists of the Register File, I/O memory and internal SRAM
+ *  (and external SRAM if applicable). For parts without SRAM, the data space
+ *  consists of the Register File only. The EEPROM has a separate address space.
+ *  A 16-bit address must be supplied. Memory access is limited to the current
+ *  data segment of 64KB. The STS instruction uses the RAMPD Register to access
+ *  memory above 64KB. To access another data segment in devices with more than
+ *  64KB data space, the RAMPD in register in the I/O area has to be changed.
+ *  This instruction is not available in all devices. Refer to the device
+ *  specific instruction set summary.
+ */
+static bool trans_STS(DisasContext *ctx, arg_STS *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv addr = tcg_temp_new_i32();
+    TCGv H = cpu_rampD;
+    a->imm = next_word(ctx);
+
+    tcg_gen_mov_tl(addr, H); /* addr = H:M:L */
+    tcg_gen_shli_tl(addr, addr, 16);
+    tcg_gen_ori_tl(addr, addr, a->imm);
+
+    gen_data_store(ctx, Rd, addr);
+
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+/*
+ *  Subtracts two registers and places the result in the destination
+ *  register Rd.
+ */
+static bool trans_SUB(DisasContext *ctx, arg_SUB *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = cpu_r[a->rr];
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_sub_CHf(R, Rd, Rr);
+    gen_sub_Vf(R, Rd, Rr);
+    gen_ZNSf(R);
+
+    /* R */
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(R);
+
+    return true;
+}
+
+/*
+ *  Subtracts a register and a constant and places the result in the
+ *  destination register Rd. This instruction is working on Register R16 to R31
+ *  and is very well suited for operations on the X, Y, and Z-pointers.
+ */
+static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv Rr = tcg_const_i32(a->imm);
+    TCGv R = tcg_temp_new_i32();
+
+    /* op */
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+    gen_sub_CHf(R, Rd, Rr);
+    gen_sub_Vf(R, Rd, Rr);
+    gen_ZNSf(R);
+
+    /* R */
+    tcg_gen_mov_tl(Rd, R);
+
+    tcg_temp_free_i32(R);
+    tcg_temp_free_i32(Rr);
+
+    return true;
+}
+
+/*
+ *  Swaps high and low nibbles in a register.
+ */
+static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
+{
+    TCGv Rd = cpu_r[a->rd];
+    TCGv t0 = tcg_temp_new_i32();
+    TCGv t1 = tcg_temp_new_i32();
+
+    tcg_gen_andi_tl(t0, Rd, 0x0f);
+    tcg_gen_shli_tl(t0, t0, 4);
+    tcg_gen_andi_tl(t1, Rd, 0xf0);
+    tcg_gen_shri_tl(t1, t1, 4);
+    tcg_gen_or_tl(Rd, t0, t1);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t0);
+
+    return true;
+}
+
+/*
+ *  This instruction resets the Watchdog Timer. This instruction must be
+ *  executed within a limited time given by the WD prescaler. See the Watchdog
+ *  Timer hardware specification.
+ */
+static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
+{
+    gen_helper_wdr(cpu_env);
+
+    return true;
+}
+
+/*
+ *  Exchanges one byte indirect between register and data space.  The data
+ *  location is pointed to by the Z (16 bits) Pointer Register in the Register
+ *  File. Memory access is limited to the current data segment of 64KB. To
+ *  access another data segment in devices with more than 64KB data space, the
+ *  RAMPZ in register in the I/O area has to be changed.  The Z-pointer Register
+ *  is left unchanged by the operation. This instruction is especially suited
+ *  for writing/reading status bits stored in SRAM.
+ */
+static bool trans_XCH(DisasContext *ctx, arg_XCH *a)
+{
+    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
+        return true;
+    }
+
+    TCGv Rd = cpu_r[a->rd];
+    TCGv t0 = tcg_temp_new_i32();
+    TCGv addr = gen_get_zaddr();
+
+    gen_data_load(ctx, t0, addr);
+    gen_data_store(ctx, Rd, addr);
+    tcg_gen_mov_tl(Rd, t0);
+
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(addr);
+
+    return true;
+}
+
+void avr_cpu_tcg_init(void)
+{
+    int i;
+
+#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
+    cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc");
+    cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");
+    cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf");
+    cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf");
+    cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf");
+    cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf");
+    cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf");
+    cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf");
+    cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If");
+    cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD");
+    cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX");
+    cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY");
+    cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ");
+    cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind");
+    cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp");
+    cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip");
+
+    for (i = 0; i < NO_CPU_REGISTERS; i++) {
+        cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]),
+                                          reg_names[i]);
+    }
+#undef AVR_REG_OFFS
+}
+
+static void translate(DisasContext *ctx)
+{
+    uint32_t opcode = next_word(ctx);
+
+    if (!decode_insn(ctx, opcode)) {
+        gen_helper_unsupported(cpu_env);
+        ctx->bstate = DISAS_NORETURN;
+    }
+}
+
+/* Standardize the cpu_skip condition to NE.  */
+static bool canonicalize_skip(DisasContext *ctx)
+{
+    switch (ctx->skip_cond) {
+    case TCG_COND_NEVER:
+        /* Normal case: cpu_skip is known to be false.  */
+        return false;
+
+    case TCG_COND_ALWAYS:
+        /*
+         * Breakpoint case: cpu_skip is known to be true, via TB_FLAGS_SKIP.
+         * The breakpoint is on the instruction being skipped, at the start
+         * of the TranslationBlock.  No need to update.
+         */
+        return false;
+
+    case TCG_COND_NE:
+        if (ctx->skip_var1 == NULL) {
+            tcg_gen_mov_tl(cpu_skip, ctx->skip_var0);
+        } else {
+            tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1);
+            ctx->skip_var1 = NULL;
+        }
+        break;
+
+    default:
+        /* Convert to a NE condition vs 0. */
+        if (ctx->skip_var1 == NULL) {
+            tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0, 0);
+        } else {
+            tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip,
+                               ctx->skip_var0, ctx->skip_var1);
+            ctx->skip_var1 = NULL;
+        }
+        ctx->skip_cond = TCG_COND_NE;
+        break;
+    }
+    if (ctx->free_skip_var0) {
+        tcg_temp_free(ctx->skip_var0);
+        ctx->free_skip_var0 = false;
+    }
+    ctx->skip_var0 = cpu_skip;
+    return true;
+}
+
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
+{
+    CPUAVRState *env = cs->env_ptr;
+    DisasContext ctx = {
+        .tb = tb,
+        .cs = cs,
+        .env = env,
+        .memidx = 0,
+        .bstate = DISAS_NEXT,
+        .skip_cond = TCG_COND_NEVER,
+        .singlestep = cs->singlestep_enabled,
+    };
+    target_ulong pc_start = tb->pc / 2;
+    int num_insns = 0;
+
+    if (tb->flags & TB_FLAGS_FULL_ACCESS) {
+        /*
+         * This flag is set by ST/LD instruction we will regenerate it ONLY
+         * with mem/cpu memory access instead of mem access
+         */
+        max_insns = 1;
+    }
+    if (ctx.singlestep) {
+        max_insns = 1;
+    }
+
+    gen_tb_start(tb);
+
+    ctx.npc = pc_start;
+    if (tb->flags & TB_FLAGS_SKIP) {
+        ctx.skip_cond = TCG_COND_ALWAYS;
+        ctx.skip_var0 = cpu_skip;
+    }
+
+    do {
+        TCGLabel *skip_label = NULL;
+
+        /* translate current instruction */
+        tcg_gen_insn_start(ctx.npc);
+        num_insns++;
+
+        /*
+         * this is due to some strange GDB behavior
+         * let's assume main has address 0x100
+         * b main   - sets breakpoint at address 0x00000100 (code)
+         * b *0x100 - sets breakpoint at address 0x00800100 (data)
+         */
+        if (unlikely(!ctx.singlestep &&
+                (cpu_breakpoint_test(cs, OFFSET_CODE + ctx.npc * 2, BP_ANY) ||
+                 cpu_breakpoint_test(cs, OFFSET_DATA + ctx.npc * 2, BP_ANY)))) {
+            canonicalize_skip(&ctx);
+            tcg_gen_movi_tl(cpu_pc, ctx.npc);
+            gen_helper_debug(cpu_env);
+            goto done_generating;
+        }
+
+        /* Conditionally skip the next instruction, if indicated.  */
+        if (ctx.skip_cond != TCG_COND_NEVER) {
+            skip_label = gen_new_label();
+            if (ctx.skip_var0 == cpu_skip) {
+                /*
+                 * Copy cpu_skip so that we may zero it before the branch.
+                 * This ensures that cpu_skip is non-zero after the label
+                 * if and only if the skipped insn itself sets a skip.
+                 */
+                ctx.free_skip_var0 = true;
+                ctx.skip_var0 = tcg_temp_new();
+                tcg_gen_mov_tl(ctx.skip_var0, cpu_skip);
+                tcg_gen_movi_tl(cpu_skip, 0);
+            }
+            if (ctx.skip_var1 == NULL) {
+                tcg_gen_brcondi_tl(ctx.skip_cond, ctx.skip_var0, 0, skip_label);
+            } else {
+                tcg_gen_brcond_tl(ctx.skip_cond, ctx.skip_var0,
+                                  ctx.skip_var1, skip_label);
+                ctx.skip_var1 = NULL;
+            }
+            if (ctx.free_skip_var0) {
+                tcg_temp_free(ctx.skip_var0);
+                ctx.free_skip_var0 = false;
+            }
+            ctx.skip_cond = TCG_COND_NEVER;
+            ctx.skip_var0 = NULL;
+        }
+
+        translate(&ctx);
+
+        if (skip_label) {
+            canonicalize_skip(&ctx);
+            gen_set_label(skip_label);
+            if (ctx.bstate == DISAS_NORETURN) {
+                ctx.bstate = DISAS_CHAIN;
+            }
+        }
+    } while (ctx.bstate == DISAS_NEXT
+             && num_insns < max_insns
+             && (ctx.npc - pc_start) * 2 < TARGET_PAGE_SIZE - 4
+             && !tcg_op_buf_full());
+
+    if (tb->cflags & CF_LAST_IO) {
+        gen_io_end();
+    }
+
+    bool nonconst_skip = canonicalize_skip(&ctx);
+
+    switch (ctx.bstate) {
+    case DISAS_NORETURN:
+        assert(!nonconst_skip);
+        break;
+    case DISAS_NEXT:
+    case DISAS_TOO_MANY:
+    case DISAS_CHAIN:
+        if (!nonconst_skip) {
+            /* Note gen_goto_tb checks singlestep.  */
+            gen_goto_tb(&ctx, 1, ctx.npc);
+            break;
+        }
+        tcg_gen_movi_tl(cpu_pc, ctx.npc);
+        /* fall through */
+    case DISAS_LOOKUP:
+        if (!ctx.singlestep) {
+            tcg_gen_lookup_and_goto_ptr();
+            break;
+        }
+        /* fall through */
+    case DISAS_EXIT:
+        if (ctx.singlestep) {
+            gen_helper_debug(cpu_env);
+        } else {
+            tcg_gen_exit_tb(NULL, 0);
+        }
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+done_generating:
+    gen_tb_end(tb, num_insns);
+
+    tb->size = (ctx.npc - pc_start) * 2;
+    tb->icount = num_insns;
+}
+
+void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb,
+                            target_ulong *data)
+{
+    env->pc_w = data[0];
+}
-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* [Qemu-devel] [PATCH v30 5/8] target/avr: Add limited support for USART and 16 bit timer peripherals
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
                   ` (3 preceding siblings ...)
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation Michael Rolnik
@ 2019-09-02 14:01 ` Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 6/8] target/avr: Add example board configuration Michael Rolnik
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, richard.henderson, Sarah Harris, dovgaluk, imammedo, philmd

From: Sarah Harris <S.E.Harris@kent.ac.uk>

These were designed to facilitate testing but should provide enough function to be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins).

Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
---
 hw/char/Kconfig                |   3 +
 hw/char/Makefile.objs          |   1 +
 hw/char/avr_usart.c            | 324 ++++++++++++++++++
 hw/misc/Kconfig                |   3 +
 hw/misc/Makefile.objs          |   2 +
 hw/misc/avr_mask.c             | 112 ++++++
 hw/timer/Kconfig               |   3 +
 hw/timer/Makefile.objs         |   1 +
 hw/timer/avr_timer16.c         | 605 +++++++++++++++++++++++++++++++++
 include/hw/char/avr_usart.h    |  97 ++++++
 include/hw/misc/avr_mask.h     |  47 +++
 include/hw/timer/avr_timer16.h |  97 ++++++
 12 files changed, 1295 insertions(+)
 create mode 100644 hw/char/avr_usart.c
 create mode 100644 hw/misc/avr_mask.c
 create mode 100644 hw/timer/avr_timer16.c
 create mode 100644 include/hw/char/avr_usart.h
 create mode 100644 include/hw/misc/avr_mask.h
 create mode 100644 include/hw/timer/avr_timer16.h

diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 40e7a8b8bb..331b20983f 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -46,3 +46,6 @@ config SCLPCONSOLE
 
 config TERMINAL3270
     bool
+
+config AVR_USART
+    bool
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index 02d8a66925..09ed50f1d0 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -21,6 +21,7 @@ obj-$(CONFIG_PSERIES) += spapr_vty.o
 obj-$(CONFIG_DIGIC) += digic-uart.o
 obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
 obj-$(CONFIG_RASPI) += bcm2835_aux.o
+obj-$(CONFIG_AVR_USART) += avr_usart.o
 
 common-obj-$(CONFIG_CMSDK_APB_UART) += cmsdk-apb-uart.o
 common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c
new file mode 100644
index 0000000000..9ca3c2a1cd
--- /dev/null
+++ b/hw/char/avr_usart.c
@@ -0,0 +1,324 @@
+/*
+ * AVR USART
+ *
+ * Copyright (c) 2018 University of Kent
+ * Author: Sarah Harris
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/avr_usart.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+
+static int avr_usart_can_receive(void *opaque)
+{
+    AVRUsartState *usart = opaque;
+
+    if (usart->data_valid || !(usart->csrb & USART_CSRB_RXEN)) {
+        return 0;
+    }
+    return 1;
+}
+
+static void avr_usart_receive(void *opaque, const uint8_t *buffer, int size)
+{
+    AVRUsartState *usart = opaque;
+    assert(size == 1);
+    assert(!usart->data_valid);
+    usart->data = buffer[0];
+    usart->data_valid = true;
+    usart->csra |= USART_CSRA_RXC;
+    if (usart->csrb & USART_CSRB_RXCIE) {
+        qemu_set_irq(usart->rxc_irq, 1);
+    }
+}
+
+static void update_char_mask(AVRUsartState *usart)
+{
+    uint8_t mode = ((usart->csrc & USART_CSRC_CSZ0) ? 1 : 0) |
+        ((usart->csrc & USART_CSRC_CSZ1) ? 2 : 0) |
+        ((usart->csrb & USART_CSRB_CSZ2) ? 4 : 0);
+    switch (mode) {
+    case 0:
+        usart->char_mask = 0b11111;
+        break;
+    case 1:
+        usart->char_mask = 0b111111;
+        break;
+    case 2:
+        usart->char_mask = 0b1111111;
+        break;
+    case 3:
+        usart->char_mask = 0b11111111;
+        break;
+    case 4:
+        /* Fallthrough. */
+    case 5:
+        /* Fallthrough. */
+    case 6:
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: Reserved character size 0x%x\n",
+            __func__,
+            mode);
+        break;
+    case 7:
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: Nine bit character size not supported (forcing eight)\n",
+            __func__);
+        usart->char_mask = 0b11111111;
+        break;
+    default:
+        assert(0);
+    }
+}
+
+static void avr_usart_reset(DeviceState *dev)
+{
+    AVRUsartState *usart = AVR_USART(dev);
+    usart->data_valid = false;
+    usart->csra = 0b00100000;
+    usart->csrb = 0b00000000;
+    usart->csrc = 0b00000110;
+    usart->brrl = 0;
+    usart->brrh = 0;
+    update_char_mask(usart);
+    qemu_set_irq(usart->rxc_irq, 0);
+    qemu_set_irq(usart->txc_irq, 0);
+    qemu_set_irq(usart->dre_irq, 0);
+}
+
+static uint64_t avr_usart_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    AVRUsartState *usart = opaque;
+    uint8_t data;
+    assert(size == 1);
+
+    if (!usart->enabled) {
+        return 0;
+    }
+
+    switch (addr) {
+    case USART_DR:
+        if (!(usart->csrb & USART_CSRB_RXEN)) {
+            /* Receiver disabled, ignore. */
+            return 0;
+        }
+        if (usart->data_valid) {
+            data = usart->data & usart->char_mask;
+            usart->data_valid = false;
+        } else {
+            data = 0;
+        }
+        usart->csra &= 0xff ^ USART_CSRA_RXC;
+        qemu_set_irq(usart->rxc_irq, 0);
+        qemu_chr_fe_accept_input(&usart->chr);
+        return data;
+    case USART_CSRA:
+        return usart->csra;
+    case USART_CSRB:
+        return usart->csrb;
+    case USART_CSRC:
+        return usart->csrc;
+    case USART_BRRL:
+        return usart->brrl;
+    case USART_BRRH:
+        return usart->brrh;
+    default:
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: Bad offset 0x%"HWADDR_PRIx"\n",
+            __func__,
+            addr);
+    }
+    return 0;
+}
+
+static void avr_usart_write(void *opaque, hwaddr addr, uint64_t value,
+                                unsigned int size)
+{
+    AVRUsartState *usart = opaque;
+    uint8_t mask;
+    uint8_t data;
+    assert((value & 0xff) == value);
+    assert(size == 1);
+
+    if (!usart->enabled) {
+        return;
+    }
+
+    switch (addr) {
+    case USART_DR:
+        if (!(usart->csrb & USART_CSRB_TXEN)) {
+            /* Transmitter disabled, ignore. */
+            return;
+        }
+        usart->csra |= USART_CSRA_TXC;
+        usart->csra |= USART_CSRA_DRE;
+        if (usart->csrb & USART_CSRB_TXCIE) {
+            qemu_set_irq(usart->txc_irq, 1);
+            usart->csra &= 0xff ^ USART_CSRA_TXC;
+        }
+        if (usart->csrb & USART_CSRB_DREIE) {
+            qemu_set_irq(usart->dre_irq, 1);
+        }
+        data = value;
+        qemu_chr_fe_write_all(&usart->chr, &data, 1);
+        break;
+    case USART_CSRA:
+        mask = 0b01000011;
+        /* Mask read-only bits. */
+        value = (value & mask) | (usart->csra & (0xff ^ mask));
+        usart->csra = value;
+        if (value & USART_CSRA_TXC) {
+            usart->csra ^= USART_CSRA_TXC;
+            qemu_set_irq(usart->txc_irq, 0);
+        }
+        if (value & USART_CSRA_MPCM) {
+            qemu_log_mask(
+                LOG_GUEST_ERROR,
+                "%s: MPCM not supported by USART\n",
+                __func__);
+        }
+        break;
+    case USART_CSRB:
+        mask = 0b11111101;
+        /* Mask read-only bits. */
+        value = (value & mask) | (usart->csrb & (0xff ^ mask));
+        usart->csrb = value;
+        if (!(value & USART_CSRB_RXEN)) {
+            /* Receiver disabled, flush input buffer. */
+            usart->data_valid = false;
+        }
+        qemu_set_irq(usart->rxc_irq,
+            ((value & USART_CSRB_RXCIE) &&
+            (usart->csra & USART_CSRA_RXC)) ? 1 : 0);
+        qemu_set_irq(usart->txc_irq,
+            ((value & USART_CSRB_TXCIE) &&
+            (usart->csra & USART_CSRA_TXC)) ? 1 : 0);
+        qemu_set_irq(usart->dre_irq,
+            ((value & USART_CSRB_DREIE) &&
+            (usart->csra & USART_CSRA_DRE)) ? 1 : 0);
+        update_char_mask(usart);
+        break;
+    case USART_CSRC:
+        usart->csrc = value;
+        if ((value & USART_CSRC_MSEL1) && (value & USART_CSRC_MSEL0)) {
+            qemu_log_mask(
+                LOG_GUEST_ERROR,
+                "%s: SPI mode not supported by USART\n",
+                __func__);
+        }
+        if ((value & USART_CSRC_MSEL1) && !(value & USART_CSRC_MSEL0)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad USART mode\n", __func__);
+        }
+        if (!(value & USART_CSRC_PM1) && (value & USART_CSRC_PM0)) {
+            qemu_log_mask(
+                LOG_GUEST_ERROR,
+                "%s: Bad USART parity mode\n",
+                __func__);
+        }
+        update_char_mask(usart);
+        break;
+    case USART_BRRL:
+        usart->brrl = value;
+        break;
+    case USART_BRRH:
+        usart->brrh = value & 0b00001111;
+        break;
+    default:
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: Bad offset 0x%"HWADDR_PRIx"\n",
+            __func__,
+            addr);
+    }
+}
+
+static const MemoryRegionOps avr_usart_ops = {
+    .read = avr_usart_read,
+    .write = avr_usart_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {.min_access_size = 1, .max_access_size = 1}
+};
+
+static Property avr_usart_properties[] = {
+    DEFINE_PROP_CHR("chardev", AVRUsartState, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void avr_usart_pr(void *opaque, int irq, int level)
+{
+    AVRUsartState *s = AVR_USART(opaque);
+
+    s->enabled = !level;
+
+    if (!s->enabled) {
+        avr_usart_reset(DEVICE(s));
+    }
+}
+
+static void avr_usart_init(Object *obj)
+{
+    AVRUsartState *s = AVR_USART(obj);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rxc_irq);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->dre_irq);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->txc_irq);
+    memory_region_init_io(&s->mmio, obj, &avr_usart_ops, s, TYPE_AVR_USART, 8);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+    qdev_init_gpio_in(DEVICE(s), avr_usart_pr, 1);
+    s->enabled = true;
+}
+
+static void avr_usart_realize(DeviceState *dev, Error **errp)
+{
+    AVRUsartState *s = AVR_USART(dev);
+    qemu_chr_fe_set_handlers(&s->chr, avr_usart_can_receive,
+                             avr_usart_receive, NULL, NULL,
+                             s, NULL, true);
+    avr_usart_reset(dev);
+}
+
+static void avr_usart_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = avr_usart_reset;
+    dc->props = avr_usart_properties;
+    dc->realize = avr_usart_realize;
+}
+
+static const TypeInfo avr_usart_info = {
+    .name          = TYPE_AVR_USART,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(AVRUsartState),
+    .instance_init = avr_usart_init,
+    .class_init    = avr_usart_class_init,
+};
+
+static void avr_usart_register_types(void)
+{
+    type_register_static(&avr_usart_info);
+}
+
+type_init(avr_usart_register_types)
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 51754bb47c..eb9e3210f4 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -120,4 +120,7 @@ config AUX
 config UNIMP
     bool
 
+config AVR_MASK
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index e4aad707fb..51e5ed96b4 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -80,3 +80,5 @@ obj-$(CONFIG_MSF2) += msf2-sysreg.o
 obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o
 
 obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o
+
+obj-$(CONFIG_AVR_MASK) += avr_mask.o
diff --git a/hw/misc/avr_mask.c b/hw/misc/avr_mask.c
new file mode 100644
index 0000000000..3af82ed9c1
--- /dev/null
+++ b/hw/misc/avr_mask.c
@@ -0,0 +1,112 @@
+/*
+ * AVR Power Reduction
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/avr_mask.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/irq.h"
+
+#define DB_PRINT(fmt, args...) /* Nothing */
+/*#define DB_PRINT(fmt, args...) printf("%s: " fmt "\n", __func__, ## args)*/
+
+static void avr_mask_reset(DeviceState *dev)
+{
+    AVRMaskState *s = AVR_MASK(dev);
+
+    s->val = 0x00;
+
+    for (int i = 0; i < 8; i++) {
+        qemu_set_irq(s->irq[i], 0);
+    }
+}
+
+static uint64_t avr_mask_read(void *opaque, hwaddr offset, unsigned size)
+{
+    assert(size == 1);
+    assert(offset == 0);
+    AVRMaskState *s = opaque;
+
+    return (uint64_t)s->val;
+}
+
+static void avr_mask_write(void *opaque, hwaddr offset,
+                              uint64_t val64, unsigned size)
+{
+    assert(size == 1);
+    assert(offset == 0);
+    AVRMaskState *s = opaque;
+    uint8_t val8 = val64;
+
+    DB_PRINT("write %d to offset %d", val8, (uint8_t)offset);
+
+    s->val = val8;
+    for (int i = 0; i < 8; i++) {
+        qemu_set_irq(s->irq[i], (val8 & (1 << i)) != 0);
+    }
+}
+
+static const MemoryRegionOps avr_mask_ops = {
+    .read = avr_mask_read,
+    .write = avr_mask_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {.max_access_size = 1}
+};
+
+static void avr_mask_init(Object *dev)
+{
+    AVRMaskState *s = AVR_MASK(dev);
+    SysBusDevice *busdev = SYS_BUS_DEVICE(dev);
+
+    memory_region_init_io(&s->iomem, dev, &avr_mask_ops, s, TYPE_AVR_MASK,
+            0x01);
+    sysbus_init_mmio(busdev, &s->iomem);
+
+    for (int i = 0; i < 8; i++) {
+        sysbus_init_irq(busdev, &s->irq[i]);
+    }
+    s->val = 0x00;
+}
+
+static void avr_mask_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = avr_mask_reset;
+}
+
+static const TypeInfo avr_mask_info = {
+    .name          = TYPE_AVR_MASK,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(AVRMaskState),
+    .class_init    = avr_mask_class_init,
+    .instance_init = avr_mask_init,
+};
+
+static void avr_mask_register_types(void)
+{
+    type_register_static(&avr_mask_info);
+}
+
+type_init(avr_mask_register_types)
diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig
index eefc95f35e..3bea322184 100644
--- a/hw/timer/Kconfig
+++ b/hw/timer/Kconfig
@@ -58,3 +58,6 @@ config CMSDK_APB_TIMER
 config CMSDK_APB_DUALTIMER
     bool
     select PTIMER
+
+config AVR_TIMER16
+    bool
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 123d92c969..4f853e265d 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -35,6 +35,7 @@ obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o
 obj-$(CONFIG_SH4) += sh_timer.o
 obj-$(CONFIG_DIGIC) += digic-timer.o
 obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o
+obj-$(CONFIG_AVR_TIMER16) += avr_timer16.o
 
 obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
 
diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c
new file mode 100644
index 0000000000..ac6ef73e77
--- /dev/null
+++ b/hw/timer/avr_timer16.c
@@ -0,0 +1,605 @@
+/*
+ * AVR 16 bit timer
+ *
+ * Copyright (c) 2018 University of Kent
+ * Author: Ed Robbins
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * Driver for 16 bit timers on 8 bit AVR devices.
+ * Note:
+ * ATmega640/V-1280/V-1281/V-2560/V-2561/V timers 1, 3, 4 and 5 are 16 bit
+ */
+
+/*
+ * XXX TODO: Power Reduction Register support
+ *           prescaler pause support
+ *           PWM modes, GPIO, output capture pins, input compare pin
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/avr_timer16.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+
+/* Register offsets */
+#define T16_CRA     0x0
+#define T16_CRB     0x1
+#define T16_CRC     0x2
+#define T16_CNTL    0x4
+#define T16_CNTH    0x5
+#define T16_ICRL    0x6
+#define T16_ICRH    0x7
+#define T16_OCRAL   0x8
+#define T16_OCRAH   0x9
+#define T16_OCRBL   0xa
+#define T16_OCRBH   0xb
+#define T16_OCRCL   0xc
+#define T16_OCRCH   0xd
+
+/* Field masks */
+#define T16_CRA_WGM01   0x3
+#define T16_CRA_COMC    0xc
+#define T16_CRA_COMB    0x30
+#define T16_CRA_COMA    0xc0
+#define T16_CRA_OC_CONF \
+    (T16_CRA_COMA | T16_CRA_COMB | T16_CRA_COMC)
+
+#define T16_CRB_CS      0x7
+#define T16_CRB_WGM23   0x18
+#define T16_CRB_ICES    0x40
+#define T16_CRB_ICNC    0x80
+
+#define T16_CRC_FOCC    0x20
+#define T16_CRC_FOCB    0x40
+#define T16_CRC_FOCA    0x80
+
+/* Fields masks both TIMSK and TIFR (interrupt mask/flag registers) */
+#define T16_INT_TOV    0x1 /* Timer overflow */
+#define T16_INT_OCA    0x2 /* Output compare A */
+#define T16_INT_OCB    0x4 /* Output compare B */
+#define T16_INT_OCC    0x8 /* Output compare C */
+#define T16_INT_IC     0x20 /* Input capture */
+
+/* Clock source values */
+#define T16_CLKSRC_STOPPED     0
+#define T16_CLKSRC_DIV1        1
+#define T16_CLKSRC_DIV8        2
+#define T16_CLKSRC_DIV64       3
+#define T16_CLKSRC_DIV256      4
+#define T16_CLKSRC_DIV1024     5
+#define T16_CLKSRC_EXT_FALLING 6
+#define T16_CLKSRC_EXT_RISING  7
+
+/* Timer mode values (not including PWM modes) */
+#define T16_MODE_NORMAL     0
+#define T16_MODE_CTC_OCRA   4
+#define T16_MODE_CTC_ICR    12
+
+/* Accessors */
+#define CLKSRC(t16) (t16->crb & T16_CRB_CS)
+#define MODE(t16)   (((t16->crb & T16_CRB_WGM23) >> 1) | \
+                     (t16->cra & T16_CRA_WGM01))
+#define CNT(t16)    VAL16(t16->cntl, t16->cnth)
+#define OCRA(t16)   VAL16(t16->ocral, t16->ocrah)
+#define OCRB(t16)   VAL16(t16->ocrbl, t16->ocrbh)
+#define OCRC(t16)   VAL16(t16->ocrcl, t16->ocrch)
+#define ICR(t16)    VAL16(t16->icrl, t16->icrh)
+
+/* Helper macros */
+#define VAL16(l, h) ((h << 8) | l)
+#define ERROR(fmt, args...) \
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## args)
+#define DB_PRINT(fmt, args...) /* Nothing */
+/*#define DB_PRINT(fmt, args...) printf("%s: " fmt "\n", __func__, ## args)*/
+
+static inline int64_t avr_timer16_ns_to_ticks(AVRTimer16State *t16, int64_t t)
+{
+    if (t16->period_ns == 0) {
+        return 0;
+    }
+    return t / t16->period_ns;
+}
+
+static void avr_timer16_update_cnt(AVRTimer16State *t16)
+{
+    uint16_t cnt;
+    cnt = avr_timer16_ns_to_ticks(t16, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
+                                       t16->reset_time_ns);
+    t16->cntl = (uint8_t)(cnt & 0xff);
+    t16->cnth = (uint8_t)((cnt & 0xff00) >> 8);
+}
+
+static inline void avr_timer16_recalc_reset_time(AVRTimer16State *t16)
+{
+    t16->reset_time_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
+                         CNT(t16) * t16->period_ns;
+}
+
+static void avr_timer16_clock_reset(AVRTimer16State *t16)
+{
+    t16->cntl = 0;
+    t16->cnth = 0;
+    t16->reset_time_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+}
+
+static void avr_timer16_clksrc_update(AVRTimer16State *t16)
+{
+    uint16_t divider = 0;
+    switch (CLKSRC(t16)) {
+    case T16_CLKSRC_EXT_FALLING:
+    case T16_CLKSRC_EXT_RISING:
+        ERROR("external clock source unsupported");
+        goto end;
+    case T16_CLKSRC_STOPPED:
+        goto end;
+    case T16_CLKSRC_DIV1:
+        divider = 1;
+        break;
+    case T16_CLKSRC_DIV8:
+        divider = 8;
+        break;
+    case T16_CLKSRC_DIV64:
+        divider = 64;
+        break;
+    case T16_CLKSRC_DIV256:
+        divider = 256;
+        break;
+    case T16_CLKSRC_DIV1024:
+        divider = 1024;
+        break;
+    default:
+        goto end;
+    }
+    t16->freq_hz = t16->cpu_freq_hz / divider;
+    t16->period_ns = 1000000000ULL / t16->freq_hz;
+    DB_PRINT("Timer frequency %" PRIu64 " hz, period %" PRIu64 " ns (%f s)",
+             t16->freq_hz, t16->period_ns, 1 / (double)t16->freq_hz);
+end:
+    return;
+}
+
+static void avr_timer16_set_alarm(AVRTimer16State *t16)
+{
+    if (CLKSRC(t16) == T16_CLKSRC_EXT_FALLING ||
+        CLKSRC(t16) == T16_CLKSRC_EXT_RISING ||
+        CLKSRC(t16) == T16_CLKSRC_STOPPED) {
+        /* Timer is disabled or set to external clock source (unsupported) */
+        goto end;
+    }
+
+    uint64_t alarm_offset = 0xffff;
+    enum NextInterrupt next_interrupt = OVERFLOW;
+
+    switch (MODE(t16)) {
+    case T16_MODE_NORMAL:
+        /* Normal mode */
+        if (OCRA(t16) < alarm_offset && OCRA(t16) > CNT(t16) &&
+            (t16->imsk & T16_INT_OCA)) {
+            alarm_offset = OCRA(t16);
+            next_interrupt = COMPA;
+        }
+        break;
+    case T16_MODE_CTC_OCRA:
+        /* CTC mode, top = ocra */
+        if (OCRA(t16) < alarm_offset && OCRA(t16) > CNT(t16)) {
+            alarm_offset = OCRA(t16);
+            next_interrupt = COMPA;
+        }
+       break;
+    case T16_MODE_CTC_ICR:
+        /* CTC mode, top = icr */
+        if (ICR(t16) < alarm_offset && ICR(t16) > CNT(t16)) {
+            alarm_offset = ICR(t16);
+            next_interrupt = CAPT;
+        }
+        if (OCRA(t16) < alarm_offset && OCRA(t16) > CNT(t16) &&
+            (t16->imsk & T16_INT_OCA)) {
+            alarm_offset = OCRA(t16);
+            next_interrupt = COMPA;
+        }
+        break;
+    default:
+        ERROR("pwm modes are unsupported");
+        goto end;
+    }
+    if (OCRB(t16) < alarm_offset && OCRB(t16) > CNT(t16) &&
+        (t16->imsk & T16_INT_OCB)) {
+        alarm_offset = OCRB(t16);
+        next_interrupt = COMPB;
+    }
+    if (OCRC(t16) < alarm_offset && OCRB(t16) > CNT(t16) &&
+        (t16->imsk & T16_INT_OCC)) {
+        alarm_offset = OCRB(t16);
+        next_interrupt = COMPC;
+    }
+    alarm_offset -= CNT(t16);
+
+    t16->next_interrupt = next_interrupt;
+    uint64_t alarm_ns =
+        t16->reset_time_ns + ((CNT(t16) + alarm_offset) * t16->period_ns);
+    timer_mod(t16->timer, alarm_ns);
+
+    DB_PRINT("next alarm %" PRIu64 " ns from now",
+        alarm_offset * t16->period_ns);
+
+end:
+    return;
+}
+
+static void avr_timer16_interrupt(void *opaque)
+{
+    AVRTimer16State *t16 = opaque;
+    uint8_t mode = MODE(t16);
+
+    avr_timer16_update_cnt(t16);
+
+    if (CLKSRC(t16) == T16_CLKSRC_EXT_FALLING ||
+        CLKSRC(t16) == T16_CLKSRC_EXT_RISING ||
+        CLKSRC(t16) == T16_CLKSRC_STOPPED) {
+        /* Timer is disabled or set to external clock source (unsupported) */
+        return;
+    }
+
+    DB_PRINT("interrupt, cnt = %d", CNT(t16));
+
+    /* Counter overflow */
+    if (t16->next_interrupt == OVERFLOW) {
+        DB_PRINT("0xffff overflow");
+        avr_timer16_clock_reset(t16);
+        if (t16->imsk & T16_INT_TOV) {
+            t16->ifr |= T16_INT_TOV;
+            qemu_set_irq(t16->ovf_irq, 1);
+        }
+    }
+    /* Check for ocra overflow in CTC mode */
+    if (mode == T16_MODE_CTC_OCRA && t16->next_interrupt == COMPA) {
+        DB_PRINT("CTC OCRA overflow");
+        avr_timer16_clock_reset(t16);
+    }
+    /* Check for icr overflow in CTC mode */
+    if (mode == T16_MODE_CTC_ICR && t16->next_interrupt == CAPT) {
+        DB_PRINT("CTC ICR overflow");
+        avr_timer16_clock_reset(t16);
+        if (t16->imsk & T16_INT_IC) {
+            t16->ifr |= T16_INT_IC;
+            qemu_set_irq(t16->capt_irq, 1);
+        }
+    }
+    /* Check for output compare interrupts */
+    if (t16->imsk & T16_INT_OCA && t16->next_interrupt == COMPA) {
+        t16->ifr |= T16_INT_OCA;
+        qemu_set_irq(t16->compa_irq, 1);
+    }
+    if (t16->imsk & T16_INT_OCB && t16->next_interrupt == COMPB) {
+        t16->ifr |= T16_INT_OCB;
+        qemu_set_irq(t16->compb_irq, 1);
+    }
+    if (t16->imsk & T16_INT_OCC && t16->next_interrupt == COMPC) {
+        t16->ifr |= T16_INT_OCC;
+        qemu_set_irq(t16->compc_irq, 1);
+    }
+    avr_timer16_set_alarm(t16);
+}
+
+static void avr_timer16_reset(DeviceState *dev)
+{
+    AVRTimer16State *t16 = AVR_TIMER16(dev);
+
+    avr_timer16_clock_reset(t16);
+    avr_timer16_clksrc_update(t16);
+    avr_timer16_set_alarm(t16);
+
+    qemu_set_irq(t16->capt_irq, 0);
+    qemu_set_irq(t16->compa_irq, 0);
+    qemu_set_irq(t16->compb_irq, 0);
+    qemu_set_irq(t16->compc_irq, 0);
+    qemu_set_irq(t16->ovf_irq, 0);
+}
+
+static uint64_t avr_timer16_read(void *opaque, hwaddr offset, unsigned size)
+{
+    assert(size == 1);
+    AVRTimer16State *t16 = opaque;
+    uint8_t retval = 0;
+
+    switch (offset) {
+    case T16_CRA:
+        retval = t16->cra;
+        break;
+    case T16_CRB:
+        retval = t16->crb;
+        break;
+    case T16_CRC:
+        retval = t16->crc;
+        break;
+    case T16_CNTL:
+        avr_timer16_update_cnt(t16);
+        t16->rtmp = t16->cnth;
+        retval = t16->cntl;
+        break;
+    case T16_CNTH:
+        retval = t16->rtmp;
+        break;
+    case T16_ICRL:
+        /*
+         * The timer copies cnt to icr when the input capture pin changes
+         * state or when the analog comparator has a match. We don't
+         * emulate this behaviour. We do support it's use for defining a
+         * TOP value in T16_MODE_CTC_ICR
+         */
+        t16->rtmp = t16->icrh;
+        retval = t16->icrl;
+        break;
+    case T16_ICRH:
+        retval = t16->rtmp;
+        break;
+    case T16_OCRAL:
+        retval = t16->ocral;
+        break;
+    case T16_OCRAH:
+        retval = t16->ocrah;
+        break;
+    case T16_OCRBL:
+        retval = t16->ocrbl;
+        break;
+    case T16_OCRBH:
+        retval = t16->ocrbh;
+        break;
+    case T16_OCRCL:
+        retval = t16->ocrcl;
+        break;
+    case T16_OCRCH:
+        retval = t16->ocrch;
+        break;
+    default:
+        break;
+    }
+    return (uint64_t)retval;
+}
+
+static void avr_timer16_write(void *opaque, hwaddr offset,
+                              uint64_t val64, unsigned size)
+{
+    assert(size == 1);
+    AVRTimer16State *t16 = opaque;
+    uint8_t val8 = (uint8_t)val64;
+    uint8_t prev_clk_src = CLKSRC(t16);
+
+    DB_PRINT("write %d to offset %d", val8, (uint8_t)offset);
+
+    switch (offset) {
+    case T16_CRA:
+        t16->cra = val8;
+        if (t16->cra & T16_CRA_OC_CONF) {
+            ERROR("output compare pins unsupported");
+        }
+        break;
+    case T16_CRB:
+        t16->crb = val8;
+        if (t16->crb & T16_CRB_ICNC) {
+            ERROR("input capture noise canceller unsupported");
+        }
+        if (t16->crb & T16_CRB_ICES) {
+            ERROR("input capture unsupported");
+        }
+        if (CLKSRC(t16) != prev_clk_src) {
+            avr_timer16_clksrc_update(t16);
+            if (prev_clk_src == T16_CLKSRC_STOPPED) {
+                t16->reset_time_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+            }
+        }
+        break;
+    case T16_CRC:
+        t16->crc = val8;
+        ERROR("output compare pins unsupported");
+        break;
+    case T16_CNTL:
+        /*
+         * CNT is the 16-bit counter value, it must be read/written via
+         * a temporary register (rtmp) to make the read/write atomic.
+         */
+        /* ICR also has this behaviour, and shares rtmp */
+        /*
+         * Writing CNT blocks compare matches for one clock cycle.
+         * Writing CNT to TOP or to an OCR value (if in use) will
+         * skip the relevant interrupt
+         */
+        t16->cntl = val8;
+        t16->cnth = t16->rtmp;
+        avr_timer16_recalc_reset_time(t16);
+        break;
+    case T16_CNTH:
+        t16->rtmp = val8;
+        break;
+    case T16_ICRL:
+        /* ICR can only be written in mode T16_MODE_CTC_ICR */
+        if (MODE(t16) == T16_MODE_CTC_ICR) {
+            t16->icrl = val8;
+            t16->icrh = t16->rtmp;
+        }
+        break;
+    case T16_ICRH:
+        if (MODE(t16) == T16_MODE_CTC_ICR) {
+            t16->rtmp = val8;
+        }
+        break;
+    case T16_OCRAL:
+        /*
+         * OCRn cause the relevant output compare flag to be raised, and
+         * trigger an interrupt, when CNT is equal to the value here
+         */
+        t16->ocral = val8;
+        break;
+    case T16_OCRAH:
+        t16->ocrah = val8;
+        break;
+    case T16_OCRBL:
+        t16->ocrbl = val8;
+        break;
+    case T16_OCRBH:
+        t16->ocrbh = val8;
+        break;
+    case T16_OCRCL:
+        t16->ocrcl = val8;
+        break;
+    case T16_OCRCH:
+        t16->ocrch = val8;
+        break;
+    default:
+        break;
+    }
+    avr_timer16_set_alarm(t16);
+}
+
+static uint64_t avr_timer16_imsk_read(void *opaque,
+                                      hwaddr offset,
+                                      unsigned size)
+{
+    assert(size == 1);
+    AVRTimer16State *t16 = opaque;
+    if (offset != 0) {
+        return 0;
+    }
+    return t16->imsk;
+}
+
+static void avr_timer16_imsk_write(void *opaque, hwaddr offset,
+                                   uint64_t val64, unsigned size)
+{
+    assert(size == 1);
+    AVRTimer16State *t16 = opaque;
+    if (offset != 0) {
+        return;
+    }
+    t16->imsk = (uint8_t)val64;
+}
+
+static uint64_t avr_timer16_ifr_read(void *opaque,
+                                     hwaddr offset,
+                                     unsigned size)
+{
+    assert(size == 1);
+    AVRTimer16State *t16 = opaque;
+    if (offset != 0) {
+        return 0;
+    }
+    return t16->ifr;
+}
+
+static void avr_timer16_ifr_write(void *opaque, hwaddr offset,
+                                  uint64_t val64, unsigned size)
+{
+    assert(size == 1);
+    AVRTimer16State *t16 = opaque;
+    if (offset != 0) {
+        return;
+    }
+    t16->ifr = (uint8_t)val64;
+}
+
+static const MemoryRegionOps avr_timer16_ops = {
+    .read = avr_timer16_read,
+    .write = avr_timer16_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {.max_access_size = 1}
+};
+
+static const MemoryRegionOps avr_timer16_imsk_ops = {
+    .read = avr_timer16_imsk_read,
+    .write = avr_timer16_imsk_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {.max_access_size = 1}
+};
+
+static const MemoryRegionOps avr_timer16_ifr_ops = {
+    .read = avr_timer16_ifr_read,
+    .write = avr_timer16_ifr_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {.max_access_size = 1}
+};
+
+static Property avr_timer16_properties[] = {
+    DEFINE_PROP_UINT64("cpu-frequency-hz", struct AVRTimer16State,
+                       cpu_freq_hz, 20000000),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void avr_timer16_pr(void *opaque, int irq, int level)
+{
+    AVRTimer16State *s = AVR_TIMER16(opaque);
+
+    s->enabled = !level;
+
+    if (!s->enabled) {
+        avr_timer16_reset(DEVICE(s));
+    }
+}
+
+static void avr_timer16_init(Object *obj)
+{
+    AVRTimer16State *s = AVR_TIMER16(obj);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->capt_irq);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->compa_irq);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->compb_irq);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->compc_irq);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->ovf_irq);
+
+    memory_region_init_io(&s->iomem, obj, &avr_timer16_ops,
+                          s, TYPE_AVR_TIMER16, 0xe);
+    memory_region_init_io(&s->imsk_iomem, obj, &avr_timer16_imsk_ops,
+                          s, TYPE_AVR_TIMER16, 0x1);
+    memory_region_init_io(&s->ifr_iomem, obj, &avr_timer16_ifr_ops,
+                          s, TYPE_AVR_TIMER16, 0x1);
+
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->imsk_iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->ifr_iomem);
+    qdev_init_gpio_in(DEVICE(s), avr_timer16_pr, 1);
+
+    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_timer16_interrupt, s);
+    s->enabled = true;
+}
+
+static void avr_timer16_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = avr_timer16_reset;
+    dc->props = avr_timer16_properties;
+}
+
+static const TypeInfo avr_timer16_info = {
+    .name          = TYPE_AVR_TIMER16,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(AVRTimer16State),
+    .instance_init = avr_timer16_init,
+    .class_init    = avr_timer16_class_init,
+};
+
+static void avr_timer16_register_types(void)
+{
+    type_register_static(&avr_timer16_info);
+}
+
+type_init(avr_timer16_register_types)
diff --git a/include/hw/char/avr_usart.h b/include/hw/char/avr_usart.h
new file mode 100644
index 0000000000..8e9ee88bbd
--- /dev/null
+++ b/include/hw/char/avr_usart.h
@@ -0,0 +1,97 @@
+/*
+ * AVR USART
+ *
+ * Copyright (c) 2018 University of Kent
+ * Author: Sarah Harris
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_AVR_USART_H
+#define HW_AVR_USART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+#include "hw/hw.h"
+
+/* Offsets of registers. */
+#define USART_DR   0x06
+#define USART_CSRA  0x00
+#define USART_CSRB  0x01
+#define USART_CSRC  0x02
+#define USART_BRRH 0x05
+#define USART_BRRL 0x04
+
+/* Relevant bits in regiters. */
+#define USART_CSRA_RXC    (1 << 7)
+#define USART_CSRA_TXC    (1 << 6)
+#define USART_CSRA_DRE    (1 << 5)
+#define USART_CSRA_MPCM   (1 << 0)
+
+#define USART_CSRB_RXCIE  (1 << 7)
+#define USART_CSRB_TXCIE  (1 << 6)
+#define USART_CSRB_DREIE  (1 << 5)
+#define USART_CSRB_RXEN   (1 << 4)
+#define USART_CSRB_TXEN   (1 << 3)
+#define USART_CSRB_CSZ2   (1 << 2)
+#define USART_CSRB_RXB8   (1 << 1)
+#define USART_CSRB_TXB8   (1 << 0)
+
+#define USART_CSRC_MSEL1  (1 << 7)
+#define USART_CSRC_MSEL0  (1 << 6)
+#define USART_CSRC_PM1    (1 << 5)
+#define USART_CSRC_PM0    (1 << 4)
+#define USART_CSRC_CSZ1   (1 << 2)
+#define USART_CSRC_CSZ0   (1 << 1)
+
+#define TYPE_AVR_USART "avr-usart"
+#define AVR_USART(obj) \
+    OBJECT_CHECK(AVRUsartState, (obj), TYPE_AVR_USART)
+
+typedef struct {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion mmio;
+
+    CharBackend chr;
+
+    bool enabled;
+
+    uint8_t data;
+    bool data_valid;
+    uint8_t char_mask;
+    /* Control and Status Registers */
+    uint8_t csra;
+    uint8_t csrb;
+    uint8_t csrc;
+    /* Baud Rate Registers (low/high byte) */
+    uint8_t brrh;
+    uint8_t brrl;
+
+    /* Receive Complete */
+    qemu_irq rxc_irq;
+    /* Transmit Complete */
+    qemu_irq txc_irq;
+    /* Data Register Empty */
+    qemu_irq dre_irq;
+} AVRUsartState;
+
+#endif /* HW_AVR_USART_H */
diff --git a/include/hw/misc/avr_mask.h b/include/hw/misc/avr_mask.h
new file mode 100644
index 0000000000..d3e21972d8
--- /dev/null
+++ b/include/hw/misc/avr_mask.h
@@ -0,0 +1,47 @@
+/*
+ * AVR Power Reduction
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_avr_mask_H
+#define HW_avr_mask_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+#include "hw/hw.h"
+
+
+#define TYPE_AVR_MASK "avr-mask"
+#define AVR_MASK(obj) OBJECT_CHECK(AVRMaskState, (obj), TYPE_AVR_MASK)
+
+typedef struct {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion iomem;
+
+    uint8_t val;
+    qemu_irq irq[8];
+} AVRMaskState;
+
+#endif /* HW_avr_mask_H */
diff --git a/include/hw/timer/avr_timer16.h b/include/hw/timer/avr_timer16.h
new file mode 100644
index 0000000000..5639074ce5
--- /dev/null
+++ b/include/hw/timer/avr_timer16.h
@@ -0,0 +1,97 @@
+/*
+ * AVR 16 bit timer
+ *
+ * Copyright (c) 2018 University of Kent
+ * Author: Ed Robbins
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * Driver for 16 bit timers on 8 bit AVR devices.
+ * Note:
+ * On ATmega640/V-1280/V-1281/V-2560/V-2561/V timers 1, 3, 4 and 5 are 16 bit
+ */
+
+#ifndef AVR_TIMER16_H
+#define AVR_TIMER16_H
+
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "hw/hw.h"
+
+enum NextInterrupt {
+    OVERFLOW,
+    COMPA,
+    COMPB,
+    COMPC,
+    CAPT
+};
+
+#define TYPE_AVR_TIMER16 "avr-timer16"
+#define AVR_TIMER16(obj) \
+    OBJECT_CHECK(AVRTimer16State, (obj), TYPE_AVR_TIMER16)
+
+typedef struct AVRTimer16State {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion iomem;
+    MemoryRegion imsk_iomem;
+    MemoryRegion ifr_iomem;
+    QEMUTimer *timer;
+    qemu_irq capt_irq;
+    qemu_irq compa_irq;
+    qemu_irq compb_irq;
+    qemu_irq compc_irq;
+    qemu_irq ovf_irq;
+
+    bool enabled;
+
+    /* registers */
+    uint8_t cra;
+    uint8_t crb;
+    uint8_t crc;
+    uint8_t cntl;
+    uint8_t cnth;
+    uint8_t icrl;
+    uint8_t icrh;
+    uint8_t ocral;
+    uint8_t ocrah;
+    uint8_t ocrbl;
+    uint8_t ocrbh;
+    uint8_t ocrcl;
+    uint8_t ocrch;
+    /*
+     * Reads and writes to CNT and ICR utilise a bizarre temporary
+     * register, which we emulate
+     */
+    uint8_t rtmp;
+    uint8_t imsk;
+    uint8_t ifr;
+
+    uint64_t cpu_freq_hz;
+    uint64_t freq_hz;
+    uint64_t period_ns;
+    uint64_t reset_time_ns;
+    enum NextInterrupt next_interrupt;
+} AVRTimer16State;
+
+#endif /* AVR_TIMER16_H */
-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* [Qemu-devel] [PATCH v30 6/8] target/avr: Add example board configuration
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
                   ` (4 preceding siblings ...)
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 5/8] target/avr: Add limited support for USART and 16 bit timer peripherals Michael Rolnik
@ 2019-09-02 14:01 ` Michael Rolnik
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
                   ` (3 subsequent siblings)
  9 siblings, 0 replies; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo, philmd

A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs include a lot of on-board peripherals.

NOTE: this is not a real board !!!!
NOTE: it's used for CPU testing!!!!

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 hw/Kconfig           |   1 +
 hw/avr/Kconfig       |   6 +
 hw/avr/Makefile.objs |   1 +
 hw/avr/sample.c      | 282 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 290 insertions(+)
 create mode 100644 hw/avr/Kconfig
 create mode 100644 hw/avr/Makefile.objs
 create mode 100644 hw/avr/sample.c

diff --git a/hw/Kconfig b/hw/Kconfig
index b45db3c813..f185fcb19e 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -42,6 +42,7 @@ source watchdog/Kconfig
 # arch Kconfig
 source arm/Kconfig
 source alpha/Kconfig
+source avr/Kconfig
 source cris/Kconfig
 source hppa/Kconfig
 source i386/Kconfig
diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
new file mode 100644
index 0000000000..92aa1e6afb
--- /dev/null
+++ b/hw/avr/Kconfig
@@ -0,0 +1,6 @@
+config AVR_SAMPLE
+    bool
+    select AVR_TIMER16
+    select AVR_USART
+    select AVR_MASK
+    select UNIMP
diff --git a/hw/avr/Makefile.objs b/hw/avr/Makefile.objs
new file mode 100644
index 0000000000..626b7064b3
--- /dev/null
+++ b/hw/avr/Makefile.objs
@@ -0,0 +1 @@
+obj-y += sample.o
diff --git a/hw/avr/sample.c b/hw/avr/sample.c
new file mode 100644
index 0000000000..2295ec1b79
--- /dev/null
+++ b/hw/avr/sample.c
@@ -0,0 +1,282 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+/*
+ *  NOTE:
+ *      This is not a real AVR board, this is an example!
+ *      The CPU is an approximation of an ATmega2560, but is missing various
+ *      built-in peripherals.
+ *
+ *      This example board loads provided binary file into flash memory and
+ *      executes it from 0x00000000 address in the code memory space.
+ *
+ *      Currently used for AVR CPU validation
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "ui/console.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "qemu/error-report.h"
+#include "exec/address-spaces.h"
+#include "include/hw/sysbus.h"
+#include "include/hw/char/avr_usart.h"
+#include "include/hw/timer/avr_timer16.h"
+#include "include/hw/misc/avr_mask.h"
+#include "elf.h"
+#include "hw/misc/unimp.h"
+
+#define SIZE_FLASH 0x00040000
+#define SIZE_SRAM 0x00002000
+/*
+ * Size of additional "external" memory, as if the AVR were configured to use
+ * an external RAM chip.
+ * Note that the configuration registers that normally enable this feature are
+ * unimplemented.
+ */
+#define SIZE_EXMEM 0x00000000
+
+/* Offsets of peripherals in emulated memory space (i.e. not host addresses)  */
+#define PRR0_BASE 0x64
+#define PRR1_BASE 0x65
+#define USART_BASE 0xc0
+#define TIMER1_BASE 0x80
+#define TIMER1_IMSK_BASE 0x6f
+#define TIMER1_IFR_BASE 0x36
+
+/* Interrupt numbers used by peripherals */
+#define USART_RXC_IRQ 24
+#define USART_DRE_IRQ 25
+#define USART_TXC_IRQ 26
+
+#define TIMER1_CAPT_IRQ 15
+#define TIMER1_COMPA_IRQ 16
+#define TIMER1_COMPB_IRQ 17
+#define TIMER1_COMPC_IRQ 18
+#define TIMER1_OVF_IRQ 19
+
+/*  Power reduction     */
+#define PRR1_BIT_PRTIM5     0x05    /*  Timer/Counter5  */
+#define PRR1_BIT_PRTIM4     0x04    /*  Timer/Counter4  */
+#define PRR1_BIT_PRTIM3     0x03    /*  Timer/Counter3  */
+#define PRR1_BIT_PRUSART3   0x02    /*  USART3  */
+#define PRR1_BIT_PRUSART2   0x01    /*  USART2  */
+#define PRR1_BIT_PRUSART1   0x00    /*  USART1  */
+
+#define PRR0_BIT_PRTWI      0x06    /*  TWI */
+#define PRR0_BIT_PRTIM2     0x05    /*  Timer/Counter2  */
+#define PRR0_BIT_PRTIM0     0x04    /*  Timer/Counter0  */
+#define PRR0_BIT_PRTIM1     0x03    /*  Timer/Counter1  */
+#define PRR0_BIT_PRSPI      0x02    /*  Serial Peripheral Interface */
+#define PRR0_BIT_PRUSART0   0x01    /*  USART0  */
+#define PRR0_BIT_PRADC      0x00    /*  ADC */
+
+typedef struct {
+    MachineClass parent;
+} SampleMachineClass;
+
+typedef struct {
+    MachineState parent;
+    MemoryRegion *ram;
+    MemoryRegion *flash;
+    AVRUsartState *usart0;
+    AVRTimer16State *timer1;
+    AVRMaskState *prr[2];
+} SampleMachineState;
+
+#define TYPE_SAMPLE_MACHINE MACHINE_TYPE_NAME("sample")
+
+#define SAMPLE_MACHINE(obj) \
+    OBJECT_CHECK(SampleMachineState, obj, TYPE_SAMPLE_MACHINE)
+#define SAMPLE_MACHINE_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(SampleMachineClass, obj, TYPE_SAMPLE_MACHINE)
+#define SAMPLE_MACHINE_CLASS(klass) \
+    OBJECT_CLASS_CHECK(SampleMachineClass, klass, TYPE_SAMPLE_MACHINE)
+
+static void sample_init(MachineState *machine)
+{
+    SampleMachineState *sms = SAMPLE_MACHINE(machine);
+    MemoryRegion *system_memory = get_system_memory();
+    AVRCPU *cpu;
+    const char *firmware = NULL;
+    const char *filename;
+    int bytes_loaded;
+    SysBusDevice *busdev;
+    DeviceState *cpudev;
+
+    system_memory = get_system_memory();
+    sms->ram = g_new(MemoryRegion, 1);
+    sms->flash = g_new(MemoryRegion, 1);
+
+    cpu = AVR_CPU(cpu_create(machine->cpu_type));
+    cpudev = DEVICE(cpu);
+
+
+    memory_region_init_rom(sms->flash, NULL, "avr.flash", SIZE_FLASH,
+            &error_fatal);
+    memory_region_add_subregion(system_memory, OFFSET_CODE, sms->flash);
+
+    /* following are atmel2560 device */
+    create_unimplemented_device("usart 3", OFFSET_DATA + 0x0130, 0x0007);
+    create_unimplemented_device("timer-counter-16bit 5",
+            OFFSET_DATA + 0x0120, 0x000e);
+    create_unimplemented_device("gpio L", OFFSET_DATA + 0x0109, 0x0003);
+    create_unimplemented_device("gpio K", OFFSET_DATA + 0x0106, 0x0003);
+    create_unimplemented_device("gpio J", OFFSET_DATA + 0x0103, 0x0003);
+    create_unimplemented_device("gpio H", OFFSET_DATA + 0x0100, 0x0003);
+    create_unimplemented_device("usart 2", OFFSET_DATA + 0x00d0, 0x0007);
+    create_unimplemented_device("usart 1", OFFSET_DATA + 0x00c8, 0x0007);
+    create_unimplemented_device("usart 0", OFFSET_DATA + 0x00c0, 0x0007);
+    create_unimplemented_device("twi", OFFSET_DATA + 0x00b8, 0x0006);
+    create_unimplemented_device("timer-counter-async-8bit 2",
+            OFFSET_DATA + 0x00b0, 0x0007);
+    create_unimplemented_device("timer-counter-16bit 4",
+            OFFSET_DATA + 0x00a0, 0x000e);
+    create_unimplemented_device("timer-counter-16bit 3",
+            OFFSET_DATA + 0x0090, 0x000e);
+    create_unimplemented_device("timer-counter-16bit 1",
+            OFFSET_DATA + 0x0080, 0x000e);
+    create_unimplemented_device("ac / adc",
+            OFFSET_DATA + 0x0078, 0x0008);
+    create_unimplemented_device("ext-mem-iface",
+            OFFSET_DATA + 0x0074, 0x0002);
+    create_unimplemented_device("int-controller",
+            OFFSET_DATA + 0x0068, 0x000c);
+    create_unimplemented_device("sys",
+            OFFSET_DATA + 0x0060, 0x0007);
+    create_unimplemented_device("spi",
+            OFFSET_DATA + 0x004c, 0x0003);
+    create_unimplemented_device("ext-mem-iface",
+            OFFSET_DATA + 0x004a, 0x0002);
+    create_unimplemented_device("timer-counter-pwm-8bit 0",
+            OFFSET_DATA + 0x0043, 0x0006);
+    create_unimplemented_device("ext-mem-iface",
+            OFFSET_DATA + 0x003e, 0x0005);
+    create_unimplemented_device("int-controller",
+            OFFSET_DATA + 0x0035, 0x0009);
+    create_unimplemented_device("gpio G", OFFSET_DATA + 0x0032, 0x0003);
+    create_unimplemented_device("gpio F", OFFSET_DATA + 0x002f, 0x0003);
+    create_unimplemented_device("gpio E", OFFSET_DATA + 0x002c, 0x0003);
+    create_unimplemented_device("gpio D", OFFSET_DATA + 0x0029, 0x0003);
+    create_unimplemented_device("gpio C", OFFSET_DATA + 0x0026, 0x0003);
+    create_unimplemented_device("gpio B", OFFSET_DATA + 0x0023, 0x0003);
+    create_unimplemented_device("gpio A", OFFSET_DATA + 0x0020, 0x0003);
+
+    memory_region_allocate_system_memory(
+        sms->ram, NULL, "avr.ram", SIZE_SRAM + SIZE_EXMEM);
+    memory_region_add_subregion(system_memory, OFFSET_DATA + 0x200, sms->ram);
+
+    /* Power Reduction built-in peripheral */
+    sms->prr[0] = AVR_MASK(sysbus_create_simple(TYPE_AVR_MASK,
+                    OFFSET_DATA + PRR0_BASE, NULL));
+    sms->prr[1] = AVR_MASK(sysbus_create_simple(TYPE_AVR_MASK,
+                    OFFSET_DATA + PRR1_BASE, NULL));
+
+    /* USART 0 built-in peripheral */
+    sms->usart0 = AVR_USART(object_new(TYPE_AVR_USART));
+    busdev = SYS_BUS_DEVICE(sms->usart0);
+    qdev_prop_set_chr(DEVICE(sms->usart0), "chardev", serial_hd(0));
+    object_property_set_bool(OBJECT(sms->usart0), true, "realized",
+            &error_fatal);
+    sysbus_mmio_map(busdev, 0, OFFSET_DATA + USART_BASE);
+    /*
+     * These IRQ numbers don't match the datasheet because we're counting from
+     * zero and not including reset.
+     */
+    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(cpudev, USART_RXC_IRQ));
+    sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(cpudev, USART_DRE_IRQ));
+    sysbus_connect_irq(busdev, 2, qdev_get_gpio_in(cpudev, USART_TXC_IRQ));
+    sysbus_connect_irq(SYS_BUS_DEVICE(sms->prr[1]), PRR1_BIT_PRUSART1,
+            qdev_get_gpio_in(DEVICE(sms->usart0), 0));
+
+    /* Timer 1 built-in periphal */
+    sms->timer1 = AVR_TIMER16(object_new(TYPE_AVR_TIMER16));
+    object_property_set_bool(OBJECT(sms->timer1), true, "realized",
+            &error_fatal);
+    busdev = SYS_BUS_DEVICE(sms->timer1);
+    sysbus_mmio_map(busdev, 0, OFFSET_DATA + TIMER1_BASE);
+    sysbus_mmio_map(busdev, 1, OFFSET_DATA + TIMER1_IMSK_BASE);
+    sysbus_mmio_map(busdev, 2, OFFSET_DATA + TIMER1_IFR_BASE);
+    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(cpudev, TIMER1_CAPT_IRQ));
+    sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(cpudev, TIMER1_COMPA_IRQ));
+    sysbus_connect_irq(busdev, 2, qdev_get_gpio_in(cpudev, TIMER1_COMPB_IRQ));
+    sysbus_connect_irq(busdev, 3, qdev_get_gpio_in(cpudev, TIMER1_COMPC_IRQ));
+    sysbus_connect_irq(busdev, 4, qdev_get_gpio_in(cpudev, TIMER1_OVF_IRQ));
+    sysbus_connect_irq(SYS_BUS_DEVICE(sms->prr[0]), PRR0_BIT_PRTIM1,
+            qdev_get_gpio_in(DEVICE(sms->timer1), 0));
+
+    /* Load firmware (contents of flash) trying to auto-detect format */
+    firmware = machine->firmware;
+    if (firmware != NULL) {
+        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware);
+        if (filename == NULL) {
+            error_report("Unable to find %s", firmware);
+            exit(1);
+        }
+
+        bytes_loaded = load_elf(
+            filename, NULL, NULL, NULL, NULL, NULL, NULL, 0, EM_NONE, 0, 0);
+        if (bytes_loaded < 0) {
+            bytes_loaded = load_image_targphys(
+                filename, OFFSET_CODE, SIZE_FLASH);
+        }
+        if (bytes_loaded < 0) {
+            error_report(
+                "Unable to load firmware image %s as ELF or raw binary",
+                firmware);
+            exit(1);
+        }
+    }
+}
+
+static void sample_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "AVR sample/example board (ATmega2560)";
+    mc->init = sample_init;
+    mc->default_cpus = 1;
+    mc->min_cpus = mc->default_cpus;
+    mc->max_cpus = mc->default_cpus;
+    mc->default_cpu_type = "avr6-avr-cpu"; /* ATmega2560. */
+    mc->is_default = 1;
+}
+
+static const TypeInfo sample_info = {
+    .name = TYPE_SAMPLE_MACHINE,
+    .parent = TYPE_MACHINE,
+    .instance_size = sizeof(SampleMachineState),
+    .class_size = sizeof(SampleMachineClass),
+    .class_init = sample_class_init,
+};
+
+static void sample_machine_init(void)
+{
+    type_register_static(&sample_info);
+}
+
+type_init(sample_machine_init);
-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
                   ` (5 preceding siblings ...)
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 6/8] target/avr: Add example board configuration Michael Rolnik
@ 2019-09-02 14:01 ` Michael Rolnik
  2019-10-11 14:20   ` Eric Blake
  2019-10-11 15:25   ` Philippe Mathieu-Daudé
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 8/8] target/avr: Add tests Michael Rolnik
                   ` (2 subsequent siblings)
  9 siblings, 2 replies; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo, philmd

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 MAINTAINERS                     |  6 +++
 arch_init.c                     |  2 +
 configure                       | 93 ++++++++++++++++++---------------
 default-configs/avr-softmmu.mak |  5 ++
 include/disas/dis-asm.h         |  6 +++
 include/sysemu/arch_init.h      |  1 +
 qapi/machine.json               |  3 +-
 target/avr/Makefile.objs        | 33 ++++++++++++
 tests/machine-none-test.c       |  1 +
 9 files changed, 106 insertions(+), 44 deletions(-)
 create mode 100644 default-configs/avr-softmmu.mak
 create mode 100644 target/avr/Makefile.objs

diff --git a/MAINTAINERS b/MAINTAINERS
index ef6c01084b..763370e6ff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -163,6 +163,12 @@ S: Maintained
 F: hw/arm/smmu*
 F: include/hw/arm/smmu*
 
+AVR TCG CPUs
+M: Michael Rolnik <mrolnik@gmail.com>
+S: Maintained
+F: target/avr/
+F: hw/avr/
+
 CRIS TCG CPUs
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 S: Maintained
diff --git a/arch_init.c b/arch_init.c
index 0a1531124c..fb308aa802 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -85,6 +85,8 @@ int graphic_depth = 32;
 #define QEMU_ARCH QEMU_ARCH_UNICORE32
 #elif defined(TARGET_XTENSA)
 #define QEMU_ARCH QEMU_ARCH_XTENSA
+#elif defined(TARGET_AVR)
+#define QEMU_ARCH QEMU_ARCH_AVR
 #endif
 
 const uint32_t arch_type = QEMU_ARCH;
diff --git a/configure b/configure
index e44e454c43..b35a7cf214 100755
--- a/configure
+++ b/configure
@@ -2032,7 +2032,7 @@ EOF
 
 if ! compile_prog "-Werror" "" ; then
     error_exit "Your compiler does not support the __thread specifier for " \
-	"Thread-Local Storage (TLS). Please upgrade to a version that does."
+    "Thread-Local Storage (TLS). Please upgrade to a version that does."
 fi
 
 if test "$pie" = ""; then
@@ -2820,7 +2820,7 @@ if test "$gnutls" != "no"; then
         fi
     fi
     if test "$pass" = "no" && test "$gnutls" = "yes"; then
-	feature_not_found "gnutls" "Install gnutls devel >= 3.1.18"
+    feature_not_found "gnutls" "Install gnutls devel >= 3.1.18"
     else
         gnutls="$pass"
     fi
@@ -2852,16 +2852,16 @@ fi
 has_libgcrypt() {
     if ! has "libgcrypt-config"
     then
-	return 1
+    return 1
     fi
 
     if test -n "$cross_prefix"
     then
-	host=$(libgcrypt-config --host)
-	if test "$host-" != $cross_prefix
-	then
-	    return 1
-	fi
+    host=$(libgcrypt-config --host)
+    if test "$host-" != $cross_prefix
+    then
+        return 1
+    fi
     fi
 
     maj=`libgcrypt-config --version | awk -F . '{print $1}'`
@@ -3071,7 +3071,7 @@ EOF
          sdl_cflags="$sdl_cflags $(aalib-config --cflags 2>/dev/null)"
       fi
       if compile_prog "$sdl_cflags" "$sdl_libs" ; then
-	:
+    :
       else
         sdl=no
       fi
@@ -3689,8 +3689,8 @@ EOF
 if ! compile_prog "$CFLAGS" "$LIBS" ; then
     error_exit "sizeof(size_t) doesn't match GLIB_SIZEOF_SIZE_T."\
                "You probably need to set PKG_CONFIG_LIBDIR"\
-	       "to point to the right pkg-config files for your"\
-	       "build target"
+           "to point to the right pkg-config files for your"\
+           "build target"
 fi
 
 # Silence clang 3.5.0 warnings about glib attribute __alloc_size__ usage
@@ -4200,8 +4200,8 @@ if test "$glusterfs" != "no" ; then
 int
 main(void)
 {
-	/* new glfs_ftruncate() passes two additional args */
-	return glfs_ftruncate(NULL, 0, NULL, NULL);
+    /* new glfs_ftruncate() passes two additional args */
+    return glfs_ftruncate(NULL, 0, NULL, NULL);
 }
 EOF
     if compile_prog "$glusterfs_cflags" "$glusterfs_libs" ; then
@@ -4218,9 +4218,9 @@ glusterfs_iocb(glfs_fd_t *fd, ssize_t ret, struct glfs_stat *prestat, struct glf
 int
 main(void)
 {
-	glfs_io_cbk iocb = &glusterfs_iocb;
-	iocb(NULL, 0 , NULL, NULL, NULL);
-	return 0;
+    glfs_io_cbk iocb = &glusterfs_iocb;
+    iocb(NULL, 0 , NULL, NULL, NULL);
+    return 0;
 }
 EOF
     if compile_prog "$glusterfs_cflags" "$glusterfs_libs" ; then
@@ -4247,8 +4247,8 @@ cat > $TMPC << EOF
 int
 main(void)
 {
-	/* try to start inotify */
-	return inotify_init();
+    /* try to start inotify */
+    return inotify_init();
 }
 EOF
 if compile_prog "" "" ; then
@@ -4921,8 +4921,8 @@ if test "$mingw32" = "yes" && test "$guest_agent" != "no" && \
     *\ *) # The SDK is installed in "Program Files" by default, but we cannot
           # handle path with spaces. So we symlink the headers into ".sdk/vss".
           vss_win32_include="-isystem $source_path/.sdk/vss"
-	  symlink "$vss_win32_sdk/inc" "$source_path/.sdk/vss/inc"
-	  ;;
+      symlink "$vss_win32_sdk/inc" "$source_path/.sdk/vss/inc"
+      ;;
     *)    vss_win32_include="-isystem $vss_win32_sdk"
   esac
   cat > $TMPC << EOF
@@ -5643,7 +5643,7 @@ if test "$membarrier" = "yes"; then
     int main(void) {
         syscall(__NR_membarrier, MEMBARRIER_CMD_QUERY, 0);
         syscall(__NR_membarrier, MEMBARRIER_CMD_SHARED, 0);
-	exit(0);
+    exit(0);
     }
 EOF
         if compile_prog "" "" ; then
@@ -5720,7 +5720,7 @@ if test "$crypto_afalg" = "yes"
 then
     if test "$have_afalg" != "yes"
     then
-	error_exit "AF_ALG requested but could not be detected"
+    error_exit "AF_ALG requested but could not be detected"
     fi
 fi
 
@@ -5908,18 +5908,18 @@ fi
 # check for libpmem
 
 if test "$libpmem" != "no"; then
-	if $pkg_config --exists "libpmem"; then
-		libpmem="yes"
-		libpmem_libs=$($pkg_config --libs libpmem)
-		libpmem_cflags=$($pkg_config --cflags libpmem)
-		libs_softmmu="$libs_softmmu $libpmem_libs"
-		QEMU_CFLAGS="$QEMU_CFLAGS $libpmem_cflags"
-	else
-		if test "$libpmem" = "yes" ; then
-			feature_not_found "libpmem" "Install nvml or pmdk"
-		fi
-		libpmem="no"
-	fi
+    if $pkg_config --exists "libpmem"; then
+        libpmem="yes"
+        libpmem_libs=$($pkg_config --libs libpmem)
+        libpmem_cflags=$($pkg_config --cflags libpmem)
+        libs_softmmu="$libs_softmmu $libpmem_libs"
+        QEMU_CFLAGS="$QEMU_CFLAGS $libpmem_cflags"
+    else
+        if test "$libpmem" = "yes" ; then
+            feature_not_found "libpmem" "Install nvml or pmdk"
+        fi
+        libpmem="no"
+    fi
 fi
 
 ##########################################
@@ -6643,10 +6643,10 @@ echo "CONFIG_AUDIO_DRIVERS=$audio_drv_list" >> $config_host_mak
 for drv in $audio_drv_list; do
     def=CONFIG_AUDIO_$(echo $drv | LC_ALL=C tr '[a-z]' '[A-Z]')
     case "$drv" in
-	alsa | oss | pa | sdl)
-	    echo "$def=m" >> $config_host_mak ;;
-	*)
-	    echo "$def=y" >> $config_host_mak ;;
+    alsa | oss | pa | sdl)
+        echo "$def=m" >> $config_host_mak ;;
+    *)
+        echo "$def=y" >> $config_host_mak ;;
     esac
 done
 echo "ALSA_LIBS=$alsa_libs" >> $config_host_mak
@@ -7479,14 +7479,14 @@ TARGET_ABI_DIR=""
 case "$target_name" in
   i386)
     mttcg="yes"
-	gdb_xml_files="i386-32bit.xml"
+    gdb_xml_files="i386-32bit.xml"
     target_compiler=$cross_cc_i386
     target_compiler_cflags=$cross_cc_ccflags_i386
   ;;
   x86_64)
     TARGET_BASE_ARCH=i386
     mttcg="yes"
-	gdb_xml_files="i386-64bit.xml"
+    gdb_xml_files="i386-64bit.xml"
     target_compiler=$cross_cc_x86_64
   ;;
   alpha)
@@ -7510,6 +7510,10 @@ case "$target_name" in
     target_compiler=$cross_cc_aarch64
     eval "target_compiler_cflags=\$cross_cc_cflags_${target_name}"
   ;;
+  avr)
+    gdb_xml_files="avr-cpu.xml"
+    target_compiler=$cross_cc_avr
+  ;;
   cris)
     target_compiler=$cross_cc_cris
   ;;
@@ -7790,6 +7794,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
       disas_config "ARM_A64"
     fi
   ;;
+  avr)
+    disas_config "AVR"
+  ;;
   cris)
     disas_config "CRIS"
   ;;
@@ -8003,10 +8010,10 @@ preserve_env() {
 
     if test -n "$envval"
     then
-	echo "$envname='$envval'" >> config.status
-	echo "export $envname" >> config.status
+    echo "$envname='$envval'" >> config.status
+    echo "export $envname" >> config.status
     else
-	echo "unset $envname" >> config.status
+    echo "unset $envname" >> config.status
     fi
 }
 
diff --git a/default-configs/avr-softmmu.mak b/default-configs/avr-softmmu.mak
new file mode 100644
index 0000000000..d1e1c28118
--- /dev/null
+++ b/default-configs/avr-softmmu.mak
@@ -0,0 +1,5 @@
+# Default configuration for avr-softmmu
+
+# Boards:
+#
+CONFIG_AVR_SAMPLE=y
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index e9c7dd8eb4..8bedce17ac 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -211,6 +211,12 @@ enum bfd_architecture
 #define bfd_mach_m32r          0  /* backwards compatibility */
   bfd_arch_mn10200,    /* Matsushita MN10200 */
   bfd_arch_mn10300,    /* Matsushita MN10300 */
+  bfd_arch_avr,       /* Atmel AVR microcontrollers.  */
+#define bfd_mach_avr1          1
+#define bfd_mach_avr2          2
+#define bfd_mach_avr3          3
+#define bfd_mach_avr4          4
+#define bfd_mach_avr5          5
   bfd_arch_cris,       /* Axis CRIS */
 #define bfd_mach_cris_v0_v10   255
 #define bfd_mach_cris_v32      32
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 62c6fe4cf1..893df26ce2 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -24,6 +24,7 @@ enum {
     QEMU_ARCH_NIOS2 = (1 << 17),
     QEMU_ARCH_HPPA = (1 << 18),
     QEMU_ARCH_RISCV = (1 << 19),
+    QEMU_ARCH_AVR = (1 << 20),
 };
 
 extern const uint32_t arch_type;
diff --git a/qapi/machine.json b/qapi/machine.json
index de5c742d72..afede0bc50 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -21,11 +21,12 @@
 #        is true even for "qemu-system-x86_64".
 #
 # ppcemb: dropped in 3.1
+# avr: sicne 4.2
 #
 # Since: 3.0
 ##
 { 'enum' : 'SysEmuTarget',
-  'data' : [ 'aarch64', 'alpha', 'arm', 'cris', 'hppa', 'i386', 'lm32',
+  'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386', 'lm32',
              'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
              'mips64el', 'mipsel', 'moxie', 'nios2', 'or1k', 'ppc',
              'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4',
diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs
new file mode 100644
index 0000000000..2976affd95
--- /dev/null
+++ b/target/avr/Makefile.objs
@@ -0,0 +1,33 @@
+#
+#  QEMU AVR CPU
+#
+#  Copyright (c) 2019 Michael Rolnik
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, see
+#  <http://www.gnu.org/licenses/lgpl-2.1.html>
+#
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+decode-y = $(SRC_PATH)/target/avr/insn.decode
+
+target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE)
+	$(call quiet-command, \
+	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \
+	  "GEN", $(TARGET_DIR)$@)
+
+target/avr/translate.o: target/avr/decode_insn.inc.c
+
+obj-y += translate.o cpu.o helper.o
+obj-y += gdbstub.o
+obj-$(CONFIG_SOFTMMU) += machine.o
diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c
index 5953d31755..3e5c74e73e 100644
--- a/tests/machine-none-test.c
+++ b/tests/machine-none-test.c
@@ -27,6 +27,7 @@ static struct arch2cpu cpus_map[] = {
     /* tested targets list */
     { "arm", "cortex-a15" },
     { "aarch64", "cortex-a57" },
+    { "avr", "avr6-avr-cpu" },
     { "x86_64", "qemu64,apic-id=0" },
     { "i386", "qemu32,apic-id=0" },
     { "alpha", "ev67" },
-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* [Qemu-devel] [PATCH v30 8/8] target/avr: Add tests
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
                   ` (6 preceding siblings ...)
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
@ 2019-09-02 14:01 ` Michael Rolnik
  2019-10-11 15:32 ` [PATCH v30 0/8] QEMU AVR 8 bit cores Philippe Mathieu-Daudé
  2019-10-11 15:41 ` Philippe Mathieu-Daudé
  9 siblings, 0 replies; 19+ messages in thread
From: Michael Rolnik @ 2019-09-02 14:01 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo, philmd

1. Avocado test
    The test is based on
    https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
    demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
    it also demostrates that timer and IRQ are working

2. Boot serial test
    Prinit out 'T' through serial port

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>
---
 tests/Makefile.include           |  2 ++
 tests/acceptance/machine_avr6.py | 36 ++++++++++++++++++++++++++++++++
 tests/boot-serial-test.c         | 10 +++++++++
 3 files changed, 48 insertions(+)
 create mode 100644 tests/acceptance/machine_avr6.py

diff --git a/tests/Makefile.include b/tests/Makefile.include
index 49684fd4f4..dbaeb87572 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -202,6 +202,8 @@ check-qtest-i386-y += tests/test-x86-cpuid-compat$(EXESUF)
 check-qtest-i386-y += tests/numa-test$(EXESUF)
 check-qtest-x86_64-y += $(check-qtest-i386-y)
 
+check-qtest-avr-y += tests/boot-serial-test$(EXESUF)
+
 check-qtest-alpha-y += tests/boot-serial-test$(EXESUF)
 check-qtest-alpha-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF)
 
diff --git a/tests/acceptance/machine_avr6.py b/tests/acceptance/machine_avr6.py
new file mode 100644
index 0000000000..0601080b01
--- /dev/null
+++ b/tests/acceptance/machine_avr6.py
@@ -0,0 +1,36 @@
+import logging
+import time
+import distutils.spawn
+
+from avocado import skipUnless
+from avocado_qemu import Test
+from avocado.utils import process
+
+class AVR6Machine(Test):
+    timeout = 5
+
+    def test_freertos(self):
+        """
+        :avocado: tags=arch:avr
+        :avocado: tags=machine:sample
+        """
+        """
+        https://github.com/seharris/qemu-avr-tests/raw/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf
+        constantly prints out 'ABCDEFGHIJKLMNOPQRSTUVWXABCDEFGHIJKLMNOPQRSTUVWX'
+        """
+        rom_url = 'https://github.com/seharris/qemu-avr-tests'
+        rom_url += '/raw/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf'
+        rom_hash = '7eb521f511ca8f2622e0a3c5e8dd686efbb911d4'
+        rom_path = self.fetch_asset(rom_url, asset_hash=rom_hash)
+
+        self.vm.set_machine('sample')
+        self.vm.add_args('-bios', rom_path)
+        self.vm.add_args('-nographic')
+        self.vm.launch()
+
+        time.sleep(2)
+        self.vm.shutdown()
+
+        match = 'ABCDEFGHIJKLMNOPQRSTUVWXABCDEFGHIJKLMNOPQRSTUVWX'
+
+        self.assertIn(match, self.vm.get_log())
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index 24852d4c7d..22cbaccc1b 100644
--- a/tests/boot-serial-test.c
+++ b/tests/boot-serial-test.c
@@ -16,6 +16,15 @@
 #include "qemu/osdep.h"
 #include "libqtest.h"
 
+static const uint8_t bios_avr[] = {
+    0x88, 0xe0,             /* ldi r24, 0x08   */
+    0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
+    0x86, 0xe0,             /* ldi r24, 0x06   */
+    0x80, 0x93, 0xc2, 0x00, /* sts 0x00C2, r24 ; Set the data bits to 8 */
+    0x84, 0xe5,             /* ldi r24, 0x54   */
+    0x80, 0x93, 0xc6, 0x00, /* sts 0x00C6, r24 ; Output 'T' */
+};
+
 static const uint8_t kernel_mcf5208[] = {
     0x41, 0xf9, 0xfc, 0x06, 0x00, 0x00,     /* lea 0xfc060000,%a0 */
     0x10, 0x3c, 0x00, 0x54,                 /* move.b #'T',%d0 */
@@ -92,6 +101,7 @@ typedef struct testdef {
 
 static testdef_t tests[] = {
     { "alpha", "clipper", "", "PCI:" },
+    { "avr", "sample", "", "T", sizeof(bios_avr), NULL, bios_avr },
     { "ppc", "ppce500", "", "U-Boot" },
     { "ppc", "40p", "-vga none -boot d", "Trying cd:," },
     { "ppc", "g3beige", "", "PowerPC,750" },
-- 
2.17.2 (Apple Git-113)



^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation Michael Rolnik
@ 2019-10-11 14:13   ` Aleksandar Markovic
  2019-10-12 16:33     ` Michael Rolnik
  0 siblings, 1 reply; 19+ messages in thread
From: Aleksandar Markovic @ 2019-10-11 14:13 UTC (permalink / raw)
  To: Michael Rolnik
  Cc: thuth, richard.henderson, qemu-devel, dovgaluk, imammedo, philmd

[-- Attachment #1: Type: text/plain, Size: 61971 bytes --]

On Monday, September 2, 2019, Michael Rolnik <mrolnik@gmail.com> wrote:

> This includes:
> - TCG translations for each instruction
>
> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
> ---
>  target/avr/translate.c | 2888 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 2888 insertions(+)
>  create mode 100644 target/avr/translate.c
>
>
Hi, Michael,


This patch is way too large. I suggest splitting it into:

- register definitions
- load instruction handling
- store instruction handling
- logic instruction handling

etc.

Thanks, Aleksandar

P.S. One more hurdle with your communication on the list is that you don't
use "inline responding" while replaying, please use it in future. See other
messages in the mailing list how "inline responding" looks.





> diff --git a/target/avr/translate.c b/target/avr/translate.c
> new file mode 100644
> index 0000000000..42cb4a690c
> --- /dev/null
> +++ b/target/avr/translate.c
> @@ -0,0 +1,2888 @@
> +/*
> + * QEMU AVR CPU
> + *
> + * Copyright (c) 2019 Michael Rolnik
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/qemu-print.h"
> +#include "tcg/tcg.h"
> +#include "cpu.h"
> +#include "exec/exec-all.h"
> +#include "disas/disas.h"
> +#include "tcg-op.h"
> +#include "exec/cpu_ldst.h"
> +#include "exec/helper-proto.h"
> +#include "exec/helper-gen.h"
> +#include "exec/log.h"
> +#include "exec/gdbstub.h"
> +#include "exec/translator.h"
> +
> +/*
> + *  Define if you want a BREAK instruction translated to a breakpoint
> + *  Active debugging connection is assumed
> + *  This is for
> + *  https://github.com/seharris/qemu-avr-tests/tree/master/
> instruction-tests
> + *  tests
> + */
> +#undef BREAKPOINT_ON_BREAK
> +
> +static TCGv cpu_pc;
> +
> +static TCGv cpu_Cf;
> +static TCGv cpu_Zf;
> +static TCGv cpu_Nf;
> +static TCGv cpu_Vf;
> +static TCGv cpu_Sf;
> +static TCGv cpu_Hf;
> +static TCGv cpu_Tf;
> +static TCGv cpu_If;
> +
> +static TCGv cpu_rampD;
> +static TCGv cpu_rampX;
> +static TCGv cpu_rampY;
> +static TCGv cpu_rampZ;
> +
> +static TCGv cpu_r[NO_CPU_REGISTERS];
> +static TCGv cpu_eind;
> +static TCGv cpu_sp;
> +
> +static TCGv cpu_skip;
> +
> +static const char reg_names[NO_CPU_REGISTERS][8] = {
> +    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
> +    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
> +    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
> +    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
> +};
> +#define REG(x) (cpu_r[x])
> +
> +enum {
> +    DISAS_EXIT   = DISAS_TARGET_0,  /* We want return to the cpu main
> loop.  */
> +    DISAS_LOOKUP = DISAS_TARGET_1,  /* We have a variable condition
> exit.  */
> +    DISAS_CHAIN  = DISAS_TARGET_2,  /* We have a single condition exit.
> */
> +};
> +
> +typedef struct DisasContext DisasContext;
> +
> +/* This is the state at translation time. */
> +struct DisasContext {
> +    TranslationBlock *tb;
> +
> +    CPUAVRState *env;
> +    CPUState *cs;
> +
> +    target_long npc;
> +    uint32_t opcode;
> +
> +    /* Routine used to access memory */
> +    int memidx;
> +    int bstate;
> +    int singlestep;
> +
> +    TCGv skip_var0;
> +    TCGv skip_var1;
> +    TCGCond skip_cond;
> +    bool free_skip_var0;
> +};
> +
> +static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); }
> +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); }
> +static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) *
> 2; }
> +static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; }
> +
> +static uint16_t next_word(DisasContext *ctx)
> +{
> +    return cpu_lduw_code(ctx->env, ctx->npc++ * 2);
> +}
> +
> +static int append_16(DisasContext *ctx, int x)
> +{
> +    return x << 16 | next_word(ctx);
> +}
> +
> +static bool decode_insn(DisasContext *ctx, uint16_t insn);
> +#include "decode_insn.inc.c"
> +
> +static bool avr_have_feature(DisasContext *ctx, int feature)
> +{
> +    if (!avr_feature(ctx->env, feature)) {
> +        gen_helper_unsupported(cpu_env);
> +        ctx->bstate = DISAS_NORETURN;
> +        return false;
> +    }
> +    return true;
> +}
> +
> +static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +{
> +    TranslationBlock *tb = ctx->tb;
> +
> +    if (ctx->singlestep == 0) {
> +        tcg_gen_goto_tb(n);
> +        tcg_gen_movi_i32(cpu_pc, dest);
> +        tcg_gen_exit_tb(tb, n);
> +    } else {
> +        tcg_gen_movi_i32(cpu_pc, dest);
> +        gen_helper_debug(cpu_env);
> +        tcg_gen_exit_tb(NULL, 0);
> +    }
> +    ctx->bstate = DISAS_NORETURN;
> +}
> +
> +#include "exec/gen-icount.h"
> +
> +static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)
> +{
> +    TCGv t1 = tcg_temp_new_i32();
> +    TCGv t2 = tcg_temp_new_i32();
> +    TCGv t3 = tcg_temp_new_i32();
> +
> +    tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */
> +    tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */
> +    tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */
> +    tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */
> +    tcg_gen_or_tl(t1, t1, t3);
> +
> +    tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */
> +    tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */
> +    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
> +
> +    tcg_temp_free_i32(t3);
> +    tcg_temp_free_i32(t2);
> +    tcg_temp_free_i32(t1);
> +}
> +
> +static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr)
> +{
> +    TCGv t1 = tcg_temp_new_i32();
> +    TCGv t2 = tcg_temp_new_i32();
> +
> +    /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R = (Rd ^ R) & ~(Rd ^ Rr) */
> +    tcg_gen_xor_tl(t1, Rd, R);
> +    tcg_gen_xor_tl(t2, Rd, Rr);
> +    tcg_gen_andc_tl(t1, t1, t2);
> +
> +    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
> +
> +    tcg_temp_free_i32(t2);
> +    tcg_temp_free_i32(t1);
> +}
> +
> +static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)
> +{
> +    TCGv t1 = tcg_temp_new_i32();
> +    TCGv t2 = tcg_temp_new_i32();
> +    TCGv t3 = tcg_temp_new_i32();
> +
> +    /* Cf & Hf */
> +    tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */
> +    tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */
> +    tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */
> +    tcg_gen_and_tl(t3, t3, R);
> +    tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
> +    tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */
> +    tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */
> +    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
> +
> +    tcg_temp_free_i32(t3);
> +    tcg_temp_free_i32(t2);
> +    tcg_temp_free_i32(t1);
> +}
> +
> +static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr)
> +{
> +    TCGv t1 = tcg_temp_new_i32();
> +    TCGv t2 = tcg_temp_new_i32();
> +
> +    /* Vf */
> +    /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R = (Rd ^ R) & (Rd ^ R) */
> +    tcg_gen_xor_tl(t1, Rd, R);
> +    tcg_gen_xor_tl(t2, Rd, Rr);
> +    tcg_gen_and_tl(t1, t1, t2);
> +    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
> +
> +    tcg_temp_free_i32(t2);
> +    tcg_temp_free_i32(t1);
> +}
> +
> +static void gen_rshift_ZNVSf(TCGv R)
> +{
> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
> +    tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf);
> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
> +}
> +
> +static void gen_NSf(TCGv R)
> +{
> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
> +}
> +
> +static void gen_ZNSf(TCGv R)
> +{
> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
> +}
> +
> +static void gen_push_ret(DisasContext *ctx, int ret)
> +{
> +    if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
> +
> +        TCGv t0 = tcg_const_i32((ret & 0x0000ff));
> +
> +        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> +
> +        tcg_temp_free_i32(t0);
> +    } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
> +
> +        TCGv t0 = tcg_const_i32((ret & 0x00ffff));
> +
> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> +        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> +
> +        tcg_temp_free_i32(t0);
> +
> +    } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
> +
> +        TCGv lo = tcg_const_i32((ret & 0x0000ff));
> +        TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
> +
> +        tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
> +        tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> +
> +        tcg_temp_free_i32(lo);
> +        tcg_temp_free_i32(hi);
> +    }
> +}
> +
> +static void gen_pop_ret(DisasContext *ctx, TCGv ret)
> +{
> +    if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> +        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
> +    } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> +        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> +    } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
> +        TCGv lo = tcg_temp_new_i32();
> +        TCGv hi = tcg_temp_new_i32();
> +
> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> +        tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> +
> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
> +        tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
> +
> +        tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
> +
> +        tcg_temp_free_i32(lo);
> +        tcg_temp_free_i32(hi);
> +    }
> +}
> +
> +static void gen_jmp_ez(DisasContext *ctx)
> +{
> +    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
> +    tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind);
> +    ctx->bstate = DISAS_LOOKUP;
> +}
> +
> +static void gen_jmp_z(DisasContext *ctx)
> +{
> +    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
> +    ctx->bstate = DISAS_LOOKUP;
> +}
> +
> +/*
> + *  in the gen_set_addr & gen_get_addr functions
> + *  H assumed to be in 0x00ff0000 format
> + *  M assumed to be in 0x000000ff format
> + *  L assumed to be in 0x000000ff format
> + */
> +static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L)
> +{
> +
> +    tcg_gen_andi_tl(L, addr, 0x000000ff);
> +
> +    tcg_gen_andi_tl(M, addr, 0x0000ff00);
> +    tcg_gen_shri_tl(M, M, 8);
> +
> +    tcg_gen_andi_tl(H, addr, 0x00ff0000);
> +}
> +
> +static void gen_set_xaddr(TCGv addr)
> +{
> +    gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]);
> +}
> +
> +static void gen_set_yaddr(TCGv addr)
> +{
> +    gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]);
> +}
> +
> +static void gen_set_zaddr(TCGv addr)
> +{
> +    gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]);
> +}
> +
> +static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L)
> +{
> +    TCGv addr = tcg_temp_new_i32();
> +
> +    tcg_gen_deposit_tl(addr, M, H, 8, 8);
> +    tcg_gen_deposit_tl(addr, L, addr, 8, 16);
> +
> +    return addr;
> +}
> +
> +static TCGv gen_get_xaddr(void)
> +{
> +    return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]);
> +}
> +
> +static TCGv gen_get_yaddr(void)
> +{
> +    return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]);
> +}
> +
> +static TCGv gen_get_zaddr(void)
> +{
> +    return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]);
> +}
> +
> +/*
> + *  Adds two registers and the contents of the C Flag and places the
> result in
> + *  the destination register Rd.
> + */
> +static bool trans_ADC(DisasContext *ctx, arg_ADC *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    /* op */
> +    tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */
> +    tcg_gen_add_tl(R, R, cpu_Cf);
> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> +
> +    gen_add_CHf(R, Rd, Rr);
> +    gen_add_Vf(R, Rd, Rr);
> +    gen_ZNSf(R);
> +
> +    /* R */
> +    tcg_gen_mov_tl(Rd, R);
> +
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  Adds two registers without the C Flag and places the result in the
> + *  destination register Rd.
> + */
> +static bool trans_ADD(DisasContext *ctx, arg_ADD *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    /* op */
> +    tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */
> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> +
> +    gen_add_CHf(R, Rd, Rr);
> +    gen_add_Vf(R, Rd, Rr);
> +    gen_ZNSf(R);
> +
> +    /* R */
> +    tcg_gen_mov_tl(Rd, R);
> +
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  Adds an immediate value (0 - 63) to a register pair and places the
> result
> + *  in the register pair. This instruction operates on the upper four
> register
> + *  pairs, and is well suited for operations on the pointer registers.
> This
> + *  instruction is not available in all devices. Refer to the device
> specific
> + *  instruction set summary.
> + */
> +static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) {
> +        return true;
> +    }
> +
> +    TCGv RdL = cpu_r[a->rd];
> +    TCGv RdH = cpu_r[a->rd + 1];
> +    int Imm = (a->imm);
> +    TCGv R = tcg_temp_new_i32();
> +    TCGv Rd = tcg_temp_new_i32();
> +
> +    /* op */
> +    tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */
> +    tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */
> +    tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */
> +
> +    /* Cf */
> +    tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */
> +    tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15);
> +
> +    /* Vf */
> +    tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R & ~Rd */
> +    tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15);
> +
> +    /* Zf */
> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
> +
> +    /* Nf */
> +    tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */
> +
> +    /* Sf */
> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */
> +
> +    /* R */
> +    tcg_gen_andi_tl(RdL, R, 0xff);
> +    tcg_gen_shri_tl(RdH, R, 8);
> +
> +    tcg_temp_free_i32(Rd);
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  Performs the logical AND between the contents of register Rd and
> register
> + *  Rr and places the result in the destination register Rd.
> + */
> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    /* op */
> +    tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
> +
> +    /* Vf */
> +    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
> +
> +    /* Zf */
> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
> +
> +    gen_ZNSf(R);
> +
> +    /* R */
> +    tcg_gen_mov_tl(Rd, R);
> +
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  Performs the logical AND between the contents of register Rd and a
> constant
> + *  and places the result in the destination register Rd.
> + */
> +static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    int Imm = (a->imm);
> +
> +    /* op */
> +    tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd & Imm */
> +
> +    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
> +    gen_ZNSf(Rd);
> +
> +    return true;
> +}
> +
> +/*
> + *  Shifts all bits in Rd one place to the right. Bit 7 is held constant.
> Bit 0
> + *  is loaded into the C Flag of the SREG. This operation effectively
> divides a
> + *  signed value by two without changing its sign. The Carry Flag can be
> used to
> + *  round the result.
> + */
> +static bool trans_ASR(DisasContext *ctx, arg_ASR *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv t0 = tcg_temp_new_i32();
> +
> +    /* Cf */
> +    tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */
> +
> +    /* op */
> +    tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */
> +    tcg_gen_shri_tl(Rd, Rd, 1);
> +    tcg_gen_or_tl(Rd, Rd, t0);
> +
> +    gen_rshift_ZNVSf(Rd);
> +
> +    tcg_temp_free_i32(t0);
> +
> +    return true;
> +}
> +
> +/*
> + *  Clears a single Flag in SREG.
> + */
> +static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
> +{
> +    switch (a->bit) {
> +    case 0x00:
> +        tcg_gen_movi_tl(cpu_Cf, 0x00);
> +        break;
> +    case 0x01:
> +        tcg_gen_movi_tl(cpu_Zf, 0x01);
> +        break;
> +    case 0x02:
> +        tcg_gen_movi_tl(cpu_Nf, 0x00);
> +        break;
> +    case 0x03:
> +        tcg_gen_movi_tl(cpu_Vf, 0x00);
> +        break;
> +    case 0x04:
> +        tcg_gen_movi_tl(cpu_Sf, 0x00);
> +        break;
> +    case 0x05:
> +        tcg_gen_movi_tl(cpu_Hf, 0x00);
> +        break;
> +    case 0x06:
> +        tcg_gen_movi_tl(cpu_Tf, 0x00);
> +        break;
> +    case 0x07:
> +        tcg_gen_movi_tl(cpu_If, 0x00);
> +        break;
> +    }
> +
> +    return true;
> +}
> +
> +/*
> + *  Copies the T Flag in the SREG (Status Register) to bit b in register
> Rd.
> + */
> +static bool trans_BLD(DisasContext *ctx, arg_BLD *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv t1 = tcg_temp_new_i32();
> +
> +    tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */
> +    tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */
> +    tcg_gen_or_tl(Rd, Rd, t1);
> +
> +    tcg_temp_free_i32(t1);
> +
> +    return true;
> +}
> +
> +/*
> + *  Conditional relative branch. Tests a single bit in SREG and branches
> + *  relatively to PC if the bit is cleared. This instruction branches
> relatively
> + *  to PC in either direction (PC - 63 < = destination <= PC + 64). The
> + *  parameter k is the offset from PC and is represented in two's
> complement
> + *  form.
> + */
> +static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a)
> +{
> +    TCGLabel *not_taken = gen_new_label();
> +    TCGCond cond = TCG_COND_EQ;
> +    TCGv var;
> +
> +    switch (a->bit) {
> +    case 0x00:
> +        var = cpu_Cf;
> +        break;
> +    case 0x01:
> +        cond = TCG_COND_NE;
> +        var = cpu_Zf;
> +        break;
> +    case 0x02:
> +        var = cpu_Nf;
> +        break;
> +    case 0x03:
> +        var = cpu_Vf;
> +        break;
> +    case 0x04:
> +        var = cpu_Sf;
> +        break;
> +    case 0x05:
> +        var = cpu_Hf;
> +        break;
> +    case 0x06:
> +        var = cpu_Tf;
> +        break;
> +    case 0x07:
> +        var = cpu_If;
> +        break;
> +    default:
> +        g_assert_not_reached();
> +    }
> +
> +    tcg_gen_brcondi_i32(tcg_invert_cond(cond), var, 0, not_taken);
> +    gen_goto_tb(ctx, 0, ctx->npc + a->imm);
> +    gen_set_label(not_taken);
> +
> +    ctx->bstate = DISAS_CHAIN;
> +    return true;
> +}
> +
> +/*
> + *  Conditional relative branch. Tests a single bit in SREG and branches
> + *  relatively to PC if the bit is set. This instruction branches
> relatively to
> + *  PC in either direction (PC - 63 < = destination <= PC + 64). The
> parameter k
> + *  is the offset from PC and is represented in two's complement form.
> + */
> +static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a)
> +{
> +    TCGLabel *not_taken = gen_new_label();
> +    TCGCond cond = TCG_COND_NE;
> +    TCGv var;
> +
> +    switch (a->bit) {
> +    case 0x00:
> +        var = cpu_Cf;
> +        break;
> +    case 0x01:
> +        cond = TCG_COND_EQ;
> +        var = cpu_Zf;
> +        break;
> +    case 0x02:
> +        var = cpu_Nf;
> +        break;
> +    case 0x03:
> +        var = cpu_Vf;
> +        break;
> +    case 0x04:
> +        var = cpu_Sf;
> +        break;
> +    case 0x05:
> +        var = cpu_Hf;
> +        break;
> +    case 0x06:
> +        var = cpu_Tf;
> +        break;
> +    case 0x07:
> +        var = cpu_If;
> +        break;
> +    default:
> +        g_assert_not_reached();
> +    }
> +
> +    tcg_gen_brcondi_i32(tcg_invert_cond(cond), var, 0, not_taken);
> +    gen_goto_tb(ctx, 0, ctx->npc + a->imm);
> +    gen_set_label(not_taken);
> +
> +    ctx->bstate = DISAS_CHAIN;
> +    return true;
> +}
> +
> +/*
> + *  Sets a single Flag or bit in SREG.
> + */
> +static bool trans_BSET(DisasContext *ctx, arg_BSET *a)
> +{
> +    switch (a->bit) {
> +    case 0x00:
> +        tcg_gen_movi_tl(cpu_Cf, 0x01);
> +        break;
> +    case 0x01:
> +        tcg_gen_movi_tl(cpu_Zf, 0x00);
> +        break;
> +    case 0x02:
> +        tcg_gen_movi_tl(cpu_Nf, 0x01);
> +        break;
> +    case 0x03:
> +        tcg_gen_movi_tl(cpu_Vf, 0x01);
> +        break;
> +    case 0x04:
> +        tcg_gen_movi_tl(cpu_Sf, 0x01);
> +        break;
> +    case 0x05:
> +        tcg_gen_movi_tl(cpu_Hf, 0x01);
> +        break;
> +    case 0x06:
> +        tcg_gen_movi_tl(cpu_Tf, 0x01);
> +        break;
> +    case 0x07:
> +        tcg_gen_movi_tl(cpu_If, 0x01);
> +        break;
> +    }
> +
> +    return true;
> +}
> +
> +/*
> + *  The BREAK instruction is used by the On-chip Debug system, and is
> + *  normally not used in the application software. When the BREAK
> instruction is
> + *  executed, the AVR CPU is set in the Stopped Mode. This gives the
> On-chip
> + *  Debugger access to internal resources.  If any Lock bits are set, or
> either
> + *  the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the
> BREAK
> + *  instruction as a NOP and will not enter the Stopped mode.  This
> instruction
> + *  is not available in all devices. Refer to the device specific
> instruction
> + *  set summary.
> + */
> +static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
> +        return true;
> +    }
> +
> +#ifdef BREAKPOINT_ON_BREAK
> +    tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
> +    gen_helper_debug(cpu_env);
> +    ctx->bstate = DISAS_EXIT;
> +#else
> +    /* NOP */
> +#endif
> +
> +    return true;
> +}
> +
> +/*
> + *  Stores bit b from Rd to the T Flag in SREG (Status Register).
> + */
> +static bool trans_BST(DisasContext *ctx, arg_BST *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +
> +    tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit);
> +    tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit);
> +
> +    return true;
> +}
> +
> +/*
> + *  Calls to a subroutine within the entire Program memory. The return
> + *  address (to the instruction after the CALL) will be stored onto the
> Stack.
> + *  (See also RCALL). The Stack Pointer uses a post-decrement scheme
> during
> + *  CALL.  This instruction is not available in all devices. Refer to the
> device
> + *  specific instruction set summary.
> + */
> +static bool trans_CALL(DisasContext *ctx, arg_CALL *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
> +        return true;
> +    }
> +
> +    int Imm = a->imm;
> +    int ret = ctx->npc;
> +
> +    gen_push_ret(ctx, ret);
> +    gen_goto_tb(ctx, 0, Imm);
> +
> +    return true;
> +}
> +
> +/*
> + *  Clears a specified bit in an I/O Register. This instruction operates
> on
> + *  the lower 32 I/O Registers -- addresses 0-31.
> + */
> +static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
> +{
> +    TCGv data = tcg_temp_new_i32();
> +    TCGv port = tcg_const_i32(a->reg);
> +
> +    gen_helper_inb(data, cpu_env, port);
> +    tcg_gen_andi_tl(data, data, ~(1 << a->bit));
> +    gen_helper_outb(cpu_env, port, data);
> +
> +    tcg_temp_free_i32(data);
> +    tcg_temp_free_i32(port);
> +
> +    return true;
> +}
> +
> +/*
> + *  Clears the specified bits in register Rd. Performs the logical AND
> + *  between the contents of register Rd and the complement of the
> constant mask
> + *  K. The result will be placed in register Rd.
> + */
> +static bool trans_COM(DisasContext *ctx, arg_COM *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    tcg_gen_xori_tl(Rd, Rd, 0xff);
> +
> +    tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */
> +    tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
> +    gen_ZNSf(Rd);
> +
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs a compare between two registers Rd and Rr.
> + *  None of the registers are changed. All conditional branches can be
> used
> + *  after this instruction.
> + */
> +static bool trans_CP(DisasContext *ctx, arg_CP *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    /* op */
> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> +
> +    gen_sub_CHf(R, Rd, Rr);
> +    gen_sub_Vf(R, Rd, Rr);
> +    gen_ZNSf(R);
> +
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs a compare between two registers Rd and Rr
> and
> + *  also takes into account the previous carry. None of the registers are
> + *  changed. All conditional branches can be used after this instruction.
> + */
> +static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    /* op */
> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
> +    tcg_gen_sub_tl(R, R, cpu_Cf);
> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> +
> +    gen_sub_CHf(R, Rd, Rr);
> +    gen_sub_Vf(R, Rd, Rr);
> +    gen_NSf(R);
> +
> +    /*
> +     * Previous value remains unchanged when the result is zero;
> +     * cleared otherwise.
> +     */
> +    tcg_gen_or_tl(cpu_Zf, cpu_Zf, R);
> +
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs a compare between register Rd and a
> constant.
> + *  The register is not changed. All conditional branches can be used
> after this
> + *  instruction.
> + */
> +static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    int Imm = a->imm;
> +    TCGv Rr = tcg_const_i32(Imm);
> +    TCGv R = tcg_temp_new_i32();
> +
> +    /* op */
> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> +
> +    gen_sub_CHf(R, Rd, Rr);
> +    gen_sub_Vf(R, Rd, Rr);
> +    gen_ZNSf(R);
> +
> +    tcg_temp_free_i32(R);
> +    tcg_temp_free_i32(Rr);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs a compare between two registers Rd and Rr,
> and
> + *  skips the next instruction if Rd = Rr.
> + */
> +static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a)
> +{
> +    ctx->skip_cond = TCG_COND_EQ;
> +    ctx->skip_var0 = cpu_r[a->rd];
> +    ctx->skip_var1 = cpu_r[a->rr];
> +    return true;
> +}
> +
> +/*
> + *  Subtracts one -1- from the contents of register Rd and places the
> result
> + *  in the destination register Rd.  The C Flag in SREG is not affected
> by the
> + *  operation, thus allowing the DEC instruction to be used on a loop
> counter in
> + *  multiple-precision computations.  When operating on unsigned values,
> only
> + *  BREQ and BRNE branches can be expected to perform consistently.  When
> + *  operating on two's complement values, all signed branches are
> available.
> + */
> +static bool trans_DEC(DisasContext *ctx, arg_DEC *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +
> +    tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */
> +    tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */
> +
> +    /* cpu_Vf = Rd == 0x7f */
> +    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f);
> +    gen_ZNSf(Rd);
> +
> +    return true;
> +}
> +
> +/*
> + *  The module is an instruction set extension to the AVR CPU, performing
> + *  DES iterations. The 64-bit data block (plaintext or ciphertext) is
> placed in
> + *  the CPU register file, registers R0-R7, where LSB of data is placed
> in LSB
> + *  of R0 and MSB of data is placed in MSB of R7. The full 64-bit key
> (including
> + *  parity bits) is placed in registers R8- R15, organized in the
> register file
> + *  with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing
> one DES
> + *  instruction performs one round in the DES algorithm. Sixteen rounds
> must be
> + *  executed in increasing order to form the correct DES ciphertext or
> + *  plaintext. Intermediate results are stored in the register file
> (R0-R15)
> + *  after each DES instruction. The instruction's operand (K) determines
> which
> + *  round is executed, and the half carry flag (H) determines whether
> encryption
> + *  or decryption is performed.  The DES algorithm is described in
> + *  "Specifications for the Data Encryption Standard" (Federal Information
> + *  Processing Standards Publication 46). Intermediate results in this
> + *  implementation differ from the standard because the initial
> permutation and
> + *  the inverse initial permutation are performed each iteration. This
> does not
> + *  affect the result in the final ciphertext or plaintext, but reduces
> + *  execution time.
> + */
> +static bool trans_DES(DisasContext *ctx, arg_DES *a)
> +{
> +    /* TODO */
> +    if (!avr_have_feature(ctx, AVR_FEATURE_DES)) {
> +        return true;
> +    }
> +
> +    return true;
> +}
> +
> +/*
> + *  Indirect call of a subroutine pointed to by the Z (16 bits) Pointer
> + *  Register in the Register File and the EIND Register in the I/O space.
> This
> + *  instruction allows for indirect calls to the entire 4M (words) Program
> + *  memory space. See also ICALL. The Stack Pointer uses a post-decrement
> scheme
> + *  during EICALL.  This instruction is not available in all devices.
> Refer to
> + *  the device specific instruction set summary.
> + */
> +static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
> +        return true;
> +    }
> +
> +    int ret = ctx->npc;
> +
> +    gen_push_ret(ctx, ret);
> +    gen_jmp_ez(ctx);
> +    return true;
> +}
> +
> +/*
> + *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
> + *  Register in the Register File and the EIND Register in the I/O space.
> This
> + *  instruction allows for indirect jumps to the entire 4M (words) Program
> + *  memory space. See also IJMP.  This instruction is not available in all
> + *  devices. Refer to the device specific instruction set summary.
> + */
> +static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
> +        return true;
> +    }
> +
> +    gen_jmp_ez(ctx);
> +    return true;
> +}
> +
> +/*
> + *  Loads one byte pointed to by the Z-register and the RAMPZ Register in
> + *  the I/O space, and places this byte in the destination register Rd.
> This
> + *  instruction features a 100% space effective constant initialization or
> + *  constant data fetch. The Program memory is organized in 16-bit words
> while
> + *  the Z-pointer is a byte address. Thus, the least significant bit of
> the
> + *  Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1).
> This
> + *  instruction can address the entire Program memory space. The Z-pointer
> + *  Register can either be left unchanged by the operation, or it can be
> + *  incremented. The incrementation applies to the entire 24-bit
> concatenation
> + *  of the RAMPZ and Z-pointer Registers.  Devices with Self-Programming
> + *  capability can use the ELPM instruction to read the Fuse and Lock bit
> value.
> + *  Refer to the device documentation for a detailed description.  This
> + *  instruction is not available in all devices. Refer to the device
> specific
> + *  instruction set summary.
> + */
> +static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
> +        return true;
> +    }
> +
> +    TCGv Rd = cpu_r[0];
> +    TCGv addr = gen_get_zaddr();
> +
> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
> +        return true;
> +    }
> +
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_zaddr();
> +
> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) {
> +        return true;
> +    }
> +
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_zaddr();
> +
> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> +
> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> +
> +    gen_set_zaddr(addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + *  Performs the logical EOR between the contents of register Rd and
> + *  register Rr and places the result in the destination register Rd.
> + */
> +static bool trans_EOR(DisasContext *ctx, arg_EOR *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +
> +    tcg_gen_xor_tl(Rd, Rd, Rr);
> +
> +    tcg_gen_movi_tl(cpu_Vf, 0);
> +    gen_ZNSf(Rd);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs 8-bit x 8-bit -> 16-bit unsigned
> + *  multiplication and shifts the result one bit left.
> + */
> +static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> +        return true;
> +    }
> +
> +    TCGv R0 = cpu_r[0];
> +    TCGv R1 = cpu_r[1];
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */
> +    tcg_gen_shli_tl(R, R, 1);
> +
> +    tcg_gen_andi_tl(R0, R, 0xff);
> +    tcg_gen_shri_tl(R1, R, 8);
> +    tcg_gen_andi_tl(R1, R1, 0xff);
> +
> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
> +
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed
> multiplication
> + *  and shifts the result one bit left.
> + */
> +static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> +        return true;
> +    }
> +
> +    TCGv R0 = cpu_r[0];
> +    TCGv R1 = cpu_r[1];
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +    TCGv t0 = tcg_temp_new_i32();
> +    TCGv t1 = tcg_temp_new_i32();
> +
> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
> +    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */
> +    tcg_gen_mul_tl(R, t0, t1); /* R = Rd *Rr */
> +    tcg_gen_shli_tl(R, R, 1);
> +
> +    tcg_gen_andi_tl(R0, R, 0xff);
> +    tcg_gen_shri_tl(R1, R, 8);
> +    tcg_gen_andi_tl(R1, R1, 0xff);
> +
> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
> +
> +    tcg_temp_free_i32(t1);
> +    tcg_temp_free_i32(t0);
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed
> multiplication
> + *  and shifts the result one bit left.
> + */
> +static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> +        return true;
> +    }
> +
> +    TCGv R0 = cpu_r[0];
> +    TCGv R1 = cpu_r[1];
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +    TCGv t0 = tcg_temp_new_i32();
> +
> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
> +    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */
> +    tcg_gen_shli_tl(R, R, 1);
> +
> +    tcg_gen_andi_tl(R0, R, 0xff);
> +    tcg_gen_shri_tl(R1, R, 8);
> +    tcg_gen_andi_tl(R1, R1, 0xff);
> +
> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
> +
> +    tcg_temp_free_i32(t0);
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  Calls to a subroutine within the entire 4M (words) Program memory. The
> + *  return address (to the instruction after the CALL) will be stored
> onto the
> + *  Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme
> during
> + *  CALL.  This instruction is not available in all devices. Refer to the
> device
> + *  specific instruction set summary.
> + */
> +static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
> +        return true;
> +    }
> +
> +    int ret = ctx->npc;
> +
> +    gen_push_ret(ctx, ret);
> +    gen_jmp_z(ctx);
> +
> +    return true;
> +}
> +
> +/*
> + *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
> + *  Register in the Register File. The Z-pointer Register is 16 bits wide
> and
> + *  allows jump within the lowest 64K words (128KB) section of Program
> memory.
> + *  This instruction is not available in all devices. Refer to the device
> + *  specific instruction set summary.
> + */
> +static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
> +        return true;
> +    }
> +
> +    gen_jmp_z(ctx);
> +
> +    return true;
> +}
> +
> +/*
> + *  Loads data from the I/O Space (Ports, Timers, Configuration Registers,
> + *  etc.) into register Rd in the Register File.
> + */
> +static bool trans_IN(DisasContext *ctx, arg_IN *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv port = tcg_const_i32(a->imm);
> +
> +    gen_helper_inb(Rd, cpu_env, port);
> +
> +    tcg_temp_free_i32(port);
> +
> +    return true;
> +}
> +
> +/*
> + *  Adds one -1- to the contents of register Rd and places the result in
> the
> + *  destination register Rd.  The C Flag in SREG is not affected by the
> + *  operation, thus allowing the INC instruction to be used on a loop
> counter in
> + *  multiple-precision computations.  When operating on unsigned numbers,
> only
> + *  BREQ and BRNE branches can be expected to perform consistently. When
> + *  operating on two's complement values, all signed branches are
> available.
> + */
> +static bool trans_INC(DisasContext *ctx, arg_INC *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +
> +    tcg_gen_addi_tl(Rd, Rd, 1);
> +    tcg_gen_andi_tl(Rd, Rd, 0xff);
> +
> +    /* cpu_Vf = Rd == 0x80 */
> +    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80);
> +    gen_ZNSf(Rd);
> +
> +    return true;
> +}
> +
> +/*
> + *  Jump to an address within the entire 4M (words) Program memory. See
> also
> + *  RJMP.  This instruction is not available in all devices. Refer to the
> device
> + *  specific instruction set summary.0
> + */
> +static bool trans_JMP(DisasContext *ctx, arg_JMP *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
> +        return true;
> +    }
> +
> +    gen_goto_tb(ctx, 0, a->imm);
> +
> +    return true;
> +}
> +
> +/*
> + *  Load one byte indirect from data space to register and stores an clear
> + *  the bits in data space specified by the register. The instruction can
> only
> + *  be used towards internal SRAM.  The data location is pointed to by
> the Z (16
> + *  bits) Pointer Register in the Register File. Memory access is limited
> to the
> + *  current data segment of 64KB. To access another data segment in
> devices with
> + *  more than 64KB data space, the RAMPZ in register in the I/O area has
> to be
> + *  changed.  The Z-pointer Register is left unchanged by the operation.
> This
> + *  instruction is especially suited for clearing status bits stored in
> SRAM.
> + */
> +static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
> +{
> +    if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
> +        gen_helper_fullwr(cpu_env, data, addr);
> +    } else {
> +        tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */
> +    }
> +}
> +
> +static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
> +{
> +    if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
> +        gen_helper_fullrd(data, cpu_env, addr);
> +    } else {
> +        tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr]
> */
> +    }
> +}
> +
> +static bool trans_LAC(DisasContext *ctx, arg_LAC *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
> +        return true;
> +    }
> +
> +    TCGv Rr = cpu_r[a->rd];
> +    TCGv addr = gen_get_zaddr();
> +    TCGv t0 = tcg_temp_new_i32();
> +    TCGv t1 = tcg_temp_new_i32();
> +
> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
> +        /* t1 = t0 & (0xff - Rr) = t0 and ~Rr */
> +    tcg_gen_andc_tl(t1, t0, Rr);
> +
> +    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */
> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
> +
> +    tcg_temp_free_i32(t1);
> +    tcg_temp_free_i32(t0);
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + *  Load one byte indirect from data space to register and set bits in
> data
> + *  space specified by the register. The instruction can only be used
> towards
> + *  internal SRAM.  The data location is pointed to by the Z (16 bits)
> Pointer
> + *  Register in the Register File. Memory access is limited to the
> current data
> + *  segment of 64KB. To access another data segment in devices with more
> than
> + *  64KB data space, the RAMPZ in register in the I/O area has to be
> changed.
> + *  The Z-pointer Register is left unchanged by the operation. This
> instruction
> + *  is especially suited for setting status bits stored in SRAM.
> + */
> +static bool trans_LAS(DisasContext *ctx, arg_LAS *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
> +        return true;
> +    }
> +
> +    TCGv Rr = cpu_r[a->rd];
> +    TCGv addr = gen_get_zaddr();
> +    TCGv t0 = tcg_temp_new_i32();
> +    TCGv t1 = tcg_temp_new_i32();
> +
> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
> +    tcg_gen_or_tl(t1, t0, Rr);
> +
> +    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */
> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
> +
> +    tcg_temp_free_i32(t1);
> +    tcg_temp_free_i32(t0);
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + *  Load one byte indirect from data space to register and toggles bits in
> + *  the data space specified by the register.  The instruction can only
> be used
> + *  towards SRAM.  The data location is pointed to by the Z (16 bits)
> Pointer
> + *  Register in the Register File. Memory access is limited to the
> current data
> + *  segment of 64KB. To access another data segment in devices with more
> than
> + *  64KB data space, the RAMPZ in register in the I/O area has to be
> changed.
> + *  The Z-pointer Register is left unchanged by the operation. This
> instruction
> + *  is especially suited for changing status bits stored in SRAM.
> + */
> +static bool trans_LAT(DisasContext *ctx, arg_LAT *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
> +        return true;
> +    }
> +
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_zaddr();
> +    TCGv t0 = tcg_temp_new_i32();
> +    TCGv t1 = tcg_temp_new_i32();
> +
> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
> +    tcg_gen_xor_tl(t1, t0, Rd);
> +
> +    tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */
> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
> +
> +    tcg_temp_free_i32(t1);
> +    tcg_temp_free_i32(t0);
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + *  Loads one byte indirect from the data space to a register. For parts
> + *  with SRAM, the data space consists of the Register File, I/O memory
> and
> + *  internal SRAM (and external SRAM if applicable). For parts without
> SRAM, the
> + *  data space consists of the Register File only. In some parts the Flash
> + *  Memory has been mapped to the data space and can be read using this
> command.
> + *  The EEPROM has a separate address space.  The data location is
> pointed to by
> + *  the X (16 bits) Pointer Register in the Register File. Memory access
> is
> + *  limited to the current data segment of 64KB. To access another data
> segment
> + *  in devices with more than 64KB data space, the RAMPX in register in
> the I/O
> + *  area has to be changed.  The X-pointer Register can either be left
> unchanged
> + *  by the operation, or it can be post-incremented or predecremented.
> These
> + *  features are especially suited for accessing arrays, tables, and Stack
> + *  Pointer usage of the X-pointer Register. Note that only the low byte
> of the
> + *  X-pointer is updated in devices with no more than 256 bytes data
> space. For
> + *  such devices, the high byte of the pointer is not used by this
> instruction
> + *  and can be used for other purposes. The RAMPX Register in the I/O
> area is
> + *  updated in parts with more than 64KB data space or more than 64KB
> Program
> + *  memory, and the increment/decrement is added to the entire 24-bit
> address on
> + *  such devices.  Not all variants of this instruction is available in
> all
> + *  devices. Refer to the device specific instruction set summary.  In the
> + *  Reduced Core tinyAVR the LD instruction can be used to achieve the
> same
> + *  operation as LPM since the program memory is mapped to the data memory
> + *  space.
> + */
> +static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_xaddr();
> +
> +    gen_data_load(ctx, Rd, addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_xaddr();
> +
> +    gen_data_load(ctx, Rd, addr);
> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> +
> +    gen_set_xaddr(addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_xaddr();
> +
> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
> +    gen_data_load(ctx, Rd, addr);
> +    gen_set_xaddr(addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + *  Loads one byte indirect with or without displacement from the data
> space
> + *  to a register. For parts with SRAM, the data space consists of the
> Register
> + *  File, I/O memory and internal SRAM (and external SRAM if applicable).
> For
> + *  parts without SRAM, the data space consists of the Register File
> only. In
> + *  some parts the Flash Memory has been mapped to the data space and can
> be
> + *  read using this command. The EEPROM has a separate address space.
> The data
> + *  location is pointed to by the Y (16 bits) Pointer Register in the
> Register
> + *  File. Memory access is limited to the current data segment of 64KB. To
> + *  access another data segment in devices with more than 64KB data
> space, the
> + *  RAMPY in register in the I/O area has to be changed.  The Y-pointer
> Register
> + *  can either be left unchanged by the operation, or it can be
> post-incremented
> + *  or predecremented.  These features are especially suited for accessing
> + *  arrays, tables, and Stack Pointer usage of the Y-pointer Register.
> Note that
> + *  only the low byte of the Y-pointer is updated in devices with no more
> than
> + *  256 bytes data space. For such devices, the high byte of the pointer
> is not
> + *  used by this instruction and can be used for other purposes. The RAMPY
> + *  Register in the I/O area is updated in parts with more than 64KB data
> space
> + *  or more than 64KB Program memory, and the increment/decrement/
> displacement
> + *  is added to the entire 24-bit address on such devices.  Not all
> variants of
> + *  this instruction is available in all devices. Refer to the device
> specific
> + *  instruction set summary.  In the Reduced Core tinyAVR the LD
> instruction can
> + *  be used to achieve the same operation as LPM since the program memory
> is
> + *  mapped to the data memory space.
> + */
> +static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_yaddr();
> +
> +    gen_data_load(ctx, Rd, addr);
> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> +
> +    gen_set_yaddr(addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_yaddr();
> +
> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
> +    gen_data_load(ctx, Rd, addr);
> +    gen_set_yaddr(addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_yaddr();
> +
> +    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
> +    gen_data_load(ctx, Rd, addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + *  Loads one byte indirect with or without displacement from the data
> space
> + *  to a register. For parts with SRAM, the data space consists of the
> Register
> + *  File, I/O memory and internal SRAM (and external SRAM if applicable).
> For
> + *  parts without SRAM, the data space consists of the Register File
> only. In
> + *  some parts the Flash Memory has been mapped to the data space and can
> be
> + *  read using this command. The EEPROM has a separate address space.
> The data
> + *  location is pointed to by the Z (16 bits) Pointer Register in the
> Register
> + *  File. Memory access is limited to the current data segment of 64KB. To
> + *  access another data segment in devices with more than 64KB data
> space, the
> + *  RAMPZ in register in the I/O area has to be changed.  The Z-pointer
> Register
> + *  can either be left unchanged by the operation, or it can be
> post-incremented
> + *  or predecremented.  These features are especially suited for Stack
> Pointer
> + *  usage of the Z-pointer Register, however because the Z-pointer
> Register can
> + *  be used for indirect subroutine calls, indirect jumps and table
> lookup, it
> + *  is often more convenient to use the X or Y-pointer as a dedicated
> Stack
> + *  Pointer. Note that only the low byte of the Z-pointer is updated in
> devices
> + *  with no more than 256 bytes data space. For such devices, the high
> byte of
> + *  the pointer is not used by this instruction and can be used for other
> + *  purposes. The RAMPZ Register in the I/O area is updated in parts with
> more
> + *  than 64KB data space or more than 64KB Program memory, and the
> + *  increment/decrement/displacement is added to the entire 24-bit
> address on
> + *  such devices.  Not all variants of this instruction is available in
> all
> + *  devices. Refer to the device specific instruction set summary.  In the
> + *  Reduced Core tinyAVR the LD instruction can be used to achieve the
> same
> + *  operation as LPM since the program memory is mapped to the data memory
> + *  space.  For using the Z-pointer for table lookup in Program memory
> see the
> + *  LPM and ELPM instructions.
> + */
> +static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_zaddr();
> +
> +    gen_data_load(ctx, Rd, addr);
> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> +
> +    gen_set_zaddr(addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_zaddr();
> +
> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
> +    gen_data_load(ctx, Rd, addr);
> +
> +    gen_set_zaddr(addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = gen_get_zaddr();
> +
> +    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
> +    gen_data_load(ctx, Rd, addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + * Loads an 8 bit constant directly to register 16 to 31.
> + */
> +static bool trans_LDI(DisasContext *ctx, arg_LDI *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    int imm = a->imm;
> +
> +    tcg_gen_movi_tl(Rd, imm);
> +
> +    return true;
> +}
> +
> +/*
> + *  Loads one byte from the data space to a register. For parts with SRAM,
> + *  the data space consists of the Register File, I/O memory and internal
> SRAM
> + *  (and external SRAM if applicable). For parts without SRAM, the data
> space
> + *  consists of the register file only. The EEPROM has a separate address
> space.
> + *  A 16-bit address must be supplied. Memory access is limited to the
> current
> + *  data segment of 64KB. The LDS instruction uses the RAMPD Register to
> access
> + *  memory above 64KB. To access another data segment in devices with
> more than
> + *  64KB data space, the RAMPD in register in the I/O area has to be
> changed.
> + *  This instruction is not available in all devices. Refer to the device
> + *  specific instruction set summary.
> + */
> +static bool trans_LDS(DisasContext *ctx, arg_LDS *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = tcg_temp_new_i32();
> +    TCGv H = cpu_rampD;
> +    a->imm = next_word(ctx);
> +
> +    tcg_gen_mov_tl(addr, H); /* addr = H:M:L */
> +    tcg_gen_shli_tl(addr, addr, 16);
> +    tcg_gen_ori_tl(addr, addr, a->imm);
> +
> +    gen_data_load(ctx, Rd, addr);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + *  Loads one byte pointed to by the Z-register into the destination
> + *  register Rd. This instruction features a 100% space effective constant
> + *  initialization or constant data fetch. The Program memory is
> organized in
> + *  16-bit words while the Z-pointer is a byte address. Thus, the least
> + *  significant bit of the Z-pointer selects either low byte (ZLSB = 0)
> or high
> + *  byte (ZLSB = 1). This instruction can address the first 64KB (32K
> words) of
> + *  Program memory. The Zpointer Register can either be left unchanged by
> the
> + *  operation, or it can be incremented. The incrementation does not
> apply to
> + *  the RAMPZ Register.  Devices with Self-Programming capability can use
> the
> + *  LPM instruction to read the Fuse and Lock bit values.  Refer to the
> device
> + *  documentation for a detailed description.  The LPM instruction is not
> + *  available in all devices. Refer to the device specific instruction set
> + *  summary
> + */
> +static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
> +        return true;
> +    }
> +
> +    TCGv Rd = cpu_r[0];
> +    TCGv addr = tcg_temp_new_i32();
> +    TCGv H = cpu_r[31];
> +    TCGv L = cpu_r[30];
> +
> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
> +    tcg_gen_or_tl(addr, addr, L);
> +
> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
> +        return true;
> +    }
> +
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = tcg_temp_new_i32();
> +    TCGv H = cpu_r[31];
> +    TCGv L = cpu_r[30];
> +
> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
> +    tcg_gen_or_tl(addr, addr, L);
> +
> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) {
> +        return true;
> +    }
> +
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv addr = tcg_temp_new_i32();
> +    TCGv H = cpu_r[31];
> +    TCGv L = cpu_r[30];
> +
> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
> +    tcg_gen_or_tl(addr, addr, L);
> +
> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> +
> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> +
> +    tcg_gen_andi_tl(L, addr, 0xff);
> +
> +    tcg_gen_shri_tl(addr, addr, 8);
> +    tcg_gen_andi_tl(H, addr, 0xff);
> +
> +    tcg_temp_free_i32(addr);
> +
> +    return true;
> +}
> +
> +/*
> + *  Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0
> is
> + *  loaded into the C Flag of the SREG. This operation effectively
> divides an
> + *  unsigned value by two. The C Flag can be used to round the result.
> + */
> +static bool trans_LSR(DisasContext *ctx, arg_LSR *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +
> +    tcg_gen_andi_tl(cpu_Cf, Rd, 1);
> +
> +    tcg_gen_shri_tl(Rd, Rd, 1);
> +
> +    tcg_gen_mov_tl(cpu_Zf, Rd);
> +    tcg_gen_movi_tl(cpu_Nf, 0);
> +    tcg_gen_mov_tl(cpu_Vf, cpu_Cf);
> +    tcg_gen_mov_tl(cpu_Sf, cpu_Vf);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction makes a copy of one register into another. The source
> + *  register Rr is left unchanged, while the destination register Rd is
> loaded
> + *  with a copy of Rr.
> + */
> +static bool trans_MOV(DisasContext *ctx, arg_MOV *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +
> +    tcg_gen_mov_tl(Rd, Rr);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction makes a copy of one register pair into another
> register
> + *  pair. The source register pair Rr+1:Rr is left unchanged, while the
> + *  destination register pair Rd+1:Rd is loaded with a copy of Rr +
> 1:Rr.  This
> + *  instruction is not available in all devices. Refer to the device
> specific
> + *  instruction set summary.
> + */
> +static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) {
> +        return true;
> +    }
> +
> +    TCGv RdL = cpu_r[a->rd];
> +    TCGv RdH = cpu_r[a->rd + 1];
> +    TCGv RrL = cpu_r[a->rr];
> +    TCGv RrH = cpu_r[a->rr + 1];
> +
> +    tcg_gen_mov_tl(RdH, RrH);
> +    tcg_gen_mov_tl(RdL, RrL);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs 8-bit x 8-bit -> 16-bit unsigned
> multiplication.
> + */
> +static bool trans_MUL(DisasContext *ctx, arg_MUL *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> +        return true;
> +    }
> +
> +    TCGv R0 = cpu_r[0];
> +    TCGv R1 = cpu_r[1];
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +
> +    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */
> +
> +    tcg_gen_andi_tl(R0, R, 0xff);
> +    tcg_gen_shri_tl(R1, R, 8);
> +
> +    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */
> +    tcg_gen_mov_tl(cpu_Zf, R);
> +
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed
> multiplication.
> + */
> +static bool trans_MULS(DisasContext *ctx, arg_MULS *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> +        return true;
> +    }
> +
> +    TCGv R0 = cpu_r[0];
> +    TCGv R1 = cpu_r[1];
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +    TCGv t0 = tcg_temp_new_i32();
> +    TCGv t1 = tcg_temp_new_i32();
> +
> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
> +    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */
> +    tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */
> +
> +    tcg_gen_andi_tl(R0, R, 0xff);
> +    tcg_gen_shri_tl(R1, R, 8);
> +
> +    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */
> +    tcg_gen_mov_tl(cpu_Zf, R);
> +
> +    tcg_temp_free_i32(t1);
> +    tcg_temp_free_i32(t0);
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a
> + *  signed and an unsigned number.
> + */
> +static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a)
> +{
> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> +        return true;
> +    }
> +
> +    TCGv R0 = cpu_r[0];
> +    TCGv R1 = cpu_r[1];
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv Rr = cpu_r[a->rr];
> +    TCGv R = tcg_temp_new_i32();
> +    TCGv t0 = tcg_temp_new_i32();
> +
> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
> +    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */
> +
> +    tcg_gen_andi_tl(R0, R, 0xff);
> +    tcg_gen_shri_tl(R1, R, 8);
> +
> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
> +    tcg_gen_mov_tl(cpu_Zf, R);
> +
> +    tcg_temp_free_i32(t0);
> +    tcg_temp_free_i32(R);
> +
> +    return true;
> +}
> +
> +/*
> + *  Replaces the contents of register Rd with its two's complement; the
> + *  value $80 is left unchanged.
> + */
> +static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
> +{
> +    TCGv Rd = cpu_r[a->rd];
> +    TCGv t0 = tcg_const_i32(0);
> +    TCGv R = tcg_temp_new_i32();
> +
> +    /* op */
> +    tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> +
> +    gen_sub_CHf(R, t0, Rd);
> +    gen_sub_Vf(R, t0, Rd);
> +    gen_ZNSf(R);
> +
> +    /* R */
> +    tcg_gen_mov_tl(Rd,--
> 2.17.2 (Apple Git-113)
>
>
>

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<br><br>On Monday, September 2, 2019, Michael Rolnik &lt;<a href="mailto:mrolnik@gmail.com">mrolnik@gmail.com</a>&gt; wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">This includes:<br>
- TCG translations for each instruction<br>
<br>
Signed-off-by: Michael Rolnik &lt;<a href="mailto:mrolnik@gmail.com" target="_blank">mrolnik@gmail.com</a>&gt;<br>
---<br>
 target/avr/translate.c | 2888 ++++++++++++++++++++++++++++++<wbr>++++++++++<br>
 1 file changed, 2888 insertions(+)<br>
 create mode 100644 target/avr/translate.c<br><br></blockquote><div><br></div><div>Hi, Michael,</div><div><br></div><div><br></div><div>This patch is way too large. I suggest splitting it into:</div><div><br></div><div>- register definitions</div><div>- load instruction handling</div><div>- store instruction handling</div><div>- logic instruction handling</div><div><br></div><div>etc.</div><div><br></div><div>Thanks, Aleksandar</div><div><br></div><div>P.S. One more hurdle with your communication on the list is that you don&#39;t use &quot;inline responding&quot; while replaying, please use it in future. See other messages in the mailing list how &quot;inline responding&quot; looks.</div><div><br></div><div><br></div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
diff --git a/target/avr/translate.c b/target/avr/translate.c<br>
new file mode 100644<br>
index 0000000000..42cb4a690c<br>
--- /dev/null<br>
+++ b/target/avr/translate.c<br>
@@ -0,0 +1,2888 @@<br>
+/*<br>
+ * QEMU AVR CPU<br>
+ *<br>
+ * Copyright (c) 2019 Michael Rolnik<br>
+ *<br>
+ * This library is free software; you can redistribute it and/or<br>
+ * modify it under the terms of the GNU Lesser General Public<br>
+ * License as published by the Free Software Foundation; either<br>
+ * version 2.1 of the License, or (at your option) any later version.<br>
+ *<br>
+ * This library is distributed in the hope that it will be useful,<br>
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU<br>
+ * Lesser General Public License for more details.<br>
+ *<br>
+ * You should have received a copy of the GNU Lesser General Public<br>
+ * License along with this library; if not, see<br>
+ * &lt;<a href="http://www.gnu.org/licenses/lgpl-2.1.html" target="_blank">http://www.gnu.org/licenses/<wbr>lgpl-2.1.html</a>&gt;<br>
+ */<br>
+<br>
+#include &quot;qemu/osdep.h&quot;<br>
+#include &quot;qemu/qemu-print.h&quot;<br>
+#include &quot;tcg/tcg.h&quot;<br>
+#include &quot;cpu.h&quot;<br>
+#include &quot;exec/exec-all.h&quot;<br>
+#include &quot;disas/disas.h&quot;<br>
+#include &quot;tcg-op.h&quot;<br>
+#include &quot;exec/cpu_ldst.h&quot;<br>
+#include &quot;exec/helper-proto.h&quot;<br>
+#include &quot;exec/helper-gen.h&quot;<br>
+#include &quot;exec/log.h&quot;<br>
+#include &quot;exec/gdbstub.h&quot;<br>
+#include &quot;exec/translator.h&quot;<br>
+<br>
+/*<br>
+ *  Define if you want a BREAK instruction translated to a breakpoint<br>
+ *  Active debugging connection is assumed<br>
+ *  This is for<br>
+ *  <a href="https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests" target="_blank">https://github.com/seharris/<wbr>qemu-avr-tests/tree/master/<wbr>instruction-tests</a><br>
+ *  tests<br>
+ */<br>
+#undef BREAKPOINT_ON_BREAK<br>
+<br>
+static TCGv cpu_pc;<br>
+<br>
+static TCGv cpu_Cf;<br>
+static TCGv cpu_Zf;<br>
+static TCGv cpu_Nf;<br>
+static TCGv cpu_Vf;<br>
+static TCGv cpu_Sf;<br>
+static TCGv cpu_Hf;<br>
+static TCGv cpu_Tf;<br>
+static TCGv cpu_If;<br>
+<br>
+static TCGv cpu_rampD;<br>
+static TCGv cpu_rampX;<br>
+static TCGv cpu_rampY;<br>
+static TCGv cpu_rampZ;<br>
+<br>
+static TCGv cpu_r[NO_CPU_REGISTERS];<br>
+static TCGv cpu_eind;<br>
+static TCGv cpu_sp;<br>
+<br>
+static TCGv cpu_skip;<br>
+<br>
+static const char reg_names[NO_CPU_REGISTERS][8] = {<br>
+    &quot;r0&quot;,  &quot;r1&quot;,  &quot;r2&quot;,  &quot;r3&quot;,  &quot;r4&quot;,  &quot;r5&quot;,  &quot;r6&quot;,  &quot;r7&quot;,<br>
+    &quot;r8&quot;,  &quot;r9&quot;,  &quot;r10&quot;, &quot;r11&quot;, &quot;r12&quot;, &quot;r13&quot;, &quot;r14&quot;, &quot;r15&quot;,<br>
+    &quot;r16&quot;, &quot;r17&quot;, &quot;r18&quot;, &quot;r19&quot;, &quot;r20&quot;, &quot;r21&quot;, &quot;r22&quot;, &quot;r23&quot;,<br>
+    &quot;r24&quot;, &quot;r25&quot;, &quot;r26&quot;, &quot;r27&quot;, &quot;r28&quot;, &quot;r29&quot;, &quot;r30&quot;, &quot;r31&quot;,<br>
+};<br>
+#define REG(x) (cpu_r[x])<br>
+<br>
+enum {<br>
+    DISAS_EXIT   = DISAS_TARGET_0,  /* We want return to the cpu main loop.  */<br>
+    DISAS_LOOKUP = DISAS_TARGET_1,  /* We have a variable condition exit.  */<br>
+    DISAS_CHAIN  = DISAS_TARGET_2,  /* We have a single condition exit.  */<br>
+};<br>
+<br>
+typedef struct DisasContext DisasContext;<br>
+<br>
+/* This is the state at translation time. */<br>
+struct DisasContext {<br>
+    TranslationBlock *tb;<br>
+<br>
+    CPUAVRState *env;<br>
+    CPUState *cs;<br>
+<br>
+    target_long npc;<br>
+    uint32_t opcode;<br>
+<br>
+    /* Routine used to access memory */<br>
+    int memidx;<br>
+    int bstate;<br>
+    int singlestep;<br>
+<br>
+    TCGv skip_var0;<br>
+    TCGv skip_var1;<br>
+    TCGCond skip_cond;<br>
+    bool free_skip_var0;<br>
+};<br>
+<br>
+static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); }<br>
+static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); }<br>
+static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) * 2; }<br>
+static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; }<br>
+<br>
+static uint16_t next_word(DisasContext *ctx)<br>
+{<br>
+    return cpu_lduw_code(ctx-&gt;env, ctx-&gt;npc++ * 2);<br>
+}<br>
+<br>
+static int append_16(DisasContext *ctx, int x)<br>
+{<br>
+    return x &lt;&lt; 16 | next_word(ctx);<br>
+}<br>
+<br>
+static bool decode_insn(DisasContext *ctx, uint16_t insn);<br>
+#include &quot;decode_insn.inc.c&quot;<br>
+<br>
+static bool avr_have_feature(DisasContext *ctx, int feature)<br>
+{<br>
+    if (!avr_feature(ctx-&gt;env, feature)) {<br>
+        gen_helper_unsupported(cpu_<wbr>env);<br>
+        ctx-&gt;bstate = DISAS_NORETURN;<br>
+        return false;<br>
+    }<br>
+    return true;<br>
+}<br>
+<br>
+static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)<br>
+{<br>
+    TranslationBlock *tb = ctx-&gt;tb;<br>
+<br>
+    if (ctx-&gt;singlestep == 0) {<br>
+        tcg_gen_goto_tb(n);<br>
+        tcg_gen_movi_i32(cpu_pc, dest);<br>
+        tcg_gen_exit_tb(tb, n);<br>
+    } else {<br>
+        tcg_gen_movi_i32(cpu_pc, dest);<br>
+        gen_helper_debug(cpu_env);<br>
+        tcg_gen_exit_tb(NULL, 0);<br>
+    }<br>
+    ctx-&gt;bstate = DISAS_NORETURN;<br>
+}<br>
+<br>
+#include &quot;exec/gen-icount.h&quot;<br>
+<br>
+static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)<br>
+{<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+    TCGv t2 = tcg_temp_new_i32();<br>
+    TCGv t3 = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd &amp; Rr */<br>
+    tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd &amp; ~R */<br>
+    tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr &amp; ~R */<br>
+    tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */<br>
+    tcg_gen_or_tl(t1, t1, t3);<br>
+<br>
+    tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */<br>
+    tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */<br>
+    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);<br>
+<br>
+    tcg_temp_free_i32(t3);<br>
+    tcg_temp_free_i32(t2);<br>
+    tcg_temp_free_i32(t1);<br>
+}<br>
+<br>
+static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr)<br>
+{<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+    TCGv t2 = tcg_temp_new_i32();<br>
+<br>
+    /* t1 = Rd &amp; Rr &amp; ~R | ~Rd &amp; ~Rr &amp; R = (Rd ^ R) &amp; ~(Rd ^ Rr) */<br>
+    tcg_gen_xor_tl(t1, Rd, R);<br>
+    tcg_gen_xor_tl(t2, Rd, Rr);<br>
+    tcg_gen_andc_tl(t1, t1, t2);<br>
+<br>
+    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */<br>
+<br>
+    tcg_temp_free_i32(t2);<br>
+    tcg_temp_free_i32(t1);<br>
+}<br>
+<br>
+static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)<br>
+{<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+    TCGv t2 = tcg_temp_new_i32();<br>
+    TCGv t3 = tcg_temp_new_i32();<br>
+<br>
+    /* Cf &amp; Hf */<br>
+    tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */<br>
+    tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd &amp; Rr */<br>
+    tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) &amp; R */<br>
+    tcg_gen_and_tl(t3, t3, R);<br>
+    tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd &amp; Rr | ~Rd &amp; R | R &amp; Rr */<br>
+    tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */<br>
+    tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */<br>
+    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);<br>
+<br>
+    tcg_temp_free_i32(t3);<br>
+    tcg_temp_free_i32(t2);<br>
+    tcg_temp_free_i32(t1);<br>
+}<br>
+<br>
+static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr)<br>
+{<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+    TCGv t2 = tcg_temp_new_i32();<br>
+<br>
+    /* Vf */<br>
+    /* t1 = Rd &amp; ~Rr &amp; ~R | ~Rd &amp; Rr &amp; R = (Rd ^ R) &amp; (Rd ^ R) */<br>
+    tcg_gen_xor_tl(t1, Rd, R);<br>
+    tcg_gen_xor_tl(t2, Rd, Rr);<br>
+    tcg_gen_and_tl(t1, t1, t2);<br>
+    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */<br>
+<br>
+    tcg_temp_free_i32(t2);<br>
+    tcg_temp_free_i32(t1);<br>
+}<br>
+<br>
+static void gen_rshift_ZNVSf(TCGv R)<br>
+{<br>
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */<br>
+    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */<br>
+    tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf);<br>
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */<br>
+}<br>
+<br>
+static void gen_NSf(TCGv R)<br>
+{<br>
+    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */<br>
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */<br>
+}<br>
+<br>
+static void gen_ZNSf(TCGv R)<br>
+{<br>
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */<br>
+    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */<br>
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */<br>
+}<br>
+<br>
+static void gen_push_ret(DisasContext *ctx, int ret)<br>
+{<br>
+    if (avr_feature(ctx-&gt;env, AVR_FEATURE_1_BYTE_PC)) {<br>
+<br>
+        TCGv t0 = tcg_const_i32((ret &amp; 0x0000ff));<br>
+<br>
+        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);<br>
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);<br>
+<br>
+        tcg_temp_free_i32(t0);<br>
+    } else if (avr_feature(ctx-&gt;env, AVR_FEATURE_2_BYTE_PC)) {<br>
+<br>
+        TCGv t0 = tcg_const_i32((ret &amp; 0x00ffff));<br>
+<br>
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);<br>
+        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);<br>
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);<br>
+<br>
+        tcg_temp_free_i32(t0);<br>
+<br>
+    } else if (avr_feature(ctx-&gt;env, AVR_FEATURE_3_BYTE_PC)) {<br>
+<br>
+        TCGv lo = tcg_const_i32((ret &amp; 0x0000ff));<br>
+        TCGv hi = tcg_const_i32((ret &amp; 0xffff00) &gt;&gt; 8);<br>
+<br>
+        tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);<br>
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);<br>
+        tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);<br>
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);<br>
+<br>
+        tcg_temp_free_i32(lo);<br>
+        tcg_temp_free_i32(hi);<br>
+    }<br>
+}<br>
+<br>
+static void gen_pop_ret(DisasContext *ctx, TCGv ret)<br>
+{<br>
+    if (avr_feature(ctx-&gt;env, AVR_FEATURE_1_BYTE_PC)) {<br>
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);<br>
+        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);<br>
+    } else if (avr_feature(ctx-&gt;env, AVR_FEATURE_2_BYTE_PC)) {<br>
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);<br>
+        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);<br>
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);<br>
+    } else if (avr_feature(ctx-&gt;env, AVR_FEATURE_3_BYTE_PC)) {<br>
+        TCGv lo = tcg_temp_new_i32();<br>
+        TCGv hi = tcg_temp_new_i32();<br>
+<br>
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);<br>
+        tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);<br>
+<br>
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);<br>
+        tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);<br>
+<br>
+        tcg_gen_deposit_tl(ret, lo, hi, 8, 16);<br>
+<br>
+        tcg_temp_free_i32(lo);<br>
+        tcg_temp_free_i32(hi);<br>
+    }<br>
+}<br>
+<br>
+static void gen_jmp_ez(DisasContext *ctx)<br>
+{<br>
+    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);<br>
+    tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind);<br>
+    ctx-&gt;bstate = DISAS_LOOKUP;<br>
+}<br>
+<br>
+static void gen_jmp_z(DisasContext *ctx)<br>
+{<br>
+    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);<br>
+    ctx-&gt;bstate = DISAS_LOOKUP;<br>
+}<br>
+<br>
+/*<br>
+ *  in the gen_set_addr &amp; gen_get_addr functions<br>
+ *  H assumed to be in 0x00ff0000 format<br>
+ *  M assumed to be in 0x000000ff format<br>
+ *  L assumed to be in 0x000000ff format<br>
+ */<br>
+static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L)<br>
+{<br>
+<br>
+    tcg_gen_andi_tl(L, addr, 0x000000ff);<br>
+<br>
+    tcg_gen_andi_tl(M, addr, 0x0000ff00);<br>
+    tcg_gen_shri_tl(M, M, 8);<br>
+<br>
+    tcg_gen_andi_tl(H, addr, 0x00ff0000);<br>
+}<br>
+<br>
+static void gen_set_xaddr(TCGv addr)<br>
+{<br>
+    gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]);<br>
+}<br>
+<br>
+static void gen_set_yaddr(TCGv addr)<br>
+{<br>
+    gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]);<br>
+}<br>
+<br>
+static void gen_set_zaddr(TCGv addr)<br>
+{<br>
+    gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]);<br>
+}<br>
+<br>
+static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L)<br>
+{<br>
+    TCGv addr = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_deposit_tl(addr, M, H, 8, 8);<br>
+    tcg_gen_deposit_tl(addr, L, addr, 8, 16);<br>
+<br>
+    return addr;<br>
+}<br>
+<br>
+static TCGv gen_get_xaddr(void)<br>
+{<br>
+    return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]);<br>
+}<br>
+<br>
+static TCGv gen_get_yaddr(void)<br>
+{<br>
+    return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]);<br>
+}<br>
+<br>
+static TCGv gen_get_zaddr(void)<br>
+{<br>
+    return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]);<br>
+}<br>
+<br>
+/*<br>
+ *  Adds two registers and the contents of the C Flag and places the result in<br>
+ *  the destination register Rd.<br>
+ */<br>
+static bool trans_ADC(DisasContext *ctx, arg_ADC *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    /* op */<br>
+    tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */<br>
+    tcg_gen_add_tl(R, R, cpu_Cf);<br>
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */<br>
+<br>
+    gen_add_CHf(R, Rd, Rr);<br>
+    gen_add_Vf(R, Rd, Rr);<br>
+    gen_ZNSf(R);<br>
+<br>
+    /* R */<br>
+    tcg_gen_mov_tl(Rd, R);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Adds two registers without the C Flag and places the result in the<br>
+ *  destination register Rd.<br>
+ */<br>
+static bool trans_ADD(DisasContext *ctx, arg_ADD *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    /* op */<br>
+    tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */<br>
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */<br>
+<br>
+    gen_add_CHf(R, Rd, Rr);<br>
+    gen_add_Vf(R, Rd, Rr);<br>
+    gen_ZNSf(R);<br>
+<br>
+    /* R */<br>
+    tcg_gen_mov_tl(Rd, R);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Adds an immediate value (0 - 63) to a register pair and places the result<br>
+ *  in the register pair. This instruction operates on the upper four register<br>
+ *  pairs, and is well suited for operations on the pointer registers.  This<br>
+ *  instruction is not available in all devices. Refer to the device specific<br>
+ *  instruction set summary.<br>
+ */<br>
+static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv RdL = cpu_r[a-&gt;rd];<br>
+    TCGv RdH = cpu_r[a-&gt;rd + 1];<br>
+    int Imm = (a-&gt;imm);<br>
+    TCGv R = tcg_temp_new_i32();<br>
+    TCGv Rd = tcg_temp_new_i32();<br>
+<br>
+    /* op */<br>
+    tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */<br>
+    tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */<br>
+    tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */<br>
+<br>
+    /* Cf */<br>
+    tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd &amp; ~R */<br>
+    tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15);<br>
+<br>
+    /* Vf */<br>
+    tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R &amp; ~Rd */<br>
+    tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15);<br>
+<br>
+    /* Zf */<br>
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */<br>
+<br>
+    /* Nf */<br>
+    tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */<br>
+<br>
+    /* Sf */<br>
+    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */<br>
+<br>
+    /* R */<br>
+    tcg_gen_andi_tl(RdL, R, 0xff);<br>
+    tcg_gen_shri_tl(RdH, R, 8);<br>
+<br>
+    tcg_temp_free_i32(Rd);<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Performs the logical AND between the contents of register Rd and register<br>
+ *  Rr and places the result in the destination register Rd.<br>
+ */<br>
+static bool trans_AND(DisasContext *ctx, arg_AND *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    /* op */<br>
+    tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */<br>
+<br>
+    /* Vf */<br>
+    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */<br>
+<br>
+    /* Zf */<br>
+    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */<br>
+<br>
+    gen_ZNSf(R);<br>
+<br>
+    /* R */<br>
+    tcg_gen_mov_tl(Rd, R);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Performs the logical AND between the contents of register Rd and a constant<br>
+ *  and places the result in the destination register Rd.<br>
+ */<br>
+static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    int Imm = (a-&gt;imm);<br>
+<br>
+    /* op */<br>
+    tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd &amp; Imm */<br>
+<br>
+    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */<br>
+    gen_ZNSf(Rd);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0<br>
+ *  is loaded into the C Flag of the SREG. This operation effectively divides a<br>
+ *  signed value by two without changing its sign. The Carry Flag can be used to<br>
+ *  round the result.<br>
+ */<br>
+static bool trans_ASR(DisasContext *ctx, arg_ASR *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv t0 = tcg_temp_new_i32();<br>
+<br>
+    /* Cf */<br>
+    tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */<br>
+<br>
+    /* op */<br>
+    tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd &amp; 0x80) | (Rd &gt;&gt; 1) */<br>
+    tcg_gen_shri_tl(Rd, Rd, 1);<br>
+    tcg_gen_or_tl(Rd, Rd, t0);<br>
+<br>
+    gen_rshift_ZNVSf(Rd);<br>
+<br>
+    tcg_temp_free_i32(t0);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Clears a single Flag in SREG.<br>
+ */<br>
+static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)<br>
+{<br>
+    switch (a-&gt;bit) {<br>
+    case 0x00:<br>
+        tcg_gen_movi_tl(cpu_Cf, 0x00);<br>
+        break;<br>
+    case 0x01:<br>
+        tcg_gen_movi_tl(cpu_Zf, 0x01);<br>
+        break;<br>
+    case 0x02:<br>
+        tcg_gen_movi_tl(cpu_Nf, 0x00);<br>
+        break;<br>
+    case 0x03:<br>
+        tcg_gen_movi_tl(cpu_Vf, 0x00);<br>
+        break;<br>
+    case 0x04:<br>
+        tcg_gen_movi_tl(cpu_Sf, 0x00);<br>
+        break;<br>
+    case 0x05:<br>
+        tcg_gen_movi_tl(cpu_Hf, 0x00);<br>
+        break;<br>
+    case 0x06:<br>
+        tcg_gen_movi_tl(cpu_Tf, 0x00);<br>
+        break;<br>
+    case 0x07:<br>
+        tcg_gen_movi_tl(cpu_If, 0x00);<br>
+        break;<br>
+    }<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Copies the T Flag in the SREG (Status Register) to bit b in register Rd.<br>
+ */<br>
+static bool trans_BLD(DisasContext *ctx, arg_BLD *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_andi_tl(Rd, Rd, ~(1u &lt;&lt; a-&gt;bit)); /* clear bit */<br>
+    tcg_gen_shli_tl(t1, cpu_Tf, a-&gt;bit); /* create mask */<br>
+    tcg_gen_or_tl(Rd, Rd, t1);<br>
+<br>
+    tcg_temp_free_i32(t1);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Conditional relative branch. Tests a single bit in SREG and branches<br>
+ *  relatively to PC if the bit is cleared. This instruction branches relatively<br>
+ *  to PC in either direction (PC - 63 &lt; = destination &lt;= PC + 64). The<br>
+ *  parameter k is the offset from PC and is represented in two&#39;s complement<br>
+ *  form.<br>
+ */<br>
+static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a)<br>
+{<br>
+    TCGLabel *not_taken = gen_new_label();<br>
+    TCGCond cond = TCG_COND_EQ;<br>
+    TCGv var;<br>
+<br>
+    switch (a-&gt;bit) {<br>
+    case 0x00:<br>
+        var = cpu_Cf;<br>
+        break;<br>
+    case 0x01:<br>
+        cond = TCG_COND_NE;<br>
+        var = cpu_Zf;<br>
+        break;<br>
+    case 0x02:<br>
+        var = cpu_Nf;<br>
+        break;<br>
+    case 0x03:<br>
+        var = cpu_Vf;<br>
+        break;<br>
+    case 0x04:<br>
+        var = cpu_Sf;<br>
+        break;<br>
+    case 0x05:<br>
+        var = cpu_Hf;<br>
+        break;<br>
+    case 0x06:<br>
+        var = cpu_Tf;<br>
+        break;<br>
+    case 0x07:<br>
+        var = cpu_If;<br>
+        break;<br>
+    default:<br>
+        g_assert_not_reached();<br>
+    }<br>
+<br>
+    tcg_gen_brcondi_i32(tcg_<wbr>invert_cond(cond), var, 0, not_taken);<br>
+    gen_goto_tb(ctx, 0, ctx-&gt;npc + a-&gt;imm);<br>
+    gen_set_label(not_taken);<br>
+<br>
+    ctx-&gt;bstate = DISAS_CHAIN;<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Conditional relative branch. Tests a single bit in SREG and branches<br>
+ *  relatively to PC if the bit is set. This instruction branches relatively to<br>
+ *  PC in either direction (PC - 63 &lt; = destination &lt;= PC + 64). The parameter k<br>
+ *  is the offset from PC and is represented in two&#39;s complement form.<br>
+ */<br>
+static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a)<br>
+{<br>
+    TCGLabel *not_taken = gen_new_label();<br>
+    TCGCond cond = TCG_COND_NE;<br>
+    TCGv var;<br>
+<br>
+    switch (a-&gt;bit) {<br>
+    case 0x00:<br>
+        var = cpu_Cf;<br>
+        break;<br>
+    case 0x01:<br>
+        cond = TCG_COND_EQ;<br>
+        var = cpu_Zf;<br>
+        break;<br>
+    case 0x02:<br>
+        var = cpu_Nf;<br>
+        break;<br>
+    case 0x03:<br>
+        var = cpu_Vf;<br>
+        break;<br>
+    case 0x04:<br>
+        var = cpu_Sf;<br>
+        break;<br>
+    case 0x05:<br>
+        var = cpu_Hf;<br>
+        break;<br>
+    case 0x06:<br>
+        var = cpu_Tf;<br>
+        break;<br>
+    case 0x07:<br>
+        var = cpu_If;<br>
+        break;<br>
+    default:<br>
+        g_assert_not_reached();<br>
+    }<br>
+<br>
+    tcg_gen_brcondi_i32(tcg_<wbr>invert_cond(cond), var, 0, not_taken);<br>
+    gen_goto_tb(ctx, 0, ctx-&gt;npc + a-&gt;imm);<br>
+    gen_set_label(not_taken);<br>
+<br>
+    ctx-&gt;bstate = DISAS_CHAIN;<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Sets a single Flag or bit in SREG.<br>
+ */<br>
+static bool trans_BSET(DisasContext *ctx, arg_BSET *a)<br>
+{<br>
+    switch (a-&gt;bit) {<br>
+    case 0x00:<br>
+        tcg_gen_movi_tl(cpu_Cf, 0x01);<br>
+        break;<br>
+    case 0x01:<br>
+        tcg_gen_movi_tl(cpu_Zf, 0x00);<br>
+        break;<br>
+    case 0x02:<br>
+        tcg_gen_movi_tl(cpu_Nf, 0x01);<br>
+        break;<br>
+    case 0x03:<br>
+        tcg_gen_movi_tl(cpu_Vf, 0x01);<br>
+        break;<br>
+    case 0x04:<br>
+        tcg_gen_movi_tl(cpu_Sf, 0x01);<br>
+        break;<br>
+    case 0x05:<br>
+        tcg_gen_movi_tl(cpu_Hf, 0x01);<br>
+        break;<br>
+    case 0x06:<br>
+        tcg_gen_movi_tl(cpu_Tf, 0x01);<br>
+        break;<br>
+    case 0x07:<br>
+        tcg_gen_movi_tl(cpu_If, 0x01);<br>
+        break;<br>
+    }<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  The BREAK instruction is used by the On-chip Debug system, and is<br>
+ *  normally not used in the application software. When the BREAK instruction is<br>
+ *  executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip<br>
+ *  Debugger access to internal resources.  If any Lock bits are set, or either<br>
+ *  the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK<br>
+ *  instruction as a NOP and will not enter the Stopped mode.  This instruction<br>
+ *  is not available in all devices. Refer to the device specific instruction<br>
+ *  set summary.<br>
+ */<br>
+static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {<br>
+        return true;<br>
+    }<br>
+<br>
+#ifdef BREAKPOINT_ON_BREAK<br>
+    tcg_gen_movi_tl(cpu_pc, ctx-&gt;npc - 1);<br>
+    gen_helper_debug(cpu_env);<br>
+    ctx-&gt;bstate = DISAS_EXIT;<br>
+#else<br>
+    /* NOP */<br>
+#endif<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Stores bit b from Rd to the T Flag in SREG (Status Register).<br>
+ */<br>
+static bool trans_BST(DisasContext *ctx, arg_BST *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+<br>
+    tcg_gen_andi_tl(cpu_Tf, Rd, 1 &lt;&lt; a-&gt;bit);<br>
+    tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a-&gt;bit);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Calls to a subroutine within the entire Program memory. The return<br>
+ *  address (to the instruction after the CALL) will be stored onto the Stack.<br>
+ *  (See also RCALL). The Stack Pointer uses a post-decrement scheme during<br>
+ *  CALL.  This instruction is not available in all devices. Refer to the device<br>
+ *  specific instruction set summary.<br>
+ */<br>
+static bool trans_CALL(DisasContext *ctx, arg_CALL *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    int Imm = a-&gt;imm;<br>
+    int ret = ctx-&gt;npc;<br>
+<br>
+    gen_push_ret(ctx, ret);<br>
+    gen_goto_tb(ctx, 0, Imm);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Clears a specified bit in an I/O Register. This instruction operates on<br>
+ *  the lower 32 I/O Registers -- addresses 0-31.<br>
+ */<br>
+static bool trans_CBI(DisasContext *ctx, arg_CBI *a)<br>
+{<br>
+    TCGv data = tcg_temp_new_i32();<br>
+    TCGv port = tcg_const_i32(a-&gt;reg);<br>
+<br>
+    gen_helper_inb(data, cpu_env, port);<br>
+    tcg_gen_andi_tl(data, data, ~(1 &lt;&lt; a-&gt;bit));<br>
+    gen_helper_outb(cpu_env, port, data);<br>
+<br>
+    tcg_temp_free_i32(data);<br>
+    tcg_temp_free_i32(port);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Clears the specified bits in register Rd. Performs the logical AND<br>
+ *  between the contents of register Rd and the complement of the constant mask<br>
+ *  K. The result will be placed in register Rd.<br>
+ */<br>
+static bool trans_COM(DisasContext *ctx, arg_COM *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_xori_tl(Rd, Rd, 0xff);<br>
+<br>
+    tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */<br>
+    tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */<br>
+    gen_ZNSf(Rd);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs a compare between two registers Rd and Rr.<br>
+ *  None of the registers are changed. All conditional branches can be used<br>
+ *  after this instruction.<br>
+ */<br>
+static bool trans_CP(DisasContext *ctx, arg_CP *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    /* op */<br>
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */<br>
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */<br>
+<br>
+    gen_sub_CHf(R, Rd, Rr);<br>
+    gen_sub_Vf(R, Rd, Rr);<br>
+    gen_ZNSf(R);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs a compare between two registers Rd and Rr and<br>
+ *  also takes into account the previous carry. None of the registers are<br>
+ *  changed. All conditional branches can be used after this instruction.<br>
+ */<br>
+static bool trans_CPC(DisasContext *ctx, arg_CPC *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    /* op */<br>
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */<br>
+    tcg_gen_sub_tl(R, R, cpu_Cf);<br>
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */<br>
+<br>
+    gen_sub_CHf(R, Rd, Rr);<br>
+    gen_sub_Vf(R, Rd, Rr);<br>
+    gen_NSf(R);<br>
+<br>
+    /*<br>
+     * Previous value remains unchanged when the result is zero;<br>
+     * cleared otherwise.<br>
+     */<br>
+    tcg_gen_or_tl(cpu_Zf, cpu_Zf, R);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs a compare between register Rd and a constant.<br>
+ *  The register is not changed. All conditional branches can be used after this<br>
+ *  instruction.<br>
+ */<br>
+static bool trans_CPI(DisasContext *ctx, arg_CPI *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    int Imm = a-&gt;imm;<br>
+    TCGv Rr = tcg_const_i32(Imm);<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    /* op */<br>
+    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */<br>
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */<br>
+<br>
+    gen_sub_CHf(R, Rd, Rr);<br>
+    gen_sub_Vf(R, Rd, Rr);<br>
+    gen_ZNSf(R);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+    tcg_temp_free_i32(Rr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs a compare between two registers Rd and Rr, and<br>
+ *  skips the next instruction if Rd = Rr.<br>
+ */<br>
+static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a)<br>
+{<br>
+    ctx-&gt;skip_cond = TCG_COND_EQ;<br>
+    ctx-&gt;skip_var0 = cpu_r[a-&gt;rd];<br>
+    ctx-&gt;skip_var1 = cpu_r[a-&gt;rr];<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Subtracts one -1- from the contents of register Rd and places the result<br>
+ *  in the destination register Rd.  The C Flag in SREG is not affected by the<br>
+ *  operation, thus allowing the DEC instruction to be used on a loop counter in<br>
+ *  multiple-precision computations.  When operating on unsigned values, only<br>
+ *  BREQ and BRNE branches can be expected to perform consistently.  When<br>
+ *  operating on two&#39;s complement values, all signed branches are available.<br>
+ */<br>
+static bool trans_DEC(DisasContext *ctx, arg_DEC *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+<br>
+    tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */<br>
+    tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */<br>
+<br>
+    /* cpu_Vf = Rd == 0x7f */<br>
+    tcg_gen_setcondi_tl(TCG_COND_<wbr>EQ, cpu_Vf, Rd, 0x7f);<br>
+    gen_ZNSf(Rd);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  The module is an instruction set extension to the AVR CPU, performing<br>
+ *  DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in<br>
+ *  the CPU register file, registers R0-R7, where LSB of data is placed in LSB<br>
+ *  of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including<br>
+ *  parity bits) is placed in registers R8- R15, organized in the register file<br>
+ *  with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES<br>
+ *  instruction performs one round in the DES algorithm. Sixteen rounds must be<br>
+ *  executed in increasing order to form the correct DES ciphertext or<br>
+ *  plaintext. Intermediate results are stored in the register file (R0-R15)<br>
+ *  after each DES instruction. The instruction&#39;s operand (K) determines which<br>
+ *  round is executed, and the half carry flag (H) determines whether encryption<br>
+ *  or decryption is performed.  The DES algorithm is described in<br>
+ *  &quot;Specifications for the Data Encryption Standard&quot; (Federal Information<br>
+ *  Processing Standards Publication 46). Intermediate results in this<br>
+ *  implementation differ from the standard because the initial permutation and<br>
+ *  the inverse initial permutation are performed each iteration. This does not<br>
+ *  affect the result in the final ciphertext or plaintext, but reduces<br>
+ *  execution time.<br>
+ */<br>
+static bool trans_DES(DisasContext *ctx, arg_DES *a)<br>
+{<br>
+    /* TODO */<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_DES)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Indirect call of a subroutine pointed to by the Z (16 bits) Pointer<br>
+ *  Register in the Register File and the EIND Register in the I/O space. This<br>
+ *  instruction allows for indirect calls to the entire 4M (words) Program<br>
+ *  memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme<br>
+ *  during EICALL.  This instruction is not available in all devices. Refer to<br>
+ *  the device specific instruction set summary.<br>
+ */<br>
+static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    int ret = ctx-&gt;npc;<br>
+<br>
+    gen_push_ret(ctx, ret);<br>
+    gen_jmp_ez(ctx);<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Indirect jump to the address pointed to by the Z (16 bits) Pointer<br>
+ *  Register in the Register File and the EIND Register in the I/O space. This<br>
+ *  instruction allows for indirect jumps to the entire 4M (words) Program<br>
+ *  memory space. See also IJMP.  This instruction is not available in all<br>
+ *  devices. Refer to the device specific instruction set summary.<br>
+ */<br>
+static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    gen_jmp_ez(ctx);<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Loads one byte pointed to by the Z-register and the RAMPZ Register in<br>
+ *  the I/O space, and places this byte in the destination register Rd. This<br>
+ *  instruction features a 100% space effective constant initialization or<br>
+ *  constant data fetch. The Program memory is organized in 16-bit words while<br>
+ *  the Z-pointer is a byte address. Thus, the least significant bit of the<br>
+ *  Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This<br>
+ *  instruction can address the entire Program memory space. The Z-pointer<br>
+ *  Register can either be left unchanged by the operation, or it can be<br>
+ *  incremented. The incrementation applies to the entire 24-bit concatenation<br>
+ *  of the RAMPZ and Z-pointer Registers.  Devices with Self-Programming<br>
+ *  capability can use the ELPM instruction to read the Fuse and Lock bit value.<br>
+ *  Refer to the device documentation for a detailed description.  This<br>
+ *  instruction is not available in all devices. Refer to the device specific<br>
+ *  instruction set summary.<br>
+ */<br>
+static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rd = cpu_r[0];<br>
+    TCGv addr = gen_get_zaddr();<br>
+<br>
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_zaddr();<br>
+<br>
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_zaddr();<br>
+<br>
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */<br>
+<br>
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */<br>
+<br>
+    gen_set_zaddr(addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Performs the logical EOR between the contents of register Rd and<br>
+ *  register Rr and places the result in the destination register Rd.<br>
+ */<br>
+static bool trans_EOR(DisasContext *ctx, arg_EOR *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+<br>
+    tcg_gen_xor_tl(Rd, Rd, Rr);<br>
+<br>
+    tcg_gen_movi_tl(cpu_Vf, 0);<br>
+    gen_ZNSf(Rd);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs 8-bit x 8-bit -&gt; 16-bit unsigned<br>
+ *  multiplication and shifts the result one bit left.<br>
+ */<br>
+static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv R0 = cpu_r[0];<br>
+    TCGv R1 = cpu_r[1];<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */<br>
+    tcg_gen_shli_tl(R, R, 1);<br>
+<br>
+    tcg_gen_andi_tl(R0, R, 0xff);<br>
+    tcg_gen_shri_tl(R1, R, 8);<br>
+    tcg_gen_andi_tl(R1, R1, 0xff);<br>
+<br>
+    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */<br>
+    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs 8-bit x 8-bit -&gt; 16-bit signed multiplication<br>
+ *  and shifts the result one bit left.<br>
+ */<br>
+static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv R0 = cpu_r[0];<br>
+    TCGv R1 = cpu_r[1];<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+    TCGv t0 = tcg_temp_new_i32();<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */<br>
+    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */<br>
+    tcg_gen_mul_tl(R, t0, t1); /* R = Rd *Rr */<br>
+    tcg_gen_shli_tl(R, R, 1);<br>
+<br>
+    tcg_gen_andi_tl(R0, R, 0xff);<br>
+    tcg_gen_shri_tl(R1, R, 8);<br>
+    tcg_gen_andi_tl(R1, R1, 0xff);<br>
+<br>
+    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */<br>
+    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);<br>
+<br>
+    tcg_temp_free_i32(t1);<br>
+    tcg_temp_free_i32(t0);<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs 8-bit x 8-bit -&gt; 16-bit signed multiplication<br>
+ *  and shifts the result one bit left.<br>
+ */<br>
+static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv R0 = cpu_r[0];<br>
+    TCGv R1 = cpu_r[1];<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+    TCGv t0 = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */<br>
+    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */<br>
+    tcg_gen_shli_tl(R, R, 1);<br>
+<br>
+    tcg_gen_andi_tl(R0, R, 0xff);<br>
+    tcg_gen_shri_tl(R1, R, 8);<br>
+    tcg_gen_andi_tl(R1, R1, 0xff);<br>
+<br>
+    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */<br>
+    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);<br>
+<br>
+    tcg_temp_free_i32(t0);<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Calls to a subroutine within the entire 4M (words) Program memory. The<br>
+ *  return address (to the instruction after the CALL) will be stored onto the<br>
+ *  Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during<br>
+ *  CALL.  This instruction is not available in all devices. Refer to the device<br>
+ *  specific instruction set summary.<br>
+ */<br>
+static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    int ret = ctx-&gt;npc;<br>
+<br>
+    gen_push_ret(ctx, ret);<br>
+    gen_jmp_z(ctx);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Indirect jump to the address pointed to by the Z (16 bits) Pointer<br>
+ *  Register in the Register File. The Z-pointer Register is 16 bits wide and<br>
+ *  allows jump within the lowest 64K words (128KB) section of Program memory.<br>
+ *  This instruction is not available in all devices. Refer to the device<br>
+ *  specific instruction set summary.<br>
+ */<br>
+static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    gen_jmp_z(ctx);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Loads data from the I/O Space (Ports, Timers, Configuration Registers,<br>
+ *  etc.) into register Rd in the Register File.<br>
+ */<br>
+static bool trans_IN(DisasContext *ctx, arg_IN *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv port = tcg_const_i32(a-&gt;imm);<br>
+<br>
+    gen_helper_inb(Rd, cpu_env, port);<br>
+<br>
+    tcg_temp_free_i32(port);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Adds one -1- to the contents of register Rd and places the result in the<br>
+ *  destination register Rd.  The C Flag in SREG is not affected by the<br>
+ *  operation, thus allowing the INC instruction to be used on a loop counter in<br>
+ *  multiple-precision computations.  When operating on unsigned numbers, only<br>
+ *  BREQ and BRNE branches can be expected to perform consistently. When<br>
+ *  operating on two&#39;s complement values, all signed branches are available.<br>
+ */<br>
+static bool trans_INC(DisasContext *ctx, arg_INC *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+<br>
+    tcg_gen_addi_tl(Rd, Rd, 1);<br>
+    tcg_gen_andi_tl(Rd, Rd, 0xff);<br>
+<br>
+    /* cpu_Vf = Rd == 0x80 */<br>
+    tcg_gen_setcondi_tl(TCG_COND_<wbr>EQ, cpu_Vf, Rd, 0x80);<br>
+    gen_ZNSf(Rd);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Jump to an address within the entire 4M (words) Program memory. See also<br>
+ *  RJMP.  This instruction is not available in all devices. Refer to the device<br>
+ *  specific instruction set summary.0<br>
+ */<br>
+static bool trans_JMP(DisasContext *ctx, arg_JMP *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    gen_goto_tb(ctx, 0, a-&gt;imm);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Load one byte indirect from data space to register and stores an clear<br>
+ *  the bits in data space specified by the register. The instruction can only<br>
+ *  be used towards internal SRAM.  The data location is pointed to by the Z (16<br>
+ *  bits) Pointer Register in the Register File. Memory access is limited to the<br>
+ *  current data segment of 64KB. To access another data segment in devices with<br>
+ *  more than 64KB data space, the RAMPZ in register in the I/O area has to be<br>
+ *  changed.  The Z-pointer Register is left unchanged by the operation. This<br>
+ *  instruction is especially suited for clearing status bits stored in SRAM.<br>
+ */<br>
+static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)<br>
+{<br>
+    if (ctx-&gt;tb-&gt;flags &amp; TB_FLAGS_FULL_ACCESS) {<br>
+        gen_helper_fullwr(cpu_env, data, addr);<br>
+    } else {<br>
+        tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */<br>
+    }<br>
+}<br>
+<br>
+static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)<br>
+{<br>
+    if (ctx-&gt;tb-&gt;flags &amp; TB_FLAGS_FULL_ACCESS) {<br>
+        gen_helper_fullrd(data, cpu_env, addr);<br>
+    } else {<br>
+        tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */<br>
+    }<br>
+}<br>
+<br>
+static bool trans_LAC(DisasContext *ctx, arg_LAC *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rr = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_zaddr();<br>
+    TCGv t0 = tcg_temp_new_i32();<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+<br>
+    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */<br>
+        /* t1 = t0 &amp; (0xff - Rr) = t0 and ~Rr */<br>
+    tcg_gen_andc_tl(t1, t0, Rr);<br>
+<br>
+    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */<br>
+    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */<br>
+<br>
+    tcg_temp_free_i32(t1);<br>
+    tcg_temp_free_i32(t0);<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Load one byte indirect from data space to register and set bits in data<br>
+ *  space specified by the register. The instruction can only be used towards<br>
+ *  internal SRAM.  The data location is pointed to by the Z (16 bits) Pointer<br>
+ *  Register in the Register File. Memory access is limited to the current data<br>
+ *  segment of 64KB. To access another data segment in devices with more than<br>
+ *  64KB data space, the RAMPZ in register in the I/O area has to be changed.<br>
+ *  The Z-pointer Register is left unchanged by the operation. This instruction<br>
+ *  is especially suited for setting status bits stored in SRAM.<br>
+ */<br>
+static bool trans_LAS(DisasContext *ctx, arg_LAS *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rr = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_zaddr();<br>
+    TCGv t0 = tcg_temp_new_i32();<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+<br>
+    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */<br>
+    tcg_gen_or_tl(t1, t0, Rr);<br>
+<br>
+    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */<br>
+    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */<br>
+<br>
+    tcg_temp_free_i32(t1);<br>
+    tcg_temp_free_i32(t0);<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Load one byte indirect from data space to register and toggles bits in<br>
+ *  the data space specified by the register.  The instruction can only be used<br>
+ *  towards SRAM.  The data location is pointed to by the Z (16 bits) Pointer<br>
+ *  Register in the Register File. Memory access is limited to the current data<br>
+ *  segment of 64KB. To access another data segment in devices with more than<br>
+ *  64KB data space, the RAMPZ in register in the I/O area has to be changed.<br>
+ *  The Z-pointer Register is left unchanged by the operation. This instruction<br>
+ *  is especially suited for changing status bits stored in SRAM.<br>
+ */<br>
+static bool trans_LAT(DisasContext *ctx, arg_LAT *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_zaddr();<br>
+    TCGv t0 = tcg_temp_new_i32();<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+<br>
+    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */<br>
+    tcg_gen_xor_tl(t1, t0, Rd);<br>
+<br>
+    tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */<br>
+    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */<br>
+<br>
+    tcg_temp_free_i32(t1);<br>
+    tcg_temp_free_i32(t0);<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Loads one byte indirect from the data space to a register. For parts<br>
+ *  with SRAM, the data space consists of the Register File, I/O memory and<br>
+ *  internal SRAM (and external SRAM if applicable). For parts without SRAM, the<br>
+ *  data space consists of the Register File only. In some parts the Flash<br>
+ *  Memory has been mapped to the data space and can be read using this command.<br>
+ *  The EEPROM has a separate address space.  The data location is pointed to by<br>
+ *  the X (16 bits) Pointer Register in the Register File. Memory access is<br>
+ *  limited to the current data segment of 64KB. To access another data segment<br>
+ *  in devices with more than 64KB data space, the RAMPX in register in the I/O<br>
+ *  area has to be changed.  The X-pointer Register can either be left unchanged<br>
+ *  by the operation, or it can be post-incremented or predecremented.  These<br>
+ *  features are especially suited for accessing arrays, tables, and Stack<br>
+ *  Pointer usage of the X-pointer Register. Note that only the low byte of the<br>
+ *  X-pointer is updated in devices with no more than 256 bytes data space. For<br>
+ *  such devices, the high byte of the pointer is not used by this instruction<br>
+ *  and can be used for other purposes. The RAMPX Register in the I/O area is<br>
+ *  updated in parts with more than 64KB data space or more than 64KB Program<br>
+ *  memory, and the increment/decrement is added to the entire 24-bit address on<br>
+ *  such devices.  Not all variants of this instruction is available in all<br>
+ *  devices. Refer to the device specific instruction set summary.  In the<br>
+ *  Reduced Core tinyAVR the LD instruction can be used to achieve the same<br>
+ *  operation as LPM since the program memory is mapped to the data memory<br>
+ *  space.<br>
+ */<br>
+static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_xaddr();<br>
+<br>
+    gen_data_load(ctx, Rd, addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_xaddr();<br>
+<br>
+    gen_data_load(ctx, Rd, addr);<br>
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */<br>
+<br>
+    gen_set_xaddr(addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_xaddr();<br>
+<br>
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */<br>
+    gen_data_load(ctx, Rd, addr);<br>
+    gen_set_xaddr(addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Loads one byte indirect with or without displacement from the data space<br>
+ *  to a register. For parts with SRAM, the data space consists of the Register<br>
+ *  File, I/O memory and internal SRAM (and external SRAM if applicable). For<br>
+ *  parts without SRAM, the data space consists of the Register File only. In<br>
+ *  some parts the Flash Memory has been mapped to the data space and can be<br>
+ *  read using this command. The EEPROM has a separate address space.  The data<br>
+ *  location is pointed to by the Y (16 bits) Pointer Register in the Register<br>
+ *  File. Memory access is limited to the current data segment of 64KB. To<br>
+ *  access another data segment in devices with more than 64KB data space, the<br>
+ *  RAMPY in register in the I/O area has to be changed.  The Y-pointer Register<br>
+ *  can either be left unchanged by the operation, or it can be post-incremented<br>
+ *  or predecremented.  These features are especially suited for accessing<br>
+ *  arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that<br>
+ *  only the low byte of the Y-pointer is updated in devices with no more than<br>
+ *  256 bytes data space. For such devices, the high byte of the pointer is not<br>
+ *  used by this instruction and can be used for other purposes. The RAMPY<br>
+ *  Register in the I/O area is updated in parts with more than 64KB data space<br>
+ *  or more than 64KB Program memory, and the increment/decrement/<wbr>displacement<br>
+ *  is added to the entire 24-bit address on such devices.  Not all variants of<br>
+ *  this instruction is available in all devices. Refer to the device specific<br>
+ *  instruction set summary.  In the Reduced Core tinyAVR the LD instruction can<br>
+ *  be used to achieve the same operation as LPM since the program memory is<br>
+ *  mapped to the data memory space.<br>
+ */<br>
+static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_yaddr();<br>
+<br>
+    gen_data_load(ctx, Rd, addr);<br>
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */<br>
+<br>
+    gen_set_yaddr(addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_yaddr();<br>
+<br>
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */<br>
+    gen_data_load(ctx, Rd, addr);<br>
+    gen_set_yaddr(addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_yaddr();<br>
+<br>
+    tcg_gen_addi_tl(addr, addr, a-&gt;imm); /* addr = addr + q */<br>
+    gen_data_load(ctx, Rd, addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Loads one byte indirect with or without displacement from the data space<br>
+ *  to a register. For parts with SRAM, the data space consists of the Register<br>
+ *  File, I/O memory and internal SRAM (and external SRAM if applicable). For<br>
+ *  parts without SRAM, the data space consists of the Register File only. In<br>
+ *  some parts the Flash Memory has been mapped to the data space and can be<br>
+ *  read using this command. The EEPROM has a separate address space.  The data<br>
+ *  location is pointed to by the Z (16 bits) Pointer Register in the Register<br>
+ *  File. Memory access is limited to the current data segment of 64KB. To<br>
+ *  access another data segment in devices with more than 64KB data space, the<br>
+ *  RAMPZ in register in the I/O area has to be changed.  The Z-pointer Register<br>
+ *  can either be left unchanged by the operation, or it can be post-incremented<br>
+ *  or predecremented.  These features are especially suited for Stack Pointer<br>
+ *  usage of the Z-pointer Register, however because the Z-pointer Register can<br>
+ *  be used for indirect subroutine calls, indirect jumps and table lookup, it<br>
+ *  is often more convenient to use the X or Y-pointer as a dedicated Stack<br>
+ *  Pointer. Note that only the low byte of the Z-pointer is updated in devices<br>
+ *  with no more than 256 bytes data space. For such devices, the high byte of<br>
+ *  the pointer is not used by this instruction and can be used for other<br>
+ *  purposes. The RAMPZ Register in the I/O area is updated in parts with more<br>
+ *  than 64KB data space or more than 64KB Program memory, and the<br>
+ *  increment/decrement/<wbr>displacement is added to the entire 24-bit address on<br>
+ *  such devices.  Not all variants of this instruction is available in all<br>
+ *  devices. Refer to the device specific instruction set summary.  In the<br>
+ *  Reduced Core tinyAVR the LD instruction can be used to achieve the same<br>
+ *  operation as LPM since the program memory is mapped to the data memory<br>
+ *  space.  For using the Z-pointer for table lookup in Program memory see the<br>
+ *  LPM and ELPM instructions.<br>
+ */<br>
+static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_zaddr();<br>
+<br>
+    gen_data_load(ctx, Rd, addr);<br>
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */<br>
+<br>
+    gen_set_zaddr(addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_zaddr();<br>
+<br>
+    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */<br>
+    gen_data_load(ctx, Rd, addr);<br>
+<br>
+    gen_set_zaddr(addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = gen_get_zaddr();<br>
+<br>
+    tcg_gen_addi_tl(addr, addr, a-&gt;imm); /* addr = addr + q */<br>
+    gen_data_load(ctx, Rd, addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ * Loads an 8 bit constant directly to register 16 to 31.<br>
+ */<br>
+static bool trans_LDI(DisasContext *ctx, arg_LDI *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    int imm = a-&gt;imm;<br>
+<br>
+    tcg_gen_movi_tl(Rd, imm);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Loads one byte from the data space to a register. For parts with SRAM,<br>
+ *  the data space consists of the Register File, I/O memory and internal SRAM<br>
+ *  (and external SRAM if applicable). For parts without SRAM, the data space<br>
+ *  consists of the register file only. The EEPROM has a separate address space.<br>
+ *  A 16-bit address must be supplied. Memory access is limited to the current<br>
+ *  data segment of 64KB. The LDS instruction uses the RAMPD Register to access<br>
+ *  memory above 64KB. To access another data segment in devices with more than<br>
+ *  64KB data space, the RAMPD in register in the I/O area has to be changed.<br>
+ *  This instruction is not available in all devices. Refer to the device<br>
+ *  specific instruction set summary.<br>
+ */<br>
+static bool trans_LDS(DisasContext *ctx, arg_LDS *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = tcg_temp_new_i32();<br>
+    TCGv H = cpu_rampD;<br>
+    a-&gt;imm = next_word(ctx);<br>
+<br>
+    tcg_gen_mov_tl(addr, H); /* addr = H:M:L */<br>
+    tcg_gen_shli_tl(addr, addr, 16);<br>
+    tcg_gen_ori_tl(addr, addr, a-&gt;imm);<br>
+<br>
+    gen_data_load(ctx, Rd, addr);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Loads one byte pointed to by the Z-register into the destination<br>
+ *  register Rd. This instruction features a 100% space effective constant<br>
+ *  initialization or constant data fetch. The Program memory is organized in<br>
+ *  16-bit words while the Z-pointer is a byte address. Thus, the least<br>
+ *  significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high<br>
+ *  byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of<br>
+ *  Program memory. The Zpointer Register can either be left unchanged by the<br>
+ *  operation, or it can be incremented. The incrementation does not apply to<br>
+ *  the RAMPZ Register.  Devices with Self-Programming capability can use the<br>
+ *  LPM instruction to read the Fuse and Lock bit values.  Refer to the device<br>
+ *  documentation for a detailed description.  The LPM instruction is not<br>
+ *  available in all devices. Refer to the device specific instruction set<br>
+ *  summary<br>
+ */<br>
+static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rd = cpu_r[0];<br>
+    TCGv addr = tcg_temp_new_i32();<br>
+    TCGv H = cpu_r[31];<br>
+    TCGv L = cpu_r[30];<br>
+<br>
+    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */<br>
+    tcg_gen_or_tl(addr, addr, L);<br>
+<br>
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = tcg_temp_new_i32();<br>
+    TCGv H = cpu_r[31];<br>
+    TCGv L = cpu_r[30];<br>
+<br>
+    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */<br>
+    tcg_gen_or_tl(addr, addr, L);<br>
+<br>
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv addr = tcg_temp_new_i32();<br>
+    TCGv H = cpu_r[31];<br>
+    TCGv L = cpu_r[30];<br>
+<br>
+    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */<br>
+    tcg_gen_or_tl(addr, addr, L);<br>
+<br>
+    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */<br>
+<br>
+    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */<br>
+<br>
+    tcg_gen_andi_tl(L, addr, 0xff);<br>
+<br>
+    tcg_gen_shri_tl(addr, addr, 8);<br>
+    tcg_gen_andi_tl(H, addr, 0xff);<br>
+<br>
+    tcg_temp_free_i32(addr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is<br>
+ *  loaded into the C Flag of the SREG. This operation effectively divides an<br>
+ *  unsigned value by two. The C Flag can be used to round the result.<br>
+ */<br>
+static bool trans_LSR(DisasContext *ctx, arg_LSR *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+<br>
+    tcg_gen_andi_tl(cpu_Cf, Rd, 1);<br>
+<br>
+    tcg_gen_shri_tl(Rd, Rd, 1);<br>
+<br>
+    tcg_gen_mov_tl(cpu_Zf, Rd);<br>
+    tcg_gen_movi_tl(cpu_Nf, 0);<br>
+    tcg_gen_mov_tl(cpu_Vf, cpu_Cf);<br>
+    tcg_gen_mov_tl(cpu_Sf, cpu_Vf);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction makes a copy of one register into another. The source<br>
+ *  register Rr is left unchanged, while the destination register Rd is loaded<br>
+ *  with a copy of Rr.<br>
+ */<br>
+static bool trans_MOV(DisasContext *ctx, arg_MOV *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+<br>
+    tcg_gen_mov_tl(Rd, Rr);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction makes a copy of one register pair into another register<br>
+ *  pair. The source register pair Rr+1:Rr is left unchanged, while the<br>
+ *  destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr.  This<br>
+ *  instruction is not available in all devices. Refer to the device specific<br>
+ *  instruction set summary.<br>
+ */<br>
+static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv RdL = cpu_r[a-&gt;rd];<br>
+    TCGv RdH = cpu_r[a-&gt;rd + 1];<br>
+    TCGv RrL = cpu_r[a-&gt;rr];<br>
+    TCGv RrH = cpu_r[a-&gt;rr + 1];<br>
+<br>
+    tcg_gen_mov_tl(RdH, RrH);<br>
+    tcg_gen_mov_tl(RdL, RrL);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs 8-bit x 8-bit -&gt; 16-bit unsigned multiplication.<br>
+ */<br>
+static bool trans_MUL(DisasContext *ctx, arg_MUL *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv R0 = cpu_r[0];<br>
+    TCGv R1 = cpu_r[1];<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */<br>
+<br>
+    tcg_gen_andi_tl(R0, R, 0xff);<br>
+    tcg_gen_shri_tl(R1, R, 8);<br>
+<br>
+    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */<br>
+    tcg_gen_mov_tl(cpu_Zf, R);<br>
+<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs 8-bit x 8-bit -&gt; 16-bit signed multiplication.<br>
+ */<br>
+static bool trans_MULS(DisasContext *ctx, arg_MULS *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv R0 = cpu_r[0];<br>
+    TCGv R1 = cpu_r[1];<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+    TCGv t0 = tcg_temp_new_i32();<br>
+    TCGv t1 = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */<br>
+    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */<br>
+    tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */<br>
+<br>
+    tcg_gen_andi_tl(R0, R, 0xff);<br>
+    tcg_gen_shri_tl(R1, R, 8);<br>
+<br>
+    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */<br>
+    tcg_gen_mov_tl(cpu_Zf, R);<br>
+<br>
+    tcg_temp_free_i32(t1);<br>
+    tcg_temp_free_i32(t0);<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  This instruction performs 8-bit x 8-bit -&gt; 16-bit multiplication of a<br>
+ *  signed and an unsigned number.<br>
+ */<br>
+static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a)<br>
+{<br>
+    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {<br>
+        return true;<br>
+    }<br>
+<br>
+    TCGv R0 = cpu_r[0];<br>
+    TCGv R1 = cpu_r[1];<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv Rr = cpu_r[a-&gt;rr];<br>
+    TCGv R = tcg_temp_new_i32();<br>
+    TCGv t0 = tcg_temp_new_i32();<br>
+<br>
+    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */<br>
+    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */<br>
+<br>
+    tcg_gen_andi_tl(R0, R, 0xff);<br>
+    tcg_gen_shri_tl(R1, R, 8);<br>
+<br>
+    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */<br>
+    tcg_gen_mov_tl(cpu_Zf, R);<br>
+<br>
+    tcg_temp_free_i32(t0);<br>
+    tcg_temp_free_i32(R);<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+/*<br>
+ *  Replaces the contents of register Rd with its two&#39;s complement; the<br>
+ *  value $80 is left unchanged.<br>
+ */<br>
+static bool trans_NEG(DisasContext *ctx, arg_NEG *a)<br>
+{<br>
+    TCGv Rd = cpu_r[a-&gt;rd];<br>
+    TCGv t0 = tcg_const_i32(0);<br>
+    TCGv R = tcg_temp_new_i32();<br>
+<br>
+    /* op */<br>
+    tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */<br>
+    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */<br>
+<br>
+    gen_sub_CHf(R, t0, Rd);<br>
+    gen_sub_Vf(R, t0, Rd);<br>
+    gen_ZNSf(R);<br>
+<br>
+    /* R */<br>
+    tcg_gen_mov_tl(Rd,-- <br>
2.17.2 (Apple Git-113)<br>
<br>
<br>
</blockquote>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
@ 2019-10-11 14:20   ` Eric Blake
  2019-10-11 15:25   ` Philippe Mathieu-Daudé
  1 sibling, 0 replies; 19+ messages in thread
From: Eric Blake @ 2019-10-11 14:20 UTC (permalink / raw)
  To: Michael Rolnik, qemu-devel
  Cc: richard.henderson, thuth, philmd, dovgaluk, imammedo

On 9/2/19 9:01 AM, Michael Rolnik wrote:
> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
> ---

> +++ b/qapi/machine.json
> @@ -21,11 +21,12 @@
>   #        is true even for "qemu-system-x86_64".
>   #
>   # ppcemb: dropped in 3.1
> +# avr: sicne 4.2

since

>   #
>   # Since: 3.0
>   ##
>   { 'enum' : 'SysEmuTarget',
> -  'data' : [ 'aarch64', 'alpha', 'arm', 'cris', 'hppa', 'i386', 'lm32',
> +  'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386', 'lm32',
>                'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
>                'mips64el', 'mipsel', 'moxie', 'nios2', 'or1k', 'ppc',
>                'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4',


-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.           +1-919-301-3226
Virtualization:  qemu.org | libvirt.org


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
  2019-10-11 14:20   ` Eric Blake
@ 2019-10-11 15:25   ` Philippe Mathieu-Daudé
  1 sibling, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-11 15:25 UTC (permalink / raw)
  To: Michael Rolnik, qemu-devel; +Cc: dovgaluk, thuth, richard.henderson, imammedo

Hi Michael,

On 9/2/19 4:01 PM, Michael Rolnik wrote:
> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
> ---
>   MAINTAINERS                     |  6 +++
>   arch_init.c                     |  2 +
>   configure                       | 93 ++++++++++++++++++---------------
>   default-configs/avr-softmmu.mak |  5 ++
>   include/disas/dis-asm.h         |  6 +++
>   include/sysemu/arch_init.h      |  1 +
>   qapi/machine.json               |  3 +-
>   target/avr/Makefile.objs        | 33 ++++++++++++
>   tests/machine-none-test.c       |  1 +
>   9 files changed, 106 insertions(+), 44 deletions(-)
>   create mode 100644 default-configs/avr-softmmu.mak
>   create mode 100644 target/avr/Makefile.objs
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ef6c01084b..763370e6ff 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -163,6 +163,12 @@ S: Maintained
>   F: hw/arm/smmu*
>   F: include/hw/arm/smmu*
>   
> +AVR TCG CPUs
> +M: Michael Rolnik <mrolnik@gmail.com>
> +S: Maintained
> +F: target/avr/
> +F: hw/avr/
> +
>   CRIS TCG CPUs
>   M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
>   S: Maintained
> diff --git a/arch_init.c b/arch_init.c
> index 0a1531124c..fb308aa802 100644
> --- a/arch_init.c
> +++ b/arch_init.c
> @@ -85,6 +85,8 @@ int graphic_depth = 32;
>   #define QEMU_ARCH QEMU_ARCH_UNICORE32
>   #elif defined(TARGET_XTENSA)
>   #define QEMU_ARCH QEMU_ARCH_XTENSA
> +#elif defined(TARGET_AVR)
> +#define QEMU_ARCH QEMU_ARCH_AVR
>   #endif
>   
>   const uint32_t arch_type = QEMU_ARCH;
> diff --git a/configure b/configure
> index e44e454c43..b35a7cf214 100755
> --- a/configure
> +++ b/configure
> @@ -2032,7 +2032,7 @@ EOF
>   
>   if ! compile_prog "-Werror" "" ; then
>       error_exit "Your compiler does not support the __thread specifier for " \
> -	"Thread-Local Storage (TLS). Please upgrade to a version that does."
> +    "Thread-Local Storage (TLS). Please upgrade to a version that does."

You included indenting changes not related to the patch :/

>   fi
>   
>   if test "$pie" = ""; then
> @@ -2820,7 +2820,7 @@ if test "$gnutls" != "no"; then
>           fi
>       fi
>       if test "$pass" = "no" && test "$gnutls" = "yes"; then
> -	feature_not_found "gnutls" "Install gnutls devel >= 3.1.18"
> +    feature_not_found "gnutls" "Install gnutls devel >= 3.1.18"
>       else
>           gnutls="$pass"
>       fi
> @@ -2852,16 +2852,16 @@ fi
>   has_libgcrypt() {
>       if ! has "libgcrypt-config"
>       then
> -	return 1
> +    return 1
>       fi
>   
>       if test -n "$cross_prefix"
>       then
> -	host=$(libgcrypt-config --host)
> -	if test "$host-" != $cross_prefix
> -	then
> -	    return 1
> -	fi
> +    host=$(libgcrypt-config --host)
> +    if test "$host-" != $cross_prefix
> +    then
> +        return 1
> +    fi
>       fi
>   
>       maj=`libgcrypt-config --version | awk -F . '{print $1}'`
> @@ -3071,7 +3071,7 @@ EOF
>            sdl_cflags="$sdl_cflags $(aalib-config --cflags 2>/dev/null)"
>         fi
>         if compile_prog "$sdl_cflags" "$sdl_libs" ; then
> -	:
> +    :
>         else
>           sdl=no
>         fi
> @@ -3689,8 +3689,8 @@ EOF
>   if ! compile_prog "$CFLAGS" "$LIBS" ; then
>       error_exit "sizeof(size_t) doesn't match GLIB_SIZEOF_SIZE_T."\
>                  "You probably need to set PKG_CONFIG_LIBDIR"\
> -	       "to point to the right pkg-config files for your"\
> -	       "build target"
> +           "to point to the right pkg-config files for your"\
> +           "build target"
>   fi
>   
>   # Silence clang 3.5.0 warnings about glib attribute __alloc_size__ usage
> @@ -4200,8 +4200,8 @@ if test "$glusterfs" != "no" ; then
>   int
>   main(void)
>   {
> -	/* new glfs_ftruncate() passes two additional args */
> -	return glfs_ftruncate(NULL, 0, NULL, NULL);
> +    /* new glfs_ftruncate() passes two additional args */
> +    return glfs_ftruncate(NULL, 0, NULL, NULL);
>   }
>   EOF
>       if compile_prog "$glusterfs_cflags" "$glusterfs_libs" ; then
> @@ -4218,9 +4218,9 @@ glusterfs_iocb(glfs_fd_t *fd, ssize_t ret, struct glfs_stat *prestat, struct glf
>   int
>   main(void)
>   {
> -	glfs_io_cbk iocb = &glusterfs_iocb;
> -	iocb(NULL, 0 , NULL, NULL, NULL);
> -	return 0;
> +    glfs_io_cbk iocb = &glusterfs_iocb;
> +    iocb(NULL, 0 , NULL, NULL, NULL);
> +    return 0;
>   }
>   EOF
>       if compile_prog "$glusterfs_cflags" "$glusterfs_libs" ; then
> @@ -4247,8 +4247,8 @@ cat > $TMPC << EOF
>   int
>   main(void)
>   {
> -	/* try to start inotify */
> -	return inotify_init();
> +    /* try to start inotify */
> +    return inotify_init();
>   }
>   EOF
>   if compile_prog "" "" ; then
> @@ -4921,8 +4921,8 @@ if test "$mingw32" = "yes" && test "$guest_agent" != "no" && \
>       *\ *) # The SDK is installed in "Program Files" by default, but we cannot
>             # handle path with spaces. So we symlink the headers into ".sdk/vss".
>             vss_win32_include="-isystem $source_path/.sdk/vss"
> -	  symlink "$vss_win32_sdk/inc" "$source_path/.sdk/vss/inc"
> -	  ;;
> +      symlink "$vss_win32_sdk/inc" "$source_path/.sdk/vss/inc"
> +      ;;
>       *)    vss_win32_include="-isystem $vss_win32_sdk"
>     esac
>     cat > $TMPC << EOF
> @@ -5643,7 +5643,7 @@ if test "$membarrier" = "yes"; then
>       int main(void) {
>           syscall(__NR_membarrier, MEMBARRIER_CMD_QUERY, 0);
>           syscall(__NR_membarrier, MEMBARRIER_CMD_SHARED, 0);
> -	exit(0);
> +    exit(0);
>       }
>   EOF
>           if compile_prog "" "" ; then
> @@ -5720,7 +5720,7 @@ if test "$crypto_afalg" = "yes"
>   then
>       if test "$have_afalg" != "yes"
>       then
> -	error_exit "AF_ALG requested but could not be detected"
> +    error_exit "AF_ALG requested but could not be detected"
>       fi
>   fi
>   
> @@ -5908,18 +5908,18 @@ fi
>   # check for libpmem
>   
>   if test "$libpmem" != "no"; then
> -	if $pkg_config --exists "libpmem"; then
> -		libpmem="yes"
> -		libpmem_libs=$($pkg_config --libs libpmem)
> -		libpmem_cflags=$($pkg_config --cflags libpmem)
> -		libs_softmmu="$libs_softmmu $libpmem_libs"
> -		QEMU_CFLAGS="$QEMU_CFLAGS $libpmem_cflags"
> -	else
> -		if test "$libpmem" = "yes" ; then
> -			feature_not_found "libpmem" "Install nvml or pmdk"
> -		fi
> -		libpmem="no"
> -	fi
> +    if $pkg_config --exists "libpmem"; then
> +        libpmem="yes"
> +        libpmem_libs=$($pkg_config --libs libpmem)
> +        libpmem_cflags=$($pkg_config --cflags libpmem)
> +        libs_softmmu="$libs_softmmu $libpmem_libs"
> +        QEMU_CFLAGS="$QEMU_CFLAGS $libpmem_cflags"
> +    else
> +        if test "$libpmem" = "yes" ; then
> +            feature_not_found "libpmem" "Install nvml or pmdk"
> +        fi
> +        libpmem="no"
> +    fi
>   fi
>   
>   ##########################################
> @@ -6643,10 +6643,10 @@ echo "CONFIG_AUDIO_DRIVERS=$audio_drv_list" >> $config_host_mak
>   for drv in $audio_drv_list; do
>       def=CONFIG_AUDIO_$(echo $drv | LC_ALL=C tr '[a-z]' '[A-Z]')
>       case "$drv" in
> -	alsa | oss | pa | sdl)
> -	    echo "$def=m" >> $config_host_mak ;;
> -	*)
> -	    echo "$def=y" >> $config_host_mak ;;
> +    alsa | oss | pa | sdl)
> +        echo "$def=m" >> $config_host_mak ;;
> +    *)
> +        echo "$def=y" >> $config_host_mak ;;
>       esac
>   done
>   echo "ALSA_LIBS=$alsa_libs" >> $config_host_mak
> @@ -7479,14 +7479,14 @@ TARGET_ABI_DIR=""
>   case "$target_name" in
>     i386)
>       mttcg="yes"
> -	gdb_xml_files="i386-32bit.xml"
> +    gdb_xml_files="i386-32bit.xml"
>       target_compiler=$cross_cc_i386
>       target_compiler_cflags=$cross_cc_ccflags_i386
>     ;;
>     x86_64)
>       TARGET_BASE_ARCH=i386
>       mttcg="yes"
> -	gdb_xml_files="i386-64bit.xml"
> +    gdb_xml_files="i386-64bit.xml"
>       target_compiler=$cross_cc_x86_64
>     ;;
>     alpha)
> @@ -7510,6 +7510,10 @@ case "$target_name" in
>       target_compiler=$cross_cc_aarch64
>       eval "target_compiler_cflags=\$cross_cc_cflags_${target_name}"
>     ;;
> +  avr)
> +    gdb_xml_files="avr-cpu.xml"
> +    target_compiler=$cross_cc_avr
> +  ;;
>     cris)
>       target_compiler=$cross_cc_cris
>     ;;
> @@ -7790,6 +7794,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
>         disas_config "ARM_A64"
>       fi
>     ;;
> +  avr)
> +    disas_config "AVR"
> +  ;;
>     cris)
>       disas_config "CRIS"
>     ;;
> @@ -8003,10 +8010,10 @@ preserve_env() {
>   
>       if test -n "$envval"
>       then
> -	echo "$envname='$envval'" >> config.status
> -	echo "export $envname" >> config.status
> +    echo "$envname='$envval'" >> config.status
> +    echo "export $envname" >> config.status
>       else
> -	echo "unset $envname" >> config.status
> +    echo "unset $envname" >> config.status
>       fi
>   }
>   
> diff --git a/default-configs/avr-softmmu.mak b/default-configs/avr-softmmu.mak
> new file mode 100644
> index 0000000000..d1e1c28118
> --- /dev/null
> +++ b/default-configs/avr-softmmu.mak
> @@ -0,0 +1,5 @@
> +# Default configuration for avr-softmmu
> +
> +# Boards:
> +#
> +CONFIG_AVR_SAMPLE=y
> diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
> index e9c7dd8eb4..8bedce17ac 100644
> --- a/include/disas/dis-asm.h
> +++ b/include/disas/dis-asm.h
> @@ -211,6 +211,12 @@ enum bfd_architecture
>   #define bfd_mach_m32r          0  /* backwards compatibility */
>     bfd_arch_mn10200,    /* Matsushita MN10200 */
>     bfd_arch_mn10300,    /* Matsushita MN10300 */
> +  bfd_arch_avr,       /* Atmel AVR microcontrollers.  */
> +#define bfd_mach_avr1          1
> +#define bfd_mach_avr2          2
> +#define bfd_mach_avr3          3
> +#define bfd_mach_avr4          4
> +#define bfd_mach_avr5          5
>     bfd_arch_cris,       /* Axis CRIS */
>   #define bfd_mach_cris_v0_v10   255
>   #define bfd_mach_cris_v32      32
> diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
> index 62c6fe4cf1..893df26ce2 100644
> --- a/include/sysemu/arch_init.h
> +++ b/include/sysemu/arch_init.h
> @@ -24,6 +24,7 @@ enum {
>       QEMU_ARCH_NIOS2 = (1 << 17),
>       QEMU_ARCH_HPPA = (1 << 18),
>       QEMU_ARCH_RISCV = (1 << 19),
> +    QEMU_ARCH_AVR = (1 << 20),
>   };
>   
>   extern const uint32_t arch_type;
> diff --git a/qapi/machine.json b/qapi/machine.json
> index de5c742d72..afede0bc50 100644
> --- a/qapi/machine.json
> +++ b/qapi/machine.json
> @@ -21,11 +21,12 @@
>   #        is true even for "qemu-system-x86_64".
>   #
>   # ppcemb: dropped in 3.1
> +# avr: sicne 4.2
>   #
>   # Since: 3.0
>   ##
>   { 'enum' : 'SysEmuTarget',
> -  'data' : [ 'aarch64', 'alpha', 'arm', 'cris', 'hppa', 'i386', 'lm32',
> +  'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386', 'lm32',
>                'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
>                'mips64el', 'mipsel', 'moxie', 'nios2', 'or1k', 'ppc',
>                'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4',
> diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs
> new file mode 100644
> index 0000000000..2976affd95
> --- /dev/null
> +++ b/target/avr/Makefile.objs
> @@ -0,0 +1,33 @@
> +#
> +#  QEMU AVR CPU
> +#
> +#  Copyright (c) 2019 Michael Rolnik
> +#
> +#  This library is free software; you can redistribute it and/or
> +#  modify it under the terms of the GNU Lesser General Public
> +#  License as published by the Free Software Foundation; either
> +#  version 2.1 of the License, or (at your option) any later version.
> +#
> +#  This library is distributed in the hope that it will be useful,
> +#  but WITHOUT ANY WARRANTY; without even the implied warranty of
> +#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> +#  Lesser General Public License for more details.
> +#
> +#  You should have received a copy of the GNU Lesser General Public
> +#  License along with this library; if not, see
> +#  <http://www.gnu.org/licenses/lgpl-2.1.html>
> +#
> +
> +DECODETREE = $(SRC_PATH)/scripts/decodetree.py
> +decode-y = $(SRC_PATH)/target/avr/insn.decode
> +
> +target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE)
> +	$(call quiet-command, \
> +	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \
> +	  "GEN", $(TARGET_DIR)$@)
> +
> +target/avr/translate.o: target/avr/decode_insn.inc.c
> +
> +obj-y += translate.o cpu.o helper.o
> +obj-y += gdbstub.o
> +obj-$(CONFIG_SOFTMMU) += machine.o
> diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c
> index 5953d31755..3e5c74e73e 100644
> --- a/tests/machine-none-test.c
> +++ b/tests/machine-none-test.c
> @@ -27,6 +27,7 @@ static struct arch2cpu cpus_map[] = {
>       /* tested targets list */
>       { "arm", "cortex-a15" },
>       { "aarch64", "cortex-a57" },
> +    { "avr", "avr6-avr-cpu" },
>       { "x86_64", "qemu64,apic-id=0" },
>       { "i386", "qemu32,apic-id=0" },
>       { "alpha", "ev67" },
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v30 0/8] QEMU AVR 8 bit cores
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
                   ` (7 preceding siblings ...)
  2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 8/8] target/avr: Add tests Michael Rolnik
@ 2019-10-11 15:32 ` Philippe Mathieu-Daudé
  2019-10-11 15:54   ` [Qemu-devel] " Aleksandar Markovic
  2019-10-11 15:41 ` Philippe Mathieu-Daudé
  9 siblings, 1 reply; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-11 15:32 UTC (permalink / raw)
  To: Michael Rolnik, qemu-devel; +Cc: dovgaluk, thuth, richard.henderson, imammedo

Hi Michael,

On 9/2/19 4:01 PM, Michael Rolnik wrote:
> This series of patches adds 8bit AVR cores to QEMU.
> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet.
> However I was able to execute simple code with functions. e.g fibonacci calculation.
> This series of patches include a non real, sample board.
> No fuses support yet. PC is set to 0 at reset.
> 
> the patches include the following
> 1. just a basic 8bit AVR CPU, without instruction decoding or translation
> 2. CPU features which allow define the following 8bit AVR cores
>       avr1
>       avr2 avr25
>       avr3 avr31 avr35
>       avr4
>       avr5 avr51
>       avr6
>       xmega2 xmega4 xmega5 xmega6 xmega7
> 3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code
> 4. encoding for all AVR instructions
> 5. interrupt handling
> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
> 7. a decoder which given an opcode decides what istruction it is
> 8. translation of AVR instruction into TCG
> 9. all features together
> 
[..]
> Michael Rolnik (7):
>    target/avr: Add outward facing interfaces and core CPU logic
>    target/avr: Add instruction helpers
>    target/avr: Add instruction decoding
>    target/avr: Add instruction translation
>    target/avr: Add example board configuration
>    target/avr: Register AVR support with the rest of QEMU, the build
>      system, and the MAINTAINERS file
>    target/avr: Add tests
> 
> Sarah Harris (1):
>    target/avr: Add limited support for USART and 16 bit timer peripherals

Overall architecture patches look good, but I'd like some more time to 
review the hardware patches. Unfortunately I won't have time until November.
There was a chat on IRC about your series, I suggested Richard we could 
merge patches 1-4 and 7. They are almost sufficient to run the 
qemu-avr-tests gdbstub tests (but not the FreeRTOS ones).

Regards,

Phil.


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v30 0/8] QEMU AVR 8 bit cores
  2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
                   ` (8 preceding siblings ...)
  2019-10-11 15:32 ` [PATCH v30 0/8] QEMU AVR 8 bit cores Philippe Mathieu-Daudé
@ 2019-10-11 15:41 ` Philippe Mathieu-Daudé
  9 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-11 15:41 UTC (permalink / raw)
  To: Michael Rolnik, qemu-devel; +Cc: dovgaluk, thuth, richard.henderson, imammedo

On 9/2/19 4:01 PM, Michael Rolnik wrote:
> Michael Rolnik (7):
>    target/avr: Add outward facing interfaces and core CPU logic
>    target/avr: Add instruction helpers
>    target/avr: Add instruction decoding
>    target/avr: Add instruction translation
[...]>   target/avr/Makefile.objs         |   33 +
>   target/avr/cpu-param.h           |   37 +
>   target/avr/cpu-qom.h             |   54 +
>   target/avr/cpu.c                 |  576 ++++++
>   target/avr/cpu.h                 |  254 +++
>   target/avr/gdbstub.c             |   85 +
>   target/avr/helper.c              |  354 ++++
>   target/avr/helper.h              |   29 +
>   target/avr/insn.decode           |  175 ++
>   target/avr/machine.c             |  121 ++
>   target/avr/translate.c           | 2888 ++++++++++++++++++++++++++++++

Hmmm I'm wondering, since the 32-bit arch is different, shouldn't we add 
this under target/avr8/ ?


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
  2019-10-11 15:32 ` [PATCH v30 0/8] QEMU AVR 8 bit cores Philippe Mathieu-Daudé
@ 2019-10-11 15:54   ` " Aleksandar Markovic
  2019-10-11 16:11     ` Alex Bennée
  0 siblings, 1 reply; 19+ messages in thread
From: Aleksandar Markovic @ 2019-10-11 15:54 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé
  Cc: thuth, richard.henderson, qemu-devel, dovgaluk, imammedo, Michael Rolnik

[-- Attachment #1: Type: text/plain, Size: 2448 bytes --]

On Friday, October 11, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:

> Hi Michael,
>
> On 9/2/19 4:01 PM, Michael Rolnik wrote:
>
>> This series of patches adds 8bit AVR cores to QEMU.
>> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
>> tested yet.
>> However I was able to execute simple code with functions. e.g fibonacci
>> calculation.
>> This series of patches include a non real, sample board.
>> No fuses support yet. PC is set to 0 at reset.
>>
>> the patches include the following
>> 1. just a basic 8bit AVR CPU, without instruction decoding or translation
>> 2. CPU features which allow define the following 8bit AVR cores
>>       avr1
>>       avr2 avr25
>>       avr3 avr31 avr35
>>       avr4
>>       avr5 avr51
>>       avr6
>>       xmega2 xmega4 xmega5 xmega6 xmega7
>> 3. a definition of sample machine with SRAM, FLASH and CPU which allows
>> to execute simple code
>> 4. encoding for all AVR instructions
>> 5. interrupt handling
>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
>> 7. a decoder which given an opcode decides what istruction it is
>> 8. translation of AVR instruction into TCG
>> 9. all features together
>>
>> [..]
>
>> Michael Rolnik (7):
>>    target/avr: Add outward facing interfaces and core CPU logic
>>    target/avr: Add instruction helpers
>>    target/avr: Add instruction decoding
>>    target/avr: Add instruction translation
>>    target/avr: Add example board configuration
>>    target/avr: Register AVR support with the rest of QEMU, the build
>>      system, and the MAINTAINERS file
>>    target/avr: Add tests
>>
>> Sarah Harris (1):
>>    target/avr: Add limited support for USART and 16 bit timer peripherals
>>
>
> Overall architecture patches look good, but I'd like some more time to
> review the hardware patches. Unfortunately I won't have time until November.
> There was a chat on IRC about your series,


>
>
I don't see the reason why do you initiate IRC communication on this topic,
if we have the mailing list for discussing such important issues as
introducing a new target (that should be definitely visible to all
participants).

Thanks, Aleksandar



>
>
>

> I suggested Richard we could merge patches 1-4 and 7. They are almost
> sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS
> ones).
>
> Regards,
>
> Phil.
>
>

[-- Attachment #2: Type: text/html, Size: 3698 bytes --]

<br><br>On Friday, October 11, 2019, Philippe Mathieu-Daudé &lt;<a href="mailto:philmd@redhat.com">philmd@redhat.com</a>&gt; wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Michael,<br>
<br>
On 9/2/19 4:01 PM, Michael Rolnik wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
This series of patches adds 8bit AVR cores to QEMU.<br>
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet.<br>
However I was able to execute simple code with functions. e.g fibonacci calculation.<br>
This series of patches include a non real, sample board.<br>
No fuses support yet. PC is set to 0 at reset.<br>
<br>
the patches include the following<br>
1. just a basic 8bit AVR CPU, without instruction decoding or translation<br>
2. CPU features which allow define the following 8bit AVR cores<br>
      avr1<br>
      avr2 avr25<br>
      avr3 avr31 avr35<br>
      avr4<br>
      avr5 avr51<br>
      avr6<br>
      xmega2 xmega4 xmega5 xmega6 xmega7<br>
3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code<br>
4. encoding for all AVR instructions<br>
5. interrupt handling<br>
6. helpers for IN, OUT, SLEEP, WBR &amp; unsupported instructions<br>
7. a decoder which given an opcode decides what istruction it is<br>
8. translation of AVR instruction into TCG<br>
9. all features together<br>
<br>
</blockquote>
[..]<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Michael Rolnik (7):<br>
   target/avr: Add outward facing interfaces and core CPU logic<br>
   target/avr: Add instruction helpers<br>
   target/avr: Add instruction decoding<br>
   target/avr: Add instruction translation<br>
   target/avr: Add example board configuration<br>
   target/avr: Register AVR support with the rest of QEMU, the build<br>
     system, and the MAINTAINERS file<br>
   target/avr: Add tests<br>
<br>
Sarah Harris (1):<br>
   target/avr: Add limited support for USART and 16 bit timer peripherals<br>
</blockquote>
<br>
Overall architecture patches look good, but I&#39;d like some more time to review the hardware patches. Unfortunately I won&#39;t have time until November.<br>
There was a chat on IRC about your series, </blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br></blockquote><div><br></div><div>I don&#39;t see the reason why do you initiate IRC communication on this topic, if we have the mailing list for discussing such important issues as introducing a new target (that should be definitely visible to all participants).</div><div><br></div><div>Thanks, Aleksandar</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> <br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">I suggested Richard we could merge patches 1-4 and 7. They are almost sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS ones).<br>
<br>
Regards,<br>
<br>
Phil.<br>
<br>
</blockquote>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
  2019-10-11 15:54   ` [Qemu-devel] " Aleksandar Markovic
@ 2019-10-11 16:11     ` Alex Bennée
  2019-10-11 21:15       ` Aleksandar Markovic
  0 siblings, 1 reply; 19+ messages in thread
From: Alex Bennée @ 2019-10-11 16:11 UTC (permalink / raw)
  To: qemu-devel
  Cc: thuth, dovgaluk, richard.henderson, Michael Rolnik, imammedo,
	Philippe Mathieu-Daudé


Aleksandar Markovic <aleksandar.m.mail@gmail.com> writes:

> On Friday, October 11, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
> wrote:
>
>> Hi Michael,
>>
>> On 9/2/19 4:01 PM, Michael Rolnik wrote:
>>
>>> This series of patches adds 8bit AVR cores to QEMU.
>>> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
>>> tested yet.
>>> However I was able to execute simple code with functions. e.g fibonacci
>>> calculation.
>>> This series of patches include a non real, sample board.
>>> No fuses support yet. PC is set to 0 at reset.
>>>
>>> the patches include the following
>>> 1. just a basic 8bit AVR CPU, without instruction decoding or translation
>>> 2. CPU features which allow define the following 8bit AVR cores
>>>       avr1
>>>       avr2 avr25
>>>       avr3 avr31 avr35
>>>       avr4
>>>       avr5 avr51
>>>       avr6
>>>       xmega2 xmega4 xmega5 xmega6 xmega7
>>> 3. a definition of sample machine with SRAM, FLASH and CPU which allows
>>> to execute simple code
>>> 4. encoding for all AVR instructions
>>> 5. interrupt handling
>>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
>>> 7. a decoder which given an opcode decides what istruction it is
>>> 8. translation of AVR instruction into TCG
>>> 9. all features together
>>>
>>> [..]
>>
>>> Michael Rolnik (7):
>>>    target/avr: Add outward facing interfaces and core CPU logic
>>>    target/avr: Add instruction helpers
>>>    target/avr: Add instruction decoding
>>>    target/avr: Add instruction translation
>>>    target/avr: Add example board configuration
>>>    target/avr: Register AVR support with the rest of QEMU, the build
>>>      system, and the MAINTAINERS file
>>>    target/avr: Add tests
>>>
>>> Sarah Harris (1):
>>>    target/avr: Add limited support for USART and 16 bit timer peripherals
>>>
>>
>> Overall architecture patches look good, but I'd like some more time to
>> review the hardware patches. Unfortunately I won't have time until November.
>> There was a chat on IRC about your series,
>>
> I don't see the reason why do you initiate IRC communication on this topic,
> if we have the mailing list for discussing such important issues as
> introducing a new target (that should be definitely visible to all
> participants).

IRC is often a good way of quickly discussing something when someone is
about (often as a tangent from another discussion). I don't think there
is anything wrong with that as long as it's followed up on the mailing
list.

>
>> I suggested Richard we could merge patches 1-4 and 7. They are almost
>> sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS
>> ones).

Which is was ;-)

--
Alex Bennée


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
  2019-10-11 16:11     ` Alex Bennée
@ 2019-10-11 21:15       ` Aleksandar Markovic
  0 siblings, 0 replies; 19+ messages in thread
From: Aleksandar Markovic @ 2019-10-11 21:15 UTC (permalink / raw)
  To: Alex Bennée
  Cc: thuth, Michael Rolnik, richard.henderson, qemu-devel, dovgaluk,
	imammedo, Philippe Mathieu-Daudé

[-- Attachment #1: Type: text/plain, Size: 3593 bytes --]

On Friday, October 11, 2019, Alex Bennée <alex.bennee@linaro.org> wrote:

>
> Aleksandar Markovic <aleksandar.m.mail@gmail.com> writes:
>
> > On Friday, October 11, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
> > wrote:
> >
> >> Hi Michael,
> >>
> >> On 9/2/19 4:01 PM, Michael Rolnik wrote:
> >>
> >>> This series of patches adds 8bit AVR cores to QEMU.
> >>> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully
> >>> tested yet.
> >>> However I was able to execute simple code with functions. e.g fibonacci
> >>> calculation.
> >>> This series of patches include a non real, sample board.
> >>> No fuses support yet. PC is set to 0 at reset.
> >>>
> >>> the patches include the following
> >>> 1. just a basic 8bit AVR CPU, without instruction decoding or
> translation
> >>> 2. CPU features which allow define the following 8bit AVR cores
> >>>       avr1
> >>>       avr2 avr25
> >>>       avr3 avr31 avr35
> >>>       avr4
> >>>       avr5 avr51
> >>>       avr6
> >>>       xmega2 xmega4 xmega5 xmega6 xmega7
> >>> 3. a definition of sample machine with SRAM, FLASH and CPU which allows
> >>> to execute simple code
> >>> 4. encoding for all AVR instructions
> >>> 5. interrupt handling
> >>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
> >>> 7. a decoder which given an opcode decides what istruction it is
> >>> 8. translation of AVR instruction into TCG
> >>> 9. all features together
> >>>
> >>> [..]
> >>
> >>> Michael Rolnik (7):
> >>>    target/avr: Add outward facing interfaces and core CPU logic
> >>>    target/avr: Add instruction helpers
> >>>    target/avr: Add instruction decoding
> >>>    target/avr: Add instruction translation
> >>>    target/avr: Add example board configuration
> >>>    target/avr: Register AVR support with the rest of QEMU, the build
> >>>      system, and the MAINTAINERS file
> >>>    target/avr: Add tests
> >>>
> >>> Sarah Harris (1):
> >>>    target/avr: Add limited support for USART and 16 bit timer
> peripherals
> >>>
> >>
> >> Overall architecture patches look good, but I'd like some more time to
> >> review the hardware patches. Unfortunately I won't have time until
> November.
> >> There was a chat on IRC about your series,
> >>
> > I don't see the reason why do you initiate IRC communication on this
> topic,
> > if we have the mailing list for discussing such important issues as
> > introducing a new target (that should be definitely visible to all
> > participants).
>
> IRC is often a good way of quickly discussing something when someone is
> about (often as a tangent from another discussion). I don't think there
> is anything wrong with that as long as it's followed up on the mailing
> list.
>
>
OK, at least the series got some attention, be it on IRC or on the list. I
still find it odd that suddenly, after months and months of this series
practically sitting on the list, any suggestion couldn't first be discussed
here, so that we collectively find the best outcome. But, yes, I probably
produced much ado about nothing. I hope that this would soon result in
helping Michael complete the integration. Micheal, whatever I said
regarding patch 4, is only a suggestion - if others are fine with it, I am
fine too. Best luck to all involved! :)

Aleksandar



> >
> >> I suggested Richard we could merge patches 1-4 and 7. They are almost
> >> sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS
> >> ones).
>
> Which is was ;-)
>
> --
> Alex Bennée
>
>

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<br><br>On Friday, October 11, 2019, Alex Bennée &lt;<a href="mailto:alex.bennee@linaro.org">alex.bennee@linaro.org</a>&gt; wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
Aleksandar Markovic &lt;<a href="mailto:aleksandar.m.mail@gmail.com">aleksandar.m.mail@gmail.com</a>&gt; writes:<br>
<br>
&gt; On Friday, October 11, 2019, Philippe Mathieu-Daudé &lt;<a href="mailto:philmd@redhat.com">philmd@redhat.com</a>&gt;<br>
&gt; wrote:<br>
&gt;<br>
&gt;&gt; Hi Michael,<br>
&gt;&gt;<br>
&gt;&gt; On 9/2/19 4:01 PM, Michael Rolnik wrote:<br>
&gt;&gt;<br>
&gt;&gt;&gt; This series of patches adds 8bit AVR cores to QEMU.<br>
&gt;&gt;&gt; All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully<br>
&gt;&gt;&gt; tested yet.<br>
&gt;&gt;&gt; However I was able to execute simple code with functions. e.g fibonacci<br>
&gt;&gt;&gt; calculation.<br>
&gt;&gt;&gt; This series of patches include a non real, sample board.<br>
&gt;&gt;&gt; No fuses support yet. PC is set to 0 at reset.<br>
&gt;&gt;&gt;<br>
&gt;&gt;&gt; the patches include the following<br>
&gt;&gt;&gt; 1. just a basic 8bit AVR CPU, without instruction decoding or translation<br>
&gt;&gt;&gt; 2. CPU features which allow define the following 8bit AVR cores<br>
&gt;&gt;&gt;       avr1<br>
&gt;&gt;&gt;       avr2 avr25<br>
&gt;&gt;&gt;       avr3 avr31 avr35<br>
&gt;&gt;&gt;       avr4<br>
&gt;&gt;&gt;       avr5 avr51<br>
&gt;&gt;&gt;       avr6<br>
&gt;&gt;&gt;       xmega2 xmega4 xmega5 xmega6 xmega7<br>
&gt;&gt;&gt; 3. a definition of sample machine with SRAM, FLASH and CPU which allows<br>
&gt;&gt;&gt; to execute simple code<br>
&gt;&gt;&gt; 4. encoding for all AVR instructions<br>
&gt;&gt;&gt; 5. interrupt handling<br>
&gt;&gt;&gt; 6. helpers for IN, OUT, SLEEP, WBR &amp; unsupported instructions<br>
&gt;&gt;&gt; 7. a decoder which given an opcode decides what istruction it is<br>
&gt;&gt;&gt; 8. translation of AVR instruction into TCG<br>
&gt;&gt;&gt; 9. all features together<br>
&gt;&gt;&gt;<br>
&gt;&gt;&gt; [..]<br>
&gt;&gt;<br>
&gt;&gt;&gt; Michael Rolnik (7):<br>
&gt;&gt;&gt;    target/avr: Add outward facing interfaces and core CPU logic<br>
&gt;&gt;&gt;    target/avr: Add instruction helpers<br>
&gt;&gt;&gt;    target/avr: Add instruction decoding<br>
&gt;&gt;&gt;    target/avr: Add instruction translation<br>
&gt;&gt;&gt;    target/avr: Add example board configuration<br>
&gt;&gt;&gt;    target/avr: Register AVR support with the rest of QEMU, the build<br>
&gt;&gt;&gt;      system, and the MAINTAINERS file<br>
&gt;&gt;&gt;    target/avr: Add tests<br>
&gt;&gt;&gt;<br>
&gt;&gt;&gt; Sarah Harris (1):<br>
&gt;&gt;&gt;    target/avr: Add limited support for USART and 16 bit timer peripherals<br>
&gt;&gt;&gt;<br>
&gt;&gt;<br>
&gt;&gt; Overall architecture patches look good, but I&#39;d like some more time to<br>
&gt;&gt; review the hardware patches. Unfortunately I won&#39;t have time until November.<br>
&gt;&gt; There was a chat on IRC about your series,<br>
&gt;&gt;<br>
&gt; I don&#39;t see the reason why do you initiate IRC communication on this topic,<br>
&gt; if we have the mailing list for discussing such important issues as<br>
&gt; introducing a new target (that should be definitely visible to all<br>
&gt; participants).<br>
<br>
IRC is often a good way of quickly discussing something when someone is<br>
about (often as a tangent from another discussion). I don&#39;t think there<br>
is anything wrong with that as long as it&#39;s followed up on the mailing<br>
list.<br>
<br></blockquote><div><br></div><div>OK, at least the series got some attention, be it on IRC or on the list. I still find it odd that suddenly, after months and months of this series practically sitting on the list, any suggestion couldn&#39;t first be discussed here, so that we collectively find the best outcome. But, yes, I probably produced much ado about nothing. I hope that this would soon result in helping Michael complete the integration. Micheal, whatever I said regarding patch 4, is only a suggestion - if others are fine with it, I am fine too. Best luck to all involved! :)</div><div><br></div><div>Aleksandar</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
&gt;<br>
&gt;&gt; I suggested Richard we could merge patches 1-4 and 7. They are almost<br>
&gt;&gt; sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS<br>
&gt;&gt; ones).<br>
<br>
Which is was ;-)<br>
<br>
--<br>
Alex Bennée<br>
<br>
</blockquote>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation
  2019-10-11 14:13   ` Aleksandar Markovic
@ 2019-10-12 16:33     ` Michael Rolnik
  2019-10-12 17:47       ` Aleksandar Markovic
  0 siblings, 1 reply; 19+ messages in thread
From: Michael Rolnik @ 2019-10-12 16:33 UTC (permalink / raw)
  To: Aleksandar Markovic
  Cc: thuth, richard.henderson, qemu-devel, dovgaluk, imammedo, philmd

Hi Aleksandar.

If I break it to multiple patches, does every patch have to compile?

On Fri, Oct 11, 2019 at 5:13 PM Aleksandar Markovic
<aleksandar.m.mail@gmail.com> wrote:
>
>
>
> On Monday, September 2, 2019, Michael Rolnik <mrolnik@gmail.com> wrote:
>>
>> This includes:
>> - TCG translations for each instruction
>>
>> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
>> ---
>>  target/avr/translate.c | 2888 ++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 2888 insertions(+)
>>  create mode 100644 target/avr/translate.c
>>
>
> Hi, Michael,
>
>
> This patch is way too large. I suggest splitting it into:
>
> - register definitions
> - load instruction handling
> - store instruction handling
> - logic instruction handling
>
> etc.
>
> Thanks, Aleksandar
>
> P.S. One more hurdle with your communication on the list is that you don't use "inline responding" while replaying, please use it in future. See other messages in the mailing list how "inline responding" looks.
>
>
>
>
>>
>> diff --git a/target/avr/translate.c b/target/avr/translate.c
>> new file mode 100644
>> index 0000000000..42cb4a690c
>> --- /dev/null
>> +++ b/target/avr/translate.c
>> @@ -0,0 +1,2888 @@
>> +/*
>> + * QEMU AVR CPU
>> + *
>> + * Copyright (c) 2019 Michael Rolnik
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2.1 of the License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>> + * Lesser General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU Lesser General Public
>> + * License along with this library; if not, see
>> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qemu/qemu-print.h"
>> +#include "tcg/tcg.h"
>> +#include "cpu.h"
>> +#include "exec/exec-all.h"
>> +#include "disas/disas.h"
>> +#include "tcg-op.h"
>> +#include "exec/cpu_ldst.h"
>> +#include "exec/helper-proto.h"
>> +#include "exec/helper-gen.h"
>> +#include "exec/log.h"
>> +#include "exec/gdbstub.h"
>> +#include "exec/translator.h"
>> +
>> +/*
>> + *  Define if you want a BREAK instruction translated to a breakpoint
>> + *  Active debugging connection is assumed
>> + *  This is for
>> + *  https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
>> + *  tests
>> + */
>> +#undef BREAKPOINT_ON_BREAK
>> +
>> +static TCGv cpu_pc;
>> +
>> +static TCGv cpu_Cf;
>> +static TCGv cpu_Zf;
>> +static TCGv cpu_Nf;
>> +static TCGv cpu_Vf;
>> +static TCGv cpu_Sf;
>> +static TCGv cpu_Hf;
>> +static TCGv cpu_Tf;
>> +static TCGv cpu_If;
>> +
>> +static TCGv cpu_rampD;
>> +static TCGv cpu_rampX;
>> +static TCGv cpu_rampY;
>> +static TCGv cpu_rampZ;
>> +
>> +static TCGv cpu_r[NO_CPU_REGISTERS];
>> +static TCGv cpu_eind;
>> +static TCGv cpu_sp;
>> +
>> +static TCGv cpu_skip;
>> +
>> +static const char reg_names[NO_CPU_REGISTERS][8] = {
>> +    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
>> +    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
>> +    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
>> +    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
>> +};
>> +#define REG(x) (cpu_r[x])
>> +
>> +enum {
>> +    DISAS_EXIT   = DISAS_TARGET_0,  /* We want return to the cpu main loop.  */
>> +    DISAS_LOOKUP = DISAS_TARGET_1,  /* We have a variable condition exit.  */
>> +    DISAS_CHAIN  = DISAS_TARGET_2,  /* We have a single condition exit.  */
>> +};
>> +
>> +typedef struct DisasContext DisasContext;
>> +
>> +/* This is the state at translation time. */
>> +struct DisasContext {
>> +    TranslationBlock *tb;
>> +
>> +    CPUAVRState *env;
>> +    CPUState *cs;
>> +
>> +    target_long npc;
>> +    uint32_t opcode;
>> +
>> +    /* Routine used to access memory */
>> +    int memidx;
>> +    int bstate;
>> +    int singlestep;
>> +
>> +    TCGv skip_var0;
>> +    TCGv skip_var1;
>> +    TCGCond skip_cond;
>> +    bool free_skip_var0;
>> +};
>> +
>> +static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); }
>> +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); }
>> +static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) * 2; }
>> +static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; }
>> +
>> +static uint16_t next_word(DisasContext *ctx)
>> +{
>> +    return cpu_lduw_code(ctx->env, ctx->npc++ * 2);
>> +}
>> +
>> +static int append_16(DisasContext *ctx, int x)
>> +{
>> +    return x << 16 | next_word(ctx);
>> +}
>> +
>> +static bool decode_insn(DisasContext *ctx, uint16_t insn);
>> +#include "decode_insn.inc.c"
>> +
>> +static bool avr_have_feature(DisasContext *ctx, int feature)
>> +{
>> +    if (!avr_feature(ctx->env, feature)) {
>> +        gen_helper_unsupported(cpu_env);
>> +        ctx->bstate = DISAS_NORETURN;
>> +        return false;
>> +    }
>> +    return true;
>> +}
>> +
>> +static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
>> +{
>> +    TranslationBlock *tb = ctx->tb;
>> +
>> +    if (ctx->singlestep == 0) {
>> +        tcg_gen_goto_tb(n);
>> +        tcg_gen_movi_i32(cpu_pc, dest);
>> +        tcg_gen_exit_tb(tb, n);
>> +    } else {
>> +        tcg_gen_movi_i32(cpu_pc, dest);
>> +        gen_helper_debug(cpu_env);
>> +        tcg_gen_exit_tb(NULL, 0);
>> +    }
>> +    ctx->bstate = DISAS_NORETURN;
>> +}
>> +
>> +#include "exec/gen-icount.h"
>> +
>> +static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)
>> +{
>> +    TCGv t1 = tcg_temp_new_i32();
>> +    TCGv t2 = tcg_temp_new_i32();
>> +    TCGv t3 = tcg_temp_new_i32();
>> +
>> +    tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */
>> +    tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */
>> +    tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */
>> +    tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */
>> +    tcg_gen_or_tl(t1, t1, t3);
>> +
>> +    tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */
>> +    tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */
>> +    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
>> +
>> +    tcg_temp_free_i32(t3);
>> +    tcg_temp_free_i32(t2);
>> +    tcg_temp_free_i32(t1);
>> +}
>> +
>> +static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr)
>> +{
>> +    TCGv t1 = tcg_temp_new_i32();
>> +    TCGv t2 = tcg_temp_new_i32();
>> +
>> +    /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R = (Rd ^ R) & ~(Rd ^ Rr) */
>> +    tcg_gen_xor_tl(t1, Rd, R);
>> +    tcg_gen_xor_tl(t2, Rd, Rr);
>> +    tcg_gen_andc_tl(t1, t1, t2);
>> +
>> +    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
>> +
>> +    tcg_temp_free_i32(t2);
>> +    tcg_temp_free_i32(t1);
>> +}
>> +
>> +static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)
>> +{
>> +    TCGv t1 = tcg_temp_new_i32();
>> +    TCGv t2 = tcg_temp_new_i32();
>> +    TCGv t3 = tcg_temp_new_i32();
>> +
>> +    /* Cf & Hf */
>> +    tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */
>> +    tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */
>> +    tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */
>> +    tcg_gen_and_tl(t3, t3, R);
>> +    tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
>> +    tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */
>> +    tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */
>> +    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
>> +
>> +    tcg_temp_free_i32(t3);
>> +    tcg_temp_free_i32(t2);
>> +    tcg_temp_free_i32(t1);
>> +}
>> +
>> +static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr)
>> +{
>> +    TCGv t1 = tcg_temp_new_i32();
>> +    TCGv t2 = tcg_temp_new_i32();
>> +
>> +    /* Vf */
>> +    /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R = (Rd ^ R) & (Rd ^ R) */
>> +    tcg_gen_xor_tl(t1, Rd, R);
>> +    tcg_gen_xor_tl(t2, Rd, Rr);
>> +    tcg_gen_and_tl(t1, t1, t2);
>> +    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
>> +
>> +    tcg_temp_free_i32(t2);
>> +    tcg_temp_free_i32(t1);
>> +}
>> +
>> +static void gen_rshift_ZNVSf(TCGv R)
>> +{
>> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
>> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
>> +    tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf);
>> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
>> +}
>> +
>> +static void gen_NSf(TCGv R)
>> +{
>> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
>> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
>> +}
>> +
>> +static void gen_ZNSf(TCGv R)
>> +{
>> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
>> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
>> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
>> +}
>> +
>> +static void gen_push_ret(DisasContext *ctx, int ret)
>> +{
>> +    if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
>> +
>> +        TCGv t0 = tcg_const_i32((ret & 0x0000ff));
>> +
>> +        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
>> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
>> +
>> +        tcg_temp_free_i32(t0);
>> +    } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
>> +
>> +        TCGv t0 = tcg_const_i32((ret & 0x00ffff));
>> +
>> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
>> +        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
>> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
>> +
>> +        tcg_temp_free_i32(t0);
>> +
>> +    } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
>> +
>> +        TCGv lo = tcg_const_i32((ret & 0x0000ff));
>> +        TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
>> +
>> +        tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
>> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
>> +        tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
>> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
>> +
>> +        tcg_temp_free_i32(lo);
>> +        tcg_temp_free_i32(hi);
>> +    }
>> +}
>> +
>> +static void gen_pop_ret(DisasContext *ctx, TCGv ret)
>> +{
>> +    if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
>> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
>> +        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
>> +    } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
>> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
>> +        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
>> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
>> +    } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
>> +        TCGv lo = tcg_temp_new_i32();
>> +        TCGv hi = tcg_temp_new_i32();
>> +
>> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
>> +        tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
>> +
>> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
>> +        tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
>> +
>> +        tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
>> +
>> +        tcg_temp_free_i32(lo);
>> +        tcg_temp_free_i32(hi);
>> +    }
>> +}
>> +
>> +static void gen_jmp_ez(DisasContext *ctx)
>> +{
>> +    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
>> +    tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind);
>> +    ctx->bstate = DISAS_LOOKUP;
>> +}
>> +
>> +static void gen_jmp_z(DisasContext *ctx)
>> +{
>> +    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
>> +    ctx->bstate = DISAS_LOOKUP;
>> +}
>> +
>> +/*
>> + *  in the gen_set_addr & gen_get_addr functions
>> + *  H assumed to be in 0x00ff0000 format
>> + *  M assumed to be in 0x000000ff format
>> + *  L assumed to be in 0x000000ff format
>> + */
>> +static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L)
>> +{
>> +
>> +    tcg_gen_andi_tl(L, addr, 0x000000ff);
>> +
>> +    tcg_gen_andi_tl(M, addr, 0x0000ff00);
>> +    tcg_gen_shri_tl(M, M, 8);
>> +
>> +    tcg_gen_andi_tl(H, addr, 0x00ff0000);
>> +}
>> +
>> +static void gen_set_xaddr(TCGv addr)
>> +{
>> +    gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]);
>> +}
>> +
>> +static void gen_set_yaddr(TCGv addr)
>> +{
>> +    gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]);
>> +}
>> +
>> +static void gen_set_zaddr(TCGv addr)
>> +{
>> +    gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]);
>> +}
>> +
>> +static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L)
>> +{
>> +    TCGv addr = tcg_temp_new_i32();
>> +
>> +    tcg_gen_deposit_tl(addr, M, H, 8, 8);
>> +    tcg_gen_deposit_tl(addr, L, addr, 8, 16);
>> +
>> +    return addr;
>> +}
>> +
>> +static TCGv gen_get_xaddr(void)
>> +{
>> +    return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]);
>> +}
>> +
>> +static TCGv gen_get_yaddr(void)
>> +{
>> +    return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]);
>> +}
>> +
>> +static TCGv gen_get_zaddr(void)
>> +{
>> +    return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]);
>> +}
>> +
>> +/*
>> + *  Adds two registers and the contents of the C Flag and places the result in
>> + *  the destination register Rd.
>> + */
>> +static bool trans_ADC(DisasContext *ctx, arg_ADC *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    /* op */
>> +    tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */
>> +    tcg_gen_add_tl(R, R, cpu_Cf);
>> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
>> +
>> +    gen_add_CHf(R, Rd, Rr);
>> +    gen_add_Vf(R, Rd, Rr);
>> +    gen_ZNSf(R);
>> +
>> +    /* R */
>> +    tcg_gen_mov_tl(Rd, R);
>> +
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Adds two registers without the C Flag and places the result in the
>> + *  destination register Rd.
>> + */
>> +static bool trans_ADD(DisasContext *ctx, arg_ADD *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    /* op */
>> +    tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */
>> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
>> +
>> +    gen_add_CHf(R, Rd, Rr);
>> +    gen_add_Vf(R, Rd, Rr);
>> +    gen_ZNSf(R);
>> +
>> +    /* R */
>> +    tcg_gen_mov_tl(Rd, R);
>> +
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Adds an immediate value (0 - 63) to a register pair and places the result
>> + *  in the register pair. This instruction operates on the upper four register
>> + *  pairs, and is well suited for operations on the pointer registers.  This
>> + *  instruction is not available in all devices. Refer to the device specific
>> + *  instruction set summary.
>> + */
>> +static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv RdL = cpu_r[a->rd];
>> +    TCGv RdH = cpu_r[a->rd + 1];
>> +    int Imm = (a->imm);
>> +    TCGv R = tcg_temp_new_i32();
>> +    TCGv Rd = tcg_temp_new_i32();
>> +
>> +    /* op */
>> +    tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */
>> +    tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */
>> +    tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */
>> +
>> +    /* Cf */
>> +    tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */
>> +    tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15);
>> +
>> +    /* Vf */
>> +    tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R & ~Rd */
>> +    tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15);
>> +
>> +    /* Zf */
>> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
>> +
>> +    /* Nf */
>> +    tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */
>> +
>> +    /* Sf */
>> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */
>> +
>> +    /* R */
>> +    tcg_gen_andi_tl(RdL, R, 0xff);
>> +    tcg_gen_shri_tl(RdH, R, 8);
>> +
>> +    tcg_temp_free_i32(Rd);
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Performs the logical AND between the contents of register Rd and register
>> + *  Rr and places the result in the destination register Rd.
>> + */
>> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    /* op */
>> +    tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
>> +
>> +    /* Vf */
>> +    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
>> +
>> +    /* Zf */
>> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
>> +
>> +    gen_ZNSf(R);
>> +
>> +    /* R */
>> +    tcg_gen_mov_tl(Rd, R);
>> +
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Performs the logical AND between the contents of register Rd and a constant
>> + *  and places the result in the destination register Rd.
>> + */
>> +static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    int Imm = (a->imm);
>> +
>> +    /* op */
>> +    tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd & Imm */
>> +
>> +    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
>> +    gen_ZNSf(Rd);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0
>> + *  is loaded into the C Flag of the SREG. This operation effectively divides a
>> + *  signed value by two without changing its sign. The Carry Flag can be used to
>> + *  round the result.
>> + */
>> +static bool trans_ASR(DisasContext *ctx, arg_ASR *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv t0 = tcg_temp_new_i32();
>> +
>> +    /* Cf */
>> +    tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */
>> +
>> +    /* op */
>> +    tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */
>> +    tcg_gen_shri_tl(Rd, Rd, 1);
>> +    tcg_gen_or_tl(Rd, Rd, t0);
>> +
>> +    gen_rshift_ZNVSf(Rd);
>> +
>> +    tcg_temp_free_i32(t0);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Clears a single Flag in SREG.
>> + */
>> +static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
>> +{
>> +    switch (a->bit) {
>> +    case 0x00:
>> +        tcg_gen_movi_tl(cpu_Cf, 0x00);
>> +        break;
>> +    case 0x01:
>> +        tcg_gen_movi_tl(cpu_Zf, 0x01);
>> +        break;
>> +    case 0x02:
>> +        tcg_gen_movi_tl(cpu_Nf, 0x00);
>> +        break;
>> +    case 0x03:
>> +        tcg_gen_movi_tl(cpu_Vf, 0x00);
>> +        break;
>> +    case 0x04:
>> +        tcg_gen_movi_tl(cpu_Sf, 0x00);
>> +        break;
>> +    case 0x05:
>> +        tcg_gen_movi_tl(cpu_Hf, 0x00);
>> +        break;
>> +    case 0x06:
>> +        tcg_gen_movi_tl(cpu_Tf, 0x00);
>> +        break;
>> +    case 0x07:
>> +        tcg_gen_movi_tl(cpu_If, 0x00);
>> +        break;
>> +    }
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Copies the T Flag in the SREG (Status Register) to bit b in register Rd.
>> + */
>> +static bool trans_BLD(DisasContext *ctx, arg_BLD *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv t1 = tcg_temp_new_i32();
>> +
>> +    tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */
>> +    tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */
>> +    tcg_gen_or_tl(Rd, Rd, t1);
>> +
>> +    tcg_temp_free_i32(t1);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Conditional relative branch. Tests a single bit in SREG and branches
>> + *  relatively to PC if the bit is cleared. This instruction branches relatively
>> + *  to PC in either direction (PC - 63 < = destination <= PC + 64). The
>> + *  parameter k is the offset from PC and is represented in two's complement
>> + *  form.
>> + */
>> +static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a)
>> +{
>> +    TCGLabel *not_taken = gen_new_label();
>> +    TCGCond cond = TCG_COND_EQ;
>> +    TCGv var;
>> +
>> +    switch (a->bit) {
>> +    case 0x00:
>> +        var = cpu_Cf;
>> +        break;
>> +    case 0x01:
>> +        cond = TCG_COND_NE;
>> +        var = cpu_Zf;
>> +        break;
>> +    case 0x02:
>> +        var = cpu_Nf;
>> +        break;
>> +    case 0x03:
>> +        var = cpu_Vf;
>> +        break;
>> +    case 0x04:
>> +        var = cpu_Sf;
>> +        break;
>> +    case 0x05:
>> +        var = cpu_Hf;
>> +        break;
>> +    case 0x06:
>> +        var = cpu_Tf;
>> +        break;
>> +    case 0x07:
>> +        var = cpu_If;
>> +        break;
>> +    default:
>> +        g_assert_not_reached();
>> +    }
>> +
>> +    tcg_gen_brcondi_i32(tcg_invert_cond(cond), var, 0, not_taken);
>> +    gen_goto_tb(ctx, 0, ctx->npc + a->imm);
>> +    gen_set_label(not_taken);
>> +
>> +    ctx->bstate = DISAS_CHAIN;
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Conditional relative branch. Tests a single bit in SREG and branches
>> + *  relatively to PC if the bit is set. This instruction branches relatively to
>> + *  PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k
>> + *  is the offset from PC and is represented in two's complement form.
>> + */
>> +static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a)
>> +{
>> +    TCGLabel *not_taken = gen_new_label();
>> +    TCGCond cond = TCG_COND_NE;
>> +    TCGv var;
>> +
>> +    switch (a->bit) {
>> +    case 0x00:
>> +        var = cpu_Cf;
>> +        break;
>> +    case 0x01:
>> +        cond = TCG_COND_EQ;
>> +        var = cpu_Zf;
>> +        break;
>> +    case 0x02:
>> +        var = cpu_Nf;
>> +        break;
>> +    case 0x03:
>> +        var = cpu_Vf;
>> +        break;
>> +    case 0x04:
>> +        var = cpu_Sf;
>> +        break;
>> +    case 0x05:
>> +        var = cpu_Hf;
>> +        break;
>> +    case 0x06:
>> +        var = cpu_Tf;
>> +        break;
>> +    case 0x07:
>> +        var = cpu_If;
>> +        break;
>> +    default:
>> +        g_assert_not_reached();
>> +    }
>> +
>> +    tcg_gen_brcondi_i32(tcg_invert_cond(cond), var, 0, not_taken);
>> +    gen_goto_tb(ctx, 0, ctx->npc + a->imm);
>> +    gen_set_label(not_taken);
>> +
>> +    ctx->bstate = DISAS_CHAIN;
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Sets a single Flag or bit in SREG.
>> + */
>> +static bool trans_BSET(DisasContext *ctx, arg_BSET *a)
>> +{
>> +    switch (a->bit) {
>> +    case 0x00:
>> +        tcg_gen_movi_tl(cpu_Cf, 0x01);
>> +        break;
>> +    case 0x01:
>> +        tcg_gen_movi_tl(cpu_Zf, 0x00);
>> +        break;
>> +    case 0x02:
>> +        tcg_gen_movi_tl(cpu_Nf, 0x01);
>> +        break;
>> +    case 0x03:
>> +        tcg_gen_movi_tl(cpu_Vf, 0x01);
>> +        break;
>> +    case 0x04:
>> +        tcg_gen_movi_tl(cpu_Sf, 0x01);
>> +        break;
>> +    case 0x05:
>> +        tcg_gen_movi_tl(cpu_Hf, 0x01);
>> +        break;
>> +    case 0x06:
>> +        tcg_gen_movi_tl(cpu_Tf, 0x01);
>> +        break;
>> +    case 0x07:
>> +        tcg_gen_movi_tl(cpu_If, 0x01);
>> +        break;
>> +    }
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  The BREAK instruction is used by the On-chip Debug system, and is
>> + *  normally not used in the application software. When the BREAK instruction is
>> + *  executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
>> + *  Debugger access to internal resources.  If any Lock bits are set, or either
>> + *  the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
>> + *  instruction as a NOP and will not enter the Stopped mode.  This instruction
>> + *  is not available in all devices. Refer to the device specific instruction
>> + *  set summary.
>> + */
>> +static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
>> +        return true;
>> +    }
>> +
>> +#ifdef BREAKPOINT_ON_BREAK
>> +    tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
>> +    gen_helper_debug(cpu_env);
>> +    ctx->bstate = DISAS_EXIT;
>> +#else
>> +    /* NOP */
>> +#endif
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Stores bit b from Rd to the T Flag in SREG (Status Register).
>> + */
>> +static bool trans_BST(DisasContext *ctx, arg_BST *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +
>> +    tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit);
>> +    tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Calls to a subroutine within the entire Program memory. The return
>> + *  address (to the instruction after the CALL) will be stored onto the Stack.
>> + *  (See also RCALL). The Stack Pointer uses a post-decrement scheme during
>> + *  CALL.  This instruction is not available in all devices. Refer to the device
>> + *  specific instruction set summary.
>> + */
>> +static bool trans_CALL(DisasContext *ctx, arg_CALL *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
>> +        return true;
>> +    }
>> +
>> +    int Imm = a->imm;
>> +    int ret = ctx->npc;
>> +
>> +    gen_push_ret(ctx, ret);
>> +    gen_goto_tb(ctx, 0, Imm);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Clears a specified bit in an I/O Register. This instruction operates on
>> + *  the lower 32 I/O Registers -- addresses 0-31.
>> + */
>> +static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
>> +{
>> +    TCGv data = tcg_temp_new_i32();
>> +    TCGv port = tcg_const_i32(a->reg);
>> +
>> +    gen_helper_inb(data, cpu_env, port);
>> +    tcg_gen_andi_tl(data, data, ~(1 << a->bit));
>> +    gen_helper_outb(cpu_env, port, data);
>> +
>> +    tcg_temp_free_i32(data);
>> +    tcg_temp_free_i32(port);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Clears the specified bits in register Rd. Performs the logical AND
>> + *  between the contents of register Rd and the complement of the constant mask
>> + *  K. The result will be placed in register Rd.
>> + */
>> +static bool trans_COM(DisasContext *ctx, arg_COM *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    tcg_gen_xori_tl(Rd, Rd, 0xff);
>> +
>> +    tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */
>> +    tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
>> +    gen_ZNSf(Rd);
>> +
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs a compare between two registers Rd and Rr.
>> + *  None of the registers are changed. All conditional branches can be used
>> + *  after this instruction.
>> + */
>> +static bool trans_CP(DisasContext *ctx, arg_CP *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    /* op */
>> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
>> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
>> +
>> +    gen_sub_CHf(R, Rd, Rr);
>> +    gen_sub_Vf(R, Rd, Rr);
>> +    gen_ZNSf(R);
>> +
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs a compare between two registers Rd and Rr and
>> + *  also takes into account the previous carry. None of the registers are
>> + *  changed. All conditional branches can be used after this instruction.
>> + */
>> +static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    /* op */
>> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
>> +    tcg_gen_sub_tl(R, R, cpu_Cf);
>> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
>> +
>> +    gen_sub_CHf(R, Rd, Rr);
>> +    gen_sub_Vf(R, Rd, Rr);
>> +    gen_NSf(R);
>> +
>> +    /*
>> +     * Previous value remains unchanged when the result is zero;
>> +     * cleared otherwise.
>> +     */
>> +    tcg_gen_or_tl(cpu_Zf, cpu_Zf, R);
>> +
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs a compare between register Rd and a constant.
>> + *  The register is not changed. All conditional branches can be used after this
>> + *  instruction.
>> + */
>> +static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    int Imm = a->imm;
>> +    TCGv Rr = tcg_const_i32(Imm);
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    /* op */
>> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
>> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
>> +
>> +    gen_sub_CHf(R, Rd, Rr);
>> +    gen_sub_Vf(R, Rd, Rr);
>> +    gen_ZNSf(R);
>> +
>> +    tcg_temp_free_i32(R);
>> +    tcg_temp_free_i32(Rr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs a compare between two registers Rd and Rr, and
>> + *  skips the next instruction if Rd = Rr.
>> + */
>> +static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a)
>> +{
>> +    ctx->skip_cond = TCG_COND_EQ;
>> +    ctx->skip_var0 = cpu_r[a->rd];
>> +    ctx->skip_var1 = cpu_r[a->rr];
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Subtracts one -1- from the contents of register Rd and places the result
>> + *  in the destination register Rd.  The C Flag in SREG is not affected by the
>> + *  operation, thus allowing the DEC instruction to be used on a loop counter in
>> + *  multiple-precision computations.  When operating on unsigned values, only
>> + *  BREQ and BRNE branches can be expected to perform consistently.  When
>> + *  operating on two's complement values, all signed branches are available.
>> + */
>> +static bool trans_DEC(DisasContext *ctx, arg_DEC *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +
>> +    tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */
>> +    tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */
>> +
>> +    /* cpu_Vf = Rd == 0x7f */
>> +    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f);
>> +    gen_ZNSf(Rd);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  The module is an instruction set extension to the AVR CPU, performing
>> + *  DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in
>> + *  the CPU register file, registers R0-R7, where LSB of data is placed in LSB
>> + *  of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including
>> + *  parity bits) is placed in registers R8- R15, organized in the register file
>> + *  with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES
>> + *  instruction performs one round in the DES algorithm. Sixteen rounds must be
>> + *  executed in increasing order to form the correct DES ciphertext or
>> + *  plaintext. Intermediate results are stored in the register file (R0-R15)
>> + *  after each DES instruction. The instruction's operand (K) determines which
>> + *  round is executed, and the half carry flag (H) determines whether encryption
>> + *  or decryption is performed.  The DES algorithm is described in
>> + *  "Specifications for the Data Encryption Standard" (Federal Information
>> + *  Processing Standards Publication 46). Intermediate results in this
>> + *  implementation differ from the standard because the initial permutation and
>> + *  the inverse initial permutation are performed each iteration. This does not
>> + *  affect the result in the final ciphertext or plaintext, but reduces
>> + *  execution time.
>> + */
>> +static bool trans_DES(DisasContext *ctx, arg_DES *a)
>> +{
>> +    /* TODO */
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_DES)) {
>> +        return true;
>> +    }
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Indirect call of a subroutine pointed to by the Z (16 bits) Pointer
>> + *  Register in the Register File and the EIND Register in the I/O space. This
>> + *  instruction allows for indirect calls to the entire 4M (words) Program
>> + *  memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme
>> + *  during EICALL.  This instruction is not available in all devices. Refer to
>> + *  the device specific instruction set summary.
>> + */
>> +static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
>> +        return true;
>> +    }
>> +
>> +    int ret = ctx->npc;
>> +
>> +    gen_push_ret(ctx, ret);
>> +    gen_jmp_ez(ctx);
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
>> + *  Register in the Register File and the EIND Register in the I/O space. This
>> + *  instruction allows for indirect jumps to the entire 4M (words) Program
>> + *  memory space. See also IJMP.  This instruction is not available in all
>> + *  devices. Refer to the device specific instruction set summary.
>> + */
>> +static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
>> +        return true;
>> +    }
>> +
>> +    gen_jmp_ez(ctx);
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Loads one byte pointed to by the Z-register and the RAMPZ Register in
>> + *  the I/O space, and places this byte in the destination register Rd. This
>> + *  instruction features a 100% space effective constant initialization or
>> + *  constant data fetch. The Program memory is organized in 16-bit words while
>> + *  the Z-pointer is a byte address. Thus, the least significant bit of the
>> + *  Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This
>> + *  instruction can address the entire Program memory space. The Z-pointer
>> + *  Register can either be left unchanged by the operation, or it can be
>> + *  incremented. The incrementation applies to the entire 24-bit concatenation
>> + *  of the RAMPZ and Z-pointer Registers.  Devices with Self-Programming
>> + *  capability can use the ELPM instruction to read the Fuse and Lock bit value.
>> + *  Refer to the device documentation for a detailed description.  This
>> + *  instruction is not available in all devices. Refer to the device specific
>> + *  instruction set summary.
>> + */
>> +static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rd = cpu_r[0];
>> +    TCGv addr = gen_get_zaddr();
>> +
>> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_zaddr();
>> +
>> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_zaddr();
>> +
>> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
>> +
>> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
>> +
>> +    gen_set_zaddr(addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Performs the logical EOR between the contents of register Rd and
>> + *  register Rr and places the result in the destination register Rd.
>> + */
>> +static bool trans_EOR(DisasContext *ctx, arg_EOR *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +
>> +    tcg_gen_xor_tl(Rd, Rd, Rr);
>> +
>> +    tcg_gen_movi_tl(cpu_Vf, 0);
>> +    gen_ZNSf(Rd);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs 8-bit x 8-bit -> 16-bit unsigned
>> + *  multiplication and shifts the result one bit left.
>> + */
>> +static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv R0 = cpu_r[0];
>> +    TCGv R1 = cpu_r[1];
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */
>> +    tcg_gen_shli_tl(R, R, 1);
>> +
>> +    tcg_gen_andi_tl(R0, R, 0xff);
>> +    tcg_gen_shri_tl(R1, R, 8);
>> +    tcg_gen_andi_tl(R1, R1, 0xff);
>> +
>> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
>> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
>> +
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
>> + *  and shifts the result one bit left.
>> + */
>> +static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv R0 = cpu_r[0];
>> +    TCGv R1 = cpu_r[1];
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +    TCGv t0 = tcg_temp_new_i32();
>> +    TCGv t1 = tcg_temp_new_i32();
>> +
>> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
>> +    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */
>> +    tcg_gen_mul_tl(R, t0, t1); /* R = Rd *Rr */
>> +    tcg_gen_shli_tl(R, R, 1);
>> +
>> +    tcg_gen_andi_tl(R0, R, 0xff);
>> +    tcg_gen_shri_tl(R1, R, 8);
>> +    tcg_gen_andi_tl(R1, R1, 0xff);
>> +
>> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
>> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
>> +
>> +    tcg_temp_free_i32(t1);
>> +    tcg_temp_free_i32(t0);
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
>> + *  and shifts the result one bit left.
>> + */
>> +static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv R0 = cpu_r[0];
>> +    TCGv R1 = cpu_r[1];
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +    TCGv t0 = tcg_temp_new_i32();
>> +
>> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
>> +    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */
>> +    tcg_gen_shli_tl(R, R, 1);
>> +
>> +    tcg_gen_andi_tl(R0, R, 0xff);
>> +    tcg_gen_shri_tl(R1, R, 8);
>> +    tcg_gen_andi_tl(R1, R1, 0xff);
>> +
>> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
>> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
>> +
>> +    tcg_temp_free_i32(t0);
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Calls to a subroutine within the entire 4M (words) Program memory. The
>> + *  return address (to the instruction after the CALL) will be stored onto the
>> + *  Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during
>> + *  CALL.  This instruction is not available in all devices. Refer to the device
>> + *  specific instruction set summary.
>> + */
>> +static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
>> +        return true;
>> +    }
>> +
>> +    int ret = ctx->npc;
>> +
>> +    gen_push_ret(ctx, ret);
>> +    gen_jmp_z(ctx);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
>> + *  Register in the Register File. The Z-pointer Register is 16 bits wide and
>> + *  allows jump within the lowest 64K words (128KB) section of Program memory.
>> + *  This instruction is not available in all devices. Refer to the device
>> + *  specific instruction set summary.
>> + */
>> +static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
>> +        return true;
>> +    }
>> +
>> +    gen_jmp_z(ctx);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Loads data from the I/O Space (Ports, Timers, Configuration Registers,
>> + *  etc.) into register Rd in the Register File.
>> + */
>> +static bool trans_IN(DisasContext *ctx, arg_IN *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv port = tcg_const_i32(a->imm);
>> +
>> +    gen_helper_inb(Rd, cpu_env, port);
>> +
>> +    tcg_temp_free_i32(port);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Adds one -1- to the contents of register Rd and places the result in the
>> + *  destination register Rd.  The C Flag in SREG is not affected by the
>> + *  operation, thus allowing the INC instruction to be used on a loop counter in
>> + *  multiple-precision computations.  When operating on unsigned numbers, only
>> + *  BREQ and BRNE branches can be expected to perform consistently. When
>> + *  operating on two's complement values, all signed branches are available.
>> + */
>> +static bool trans_INC(DisasContext *ctx, arg_INC *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +
>> +    tcg_gen_addi_tl(Rd, Rd, 1);
>> +    tcg_gen_andi_tl(Rd, Rd, 0xff);
>> +
>> +    /* cpu_Vf = Rd == 0x80 */
>> +    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80);
>> +    gen_ZNSf(Rd);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Jump to an address within the entire 4M (words) Program memory. See also
>> + *  RJMP.  This instruction is not available in all devices. Refer to the device
>> + *  specific instruction set summary.0
>> + */
>> +static bool trans_JMP(DisasContext *ctx, arg_JMP *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
>> +        return true;
>> +    }
>> +
>> +    gen_goto_tb(ctx, 0, a->imm);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Load one byte indirect from data space to register and stores an clear
>> + *  the bits in data space specified by the register. The instruction can only
>> + *  be used towards internal SRAM.  The data location is pointed to by the Z (16
>> + *  bits) Pointer Register in the Register File. Memory access is limited to the
>> + *  current data segment of 64KB. To access another data segment in devices with
>> + *  more than 64KB data space, the RAMPZ in register in the I/O area has to be
>> + *  changed.  The Z-pointer Register is left unchanged by the operation. This
>> + *  instruction is especially suited for clearing status bits stored in SRAM.
>> + */
>> +static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
>> +{
>> +    if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
>> +        gen_helper_fullwr(cpu_env, data, addr);
>> +    } else {
>> +        tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */
>> +    }
>> +}
>> +
>> +static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
>> +{
>> +    if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
>> +        gen_helper_fullrd(data, cpu_env, addr);
>> +    } else {
>> +        tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */
>> +    }
>> +}
>> +
>> +static bool trans_LAC(DisasContext *ctx, arg_LAC *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rr = cpu_r[a->rd];
>> +    TCGv addr = gen_get_zaddr();
>> +    TCGv t0 = tcg_temp_new_i32();
>> +    TCGv t1 = tcg_temp_new_i32();
>> +
>> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
>> +        /* t1 = t0 & (0xff - Rr) = t0 and ~Rr */
>> +    tcg_gen_andc_tl(t1, t0, Rr);
>> +
>> +    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */
>> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
>> +
>> +    tcg_temp_free_i32(t1);
>> +    tcg_temp_free_i32(t0);
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Load one byte indirect from data space to register and set bits in data
>> + *  space specified by the register. The instruction can only be used towards
>> + *  internal SRAM.  The data location is pointed to by the Z (16 bits) Pointer
>> + *  Register in the Register File. Memory access is limited to the current data
>> + *  segment of 64KB. To access another data segment in devices with more than
>> + *  64KB data space, the RAMPZ in register in the I/O area has to be changed.
>> + *  The Z-pointer Register is left unchanged by the operation. This instruction
>> + *  is especially suited for setting status bits stored in SRAM.
>> + */
>> +static bool trans_LAS(DisasContext *ctx, arg_LAS *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rr = cpu_r[a->rd];
>> +    TCGv addr = gen_get_zaddr();
>> +    TCGv t0 = tcg_temp_new_i32();
>> +    TCGv t1 = tcg_temp_new_i32();
>> +
>> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
>> +    tcg_gen_or_tl(t1, t0, Rr);
>> +
>> +    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */
>> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
>> +
>> +    tcg_temp_free_i32(t1);
>> +    tcg_temp_free_i32(t0);
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Load one byte indirect from data space to register and toggles bits in
>> + *  the data space specified by the register.  The instruction can only be used
>> + *  towards SRAM.  The data location is pointed to by the Z (16 bits) Pointer
>> + *  Register in the Register File. Memory access is limited to the current data
>> + *  segment of 64KB. To access another data segment in devices with more than
>> + *  64KB data space, the RAMPZ in register in the I/O area has to be changed.
>> + *  The Z-pointer Register is left unchanged by the operation. This instruction
>> + *  is especially suited for changing status bits stored in SRAM.
>> + */
>> +static bool trans_LAT(DisasContext *ctx, arg_LAT *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_zaddr();
>> +    TCGv t0 = tcg_temp_new_i32();
>> +    TCGv t1 = tcg_temp_new_i32();
>> +
>> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
>> +    tcg_gen_xor_tl(t1, t0, Rd);
>> +
>> +    tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */
>> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
>> +
>> +    tcg_temp_free_i32(t1);
>> +    tcg_temp_free_i32(t0);
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Loads one byte indirect from the data space to a register. For parts
>> + *  with SRAM, the data space consists of the Register File, I/O memory and
>> + *  internal SRAM (and external SRAM if applicable). For parts without SRAM, the
>> + *  data space consists of the Register File only. In some parts the Flash
>> + *  Memory has been mapped to the data space and can be read using this command.
>> + *  The EEPROM has a separate address space.  The data location is pointed to by
>> + *  the X (16 bits) Pointer Register in the Register File. Memory access is
>> + *  limited to the current data segment of 64KB. To access another data segment
>> + *  in devices with more than 64KB data space, the RAMPX in register in the I/O
>> + *  area has to be changed.  The X-pointer Register can either be left unchanged
>> + *  by the operation, or it can be post-incremented or predecremented.  These
>> + *  features are especially suited for accessing arrays, tables, and Stack
>> + *  Pointer usage of the X-pointer Register. Note that only the low byte of the
>> + *  X-pointer is updated in devices with no more than 256 bytes data space. For
>> + *  such devices, the high byte of the pointer is not used by this instruction
>> + *  and can be used for other purposes. The RAMPX Register in the I/O area is
>> + *  updated in parts with more than 64KB data space or more than 64KB Program
>> + *  memory, and the increment/decrement is added to the entire 24-bit address on
>> + *  such devices.  Not all variants of this instruction is available in all
>> + *  devices. Refer to the device specific instruction set summary.  In the
>> + *  Reduced Core tinyAVR the LD instruction can be used to achieve the same
>> + *  operation as LPM since the program memory is mapped to the data memory
>> + *  space.
>> + */
>> +static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_xaddr();
>> +
>> +    gen_data_load(ctx, Rd, addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_xaddr();
>> +
>> +    gen_data_load(ctx, Rd, addr);
>> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
>> +
>> +    gen_set_xaddr(addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_xaddr();
>> +
>> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
>> +    gen_data_load(ctx, Rd, addr);
>> +    gen_set_xaddr(addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Loads one byte indirect with or without displacement from the data space
>> + *  to a register. For parts with SRAM, the data space consists of the Register
>> + *  File, I/O memory and internal SRAM (and external SRAM if applicable). For
>> + *  parts without SRAM, the data space consists of the Register File only. In
>> + *  some parts the Flash Memory has been mapped to the data space and can be
>> + *  read using this command. The EEPROM has a separate address space.  The data
>> + *  location is pointed to by the Y (16 bits) Pointer Register in the Register
>> + *  File. Memory access is limited to the current data segment of 64KB. To
>> + *  access another data segment in devices with more than 64KB data space, the
>> + *  RAMPY in register in the I/O area has to be changed.  The Y-pointer Register
>> + *  can either be left unchanged by the operation, or it can be post-incremented
>> + *  or predecremented.  These features are especially suited for accessing
>> + *  arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that
>> + *  only the low byte of the Y-pointer is updated in devices with no more than
>> + *  256 bytes data space. For such devices, the high byte of the pointer is not
>> + *  used by this instruction and can be used for other purposes. The RAMPY
>> + *  Register in the I/O area is updated in parts with more than 64KB data space
>> + *  or more than 64KB Program memory, and the increment/decrement/displacement
>> + *  is added to the entire 24-bit address on such devices.  Not all variants of
>> + *  this instruction is available in all devices. Refer to the device specific
>> + *  instruction set summary.  In the Reduced Core tinyAVR the LD instruction can
>> + *  be used to achieve the same operation as LPM since the program memory is
>> + *  mapped to the data memory space.
>> + */
>> +static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_yaddr();
>> +
>> +    gen_data_load(ctx, Rd, addr);
>> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
>> +
>> +    gen_set_yaddr(addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_yaddr();
>> +
>> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
>> +    gen_data_load(ctx, Rd, addr);
>> +    gen_set_yaddr(addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_yaddr();
>> +
>> +    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
>> +    gen_data_load(ctx, Rd, addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Loads one byte indirect with or without displacement from the data space
>> + *  to a register. For parts with SRAM, the data space consists of the Register
>> + *  File, I/O memory and internal SRAM (and external SRAM if applicable). For
>> + *  parts without SRAM, the data space consists of the Register File only. In
>> + *  some parts the Flash Memory has been mapped to the data space and can be
>> + *  read using this command. The EEPROM has a separate address space.  The data
>> + *  location is pointed to by the Z (16 bits) Pointer Register in the Register
>> + *  File. Memory access is limited to the current data segment of 64KB. To
>> + *  access another data segment in devices with more than 64KB data space, the
>> + *  RAMPZ in register in the I/O area has to be changed.  The Z-pointer Register
>> + *  can either be left unchanged by the operation, or it can be post-incremented
>> + *  or predecremented.  These features are especially suited for Stack Pointer
>> + *  usage of the Z-pointer Register, however because the Z-pointer Register can
>> + *  be used for indirect subroutine calls, indirect jumps and table lookup, it
>> + *  is often more convenient to use the X or Y-pointer as a dedicated Stack
>> + *  Pointer. Note that only the low byte of the Z-pointer is updated in devices
>> + *  with no more than 256 bytes data space. For such devices, the high byte of
>> + *  the pointer is not used by this instruction and can be used for other
>> + *  purposes. The RAMPZ Register in the I/O area is updated in parts with more
>> + *  than 64KB data space or more than 64KB Program memory, and the
>> + *  increment/decrement/displacement is added to the entire 24-bit address on
>> + *  such devices.  Not all variants of this instruction is available in all
>> + *  devices. Refer to the device specific instruction set summary.  In the
>> + *  Reduced Core tinyAVR the LD instruction can be used to achieve the same
>> + *  operation as LPM since the program memory is mapped to the data memory
>> + *  space.  For using the Z-pointer for table lookup in Program memory see the
>> + *  LPM and ELPM instructions.
>> + */
>> +static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_zaddr();
>> +
>> +    gen_data_load(ctx, Rd, addr);
>> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
>> +
>> +    gen_set_zaddr(addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_zaddr();
>> +
>> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
>> +    gen_data_load(ctx, Rd, addr);
>> +
>> +    gen_set_zaddr(addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = gen_get_zaddr();
>> +
>> +    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
>> +    gen_data_load(ctx, Rd, addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + * Loads an 8 bit constant directly to register 16 to 31.
>> + */
>> +static bool trans_LDI(DisasContext *ctx, arg_LDI *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    int imm = a->imm;
>> +
>> +    tcg_gen_movi_tl(Rd, imm);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Loads one byte from the data space to a register. For parts with SRAM,
>> + *  the data space consists of the Register File, I/O memory and internal SRAM
>> + *  (and external SRAM if applicable). For parts without SRAM, the data space
>> + *  consists of the register file only. The EEPROM has a separate address space.
>> + *  A 16-bit address must be supplied. Memory access is limited to the current
>> + *  data segment of 64KB. The LDS instruction uses the RAMPD Register to access
>> + *  memory above 64KB. To access another data segment in devices with more than
>> + *  64KB data space, the RAMPD in register in the I/O area has to be changed.
>> + *  This instruction is not available in all devices. Refer to the device
>> + *  specific instruction set summary.
>> + */
>> +static bool trans_LDS(DisasContext *ctx, arg_LDS *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = tcg_temp_new_i32();
>> +    TCGv H = cpu_rampD;
>> +    a->imm = next_word(ctx);
>> +
>> +    tcg_gen_mov_tl(addr, H); /* addr = H:M:L */
>> +    tcg_gen_shli_tl(addr, addr, 16);
>> +    tcg_gen_ori_tl(addr, addr, a->imm);
>> +
>> +    gen_data_load(ctx, Rd, addr);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Loads one byte pointed to by the Z-register into the destination
>> + *  register Rd. This instruction features a 100% space effective constant
>> + *  initialization or constant data fetch. The Program memory is organized in
>> + *  16-bit words while the Z-pointer is a byte address. Thus, the least
>> + *  significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high
>> + *  byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of
>> + *  Program memory. The Zpointer Register can either be left unchanged by the
>> + *  operation, or it can be incremented. The incrementation does not apply to
>> + *  the RAMPZ Register.  Devices with Self-Programming capability can use the
>> + *  LPM instruction to read the Fuse and Lock bit values.  Refer to the device
>> + *  documentation for a detailed description.  The LPM instruction is not
>> + *  available in all devices. Refer to the device specific instruction set
>> + *  summary
>> + */
>> +static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rd = cpu_r[0];
>> +    TCGv addr = tcg_temp_new_i32();
>> +    TCGv H = cpu_r[31];
>> +    TCGv L = cpu_r[30];
>> +
>> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
>> +    tcg_gen_or_tl(addr, addr, L);
>> +
>> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = tcg_temp_new_i32();
>> +    TCGv H = cpu_r[31];
>> +    TCGv L = cpu_r[30];
>> +
>> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
>> +    tcg_gen_or_tl(addr, addr, L);
>> +
>> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv addr = tcg_temp_new_i32();
>> +    TCGv H = cpu_r[31];
>> +    TCGv L = cpu_r[30];
>> +
>> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
>> +    tcg_gen_or_tl(addr, addr, L);
>> +
>> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
>> +
>> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
>> +
>> +    tcg_gen_andi_tl(L, addr, 0xff);
>> +
>> +    tcg_gen_shri_tl(addr, addr, 8);
>> +    tcg_gen_andi_tl(H, addr, 0xff);
>> +
>> +    tcg_temp_free_i32(addr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is
>> + *  loaded into the C Flag of the SREG. This operation effectively divides an
>> + *  unsigned value by two. The C Flag can be used to round the result.
>> + */
>> +static bool trans_LSR(DisasContext *ctx, arg_LSR *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +
>> +    tcg_gen_andi_tl(cpu_Cf, Rd, 1);
>> +
>> +    tcg_gen_shri_tl(Rd, Rd, 1);
>> +
>> +    tcg_gen_mov_tl(cpu_Zf, Rd);
>> +    tcg_gen_movi_tl(cpu_Nf, 0);
>> +    tcg_gen_mov_tl(cpu_Vf, cpu_Cf);
>> +    tcg_gen_mov_tl(cpu_Sf, cpu_Vf);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction makes a copy of one register into another. The source
>> + *  register Rr is left unchanged, while the destination register Rd is loaded
>> + *  with a copy of Rr.
>> + */
>> +static bool trans_MOV(DisasContext *ctx, arg_MOV *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +
>> +    tcg_gen_mov_tl(Rd, Rr);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction makes a copy of one register pair into another register
>> + *  pair. The source register pair Rr+1:Rr is left unchanged, while the
>> + *  destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr.  This
>> + *  instruction is not available in all devices. Refer to the device specific
>> + *  instruction set summary.
>> + */
>> +static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv RdL = cpu_r[a->rd];
>> +    TCGv RdH = cpu_r[a->rd + 1];
>> +    TCGv RrL = cpu_r[a->rr];
>> +    TCGv RrH = cpu_r[a->rr + 1];
>> +
>> +    tcg_gen_mov_tl(RdH, RrH);
>> +    tcg_gen_mov_tl(RdL, RrL);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication.
>> + */
>> +static bool trans_MUL(DisasContext *ctx, arg_MUL *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv R0 = cpu_r[0];
>> +    TCGv R1 = cpu_r[1];
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */
>> +
>> +    tcg_gen_andi_tl(R0, R, 0xff);
>> +    tcg_gen_shri_tl(R1, R, 8);
>> +
>> +    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */
>> +    tcg_gen_mov_tl(cpu_Zf, R);
>> +
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication.
>> + */
>> +static bool trans_MULS(DisasContext *ctx, arg_MULS *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv R0 = cpu_r[0];
>> +    TCGv R1 = cpu_r[1];
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +    TCGv t0 = tcg_temp_new_i32();
>> +    TCGv t1 = tcg_temp_new_i32();
>> +
>> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
>> +    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */
>> +    tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */
>> +
>> +    tcg_gen_andi_tl(R0, R, 0xff);
>> +    tcg_gen_shri_tl(R1, R, 8);
>> +
>> +    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */
>> +    tcg_gen_mov_tl(cpu_Zf, R);
>> +
>> +    tcg_temp_free_i32(t1);
>> +    tcg_temp_free_i32(t0);
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a
>> + *  signed and an unsigned number.
>> + */
>> +static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a)
>> +{
>> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
>> +        return true;
>> +    }
>> +
>> +    TCGv R0 = cpu_r[0];
>> +    TCGv R1 = cpu_r[1];
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv Rr = cpu_r[a->rr];
>> +    TCGv R = tcg_temp_new_i32();
>> +    TCGv t0 = tcg_temp_new_i32();
>> +
>> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
>> +    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */
>> +
>> +    tcg_gen_andi_tl(R0, R, 0xff);
>> +    tcg_gen_shri_tl(R1, R, 8);
>> +
>> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
>> +    tcg_gen_mov_tl(cpu_Zf, R);
>> +
>> +    tcg_temp_free_i32(t0);
>> +    tcg_temp_free_i32(R);
>> +
>> +    return true;
>> +}
>> +
>> +/*
>> + *  Replaces the contents of register Rd with its two's complement; the
>> + *  value $80 is left unchanged.
>> + */
>> +static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
>> +{
>> +    TCGv Rd = cpu_r[a->rd];
>> +    TCGv t0 = tcg_const_i32(0);
>> +    TCGv R = tcg_temp_new_i32();
>> +
>> +    /* op */
>> +    tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
>> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
>> +
>> +    gen_sub_CHf(R, t0, Rd);
>> +    gen_sub_Vf(R, t0, Rd);
>> +    gen_ZNSf(R);
>> +
>> +    /* R */
>> +    tcg_gen_mov_tl(Rd,--
>> 2.17.2 (Apple Git-113)
>>
>>


-- 
Best Regards,
Michael Rolnik


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation
  2019-10-12 16:33     ` Michael Rolnik
@ 2019-10-12 17:47       ` Aleksandar Markovic
  0 siblings, 0 replies; 19+ messages in thread
From: Aleksandar Markovic @ 2019-10-12 17:47 UTC (permalink / raw)
  To: Michael Rolnik
  Cc: thuth, richard.henderson, qemu-devel, dovgaluk, imammedo, philmd

On Sat, Oct 12, 2019 at 6:34 PM Michael Rolnik <mrolnik@gmail.com> wrote:
>
> Hi Aleksandar.
>
> If I break it to multiple patches, does every patch have to compile?
>

Micheal,

Well, it does. This is because people are using various automated or
semi-automated
"bisect" scripts when they want to find what commit caused certain
problem, and if
any patch breaks build, this may make those "bisect" scripts not work.

But... since I see others are inclined to accept this patch 4 as-is, I
am not going to
place obstacles on that. So, it looks you can leave patch 4 as-is.

How ever, in future, when you hopefully submit some other larger piece of code,
I recommend to you to try not to place all code in a single patch, but
in several
logical sub-parts. This makes your patches easier to review, and there are some
other reasons too - for example, it is easier to spot a bug in a
smaller patch than
in a larger.

Again, for now, do not spend your time doing tedious job of splitting
this patch.

Yours,
Aleksandar

> On Fri, Oct 11, 2019 at 5:13 PM Aleksandar Markovic
> <aleksandar.m.mail@gmail.com> wrote:
> >
> >
> >
> > On Monday, September 2, 2019, Michael Rolnik <mrolnik@gmail.com> wrote:
> >>
> >> This includes:
> >> - TCG translations for each instruction
> >>
> >> Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
> >> ---
> >>  target/avr/translate.c | 2888 ++++++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 2888 insertions(+)
> >>  create mode 100644 target/avr/translate.c
> >>
> >
> > Hi, Michael,
> >
> >
> > This patch is way too large. I suggest splitting it into:
> >
> > - register definitions
> > - load instruction handling
> > - store instruction handling
> > - logic instruction handling
> >
> > etc.
> >
> > Thanks, Aleksandar
> >
> > P.S. One more hurdle with your communication on the list is that you don't use "inline responding" while replaying, please use it in future. See other messages in the mailing list how "inline responding" looks.
> >
> >
> >
> >
> >>
> >> diff --git a/target/avr/translate.c b/target/avr/translate.c
> >> new file mode 100644
> >> index 0000000000..42cb4a690c
> >> --- /dev/null
> >> +++ b/target/avr/translate.c
> >> @@ -0,0 +1,2888 @@
> >> +/*
> >> + * QEMU AVR CPU
> >> + *
> >> + * Copyright (c) 2019 Michael Rolnik
> >> + *
> >> + * This library is free software; you can redistribute it and/or
> >> + * modify it under the terms of the GNU Lesser General Public
> >> + * License as published by the Free Software Foundation; either
> >> + * version 2.1 of the License, or (at your option) any later version.
> >> + *
> >> + * This library is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> >> + * Lesser General Public License for more details.
> >> + *
> >> + * You should have received a copy of the GNU Lesser General Public
> >> + * License along with this library; if not, see
> >> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> >> + */
> >> +
> >> +#include "qemu/osdep.h"
> >> +#include "qemu/qemu-print.h"
> >> +#include "tcg/tcg.h"
> >> +#include "cpu.h"
> >> +#include "exec/exec-all.h"
> >> +#include "disas/disas.h"
> >> +#include "tcg-op.h"
> >> +#include "exec/cpu_ldst.h"
> >> +#include "exec/helper-proto.h"
> >> +#include "exec/helper-gen.h"
> >> +#include "exec/log.h"
> >> +#include "exec/gdbstub.h"
> >> +#include "exec/translator.h"
> >> +
> >> +/*
> >> + *  Define if you want a BREAK instruction translated to a breakpoint
> >> + *  Active debugging connection is assumed
> >> + *  This is for
> >> + *  https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
> >> + *  tests
> >> + */
> >> +#undef BREAKPOINT_ON_BREAK
> >> +
> >> +static TCGv cpu_pc;
> >> +
> >> +static TCGv cpu_Cf;
> >> +static TCGv cpu_Zf;
> >> +static TCGv cpu_Nf;
> >> +static TCGv cpu_Vf;
> >> +static TCGv cpu_Sf;
> >> +static TCGv cpu_Hf;
> >> +static TCGv cpu_Tf;
> >> +static TCGv cpu_If;
> >> +
> >> +static TCGv cpu_rampD;
> >> +static TCGv cpu_rampX;
> >> +static TCGv cpu_rampY;
> >> +static TCGv cpu_rampZ;
> >> +
> >> +static TCGv cpu_r[NO_CPU_REGISTERS];
> >> +static TCGv cpu_eind;
> >> +static TCGv cpu_sp;
> >> +
> >> +static TCGv cpu_skip;
> >> +
> >> +static const char reg_names[NO_CPU_REGISTERS][8] = {
> >> +    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
> >> +    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
> >> +    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
> >> +    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
> >> +};
> >> +#define REG(x) (cpu_r[x])
> >> +
> >> +enum {
> >> +    DISAS_EXIT   = DISAS_TARGET_0,  /* We want return to the cpu main loop.  */
> >> +    DISAS_LOOKUP = DISAS_TARGET_1,  /* We have a variable condition exit.  */
> >> +    DISAS_CHAIN  = DISAS_TARGET_2,  /* We have a single condition exit.  */
> >> +};
> >> +
> >> +typedef struct DisasContext DisasContext;
> >> +
> >> +/* This is the state at translation time. */
> >> +struct DisasContext {
> >> +    TranslationBlock *tb;
> >> +
> >> +    CPUAVRState *env;
> >> +    CPUState *cs;
> >> +
> >> +    target_long npc;
> >> +    uint32_t opcode;
> >> +
> >> +    /* Routine used to access memory */
> >> +    int memidx;
> >> +    int bstate;
> >> +    int singlestep;
> >> +
> >> +    TCGv skip_var0;
> >> +    TCGv skip_var1;
> >> +    TCGCond skip_cond;
> >> +    bool free_skip_var0;
> >> +};
> >> +
> >> +static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); }
> >> +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); }
> >> +static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) * 2; }
> >> +static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; }
> >> +
> >> +static uint16_t next_word(DisasContext *ctx)
> >> +{
> >> +    return cpu_lduw_code(ctx->env, ctx->npc++ * 2);
> >> +}
> >> +
> >> +static int append_16(DisasContext *ctx, int x)
> >> +{
> >> +    return x << 16 | next_word(ctx);
> >> +}
> >> +
> >> +static bool decode_insn(DisasContext *ctx, uint16_t insn);
> >> +#include "decode_insn.inc.c"
> >> +
> >> +static bool avr_have_feature(DisasContext *ctx, int feature)
> >> +{
> >> +    if (!avr_feature(ctx->env, feature)) {
> >> +        gen_helper_unsupported(cpu_env);
> >> +        ctx->bstate = DISAS_NORETURN;
> >> +        return false;
> >> +    }
> >> +    return true;
> >> +}
> >> +
> >> +static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> >> +{
> >> +    TranslationBlock *tb = ctx->tb;
> >> +
> >> +    if (ctx->singlestep == 0) {
> >> +        tcg_gen_goto_tb(n);
> >> +        tcg_gen_movi_i32(cpu_pc, dest);
> >> +        tcg_gen_exit_tb(tb, n);
> >> +    } else {
> >> +        tcg_gen_movi_i32(cpu_pc, dest);
> >> +        gen_helper_debug(cpu_env);
> >> +        tcg_gen_exit_tb(NULL, 0);
> >> +    }
> >> +    ctx->bstate = DISAS_NORETURN;
> >> +}
> >> +
> >> +#include "exec/gen-icount.h"
> >> +
> >> +static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)
> >> +{
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +    TCGv t2 = tcg_temp_new_i32();
> >> +    TCGv t3 = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */
> >> +    tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */
> >> +    tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */
> >> +    tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */
> >> +    tcg_gen_or_tl(t1, t1, t3);
> >> +
> >> +    tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */
> >> +    tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */
> >> +    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
> >> +
> >> +    tcg_temp_free_i32(t3);
> >> +    tcg_temp_free_i32(t2);
> >> +    tcg_temp_free_i32(t1);
> >> +}
> >> +
> >> +static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr)
> >> +{
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +    TCGv t2 = tcg_temp_new_i32();
> >> +
> >> +    /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R = (Rd ^ R) & ~(Rd ^ Rr) */
> >> +    tcg_gen_xor_tl(t1, Rd, R);
> >> +    tcg_gen_xor_tl(t2, Rd, Rr);
> >> +    tcg_gen_andc_tl(t1, t1, t2);
> >> +
> >> +    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
> >> +
> >> +    tcg_temp_free_i32(t2);
> >> +    tcg_temp_free_i32(t1);
> >> +}
> >> +
> >> +static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)
> >> +{
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +    TCGv t2 = tcg_temp_new_i32();
> >> +    TCGv t3 = tcg_temp_new_i32();
> >> +
> >> +    /* Cf & Hf */
> >> +    tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */
> >> +    tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */
> >> +    tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */
> >> +    tcg_gen_and_tl(t3, t3, R);
> >> +    tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
> >> +    tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */
> >> +    tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */
> >> +    tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
> >> +
> >> +    tcg_temp_free_i32(t3);
> >> +    tcg_temp_free_i32(t2);
> >> +    tcg_temp_free_i32(t1);
> >> +}
> >> +
> >> +static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr)
> >> +{
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +    TCGv t2 = tcg_temp_new_i32();
> >> +
> >> +    /* Vf */
> >> +    /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R = (Rd ^ R) & (Rd ^ R) */
> >> +    tcg_gen_xor_tl(t1, Rd, R);
> >> +    tcg_gen_xor_tl(t2, Rd, Rr);
> >> +    tcg_gen_and_tl(t1, t1, t2);
> >> +    tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
> >> +
> >> +    tcg_temp_free_i32(t2);
> >> +    tcg_temp_free_i32(t1);
> >> +}
> >> +
> >> +static void gen_rshift_ZNVSf(TCGv R)
> >> +{
> >> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
> >> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
> >> +    tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf);
> >> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
> >> +}
> >> +
> >> +static void gen_NSf(TCGv R)
> >> +{
> >> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
> >> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
> >> +}
> >> +
> >> +static void gen_ZNSf(TCGv R)
> >> +{
> >> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
> >> +    tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
> >> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
> >> +}
> >> +
> >> +static void gen_push_ret(DisasContext *ctx, int ret)
> >> +{
> >> +    if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
> >> +
> >> +        TCGv t0 = tcg_const_i32((ret & 0x0000ff));
> >> +
> >> +        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
> >> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> >> +
> >> +        tcg_temp_free_i32(t0);
> >> +    } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
> >> +
> >> +        TCGv t0 = tcg_const_i32((ret & 0x00ffff));
> >> +
> >> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> >> +        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> >> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> >> +
> >> +        tcg_temp_free_i32(t0);
> >> +
> >> +    } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
> >> +
> >> +        TCGv lo = tcg_const_i32((ret & 0x0000ff));
> >> +        TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
> >> +
> >> +        tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
> >> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
> >> +        tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> >> +        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> >> +
> >> +        tcg_temp_free_i32(lo);
> >> +        tcg_temp_free_i32(hi);
> >> +    }
> >> +}
> >> +
> >> +static void gen_pop_ret(DisasContext *ctx, TCGv ret)
> >> +{
> >> +    if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
> >> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> >> +        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
> >> +    } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
> >> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> >> +        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> >> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> >> +    } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
> >> +        TCGv lo = tcg_temp_new_i32();
> >> +        TCGv hi = tcg_temp_new_i32();
> >> +
> >> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> >> +        tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> >> +
> >> +        tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
> >> +        tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
> >> +
> >> +        tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
> >> +
> >> +        tcg_temp_free_i32(lo);
> >> +        tcg_temp_free_i32(hi);
> >> +    }
> >> +}
> >> +
> >> +static void gen_jmp_ez(DisasContext *ctx)
> >> +{
> >> +    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
> >> +    tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind);
> >> +    ctx->bstate = DISAS_LOOKUP;
> >> +}
> >> +
> >> +static void gen_jmp_z(DisasContext *ctx)
> >> +{
> >> +    tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
> >> +    ctx->bstate = DISAS_LOOKUP;
> >> +}
> >> +
> >> +/*
> >> + *  in the gen_set_addr & gen_get_addr functions
> >> + *  H assumed to be in 0x00ff0000 format
> >> + *  M assumed to be in 0x000000ff format
> >> + *  L assumed to be in 0x000000ff format
> >> + */
> >> +static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L)
> >> +{
> >> +
> >> +    tcg_gen_andi_tl(L, addr, 0x000000ff);
> >> +
> >> +    tcg_gen_andi_tl(M, addr, 0x0000ff00);
> >> +    tcg_gen_shri_tl(M, M, 8);
> >> +
> >> +    tcg_gen_andi_tl(H, addr, 0x00ff0000);
> >> +}
> >> +
> >> +static void gen_set_xaddr(TCGv addr)
> >> +{
> >> +    gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]);
> >> +}
> >> +
> >> +static void gen_set_yaddr(TCGv addr)
> >> +{
> >> +    gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]);
> >> +}
> >> +
> >> +static void gen_set_zaddr(TCGv addr)
> >> +{
> >> +    gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]);
> >> +}
> >> +
> >> +static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L)
> >> +{
> >> +    TCGv addr = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_deposit_tl(addr, M, H, 8, 8);
> >> +    tcg_gen_deposit_tl(addr, L, addr, 8, 16);
> >> +
> >> +    return addr;
> >> +}
> >> +
> >> +static TCGv gen_get_xaddr(void)
> >> +{
> >> +    return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]);
> >> +}
> >> +
> >> +static TCGv gen_get_yaddr(void)
> >> +{
> >> +    return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]);
> >> +}
> >> +
> >> +static TCGv gen_get_zaddr(void)
> >> +{
> >> +    return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]);
> >> +}
> >> +
> >> +/*
> >> + *  Adds two registers and the contents of the C Flag and places the result in
> >> + *  the destination register Rd.
> >> + */
> >> +static bool trans_ADC(DisasContext *ctx, arg_ADC *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    /* op */
> >> +    tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */
> >> +    tcg_gen_add_tl(R, R, cpu_Cf);
> >> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> >> +
> >> +    gen_add_CHf(R, Rd, Rr);
> >> +    gen_add_Vf(R, Rd, Rr);
> >> +    gen_ZNSf(R);
> >> +
> >> +    /* R */
> >> +    tcg_gen_mov_tl(Rd, R);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Adds two registers without the C Flag and places the result in the
> >> + *  destination register Rd.
> >> + */
> >> +static bool trans_ADD(DisasContext *ctx, arg_ADD *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    /* op */
> >> +    tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */
> >> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> >> +
> >> +    gen_add_CHf(R, Rd, Rr);
> >> +    gen_add_Vf(R, Rd, Rr);
> >> +    gen_ZNSf(R);
> >> +
> >> +    /* R */
> >> +    tcg_gen_mov_tl(Rd, R);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Adds an immediate value (0 - 63) to a register pair and places the result
> >> + *  in the register pair. This instruction operates on the upper four register
> >> + *  pairs, and is well suited for operations on the pointer registers.  This
> >> + *  instruction is not available in all devices. Refer to the device specific
> >> + *  instruction set summary.
> >> + */
> >> +static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv RdL = cpu_r[a->rd];
> >> +    TCGv RdH = cpu_r[a->rd + 1];
> >> +    int Imm = (a->imm);
> >> +    TCGv R = tcg_temp_new_i32();
> >> +    TCGv Rd = tcg_temp_new_i32();
> >> +
> >> +    /* op */
> >> +    tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */
> >> +    tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */
> >> +    tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */
> >> +
> >> +    /* Cf */
> >> +    tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */
> >> +    tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15);
> >> +
> >> +    /* Vf */
> >> +    tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R & ~Rd */
> >> +    tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15);
> >> +
> >> +    /* Zf */
> >> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
> >> +
> >> +    /* Nf */
> >> +    tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */
> >> +
> >> +    /* Sf */
> >> +    tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */
> >> +
> >> +    /* R */
> >> +    tcg_gen_andi_tl(RdL, R, 0xff);
> >> +    tcg_gen_shri_tl(RdH, R, 8);
> >> +
> >> +    tcg_temp_free_i32(Rd);
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Performs the logical AND between the contents of register Rd and register
> >> + *  Rr and places the result in the destination register Rd.
> >> + */
> >> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    /* op */
> >> +    tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
> >> +
> >> +    /* Vf */
> >> +    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
> >> +
> >> +    /* Zf */
> >> +    tcg_gen_mov_tl(cpu_Zf, R); /* Zf = R */
> >> +
> >> +    gen_ZNSf(R);
> >> +
> >> +    /* R */
> >> +    tcg_gen_mov_tl(Rd, R);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Performs the logical AND between the contents of register Rd and a constant
> >> + *  and places the result in the destination register Rd.
> >> + */
> >> +static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    int Imm = (a->imm);
> >> +
> >> +    /* op */
> >> +    tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd & Imm */
> >> +
> >> +    tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */
> >> +    gen_ZNSf(Rd);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0
> >> + *  is loaded into the C Flag of the SREG. This operation effectively divides a
> >> + *  signed value by two without changing its sign. The Carry Flag can be used to
> >> + *  round the result.
> >> + */
> >> +static bool trans_ASR(DisasContext *ctx, arg_ASR *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv t0 = tcg_temp_new_i32();
> >> +
> >> +    /* Cf */
> >> +    tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */
> >> +
> >> +    /* op */
> >> +    tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */
> >> +    tcg_gen_shri_tl(Rd, Rd, 1);
> >> +    tcg_gen_or_tl(Rd, Rd, t0);
> >> +
> >> +    gen_rshift_ZNVSf(Rd);
> >> +
> >> +    tcg_temp_free_i32(t0);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Clears a single Flag in SREG.
> >> + */
> >> +static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
> >> +{
> >> +    switch (a->bit) {
> >> +    case 0x00:
> >> +        tcg_gen_movi_tl(cpu_Cf, 0x00);
> >> +        break;
> >> +    case 0x01:
> >> +        tcg_gen_movi_tl(cpu_Zf, 0x01);
> >> +        break;
> >> +    case 0x02:
> >> +        tcg_gen_movi_tl(cpu_Nf, 0x00);
> >> +        break;
> >> +    case 0x03:
> >> +        tcg_gen_movi_tl(cpu_Vf, 0x00);
> >> +        break;
> >> +    case 0x04:
> >> +        tcg_gen_movi_tl(cpu_Sf, 0x00);
> >> +        break;
> >> +    case 0x05:
> >> +        tcg_gen_movi_tl(cpu_Hf, 0x00);
> >> +        break;
> >> +    case 0x06:
> >> +        tcg_gen_movi_tl(cpu_Tf, 0x00);
> >> +        break;
> >> +    case 0x07:
> >> +        tcg_gen_movi_tl(cpu_If, 0x00);
> >> +        break;
> >> +    }
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Copies the T Flag in the SREG (Status Register) to bit b in register Rd.
> >> + */
> >> +static bool trans_BLD(DisasContext *ctx, arg_BLD *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */
> >> +    tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */
> >> +    tcg_gen_or_tl(Rd, Rd, t1);
> >> +
> >> +    tcg_temp_free_i32(t1);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Conditional relative branch. Tests a single bit in SREG and branches
> >> + *  relatively to PC if the bit is cleared. This instruction branches relatively
> >> + *  to PC in either direction (PC - 63 < = destination <= PC + 64). The
> >> + *  parameter k is the offset from PC and is represented in two's complement
> >> + *  form.
> >> + */
> >> +static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a)
> >> +{
> >> +    TCGLabel *not_taken = gen_new_label();
> >> +    TCGCond cond = TCG_COND_EQ;
> >> +    TCGv var;
> >> +
> >> +    switch (a->bit) {
> >> +    case 0x00:
> >> +        var = cpu_Cf;
> >> +        break;
> >> +    case 0x01:
> >> +        cond = TCG_COND_NE;
> >> +        var = cpu_Zf;
> >> +        break;
> >> +    case 0x02:
> >> +        var = cpu_Nf;
> >> +        break;
> >> +    case 0x03:
> >> +        var = cpu_Vf;
> >> +        break;
> >> +    case 0x04:
> >> +        var = cpu_Sf;
> >> +        break;
> >> +    case 0x05:
> >> +        var = cpu_Hf;
> >> +        break;
> >> +    case 0x06:
> >> +        var = cpu_Tf;
> >> +        break;
> >> +    case 0x07:
> >> +        var = cpu_If;
> >> +        break;
> >> +    default:
> >> +        g_assert_not_reached();
> >> +    }
> >> +
> >> +    tcg_gen_brcondi_i32(tcg_invert_cond(cond), var, 0, not_taken);
> >> +    gen_goto_tb(ctx, 0, ctx->npc + a->imm);
> >> +    gen_set_label(not_taken);
> >> +
> >> +    ctx->bstate = DISAS_CHAIN;
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Conditional relative branch. Tests a single bit in SREG and branches
> >> + *  relatively to PC if the bit is set. This instruction branches relatively to
> >> + *  PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k
> >> + *  is the offset from PC and is represented in two's complement form.
> >> + */
> >> +static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a)
> >> +{
> >> +    TCGLabel *not_taken = gen_new_label();
> >> +    TCGCond cond = TCG_COND_NE;
> >> +    TCGv var;
> >> +
> >> +    switch (a->bit) {
> >> +    case 0x00:
> >> +        var = cpu_Cf;
> >> +        break;
> >> +    case 0x01:
> >> +        cond = TCG_COND_EQ;
> >> +        var = cpu_Zf;
> >> +        break;
> >> +    case 0x02:
> >> +        var = cpu_Nf;
> >> +        break;
> >> +    case 0x03:
> >> +        var = cpu_Vf;
> >> +        break;
> >> +    case 0x04:
> >> +        var = cpu_Sf;
> >> +        break;
> >> +    case 0x05:
> >> +        var = cpu_Hf;
> >> +        break;
> >> +    case 0x06:
> >> +        var = cpu_Tf;
> >> +        break;
> >> +    case 0x07:
> >> +        var = cpu_If;
> >> +        break;
> >> +    default:
> >> +        g_assert_not_reached();
> >> +    }
> >> +
> >> +    tcg_gen_brcondi_i32(tcg_invert_cond(cond), var, 0, not_taken);
> >> +    gen_goto_tb(ctx, 0, ctx->npc + a->imm);
> >> +    gen_set_label(not_taken);
> >> +
> >> +    ctx->bstate = DISAS_CHAIN;
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Sets a single Flag or bit in SREG.
> >> + */
> >> +static bool trans_BSET(DisasContext *ctx, arg_BSET *a)
> >> +{
> >> +    switch (a->bit) {
> >> +    case 0x00:
> >> +        tcg_gen_movi_tl(cpu_Cf, 0x01);
> >> +        break;
> >> +    case 0x01:
> >> +        tcg_gen_movi_tl(cpu_Zf, 0x00);
> >> +        break;
> >> +    case 0x02:
> >> +        tcg_gen_movi_tl(cpu_Nf, 0x01);
> >> +        break;
> >> +    case 0x03:
> >> +        tcg_gen_movi_tl(cpu_Vf, 0x01);
> >> +        break;
> >> +    case 0x04:
> >> +        tcg_gen_movi_tl(cpu_Sf, 0x01);
> >> +        break;
> >> +    case 0x05:
> >> +        tcg_gen_movi_tl(cpu_Hf, 0x01);
> >> +        break;
> >> +    case 0x06:
> >> +        tcg_gen_movi_tl(cpu_Tf, 0x01);
> >> +        break;
> >> +    case 0x07:
> >> +        tcg_gen_movi_tl(cpu_If, 0x01);
> >> +        break;
> >> +    }
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  The BREAK instruction is used by the On-chip Debug system, and is
> >> + *  normally not used in the application software. When the BREAK instruction is
> >> + *  executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
> >> + *  Debugger access to internal resources.  If any Lock bits are set, or either
> >> + *  the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
> >> + *  instruction as a NOP and will not enter the Stopped mode.  This instruction
> >> + *  is not available in all devices. Refer to the device specific instruction
> >> + *  set summary.
> >> + */
> >> +static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
> >> +        return true;
> >> +    }
> >> +
> >> +#ifdef BREAKPOINT_ON_BREAK
> >> +    tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
> >> +    gen_helper_debug(cpu_env);
> >> +    ctx->bstate = DISAS_EXIT;
> >> +#else
> >> +    /* NOP */
> >> +#endif
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Stores bit b from Rd to the T Flag in SREG (Status Register).
> >> + */
> >> +static bool trans_BST(DisasContext *ctx, arg_BST *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +
> >> +    tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit);
> >> +    tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Calls to a subroutine within the entire Program memory. The return
> >> + *  address (to the instruction after the CALL) will be stored onto the Stack.
> >> + *  (See also RCALL). The Stack Pointer uses a post-decrement scheme during
> >> + *  CALL.  This instruction is not available in all devices. Refer to the device
> >> + *  specific instruction set summary.
> >> + */
> >> +static bool trans_CALL(DisasContext *ctx, arg_CALL *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    int Imm = a->imm;
> >> +    int ret = ctx->npc;
> >> +
> >> +    gen_push_ret(ctx, ret);
> >> +    gen_goto_tb(ctx, 0, Imm);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Clears a specified bit in an I/O Register. This instruction operates on
> >> + *  the lower 32 I/O Registers -- addresses 0-31.
> >> + */
> >> +static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
> >> +{
> >> +    TCGv data = tcg_temp_new_i32();
> >> +    TCGv port = tcg_const_i32(a->reg);
> >> +
> >> +    gen_helper_inb(data, cpu_env, port);
> >> +    tcg_gen_andi_tl(data, data, ~(1 << a->bit));
> >> +    gen_helper_outb(cpu_env, port, data);
> >> +
> >> +    tcg_temp_free_i32(data);
> >> +    tcg_temp_free_i32(port);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Clears the specified bits in register Rd. Performs the logical AND
> >> + *  between the contents of register Rd and the complement of the constant mask
> >> + *  K. The result will be placed in register Rd.
> >> + */
> >> +static bool trans_COM(DisasContext *ctx, arg_COM *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_xori_tl(Rd, Rd, 0xff);
> >> +
> >> +    tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */
> >> +    tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
> >> +    gen_ZNSf(Rd);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs a compare between two registers Rd and Rr.
> >> + *  None of the registers are changed. All conditional branches can be used
> >> + *  after this instruction.
> >> + */
> >> +static bool trans_CP(DisasContext *ctx, arg_CP *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    /* op */
> >> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
> >> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> >> +
> >> +    gen_sub_CHf(R, Rd, Rr);
> >> +    gen_sub_Vf(R, Rd, Rr);
> >> +    gen_ZNSf(R);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs a compare between two registers Rd and Rr and
> >> + *  also takes into account the previous carry. None of the registers are
> >> + *  changed. All conditional branches can be used after this instruction.
> >> + */
> >> +static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    /* op */
> >> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
> >> +    tcg_gen_sub_tl(R, R, cpu_Cf);
> >> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> >> +
> >> +    gen_sub_CHf(R, Rd, Rr);
> >> +    gen_sub_Vf(R, Rd, Rr);
> >> +    gen_NSf(R);
> >> +
> >> +    /*
> >> +     * Previous value remains unchanged when the result is zero;
> >> +     * cleared otherwise.
> >> +     */
> >> +    tcg_gen_or_tl(cpu_Zf, cpu_Zf, R);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs a compare between register Rd and a constant.
> >> + *  The register is not changed. All conditional branches can be used after this
> >> + *  instruction.
> >> + */
> >> +static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    int Imm = a->imm;
> >> +    TCGv Rr = tcg_const_i32(Imm);
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    /* op */
> >> +    tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
> >> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> >> +
> >> +    gen_sub_CHf(R, Rd, Rr);
> >> +    gen_sub_Vf(R, Rd, Rr);
> >> +    gen_ZNSf(R);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +    tcg_temp_free_i32(Rr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs a compare between two registers Rd and Rr, and
> >> + *  skips the next instruction if Rd = Rr.
> >> + */
> >> +static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a)
> >> +{
> >> +    ctx->skip_cond = TCG_COND_EQ;
> >> +    ctx->skip_var0 = cpu_r[a->rd];
> >> +    ctx->skip_var1 = cpu_r[a->rr];
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Subtracts one -1- from the contents of register Rd and places the result
> >> + *  in the destination register Rd.  The C Flag in SREG is not affected by the
> >> + *  operation, thus allowing the DEC instruction to be used on a loop counter in
> >> + *  multiple-precision computations.  When operating on unsigned values, only
> >> + *  BREQ and BRNE branches can be expected to perform consistently.  When
> >> + *  operating on two's complement values, all signed branches are available.
> >> + */
> >> +static bool trans_DEC(DisasContext *ctx, arg_DEC *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +
> >> +    tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */
> >> +    tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */
> >> +
> >> +    /* cpu_Vf = Rd == 0x7f */
> >> +    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f);
> >> +    gen_ZNSf(Rd);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  The module is an instruction set extension to the AVR CPU, performing
> >> + *  DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in
> >> + *  the CPU register file, registers R0-R7, where LSB of data is placed in LSB
> >> + *  of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including
> >> + *  parity bits) is placed in registers R8- R15, organized in the register file
> >> + *  with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES
> >> + *  instruction performs one round in the DES algorithm. Sixteen rounds must be
> >> + *  executed in increasing order to form the correct DES ciphertext or
> >> + *  plaintext. Intermediate results are stored in the register file (R0-R15)
> >> + *  after each DES instruction. The instruction's operand (K) determines which
> >> + *  round is executed, and the half carry flag (H) determines whether encryption
> >> + *  or decryption is performed.  The DES algorithm is described in
> >> + *  "Specifications for the Data Encryption Standard" (Federal Information
> >> + *  Processing Standards Publication 46). Intermediate results in this
> >> + *  implementation differ from the standard because the initial permutation and
> >> + *  the inverse initial permutation are performed each iteration. This does not
> >> + *  affect the result in the final ciphertext or plaintext, but reduces
> >> + *  execution time.
> >> + */
> >> +static bool trans_DES(DisasContext *ctx, arg_DES *a)
> >> +{
> >> +    /* TODO */
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_DES)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Indirect call of a subroutine pointed to by the Z (16 bits) Pointer
> >> + *  Register in the Register File and the EIND Register in the I/O space. This
> >> + *  instruction allows for indirect calls to the entire 4M (words) Program
> >> + *  memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme
> >> + *  during EICALL.  This instruction is not available in all devices. Refer to
> >> + *  the device specific instruction set summary.
> >> + */
> >> +static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    int ret = ctx->npc;
> >> +
> >> +    gen_push_ret(ctx, ret);
> >> +    gen_jmp_ez(ctx);
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
> >> + *  Register in the Register File and the EIND Register in the I/O space. This
> >> + *  instruction allows for indirect jumps to the entire 4M (words) Program
> >> + *  memory space. See also IJMP.  This instruction is not available in all
> >> + *  devices. Refer to the device specific instruction set summary.
> >> + */
> >> +static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    gen_jmp_ez(ctx);
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Loads one byte pointed to by the Z-register and the RAMPZ Register in
> >> + *  the I/O space, and places this byte in the destination register Rd. This
> >> + *  instruction features a 100% space effective constant initialization or
> >> + *  constant data fetch. The Program memory is organized in 16-bit words while
> >> + *  the Z-pointer is a byte address. Thus, the least significant bit of the
> >> + *  Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This
> >> + *  instruction can address the entire Program memory space. The Z-pointer
> >> + *  Register can either be left unchanged by the operation, or it can be
> >> + *  incremented. The incrementation applies to the entire 24-bit concatenation
> >> + *  of the RAMPZ and Z-pointer Registers.  Devices with Self-Programming
> >> + *  capability can use the ELPM instruction to read the Fuse and Lock bit value.
> >> + *  Refer to the device documentation for a detailed description.  This
> >> + *  instruction is not available in all devices. Refer to the device specific
> >> + *  instruction set summary.
> >> + */
> >> +static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rd = cpu_r[0];
> >> +    TCGv addr = gen_get_zaddr();
> >> +
> >> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_zaddr();
> >> +
> >> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_zaddr();
> >> +
> >> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> >> +
> >> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> >> +
> >> +    gen_set_zaddr(addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Performs the logical EOR between the contents of register Rd and
> >> + *  register Rr and places the result in the destination register Rd.
> >> + */
> >> +static bool trans_EOR(DisasContext *ctx, arg_EOR *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +
> >> +    tcg_gen_xor_tl(Rd, Rd, Rr);
> >> +
> >> +    tcg_gen_movi_tl(cpu_Vf, 0);
> >> +    gen_ZNSf(Rd);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs 8-bit x 8-bit -> 16-bit unsigned
> >> + *  multiplication and shifts the result one bit left.
> >> + */
> >> +static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv R0 = cpu_r[0];
> >> +    TCGv R1 = cpu_r[1];
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */
> >> +    tcg_gen_shli_tl(R, R, 1);
> >> +
> >> +    tcg_gen_andi_tl(R0, R, 0xff);
> >> +    tcg_gen_shri_tl(R1, R, 8);
> >> +    tcg_gen_andi_tl(R1, R1, 0xff);
> >> +
> >> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
> >> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
> >> + *  and shifts the result one bit left.
> >> + */
> >> +static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv R0 = cpu_r[0];
> >> +    TCGv R1 = cpu_r[1];
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +    TCGv t0 = tcg_temp_new_i32();
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
> >> +    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */
> >> +    tcg_gen_mul_tl(R, t0, t1); /* R = Rd *Rr */
> >> +    tcg_gen_shli_tl(R, R, 1);
> >> +
> >> +    tcg_gen_andi_tl(R0, R, 0xff);
> >> +    tcg_gen_shri_tl(R1, R, 8);
> >> +    tcg_gen_andi_tl(R1, R1, 0xff);
> >> +
> >> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
> >> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
> >> +
> >> +    tcg_temp_free_i32(t1);
> >> +    tcg_temp_free_i32(t0);
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
> >> + *  and shifts the result one bit left.
> >> + */
> >> +static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv R0 = cpu_r[0];
> >> +    TCGv R1 = cpu_r[1];
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +    TCGv t0 = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
> >> +    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */
> >> +    tcg_gen_shli_tl(R, R, 1);
> >> +
> >> +    tcg_gen_andi_tl(R0, R, 0xff);
> >> +    tcg_gen_shri_tl(R1, R, 8);
> >> +    tcg_gen_andi_tl(R1, R1, 0xff);
> >> +
> >> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
> >> +    tcg_gen_andi_tl(cpu_Zf, R, 0x0000ffff);
> >> +
> >> +    tcg_temp_free_i32(t0);
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Calls to a subroutine within the entire 4M (words) Program memory. The
> >> + *  return address (to the instruction after the CALL) will be stored onto the
> >> + *  Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during
> >> + *  CALL.  This instruction is not available in all devices. Refer to the device
> >> + *  specific instruction set summary.
> >> + */
> >> +static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    int ret = ctx->npc;
> >> +
> >> +    gen_push_ret(ctx, ret);
> >> +    gen_jmp_z(ctx);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Indirect jump to the address pointed to by the Z (16 bits) Pointer
> >> + *  Register in the Register File. The Z-pointer Register is 16 bits wide and
> >> + *  allows jump within the lowest 64K words (128KB) section of Program memory.
> >> + *  This instruction is not available in all devices. Refer to the device
> >> + *  specific instruction set summary.
> >> + */
> >> +static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    gen_jmp_z(ctx);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Loads data from the I/O Space (Ports, Timers, Configuration Registers,
> >> + *  etc.) into register Rd in the Register File.
> >> + */
> >> +static bool trans_IN(DisasContext *ctx, arg_IN *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv port = tcg_const_i32(a->imm);
> >> +
> >> +    gen_helper_inb(Rd, cpu_env, port);
> >> +
> >> +    tcg_temp_free_i32(port);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Adds one -1- to the contents of register Rd and places the result in the
> >> + *  destination register Rd.  The C Flag in SREG is not affected by the
> >> + *  operation, thus allowing the INC instruction to be used on a loop counter in
> >> + *  multiple-precision computations.  When operating on unsigned numbers, only
> >> + *  BREQ and BRNE branches can be expected to perform consistently. When
> >> + *  operating on two's complement values, all signed branches are available.
> >> + */
> >> +static bool trans_INC(DisasContext *ctx, arg_INC *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +
> >> +    tcg_gen_addi_tl(Rd, Rd, 1);
> >> +    tcg_gen_andi_tl(Rd, Rd, 0xff);
> >> +
> >> +    /* cpu_Vf = Rd == 0x80 */
> >> +    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80);
> >> +    gen_ZNSf(Rd);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Jump to an address within the entire 4M (words) Program memory. See also
> >> + *  RJMP.  This instruction is not available in all devices. Refer to the device
> >> + *  specific instruction set summary.0
> >> + */
> >> +static bool trans_JMP(DisasContext *ctx, arg_JMP *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    gen_goto_tb(ctx, 0, a->imm);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Load one byte indirect from data space to register and stores an clear
> >> + *  the bits in data space specified by the register. The instruction can only
> >> + *  be used towards internal SRAM.  The data location is pointed to by the Z (16
> >> + *  bits) Pointer Register in the Register File. Memory access is limited to the
> >> + *  current data segment of 64KB. To access another data segment in devices with
> >> + *  more than 64KB data space, the RAMPZ in register in the I/O area has to be
> >> + *  changed.  The Z-pointer Register is left unchanged by the operation. This
> >> + *  instruction is especially suited for clearing status bits stored in SRAM.
> >> + */
> >> +static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
> >> +{
> >> +    if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
> >> +        gen_helper_fullwr(cpu_env, data, addr);
> >> +    } else {
> >> +        tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */
> >> +    }
> >> +}
> >> +
> >> +static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
> >> +{
> >> +    if (ctx->tb->flags & TB_FLAGS_FULL_ACCESS) {
> >> +        gen_helper_fullrd(data, cpu_env, addr);
> >> +    } else {
> >> +        tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */
> >> +    }
> >> +}
> >> +
> >> +static bool trans_LAC(DisasContext *ctx, arg_LAC *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rr = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_zaddr();
> >> +    TCGv t0 = tcg_temp_new_i32();
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +
> >> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
> >> +        /* t1 = t0 & (0xff - Rr) = t0 and ~Rr */
> >> +    tcg_gen_andc_tl(t1, t0, Rr);
> >> +
> >> +    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */
> >> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
> >> +
> >> +    tcg_temp_free_i32(t1);
> >> +    tcg_temp_free_i32(t0);
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Load one byte indirect from data space to register and set bits in data
> >> + *  space specified by the register. The instruction can only be used towards
> >> + *  internal SRAM.  The data location is pointed to by the Z (16 bits) Pointer
> >> + *  Register in the Register File. Memory access is limited to the current data
> >> + *  segment of 64KB. To access another data segment in devices with more than
> >> + *  64KB data space, the RAMPZ in register in the I/O area has to be changed.
> >> + *  The Z-pointer Register is left unchanged by the operation. This instruction
> >> + *  is especially suited for setting status bits stored in SRAM.
> >> + */
> >> +static bool trans_LAS(DisasContext *ctx, arg_LAS *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rr = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_zaddr();
> >> +    TCGv t0 = tcg_temp_new_i32();
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +
> >> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
> >> +    tcg_gen_or_tl(t1, t0, Rr);
> >> +
> >> +    tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */
> >> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
> >> +
> >> +    tcg_temp_free_i32(t1);
> >> +    tcg_temp_free_i32(t0);
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Load one byte indirect from data space to register and toggles bits in
> >> + *  the data space specified by the register.  The instruction can only be used
> >> + *  towards SRAM.  The data location is pointed to by the Z (16 bits) Pointer
> >> + *  Register in the Register File. Memory access is limited to the current data
> >> + *  segment of 64KB. To access another data segment in devices with more than
> >> + *  64KB data space, the RAMPZ in register in the I/O area has to be changed.
> >> + *  The Z-pointer Register is left unchanged by the operation. This instruction
> >> + *  is especially suited for changing status bits stored in SRAM.
> >> + */
> >> +static bool trans_LAT(DisasContext *ctx, arg_LAT *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_zaddr();
> >> +    TCGv t0 = tcg_temp_new_i32();
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +
> >> +    gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */
> >> +    tcg_gen_xor_tl(t1, t0, Rd);
> >> +
> >> +    tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */
> >> +    gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */
> >> +
> >> +    tcg_temp_free_i32(t1);
> >> +    tcg_temp_free_i32(t0);
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Loads one byte indirect from the data space to a register. For parts
> >> + *  with SRAM, the data space consists of the Register File, I/O memory and
> >> + *  internal SRAM (and external SRAM if applicable). For parts without SRAM, the
> >> + *  data space consists of the Register File only. In some parts the Flash
> >> + *  Memory has been mapped to the data space and can be read using this command.
> >> + *  The EEPROM has a separate address space.  The data location is pointed to by
> >> + *  the X (16 bits) Pointer Register in the Register File. Memory access is
> >> + *  limited to the current data segment of 64KB. To access another data segment
> >> + *  in devices with more than 64KB data space, the RAMPX in register in the I/O
> >> + *  area has to be changed.  The X-pointer Register can either be left unchanged
> >> + *  by the operation, or it can be post-incremented or predecremented.  These
> >> + *  features are especially suited for accessing arrays, tables, and Stack
> >> + *  Pointer usage of the X-pointer Register. Note that only the low byte of the
> >> + *  X-pointer is updated in devices with no more than 256 bytes data space. For
> >> + *  such devices, the high byte of the pointer is not used by this instruction
> >> + *  and can be used for other purposes. The RAMPX Register in the I/O area is
> >> + *  updated in parts with more than 64KB data space or more than 64KB Program
> >> + *  memory, and the increment/decrement is added to the entire 24-bit address on
> >> + *  such devices.  Not all variants of this instruction is available in all
> >> + *  devices. Refer to the device specific instruction set summary.  In the
> >> + *  Reduced Core tinyAVR the LD instruction can be used to achieve the same
> >> + *  operation as LPM since the program memory is mapped to the data memory
> >> + *  space.
> >> + */
> >> +static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_xaddr();
> >> +
> >> +    gen_data_load(ctx, Rd, addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_xaddr();
> >> +
> >> +    gen_data_load(ctx, Rd, addr);
> >> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> >> +
> >> +    gen_set_xaddr(addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_xaddr();
> >> +
> >> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
> >> +    gen_data_load(ctx, Rd, addr);
> >> +    gen_set_xaddr(addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Loads one byte indirect with or without displacement from the data space
> >> + *  to a register. For parts with SRAM, the data space consists of the Register
> >> + *  File, I/O memory and internal SRAM (and external SRAM if applicable). For
> >> + *  parts without SRAM, the data space consists of the Register File only. In
> >> + *  some parts the Flash Memory has been mapped to the data space and can be
> >> + *  read using this command. The EEPROM has a separate address space.  The data
> >> + *  location is pointed to by the Y (16 bits) Pointer Register in the Register
> >> + *  File. Memory access is limited to the current data segment of 64KB. To
> >> + *  access another data segment in devices with more than 64KB data space, the
> >> + *  RAMPY in register in the I/O area has to be changed.  The Y-pointer Register
> >> + *  can either be left unchanged by the operation, or it can be post-incremented
> >> + *  or predecremented.  These features are especially suited for accessing
> >> + *  arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that
> >> + *  only the low byte of the Y-pointer is updated in devices with no more than
> >> + *  256 bytes data space. For such devices, the high byte of the pointer is not
> >> + *  used by this instruction and can be used for other purposes. The RAMPY
> >> + *  Register in the I/O area is updated in parts with more than 64KB data space
> >> + *  or more than 64KB Program memory, and the increment/decrement/displacement
> >> + *  is added to the entire 24-bit address on such devices.  Not all variants of
> >> + *  this instruction is available in all devices. Refer to the device specific
> >> + *  instruction set summary.  In the Reduced Core tinyAVR the LD instruction can
> >> + *  be used to achieve the same operation as LPM since the program memory is
> >> + *  mapped to the data memory space.
> >> + */
> >> +static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_yaddr();
> >> +
> >> +    gen_data_load(ctx, Rd, addr);
> >> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> >> +
> >> +    gen_set_yaddr(addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_yaddr();
> >> +
> >> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
> >> +    gen_data_load(ctx, Rd, addr);
> >> +    gen_set_yaddr(addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_yaddr();
> >> +
> >> +    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
> >> +    gen_data_load(ctx, Rd, addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Loads one byte indirect with or without displacement from the data space
> >> + *  to a register. For parts with SRAM, the data space consists of the Register
> >> + *  File, I/O memory and internal SRAM (and external SRAM if applicable). For
> >> + *  parts without SRAM, the data space consists of the Register File only. In
> >> + *  some parts the Flash Memory has been mapped to the data space and can be
> >> + *  read using this command. The EEPROM has a separate address space.  The data
> >> + *  location is pointed to by the Z (16 bits) Pointer Register in the Register
> >> + *  File. Memory access is limited to the current data segment of 64KB. To
> >> + *  access another data segment in devices with more than 64KB data space, the
> >> + *  RAMPZ in register in the I/O area has to be changed.  The Z-pointer Register
> >> + *  can either be left unchanged by the operation, or it can be post-incremented
> >> + *  or predecremented.  These features are especially suited for Stack Pointer
> >> + *  usage of the Z-pointer Register, however because the Z-pointer Register can
> >> + *  be used for indirect subroutine calls, indirect jumps and table lookup, it
> >> + *  is often more convenient to use the X or Y-pointer as a dedicated Stack
> >> + *  Pointer. Note that only the low byte of the Z-pointer is updated in devices
> >> + *  with no more than 256 bytes data space. For such devices, the high byte of
> >> + *  the pointer is not used by this instruction and can be used for other
> >> + *  purposes. The RAMPZ Register in the I/O area is updated in parts with more
> >> + *  than 64KB data space or more than 64KB Program memory, and the
> >> + *  increment/decrement/displacement is added to the entire 24-bit address on
> >> + *  such devices.  Not all variants of this instruction is available in all
> >> + *  devices. Refer to the device specific instruction set summary.  In the
> >> + *  Reduced Core tinyAVR the LD instruction can be used to achieve the same
> >> + *  operation as LPM since the program memory is mapped to the data memory
> >> + *  space.  For using the Z-pointer for table lookup in Program memory see the
> >> + *  LPM and ELPM instructions.
> >> + */
> >> +static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_zaddr();
> >> +
> >> +    gen_data_load(ctx, Rd, addr);
> >> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> >> +
> >> +    gen_set_zaddr(addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_zaddr();
> >> +
> >> +    tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */
> >> +    gen_data_load(ctx, Rd, addr);
> >> +
> >> +    gen_set_zaddr(addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = gen_get_zaddr();
> >> +
> >> +    tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */
> >> +    gen_data_load(ctx, Rd, addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + * Loads an 8 bit constant directly to register 16 to 31.
> >> + */
> >> +static bool trans_LDI(DisasContext *ctx, arg_LDI *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    int imm = a->imm;
> >> +
> >> +    tcg_gen_movi_tl(Rd, imm);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Loads one byte from the data space to a register. For parts with SRAM,
> >> + *  the data space consists of the Register File, I/O memory and internal SRAM
> >> + *  (and external SRAM if applicable). For parts without SRAM, the data space
> >> + *  consists of the register file only. The EEPROM has a separate address space.
> >> + *  A 16-bit address must be supplied. Memory access is limited to the current
> >> + *  data segment of 64KB. The LDS instruction uses the RAMPD Register to access
> >> + *  memory above 64KB. To access another data segment in devices with more than
> >> + *  64KB data space, the RAMPD in register in the I/O area has to be changed.
> >> + *  This instruction is not available in all devices. Refer to the device
> >> + *  specific instruction set summary.
> >> + */
> >> +static bool trans_LDS(DisasContext *ctx, arg_LDS *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = tcg_temp_new_i32();
> >> +    TCGv H = cpu_rampD;
> >> +    a->imm = next_word(ctx);
> >> +
> >> +    tcg_gen_mov_tl(addr, H); /* addr = H:M:L */
> >> +    tcg_gen_shli_tl(addr, addr, 16);
> >> +    tcg_gen_ori_tl(addr, addr, a->imm);
> >> +
> >> +    gen_data_load(ctx, Rd, addr);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Loads one byte pointed to by the Z-register into the destination
> >> + *  register Rd. This instruction features a 100% space effective constant
> >> + *  initialization or constant data fetch. The Program memory is organized in
> >> + *  16-bit words while the Z-pointer is a byte address. Thus, the least
> >> + *  significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high
> >> + *  byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of
> >> + *  Program memory. The Zpointer Register can either be left unchanged by the
> >> + *  operation, or it can be incremented. The incrementation does not apply to
> >> + *  the RAMPZ Register.  Devices with Self-Programming capability can use the
> >> + *  LPM instruction to read the Fuse and Lock bit values.  Refer to the device
> >> + *  documentation for a detailed description.  The LPM instruction is not
> >> + *  available in all devices. Refer to the device specific instruction set
> >> + *  summary
> >> + */
> >> +static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rd = cpu_r[0];
> >> +    TCGv addr = tcg_temp_new_i32();
> >> +    TCGv H = cpu_r[31];
> >> +    TCGv L = cpu_r[30];
> >> +
> >> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
> >> +    tcg_gen_or_tl(addr, addr, L);
> >> +
> >> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = tcg_temp_new_i32();
> >> +    TCGv H = cpu_r[31];
> >> +    TCGv L = cpu_r[30];
> >> +
> >> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
> >> +    tcg_gen_or_tl(addr, addr, L);
> >> +
> >> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv addr = tcg_temp_new_i32();
> >> +    TCGv H = cpu_r[31];
> >> +    TCGv L = cpu_r[30];
> >> +
> >> +    tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
> >> +    tcg_gen_or_tl(addr, addr, L);
> >> +
> >> +    tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
> >> +
> >> +    tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
> >> +
> >> +    tcg_gen_andi_tl(L, addr, 0xff);
> >> +
> >> +    tcg_gen_shri_tl(addr, addr, 8);
> >> +    tcg_gen_andi_tl(H, addr, 0xff);
> >> +
> >> +    tcg_temp_free_i32(addr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is
> >> + *  loaded into the C Flag of the SREG. This operation effectively divides an
> >> + *  unsigned value by two. The C Flag can be used to round the result.
> >> + */
> >> +static bool trans_LSR(DisasContext *ctx, arg_LSR *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +
> >> +    tcg_gen_andi_tl(cpu_Cf, Rd, 1);
> >> +
> >> +    tcg_gen_shri_tl(Rd, Rd, 1);
> >> +
> >> +    tcg_gen_mov_tl(cpu_Zf, Rd);
> >> +    tcg_gen_movi_tl(cpu_Nf, 0);
> >> +    tcg_gen_mov_tl(cpu_Vf, cpu_Cf);
> >> +    tcg_gen_mov_tl(cpu_Sf, cpu_Vf);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction makes a copy of one register into another. The source
> >> + *  register Rr is left unchanged, while the destination register Rd is loaded
> >> + *  with a copy of Rr.
> >> + */
> >> +static bool trans_MOV(DisasContext *ctx, arg_MOV *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +
> >> +    tcg_gen_mov_tl(Rd, Rr);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction makes a copy of one register pair into another register
> >> + *  pair. The source register pair Rr+1:Rr is left unchanged, while the
> >> + *  destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr.  This
> >> + *  instruction is not available in all devices. Refer to the device specific
> >> + *  instruction set summary.
> >> + */
> >> +static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv RdL = cpu_r[a->rd];
> >> +    TCGv RdH = cpu_r[a->rd + 1];
> >> +    TCGv RrL = cpu_r[a->rr];
> >> +    TCGv RrH = cpu_r[a->rr + 1];
> >> +
> >> +    tcg_gen_mov_tl(RdH, RrH);
> >> +    tcg_gen_mov_tl(RdL, RrL);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication.
> >> + */
> >> +static bool trans_MUL(DisasContext *ctx, arg_MUL *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv R0 = cpu_r[0];
> >> +    TCGv R1 = cpu_r[1];
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd *Rr */
> >> +
> >> +    tcg_gen_andi_tl(R0, R, 0xff);
> >> +    tcg_gen_shri_tl(R1, R, 8);
> >> +
> >> +    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */
> >> +    tcg_gen_mov_tl(cpu_Zf, R);
> >> +
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication.
> >> + */
> >> +static bool trans_MULS(DisasContext *ctx, arg_MULS *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv R0 = cpu_r[0];
> >> +    TCGv R1 = cpu_r[1];
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +    TCGv t0 = tcg_temp_new_i32();
> >> +    TCGv t1 = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
> >> +    tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */
> >> +    tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */
> >> +
> >> +    tcg_gen_andi_tl(R0, R, 0xff);
> >> +    tcg_gen_shri_tl(R1, R, 8);
> >> +
> >> +    tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(16) */
> >> +    tcg_gen_mov_tl(cpu_Zf, R);
> >> +
> >> +    tcg_temp_free_i32(t1);
> >> +    tcg_temp_free_i32(t0);
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a
> >> + *  signed and an unsigned number.
> >> + */
> >> +static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a)
> >> +{
> >> +    if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) {
> >> +        return true;
> >> +    }
> >> +
> >> +    TCGv R0 = cpu_r[0];
> >> +    TCGv R1 = cpu_r[1];
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv Rr = cpu_r[a->rr];
> >> +    TCGv R = tcg_temp_new_i32();
> >> +    TCGv t0 = tcg_temp_new_i32();
> >> +
> >> +    tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */
> >> +    tcg_gen_mul_tl(R, t0, Rr); /* R = Rd *Rr */
> >> +
> >> +    tcg_gen_andi_tl(R0, R, 0xff);
> >> +    tcg_gen_shri_tl(R1, R, 8);
> >> +
> >> +    tcg_gen_shri_tl(cpu_Cf, R, 16); /* Cf = R(16) */
> >> +    tcg_gen_mov_tl(cpu_Zf, R);
> >> +
> >> +    tcg_temp_free_i32(t0);
> >> +    tcg_temp_free_i32(R);
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +/*
> >> + *  Replaces the contents of register Rd with its two's complement; the
> >> + *  value $80 is left unchanged.
> >> + */
> >> +static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
> >> +{
> >> +    TCGv Rd = cpu_r[a->rd];
> >> +    TCGv t0 = tcg_const_i32(0);
> >> +    TCGv R = tcg_temp_new_i32();
> >> +
> >> +    /* op */
> >> +    tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
> >> +    tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
> >> +
> >> +    gen_sub_CHf(R, t0, Rd);
> >> +    gen_sub_Vf(R, t0, Rd);
> >> +    gen_ZNSf(R);
> >> +
> >> +    /* R */
> >> +    tcg_gen_mov_tl(Rd,--
> >> 2.17.2 (Apple Git-113)
> >>
> >>
>
>
> --
> Best Regards,
> Michael Rolnik


^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, back to index

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-02 14:01 [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 1/8] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 2/8] target/avr: Add instruction helpers Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 3/8] target/avr: Add instruction decoding Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 4/8] target/avr: Add instruction translation Michael Rolnik
2019-10-11 14:13   ` Aleksandar Markovic
2019-10-12 16:33     ` Michael Rolnik
2019-10-12 17:47       ` Aleksandar Markovic
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 5/8] target/avr: Add limited support for USART and 16 bit timer peripherals Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 6/8] target/avr: Add example board configuration Michael Rolnik
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
2019-10-11 14:20   ` Eric Blake
2019-10-11 15:25   ` Philippe Mathieu-Daudé
2019-09-02 14:01 ` [Qemu-devel] [PATCH v30 8/8] target/avr: Add tests Michael Rolnik
2019-10-11 15:32 ` [PATCH v30 0/8] QEMU AVR 8 bit cores Philippe Mathieu-Daudé
2019-10-11 15:54   ` [Qemu-devel] " Aleksandar Markovic
2019-10-11 16:11     ` Alex Bennée
2019-10-11 21:15       ` Aleksandar Markovic
2019-10-11 15:41 ` Philippe Mathieu-Daudé

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